1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#include <linux/clk.h>
21#include <linux/completion.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
24#include <linux/err.h>
25#include <linux/i2c.h>
26#include <linux/interrupt.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/of.h>
30#include <linux/of_device.h>
31#include <linux/platform_device.h>
32#include <linux/slab.h>
33#include <linux/platform_data/dma-atmel.h>
34#include <linux/pm_runtime.h>
35#include <linux/pinctrl/consumer.h>
36
37#define DEFAULT_TWI_CLK_HZ 100000
38#define AT91_I2C_TIMEOUT msecs_to_jiffies(100)
39#define AT91_I2C_DMA_THRESHOLD 8
40#define AUTOSUSPEND_TIMEOUT 2000
41
42
43#define AT91_TWI_CR 0x0000
44#define AT91_TWI_START BIT(0)
45#define AT91_TWI_STOP BIT(1)
46#define AT91_TWI_MSEN BIT(2)
47#define AT91_TWI_MSDIS BIT(3)
48#define AT91_TWI_SVEN BIT(4)
49#define AT91_TWI_SVDIS BIT(5)
50#define AT91_TWI_QUICK BIT(6)
51#define AT91_TWI_SWRST BIT(7)
52#define AT91_TWI_ACMEN BIT(16)
53#define AT91_TWI_ACMDIS BIT(17)
54#define AT91_TWI_THRCLR BIT(24)
55#define AT91_TWI_RHRCLR BIT(25)
56#define AT91_TWI_LOCKCLR BIT(26)
57#define AT91_TWI_FIFOEN BIT(28)
58#define AT91_TWI_FIFODIS BIT(29)
59
60#define AT91_TWI_MMR 0x0004
61#define AT91_TWI_IADRSZ_1 0x0100
62#define AT91_TWI_MREAD BIT(12)
63
64#define AT91_TWI_IADR 0x000c
65
66#define AT91_TWI_CWGR 0x0010
67#define AT91_TWI_CWGR_HOLD_MAX 0x1f
68#define AT91_TWI_CWGR_HOLD(x) (((x) & AT91_TWI_CWGR_HOLD_MAX) << 24)
69
70#define AT91_TWI_SR 0x0020
71#define AT91_TWI_TXCOMP BIT(0)
72#define AT91_TWI_RXRDY BIT(1)
73#define AT91_TWI_TXRDY BIT(2)
74#define AT91_TWI_OVRE BIT(6)
75#define AT91_TWI_UNRE BIT(7)
76#define AT91_TWI_NACK BIT(8)
77#define AT91_TWI_LOCK BIT(23)
78
79#define AT91_TWI_INT_MASK \
80 (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
81
82#define AT91_TWI_IER 0x0024
83#define AT91_TWI_IDR 0x0028
84#define AT91_TWI_IMR 0x002c
85#define AT91_TWI_RHR 0x0030
86#define AT91_TWI_THR 0x0034
87
88#define AT91_TWI_ACR 0x0040
89#define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
90#define AT91_TWI_ACR_DIR BIT(8)
91
92#define AT91_TWI_FMR 0x0050
93#define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
94#define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
95#define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
96#define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
97#define AT91_TWI_ONE_DATA 0x0
98#define AT91_TWI_TWO_DATA 0x1
99#define AT91_TWI_FOUR_DATA 0x2
100
101#define AT91_TWI_FLR 0x0054
102
103#define AT91_TWI_FSR 0x0060
104#define AT91_TWI_FIER 0x0064
105#define AT91_TWI_FIDR 0x0068
106#define AT91_TWI_FIMR 0x006c
107
108#define AT91_TWI_VER 0x00fc
109
110struct at91_twi_pdata {
111 unsigned clk_max_div;
112 unsigned clk_offset;
113 bool has_unre_flag;
114 bool has_alt_cmd;
115 bool has_hold_field;
116 struct at_dma_slave dma_slave;
117};
118
119struct at91_twi_dma {
120 struct dma_chan *chan_rx;
121 struct dma_chan *chan_tx;
122 struct scatterlist sg[2];
123 struct dma_async_tx_descriptor *data_desc;
124 enum dma_data_direction direction;
125 bool buf_mapped;
126 bool xfer_in_progress;
127};
128
129struct at91_twi_dev {
130 struct device *dev;
131 void __iomem *base;
132 struct completion cmd_complete;
133 struct clk *clk;
134 u8 *buf;
135 size_t buf_len;
136 struct i2c_msg *msg;
137 int irq;
138 unsigned imr;
139 unsigned transfer_status;
140 struct i2c_adapter adapter;
141 unsigned twi_cwgr_reg;
142 struct at91_twi_pdata *pdata;
143 bool use_dma;
144 bool recv_len_abort;
145 u32 fifo_size;
146 struct at91_twi_dma dma;
147};
148
149static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
150{
151 return readl_relaxed(dev->base + reg);
152}
153
154static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
155{
156 writel_relaxed(val, dev->base + reg);
157}
158
159static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
160{
161 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
162}
163
164static void at91_twi_irq_save(struct at91_twi_dev *dev)
165{
166 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
167 at91_disable_twi_interrupts(dev);
168}
169
170static void at91_twi_irq_restore(struct at91_twi_dev *dev)
171{
172 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
173}
174
175static void at91_init_twi_bus(struct at91_twi_dev *dev)
176{
177 at91_disable_twi_interrupts(dev);
178 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
179
180 if (dev->fifo_size)
181 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN);
182 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
183 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
184 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
185}
186
187
188
189
190
191static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
192{
193 int ckdiv, cdiv, div, hold = 0;
194 struct at91_twi_pdata *pdata = dev->pdata;
195 int offset = pdata->clk_offset;
196 int max_ckdiv = pdata->clk_max_div;
197 u32 twd_hold_time_ns = 0;
198
199 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
200 2 * twi_clk) - offset);
201 ckdiv = fls(div >> 8);
202 cdiv = div >> ckdiv;
203
204 if (ckdiv > max_ckdiv) {
205 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
206 ckdiv, max_ckdiv);
207 ckdiv = max_ckdiv;
208 cdiv = 255;
209 }
210
211 if (pdata->has_hold_field) {
212 of_property_read_u32(dev->dev->of_node, "i2c-sda-hold-time-ns",
213 &twd_hold_time_ns);
214
215
216
217
218
219
220 hold = DIV_ROUND_UP(twd_hold_time_ns
221 * (clk_get_rate(dev->clk) / 1000), 1000000);
222 hold -= 3;
223 if (hold < 0)
224 hold = 0;
225 if (hold > AT91_TWI_CWGR_HOLD_MAX) {
226 dev_warn(dev->dev,
227 "HOLD field set to its maximum value (%d instead of %d)\n",
228 AT91_TWI_CWGR_HOLD_MAX, hold);
229 hold = AT91_TWI_CWGR_HOLD_MAX;
230 }
231 }
232
233 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv
234 | AT91_TWI_CWGR_HOLD(hold);
235
236 dev_dbg(dev->dev, "cdiv %d ckdiv %d hold %d (%d ns)\n",
237 cdiv, ckdiv, hold, twd_hold_time_ns);
238}
239
240static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
241{
242 struct at91_twi_dma *dma = &dev->dma;
243
244 at91_twi_irq_save(dev);
245
246 if (dma->xfer_in_progress) {
247 if (dma->direction == DMA_FROM_DEVICE)
248 dmaengine_terminate_all(dma->chan_rx);
249 else
250 dmaengine_terminate_all(dma->chan_tx);
251 dma->xfer_in_progress = false;
252 }
253 if (dma->buf_mapped) {
254 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg[0]),
255 dev->buf_len, dma->direction);
256 dma->buf_mapped = false;
257 }
258
259 at91_twi_irq_restore(dev);
260}
261
262static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
263{
264 if (!dev->buf_len)
265 return;
266
267
268 writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);
269
270
271 if (--dev->buf_len == 0)
272 if (!dev->pdata->has_alt_cmd)
273 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
274
275 dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
276
277 ++dev->buf;
278}
279
280static void at91_twi_write_data_dma_callback(void *data)
281{
282 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
283
284 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
285 dev->buf_len, DMA_TO_DEVICE);
286
287
288
289
290
291
292
293
294 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
295 if (!dev->pdata->has_alt_cmd)
296 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
297}
298
299static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
300{
301 dma_addr_t dma_addr;
302 struct dma_async_tx_descriptor *txdesc;
303 struct at91_twi_dma *dma = &dev->dma;
304 struct dma_chan *chan_tx = dma->chan_tx;
305 unsigned int sg_len = 1;
306
307 if (!dev->buf_len)
308 return;
309
310 dma->direction = DMA_TO_DEVICE;
311
312 at91_twi_irq_save(dev);
313 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
314 DMA_TO_DEVICE);
315 if (dma_mapping_error(dev->dev, dma_addr)) {
316 dev_err(dev->dev, "dma map failed\n");
317 return;
318 }
319 dma->buf_mapped = true;
320 at91_twi_irq_restore(dev);
321
322 if (dev->fifo_size) {
323 size_t part1_len, part2_len;
324 struct scatterlist *sg;
325 unsigned fifo_mr;
326
327 sg_len = 0;
328
329 part1_len = dev->buf_len & ~0x3;
330 if (part1_len) {
331 sg = &dma->sg[sg_len++];
332 sg_dma_len(sg) = part1_len;
333 sg_dma_address(sg) = dma_addr;
334 }
335
336 part2_len = dev->buf_len & 0x3;
337 if (part2_len) {
338 sg = &dma->sg[sg_len++];
339 sg_dma_len(sg) = part2_len;
340 sg_dma_address(sg) = dma_addr + part1_len;
341 }
342
343
344
345
346
347 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
348 fifo_mr &= ~AT91_TWI_FMR_TXRDYM_MASK;
349 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_FOUR_DATA);
350 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
351 } else {
352 sg_dma_len(&dma->sg[0]) = dev->buf_len;
353 sg_dma_address(&dma->sg[0]) = dma_addr;
354 }
355
356 txdesc = dmaengine_prep_slave_sg(chan_tx, dma->sg, sg_len,
357 DMA_MEM_TO_DEV,
358 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
359 if (!txdesc) {
360 dev_err(dev->dev, "dma prep slave sg failed\n");
361 goto error;
362 }
363
364 txdesc->callback = at91_twi_write_data_dma_callback;
365 txdesc->callback_param = dev;
366
367 dma->xfer_in_progress = true;
368 dmaengine_submit(txdesc);
369 dma_async_issue_pending(chan_tx);
370
371 return;
372
373error:
374 at91_twi_dma_cleanup(dev);
375}
376
377static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
378{
379
380
381
382
383 if (!dev->buf_len) {
384 at91_twi_read(dev, AT91_TWI_RHR);
385 return;
386 }
387
388
389 *dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR);
390 --dev->buf_len;
391
392
393 if (dev->recv_len_abort)
394 return;
395
396
397 if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
398
399 if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
400 dev->msg->flags &= ~I2C_M_RECV_LEN;
401 dev->buf_len += *dev->buf;
402 dev->msg->len = dev->buf_len + 1;
403 dev_dbg(dev->dev, "received block length %d\n",
404 dev->buf_len);
405 } else {
406
407 dev->recv_len_abort = true;
408 dev->buf_len = 1;
409 }
410 }
411
412
413 if (!dev->pdata->has_alt_cmd && dev->buf_len == 1)
414 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
415
416 dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
417
418 ++dev->buf;
419}
420
421static void at91_twi_read_data_dma_callback(void *data)
422{
423 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
424 unsigned ier = AT91_TWI_TXCOMP;
425
426 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
427 dev->buf_len, DMA_FROM_DEVICE);
428
429 if (!dev->pdata->has_alt_cmd) {
430
431 dev->buf += dev->buf_len - 2;
432 dev->buf_len = 2;
433 ier |= AT91_TWI_RXRDY;
434 }
435 at91_twi_write(dev, AT91_TWI_IER, ier);
436}
437
438static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
439{
440 dma_addr_t dma_addr;
441 struct dma_async_tx_descriptor *rxdesc;
442 struct at91_twi_dma *dma = &dev->dma;
443 struct dma_chan *chan_rx = dma->chan_rx;
444 size_t buf_len;
445
446 buf_len = (dev->pdata->has_alt_cmd) ? dev->buf_len : dev->buf_len - 2;
447 dma->direction = DMA_FROM_DEVICE;
448
449
450 at91_twi_irq_save(dev);
451 dma_addr = dma_map_single(dev->dev, dev->buf, buf_len, DMA_FROM_DEVICE);
452 if (dma_mapping_error(dev->dev, dma_addr)) {
453 dev_err(dev->dev, "dma map failed\n");
454 return;
455 }
456 dma->buf_mapped = true;
457 at91_twi_irq_restore(dev);
458
459 if (dev->fifo_size && IS_ALIGNED(buf_len, 4)) {
460 unsigned fifo_mr;
461
462
463
464
465
466 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
467 fifo_mr &= ~AT91_TWI_FMR_RXRDYM_MASK;
468 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_FOUR_DATA);
469 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
470 }
471
472 sg_dma_len(&dma->sg[0]) = buf_len;
473 sg_dma_address(&dma->sg[0]) = dma_addr;
474
475 rxdesc = dmaengine_prep_slave_sg(chan_rx, dma->sg, 1, DMA_DEV_TO_MEM,
476 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
477 if (!rxdesc) {
478 dev_err(dev->dev, "dma prep slave sg failed\n");
479 goto error;
480 }
481
482 rxdesc->callback = at91_twi_read_data_dma_callback;
483 rxdesc->callback_param = dev;
484
485 dma->xfer_in_progress = true;
486 dmaengine_submit(rxdesc);
487 dma_async_issue_pending(dma->chan_rx);
488
489 return;
490
491error:
492 at91_twi_dma_cleanup(dev);
493}
494
495static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
496{
497 struct at91_twi_dev *dev = dev_id;
498 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
499 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
500
501 if (!irqstatus)
502 return IRQ_NONE;
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519 if (irqstatus & AT91_TWI_RXRDY)
520 at91_twi_read_next_byte(dev);
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560 if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
561 at91_disable_twi_interrupts(dev);
562 complete(&dev->cmd_complete);
563 } else if (irqstatus & AT91_TWI_TXRDY) {
564 at91_twi_write_next_byte(dev);
565 }
566
567
568 dev->transfer_status |= status;
569
570 return IRQ_HANDLED;
571}
572
573static int at91_do_twi_transfer(struct at91_twi_dev *dev)
574{
575 int ret;
576 unsigned long time_left;
577 bool has_unre_flag = dev->pdata->has_unre_flag;
578 bool has_alt_cmd = dev->pdata->has_alt_cmd;
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623 dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
624 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
625
626 reinit_completion(&dev->cmd_complete);
627 dev->transfer_status = 0;
628
629
630 at91_twi_read(dev, AT91_TWI_SR);
631
632 if (dev->fifo_size) {
633 unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
634
635
636 fifo_mr &= ~(AT91_TWI_FMR_TXRDYM_MASK |
637 AT91_TWI_FMR_RXRDYM_MASK);
638 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_ONE_DATA);
639 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_ONE_DATA);
640 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
641
642
643 at91_twi_write(dev, AT91_TWI_CR,
644 AT91_TWI_THRCLR | AT91_TWI_RHRCLR);
645 }
646
647 if (!dev->buf_len) {
648 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
649 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
650 } else if (dev->msg->flags & I2C_M_RD) {
651 unsigned start_flags = AT91_TWI_START;
652
653
654 if (!has_alt_cmd && dev->buf_len <= 1 &&
655 !(dev->msg->flags & I2C_M_RECV_LEN))
656 start_flags |= AT91_TWI_STOP;
657 at91_twi_write(dev, AT91_TWI_CR, start_flags);
658
659
660
661
662
663
664
665
666
667 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
668 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
669 at91_twi_read_data_dma(dev);
670 } else {
671 at91_twi_write(dev, AT91_TWI_IER,
672 AT91_TWI_TXCOMP |
673 AT91_TWI_NACK |
674 AT91_TWI_RXRDY);
675 }
676 } else {
677 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
678 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
679 at91_twi_write_data_dma(dev);
680 } else {
681 at91_twi_write_next_byte(dev);
682 at91_twi_write(dev, AT91_TWI_IER,
683 AT91_TWI_TXCOMP |
684 AT91_TWI_NACK |
685 AT91_TWI_TXRDY);
686 }
687 }
688
689 time_left = wait_for_completion_timeout(&dev->cmd_complete,
690 dev->adapter.timeout);
691 if (time_left == 0) {
692 dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR);
693 dev_err(dev->dev, "controller timed out\n");
694 at91_init_twi_bus(dev);
695 ret = -ETIMEDOUT;
696 goto error;
697 }
698 if (dev->transfer_status & AT91_TWI_NACK) {
699 dev_dbg(dev->dev, "received nack\n");
700 ret = -EREMOTEIO;
701 goto error;
702 }
703 if (dev->transfer_status & AT91_TWI_OVRE) {
704 dev_err(dev->dev, "overrun while reading\n");
705 ret = -EIO;
706 goto error;
707 }
708 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
709 dev_err(dev->dev, "underrun while writing\n");
710 ret = -EIO;
711 goto error;
712 }
713 if ((has_alt_cmd || dev->fifo_size) &&
714 (dev->transfer_status & AT91_TWI_LOCK)) {
715 dev_err(dev->dev, "tx locked\n");
716 ret = -EIO;
717 goto error;
718 }
719 if (dev->recv_len_abort) {
720 dev_err(dev->dev, "invalid smbus block length recvd\n");
721 ret = -EPROTO;
722 goto error;
723 }
724
725 dev_dbg(dev->dev, "transfer complete\n");
726
727 return 0;
728
729error:
730
731 at91_twi_dma_cleanup(dev);
732
733 if ((has_alt_cmd || dev->fifo_size) &&
734 (dev->transfer_status & AT91_TWI_LOCK)) {
735 dev_dbg(dev->dev, "unlock tx\n");
736 at91_twi_write(dev, AT91_TWI_CR,
737 AT91_TWI_THRCLR | AT91_TWI_LOCKCLR);
738 }
739 return ret;
740}
741
742static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
743{
744 struct at91_twi_dev *dev = i2c_get_adapdata(adap);
745 int ret;
746 unsigned int_addr_flag = 0;
747 struct i2c_msg *m_start = msg;
748 bool is_read, use_alt_cmd = false;
749
750 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
751
752 ret = pm_runtime_get_sync(dev->dev);
753 if (ret < 0)
754 goto out;
755
756 if (num == 2) {
757 int internal_address = 0;
758 int i;
759
760
761 m_start = &msg[1];
762 for (i = 0; i < msg->len; ++i) {
763 const unsigned addr = msg->buf[msg->len - 1 - i];
764
765 internal_address |= addr << (8 * i);
766 int_addr_flag += AT91_TWI_IADRSZ_1;
767 }
768 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
769 }
770
771 is_read = (m_start->flags & I2C_M_RD);
772 if (dev->pdata->has_alt_cmd) {
773 if (m_start->len > 0) {
774 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN);
775 at91_twi_write(dev, AT91_TWI_ACR,
776 AT91_TWI_ACR_DATAL(m_start->len) |
777 ((is_read) ? AT91_TWI_ACR_DIR : 0));
778 use_alt_cmd = true;
779 } else {
780 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS);
781 }
782 }
783
784 at91_twi_write(dev, AT91_TWI_MMR,
785 (m_start->addr << 16) |
786 int_addr_flag |
787 ((!use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0));
788
789 dev->buf_len = m_start->len;
790 dev->buf = m_start->buf;
791 dev->msg = m_start;
792 dev->recv_len_abort = false;
793
794 ret = at91_do_twi_transfer(dev);
795
796 ret = (ret < 0) ? ret : num;
797out:
798 pm_runtime_mark_last_busy(dev->dev);
799 pm_runtime_put_autosuspend(dev->dev);
800
801 return ret;
802}
803
804
805
806
807
808static struct i2c_adapter_quirks at91_twi_quirks = {
809 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
810 .max_comb_1st_msg_len = 3,
811};
812
813static u32 at91_twi_func(struct i2c_adapter *adapter)
814{
815 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
816 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
817}
818
819static struct i2c_algorithm at91_twi_algorithm = {
820 .master_xfer = at91_twi_xfer,
821 .functionality = at91_twi_func,
822};
823
824static struct at91_twi_pdata at91rm9200_config = {
825 .clk_max_div = 5,
826 .clk_offset = 3,
827 .has_unre_flag = true,
828 .has_alt_cmd = false,
829 .has_hold_field = false,
830};
831
832static struct at91_twi_pdata at91sam9261_config = {
833 .clk_max_div = 5,
834 .clk_offset = 4,
835 .has_unre_flag = false,
836 .has_alt_cmd = false,
837 .has_hold_field = false,
838};
839
840static struct at91_twi_pdata at91sam9260_config = {
841 .clk_max_div = 7,
842 .clk_offset = 4,
843 .has_unre_flag = false,
844 .has_alt_cmd = false,
845 .has_hold_field = false,
846};
847
848static struct at91_twi_pdata at91sam9g20_config = {
849 .clk_max_div = 7,
850 .clk_offset = 4,
851 .has_unre_flag = false,
852 .has_alt_cmd = false,
853 .has_hold_field = false,
854};
855
856static struct at91_twi_pdata at91sam9g10_config = {
857 .clk_max_div = 7,
858 .clk_offset = 4,
859 .has_unre_flag = false,
860 .has_alt_cmd = false,
861 .has_hold_field = false,
862};
863
864static const struct platform_device_id at91_twi_devtypes[] = {
865 {
866 .name = "i2c-at91rm9200",
867 .driver_data = (unsigned long) &at91rm9200_config,
868 }, {
869 .name = "i2c-at91sam9261",
870 .driver_data = (unsigned long) &at91sam9261_config,
871 }, {
872 .name = "i2c-at91sam9260",
873 .driver_data = (unsigned long) &at91sam9260_config,
874 }, {
875 .name = "i2c-at91sam9g20",
876 .driver_data = (unsigned long) &at91sam9g20_config,
877 }, {
878 .name = "i2c-at91sam9g10",
879 .driver_data = (unsigned long) &at91sam9g10_config,
880 }, {
881
882 }
883};
884
885#if defined(CONFIG_OF)
886static struct at91_twi_pdata at91sam9x5_config = {
887 .clk_max_div = 7,
888 .clk_offset = 4,
889 .has_unre_flag = false,
890 .has_alt_cmd = false,
891 .has_hold_field = false,
892};
893
894static struct at91_twi_pdata sama5d4_config = {
895 .clk_max_div = 7,
896 .clk_offset = 4,
897 .has_unre_flag = false,
898 .has_alt_cmd = false,
899 .has_hold_field = true,
900};
901
902static struct at91_twi_pdata sama5d2_config = {
903 .clk_max_div = 7,
904 .clk_offset = 4,
905 .has_unre_flag = true,
906 .has_alt_cmd = true,
907 .has_hold_field = true,
908};
909
910static const struct of_device_id atmel_twi_dt_ids[] = {
911 {
912 .compatible = "atmel,at91rm9200-i2c",
913 .data = &at91rm9200_config,
914 } , {
915 .compatible = "atmel,at91sam9260-i2c",
916 .data = &at91sam9260_config,
917 } , {
918 .compatible = "atmel,at91sam9261-i2c",
919 .data = &at91sam9261_config,
920 } , {
921 .compatible = "atmel,at91sam9g20-i2c",
922 .data = &at91sam9g20_config,
923 } , {
924 .compatible = "atmel,at91sam9g10-i2c",
925 .data = &at91sam9g10_config,
926 }, {
927 .compatible = "atmel,at91sam9x5-i2c",
928 .data = &at91sam9x5_config,
929 }, {
930 .compatible = "atmel,sama5d4-i2c",
931 .data = &sama5d4_config,
932 }, {
933 .compatible = "atmel,sama5d2-i2c",
934 .data = &sama5d2_config,
935 }, {
936
937 }
938};
939MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
940#endif
941
942static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
943{
944 int ret = 0;
945 struct dma_slave_config slave_config;
946 struct at91_twi_dma *dma = &dev->dma;
947 enum dma_slave_buswidth addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964 if (dev->fifo_size)
965 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
966
967 memset(&slave_config, 0, sizeof(slave_config));
968 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
969 slave_config.src_addr_width = addr_width;
970 slave_config.src_maxburst = 1;
971 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
972 slave_config.dst_addr_width = addr_width;
973 slave_config.dst_maxburst = 1;
974 slave_config.device_fc = false;
975
976 dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
977 if (IS_ERR(dma->chan_tx)) {
978 ret = PTR_ERR(dma->chan_tx);
979 dma->chan_tx = NULL;
980 goto error;
981 }
982
983 dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
984 if (IS_ERR(dma->chan_rx)) {
985 ret = PTR_ERR(dma->chan_rx);
986 dma->chan_rx = NULL;
987 goto error;
988 }
989
990 slave_config.direction = DMA_MEM_TO_DEV;
991 if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
992 dev_err(dev->dev, "failed to configure tx channel\n");
993 ret = -EINVAL;
994 goto error;
995 }
996
997 slave_config.direction = DMA_DEV_TO_MEM;
998 if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
999 dev_err(dev->dev, "failed to configure rx channel\n");
1000 ret = -EINVAL;
1001 goto error;
1002 }
1003
1004 sg_init_table(dma->sg, 2);
1005 dma->buf_mapped = false;
1006 dma->xfer_in_progress = false;
1007 dev->use_dma = true;
1008
1009 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
1010 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
1011
1012 return ret;
1013
1014error:
1015 if (ret != -EPROBE_DEFER)
1016 dev_info(dev->dev, "can't use DMA, error %d\n", ret);
1017 if (dma->chan_rx)
1018 dma_release_channel(dma->chan_rx);
1019 if (dma->chan_tx)
1020 dma_release_channel(dma->chan_tx);
1021 return ret;
1022}
1023
1024static struct at91_twi_pdata *at91_twi_get_driver_data(
1025 struct platform_device *pdev)
1026{
1027 if (pdev->dev.of_node) {
1028 const struct of_device_id *match;
1029 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
1030 if (!match)
1031 return NULL;
1032 return (struct at91_twi_pdata *)match->data;
1033 }
1034 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
1035}
1036
1037static int at91_twi_probe(struct platform_device *pdev)
1038{
1039 struct at91_twi_dev *dev;
1040 struct resource *mem;
1041 int rc;
1042 u32 phy_addr;
1043 u32 bus_clk_rate;
1044
1045 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1046 if (!dev)
1047 return -ENOMEM;
1048 init_completion(&dev->cmd_complete);
1049 dev->dev = &pdev->dev;
1050
1051 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1052 if (!mem)
1053 return -ENODEV;
1054 phy_addr = mem->start;
1055
1056 dev->pdata = at91_twi_get_driver_data(pdev);
1057 if (!dev->pdata)
1058 return -ENODEV;
1059
1060 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1061 if (IS_ERR(dev->base))
1062 return PTR_ERR(dev->base);
1063
1064 dev->irq = platform_get_irq(pdev, 0);
1065 if (dev->irq < 0)
1066 return dev->irq;
1067
1068 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
1069 dev_name(dev->dev), dev);
1070 if (rc) {
1071 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
1072 return rc;
1073 }
1074
1075 platform_set_drvdata(pdev, dev);
1076
1077 dev->clk = devm_clk_get(dev->dev, NULL);
1078 if (IS_ERR(dev->clk)) {
1079 dev_err(dev->dev, "no clock defined\n");
1080 return -ENODEV;
1081 }
1082 clk_prepare_enable(dev->clk);
1083
1084 if (dev->dev->of_node) {
1085 rc = at91_twi_configure_dma(dev, phy_addr);
1086 if (rc == -EPROBE_DEFER)
1087 return rc;
1088 }
1089
1090 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
1091 &dev->fifo_size)) {
1092 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);
1093 }
1094
1095 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
1096 &bus_clk_rate);
1097 if (rc)
1098 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
1099
1100 at91_calc_twi_clock(dev, bus_clk_rate);
1101 at91_init_twi_bus(dev);
1102
1103 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
1104 i2c_set_adapdata(&dev->adapter, dev);
1105 dev->adapter.owner = THIS_MODULE;
1106 dev->adapter.class = I2C_CLASS_DEPRECATED;
1107 dev->adapter.algo = &at91_twi_algorithm;
1108 dev->adapter.quirks = &at91_twi_quirks;
1109 dev->adapter.dev.parent = dev->dev;
1110 dev->adapter.nr = pdev->id;
1111 dev->adapter.timeout = AT91_I2C_TIMEOUT;
1112 dev->adapter.dev.of_node = pdev->dev.of_node;
1113
1114 pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
1115 pm_runtime_use_autosuspend(dev->dev);
1116 pm_runtime_set_active(dev->dev);
1117 pm_runtime_enable(dev->dev);
1118
1119 rc = i2c_add_numbered_adapter(&dev->adapter);
1120 if (rc) {
1121 dev_err(dev->dev, "Adapter %s registration failed\n",
1122 dev->adapter.name);
1123 clk_disable_unprepare(dev->clk);
1124
1125 pm_runtime_disable(dev->dev);
1126 pm_runtime_set_suspended(dev->dev);
1127
1128 return rc;
1129 }
1130
1131 dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
1132 at91_twi_read(dev, AT91_TWI_VER));
1133 return 0;
1134}
1135
1136static int at91_twi_remove(struct platform_device *pdev)
1137{
1138 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
1139
1140 i2c_del_adapter(&dev->adapter);
1141 clk_disable_unprepare(dev->clk);
1142
1143 pm_runtime_disable(dev->dev);
1144 pm_runtime_set_suspended(dev->dev);
1145
1146 return 0;
1147}
1148
1149#ifdef CONFIG_PM
1150
1151static int at91_twi_runtime_suspend(struct device *dev)
1152{
1153 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1154
1155 clk_disable_unprepare(twi_dev->clk);
1156
1157 pinctrl_pm_select_sleep_state(dev);
1158
1159 return 0;
1160}
1161
1162static int at91_twi_runtime_resume(struct device *dev)
1163{
1164 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1165
1166 pinctrl_pm_select_default_state(dev);
1167
1168 return clk_prepare_enable(twi_dev->clk);
1169}
1170
1171static int at91_twi_suspend_noirq(struct device *dev)
1172{
1173 if (!pm_runtime_status_suspended(dev))
1174 at91_twi_runtime_suspend(dev);
1175
1176 return 0;
1177}
1178
1179static int at91_twi_resume_noirq(struct device *dev)
1180{
1181 int ret;
1182
1183 if (!pm_runtime_status_suspended(dev)) {
1184 ret = at91_twi_runtime_resume(dev);
1185 if (ret)
1186 return ret;
1187 }
1188
1189 pm_runtime_mark_last_busy(dev);
1190 pm_request_autosuspend(dev);
1191
1192 return 0;
1193}
1194
1195static const struct dev_pm_ops at91_twi_pm = {
1196 .suspend_noirq = at91_twi_suspend_noirq,
1197 .resume_noirq = at91_twi_resume_noirq,
1198 .runtime_suspend = at91_twi_runtime_suspend,
1199 .runtime_resume = at91_twi_runtime_resume,
1200};
1201
1202#define at91_twi_pm_ops (&at91_twi_pm)
1203#else
1204#define at91_twi_pm_ops NULL
1205#endif
1206
1207static struct platform_driver at91_twi_driver = {
1208 .probe = at91_twi_probe,
1209 .remove = at91_twi_remove,
1210 .id_table = at91_twi_devtypes,
1211 .driver = {
1212 .name = "at91_i2c",
1213 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
1214 .pm = at91_twi_pm_ops,
1215 },
1216};
1217
1218static int __init at91_twi_init(void)
1219{
1220 return platform_driver_register(&at91_twi_driver);
1221}
1222
1223static void __exit at91_twi_exit(void)
1224{
1225 platform_driver_unregister(&at91_twi_driver);
1226}
1227
1228subsys_initcall(at91_twi_init);
1229module_exit(at91_twi_exit);
1230
1231MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
1232MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
1233MODULE_LICENSE("GPL");
1234MODULE_ALIAS("platform:at91_i2c");
1235