LXR linux/drivers/i2c/busses/i2c-axxia.c

   1/*
   2 * This driver implements I2C master functionality using the LSI API2C
   3 * controller.
   4 *
   5 * NOTE: The controller has a limitation in that it can only do transfers of
   6 * maximum 255 bytes at a time. If a larger transfer is attempted, error code
   7 * (-EINVAL) is returned.
   8 *
   9 * This software is licensed under the terms of the GNU General Public
  10 * License version 2, as published by the Free Software Foundation, and
  11 * may be copied, distributed, and modified under those terms.
  12 */
  13#include <linux/clk.h>
  14#include <linux/clkdev.h>
  15#include <linux/err.h>
  16#include <linux/i2c.h>
  17#include <linux/init.h>
  18#include <linux/interrupt.h>
  19#include <linux/module.h>
  20#include <linux/io.h>
  21#include <linux/kernel.h>
  22#include <linux/platform_device.h>
  23
  24#define SCL_WAIT_TIMEOUT_NS 25000000
  25#define I2C_XFER_TIMEOUT    (msecs_to_jiffies(250))
  26#define I2C_STOP_TIMEOUT    (msecs_to_jiffies(100))
  27#define FIFO_SIZE           8
  28
  29#define GLOBAL_CONTROL          0x00
  30#define   GLOBAL_MST_EN         BIT(0)
  31#define   GLOBAL_SLV_EN         BIT(1)
  32#define   GLOBAL_IBML_EN        BIT(2)
  33#define INTERRUPT_STATUS        0x04
  34#define INTERRUPT_ENABLE        0x08
  35#define   INT_SLV               BIT(1)
  36#define   INT_MST               BIT(0)
  37#define WAIT_TIMER_CONTROL      0x0c
  38#define   WT_EN                 BIT(15)
  39#define   WT_VALUE(_x)          ((_x) & 0x7fff)
  40#define IBML_TIMEOUT            0x10
  41#define IBML_LOW_MEXT           0x14
  42#define IBML_LOW_SEXT           0x18
  43#define TIMER_CLOCK_DIV         0x1c
  44#define I2C_BUS_MONITOR         0x20
  45#define   BM_SDAC               BIT(3)
  46#define   BM_SCLC               BIT(2)
  47#define   BM_SDAS               BIT(1)
  48#define   BM_SCLS               BIT(0)
  49#define SOFT_RESET              0x24
  50#define MST_COMMAND             0x28
  51#define   CMD_BUSY              (1<<3)
  52#define   CMD_MANUAL            (0x00 | CMD_BUSY)
  53#define   CMD_AUTO              (0x01 | CMD_BUSY)
  54#define MST_RX_XFER             0x2c
  55#define MST_TX_XFER             0x30
  56#define MST_ADDR_1              0x34
  57#define MST_ADDR_2              0x38
  58#define MST_DATA                0x3c
  59#define MST_TX_FIFO             0x40
  60#define MST_RX_FIFO             0x44
  61#define MST_INT_ENABLE          0x48
  62#define MST_INT_STATUS          0x4c
  63#define   MST_STATUS_RFL        (1 << 13) /* RX FIFO serivce */
  64#define   MST_STATUS_TFL        (1 << 12) /* TX FIFO service */
  65#define   MST_STATUS_SNS        (1 << 11) /* Manual mode done */
  66#define   MST_STATUS_SS         (1 << 10) /* Automatic mode done */
  67#define   MST_STATUS_SCC        (1 << 9)  /* Stop complete */
  68#define   MST_STATUS_IP         (1 << 8)  /* Invalid parameter */
  69#define   MST_STATUS_TSS        (1 << 7)  /* Timeout */
  70#define   MST_STATUS_AL         (1 << 6)  /* Arbitration lost */
  71#define   MST_STATUS_ND         (1 << 5)  /* NAK on data phase */
  72#define   MST_STATUS_NA         (1 << 4)  /* NAK on address phase */
  73#define   MST_STATUS_NAK        (MST_STATUS_NA | \
  74                                 MST_STATUS_ND)
  75#define   MST_STATUS_ERR        (MST_STATUS_NAK | \
  76                                 MST_STATUS_AL  | \
  77                                 MST_STATUS_IP  | \
  78                                 MST_STATUS_TSS)
  79#define MST_TX_BYTES_XFRD       0x50
  80#define MST_RX_BYTES_XFRD       0x54
  81#define SCL_HIGH_PERIOD         0x80
  82#define SCL_LOW_PERIOD          0x84
  83#define SPIKE_FLTR_LEN          0x88
  84#define SDA_SETUP_TIME          0x8c
  85#define SDA_HOLD_TIME           0x90
  86
  87/**
  88 * axxia_i2c_dev - I2C device context
  89 * @base: pointer to register struct
  90 * @msg: pointer to current message
  91 * @msg_xfrd: number of bytes transferred in msg
  92 * @msg_err: error code for completed message
  93 * @msg_complete: xfer completion object
  94 * @dev: device reference
  95 * @adapter: core i2c abstraction
  96 * @i2c_clk: clock reference for i2c input clock
  97 * @bus_clk_rate: current i2c bus clock rate
  98 */
  99struct axxia_i2c_dev {
 100        void __iomem *base;
 101        struct i2c_msg *msg;
 102        size_t msg_xfrd;
 103        int msg_err;
 104        struct completion msg_complete;
 105        struct device *dev;
 106        struct i2c_adapter adapter;
 107        struct clk *i2c_clk;
 108        u32 bus_clk_rate;
 109};
 110
 111static void i2c_int_disable(struct axxia_i2c_dev *idev, u32 mask)
 112{
 113        u32 int_en;
 114
 115        int_en = readl(idev->base + MST_INT_ENABLE);
 116        writel(int_en & ~mask, idev->base + MST_INT_ENABLE);
 117}
 118
 119static void i2c_int_enable(struct axxia_i2c_dev *idev, u32 mask)
 120{
 121        u32 int_en;
 122
 123        int_en = readl(idev->base + MST_INT_ENABLE);
 124        writel(int_en | mask, idev->base + MST_INT_ENABLE);
 125}
 126
 127/**
 128 * ns_to_clk - Convert time (ns) to clock cycles for the given clock frequency.
 129 */
 130static u32 ns_to_clk(u64 ns, u32 clk_mhz)
 131{
 132        return div_u64(ns * clk_mhz, 1000);
 133}
 134
 135static int axxia_i2c_init(struct axxia_i2c_dev *idev)
 136{
 137        u32 divisor = clk_get_rate(idev->i2c_clk) / idev->bus_clk_rate;
 138        u32 clk_mhz = clk_get_rate(idev->i2c_clk) / 1000000;
 139        u32 t_setup;
 140        u32 t_high, t_low;
 141        u32 tmo_clk;
 142        u32 prescale;
 143        unsigned long timeout;
 144
 145        dev_dbg(idev->dev, "rate=%uHz per_clk=%uMHz -> ratio=1:%u\n",
 146                idev->bus_clk_rate, clk_mhz, divisor);
 147
 148        /* Reset controller */
 149        writel(0x01, idev->base + SOFT_RESET);
 150        timeout = jiffies + msecs_to_jiffies(100);
 151        while (readl(idev->base + SOFT_RESET) & 1) {
 152                if (time_after(jiffies, timeout)) {
 153                        dev_warn(idev->dev, "Soft reset failed\n");
 154                        break;
 155                }
 156        }
 157
 158        /* Enable Master Mode */
 159        writel(0x1, idev->base + GLOBAL_CONTROL);
 160
 161        if (idev->bus_clk_rate <= 100000) {
 162                /* Standard mode SCL 50/50, tSU:DAT = 250 ns */
 163                t_high = divisor * 1 / 2;
 164                t_low = divisor * 1 / 2;
 165                t_setup = ns_to_clk(250, clk_mhz);
 166        } else {
 167                /* Fast mode SCL 33/66, tSU:DAT = 100 ns */
 168                t_high = divisor * 1 / 3;
 169                t_low = divisor * 2 / 3;
 170                t_setup = ns_to_clk(100, clk_mhz);
 171        }
 172
 173        /* SCL High Time */
 174        writel(t_high, idev->base + SCL_HIGH_PERIOD);
 175        /* SCL Low Time */
 176        writel(t_low, idev->base + SCL_LOW_PERIOD);
 177        /* SDA Setup Time */
 178        writel(t_setup, idev->base + SDA_SETUP_TIME);
 179        /* SDA Hold Time, 300ns */
 180        writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);
 181        /* Filter <50ns spikes */
 182        writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);
 183
 184        /* Configure Time-Out Registers */
 185        tmo_clk = ns_to_clk(SCL_WAIT_TIMEOUT_NS, clk_mhz);
 186
 187        /* Find prescaler value that makes tmo_clk fit in 15-bits counter. */
 188        for (prescale = 0; prescale < 15; ++prescale) {
 189                if (tmo_clk <= 0x7fff)
 190                        break;
 191                tmo_clk >>= 1;
 192        }
 193        if (tmo_clk > 0x7fff)
 194                tmo_clk = 0x7fff;
 195
 196        /* Prescale divider (log2) */
 197        writel(prescale, idev->base + TIMER_CLOCK_DIV);
 198        /* Timeout in divided clocks */
 199        writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);
 200
 201        /* Mask all master interrupt bits */
 202        i2c_int_disable(idev, ~0);
 203
 204        /* Interrupt enable */
 205        writel(0x01, idev->base + INTERRUPT_ENABLE);
 206
 207        return 0;
 208}
 209
 210static int i2c_m_rd(const struct i2c_msg *msg)
 211{
 212        return (msg->flags & I2C_M_RD) != 0;
 213}
 214
 215static int i2c_m_ten(const struct i2c_msg *msg)
 216{
 217        return (msg->flags & I2C_M_TEN) != 0;
 218}
 219
 220static int i2c_m_recv_len(const struct i2c_msg *msg)
 221{
 222        return (msg->flags & I2C_M_RECV_LEN) != 0;
 223}
 224
 225/**
 226 * axxia_i2c_empty_rx_fifo - Fetch data from RX FIFO and update SMBus block
 227 * transfer length if this is the first byte of such a transfer.
 228 */
 229static int axxia_i2c_empty_rx_fifo(struct axxia_i2c_dev *idev)
 230{
 231        struct i2c_msg *msg = idev->msg;
 232        size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);
 233        int bytes_to_transfer = min(rx_fifo_avail, msg->len - idev->msg_xfrd);
 234
 235        while (bytes_to_transfer-- > 0) {
 236                int c = readl(idev->base + MST_DATA);
 237
 238                if (idev->msg_xfrd == 0 && i2c_m_recv_len(msg)) {
 239                        /*
 240                         * Check length byte for SMBus block read
 241                         */
 242                        if (c <= 0 || c > I2C_SMBUS_BLOCK_MAX) {
 243                                idev->msg_err = -EPROTO;
 244                                i2c_int_disable(idev, ~0);
 245                                complete(&idev->msg_complete);
 246                                break;
 247                        }
 248                        msg->len = 1 + c;
 249                        writel(msg->len, idev->base + MST_RX_XFER);
 250                }
 251                msg->buf[idev->msg_xfrd++] = c;
 252        }
 253
 254        return 0;
 255}
 256
 257/**
 258 * axxia_i2c_fill_tx_fifo - Fill TX FIFO from current message buffer.
 259 * @return: Number of bytes left to transfer.
 260 */
 261static int axxia_i2c_fill_tx_fifo(struct axxia_i2c_dev *idev)
 262{
 263        struct i2c_msg *msg = idev->msg;
 264        size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);
 265        int bytes_to_transfer = min(tx_fifo_avail, msg->len - idev->msg_xfrd);
 266        int ret = msg->len - idev->msg_xfrd - bytes_to_transfer;
 267
 268        while (bytes_to_transfer-- > 0)
 269                writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);
 270
 271        return ret;
 272}
 273
 274static irqreturn_t axxia_i2c_isr(int irq, void *_dev)
 275{
 276        struct axxia_i2c_dev *idev = _dev;
 277        u32 status;
 278
 279        if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST))
 280                return IRQ_NONE;
 281
 282        /* Read interrupt status bits */
 283        status = readl(idev->base + MST_INT_STATUS);
 284
 285        if (!idev->msg) {
 286                dev_warn(idev->dev, "unexpected interrupt\n");
 287                goto out;
 288        }
 289
 290        /* RX FIFO needs service? */
 291        if (i2c_m_rd(idev->msg) && (status & MST_STATUS_RFL))
 292                axxia_i2c_empty_rx_fifo(idev);
 293
 294        /* TX FIFO needs service? */
 295        if (!i2c_m_rd(idev->msg) && (status & MST_STATUS_TFL)) {
 296                if (axxia_i2c_fill_tx_fifo(idev) == 0)
 297                        i2c_int_disable(idev, MST_STATUS_TFL);
 298        }
 299
 300        if (status & MST_STATUS_SCC) {
 301                /* Stop completed */
 302                i2c_int_disable(idev, ~0);
 303                complete(&idev->msg_complete);
 304        } else if (status & MST_STATUS_SNS) {
 305                /* Transfer done */
 306                i2c_int_disable(idev, ~0);
 307                if (i2c_m_rd(idev->msg) && idev->msg_xfrd < idev->msg->len)
 308                        axxia_i2c_empty_rx_fifo(idev);
 309                complete(&idev->msg_complete);
 310        } else if (unlikely(status & MST_STATUS_ERR)) {
 311                /* Transfer error */
 312                i2c_int_disable(idev, ~0);
 313                if (status & MST_STATUS_AL)
 314                        idev->msg_err = -EAGAIN;
 315                else if (status & MST_STATUS_NAK)
 316                        idev->msg_err = -ENXIO;
 317                else
 318                        idev->msg_err = -EIO;
 319                dev_dbg(idev->dev, "error %#x, addr=%#x rx=%u/%u tx=%u/%u\n",
 320                        status,
 321                        idev->msg->addr,
 322                        readl(idev->base + MST_RX_BYTES_XFRD),
 323                        readl(idev->base + MST_RX_XFER),
 324                        readl(idev->base + MST_TX_BYTES_XFRD),
 325                        readl(idev->base + MST_TX_XFER));
 326                complete(&idev->msg_complete);
 327        }
 328
 329out:
 330        /* Clear interrupt */
 331        writel(INT_MST, idev->base + INTERRUPT_STATUS);
 332
 333        return IRQ_HANDLED;
 334}
 335
 336static int axxia_i2c_xfer_msg(struct axxia_i2c_dev *idev, struct i2c_msg *msg)
 337{
 338        u32 int_mask = MST_STATUS_ERR | MST_STATUS_SNS;
 339        u32 rx_xfer, tx_xfer;
 340        u32 addr_1, addr_2;
 341        unsigned long time_left;
 342
 343        idev->msg = msg;
 344        idev->msg_xfrd = 0;
 345        idev->msg_err = 0;
 346        reinit_completion(&idev->msg_complete);
 347
 348        if (i2c_m_ten(msg)) {
 349                /* 10-bit address
 350                 *   addr_1: 5'b11110 | addr[9:8] | (R/nW)
 351                 *   addr_2: addr[7:0]
 352                 */
 353                addr_1 = 0xF0 | ((msg->addr >> 7) & 0x06);
 354                addr_2 = msg->addr & 0xFF;
 355        } else {
 356                /* 7-bit address
 357                 *   addr_1: addr[6:0] | (R/nW)
 358                 *   addr_2: dont care
 359                 */
 360                addr_1 = (msg->addr << 1) & 0xFF;
 361                addr_2 = 0;
 362        }
 363
 364        if (i2c_m_rd(msg)) {
 365                /* I2C read transfer */
 366                rx_xfer = i2c_m_recv_len(msg) ? I2C_SMBUS_BLOCK_MAX : msg->len;
 367                tx_xfer = 0;
 368                addr_1 |= 1;    /* Set the R/nW bit of the address */
 369        } else {
 370                /* I2C write transfer */
 371                rx_xfer = 0;
 372                tx_xfer = msg->len;
 373        }
 374
 375        writel(rx_xfer, idev->base + MST_RX_XFER);
 376        writel(tx_xfer, idev->base + MST_TX_XFER);
 377        writel(addr_1, idev->base + MST_ADDR_1);
 378        writel(addr_2, idev->base + MST_ADDR_2);
 379
 380        if (i2c_m_rd(msg))
 381                int_mask |= MST_STATUS_RFL;
 382        else if (axxia_i2c_fill_tx_fifo(idev) != 0)
 383                int_mask |= MST_STATUS_TFL;
 384
 385        /* Start manual mode */
 386        writel(CMD_MANUAL, idev->base + MST_COMMAND);
 387
 388        i2c_int_enable(idev, int_mask);
 389
 390        time_left = wait_for_completion_timeout(&idev->msg_complete,
 391                                              I2C_XFER_TIMEOUT);
 392
 393        i2c_int_disable(idev, int_mask);
 394
 395        if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
 396                dev_warn(idev->dev, "busy after xfer\n");
 397
 398        if (time_left == 0)
 399                idev->msg_err = -ETIMEDOUT;
 400
 401        if (idev->msg_err == -ETIMEDOUT)
 402                i2c_recover_bus(&idev->adapter);
 403
 404        if (unlikely(idev->msg_err) && idev->msg_err != -ENXIO)
 405                axxia_i2c_init(idev);
 406
 407        return idev->msg_err;
 408}
 409
 410static int axxia_i2c_stop(struct axxia_i2c_dev *idev)
 411{
 412        u32 int_mask = MST_STATUS_ERR | MST_STATUS_SCC;
 413        unsigned long time_left;
 414
 415        reinit_completion(&idev->msg_complete);
 416
 417        /* Issue stop */
 418        writel(0xb, idev->base + MST_COMMAND);
 419        i2c_int_enable(idev, int_mask);
 420        time_left = wait_for_completion_timeout(&idev->msg_complete,
 421                                              I2C_STOP_TIMEOUT);
 422        i2c_int_disable(idev, int_mask);
 423        if (time_left == 0)
 424                return -ETIMEDOUT;
 425
 426        if (readl(idev->base + MST_COMMAND) & CMD_BUSY)
 427                dev_warn(idev->dev, "busy after stop\n");
 428
 429        return 0;
 430}
 431
 432static int
 433axxia_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 434{
 435        struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
 436        int i;
 437        int ret = 0;
 438
 439        for (i = 0; ret == 0 && i < num; ++i)
 440                ret = axxia_i2c_xfer_msg(idev, &msgs[i]);
 441
 442        axxia_i2c_stop(idev);
 443
 444        return ret ? : i;
 445}
 446
 447static int axxia_i2c_get_scl(struct i2c_adapter *adap)
 448{
 449        struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
 450
 451        return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SCLS);
 452}
 453
 454static void axxia_i2c_set_scl(struct i2c_adapter *adap, int val)
 455{
 456        struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
 457        u32 tmp;
 458
 459        /* Preserve SDA Control */
 460        tmp = readl(idev->base + I2C_BUS_MONITOR) & BM_SDAC;
 461        if (!val)
 462                tmp |= BM_SCLC;
 463        writel(tmp, idev->base + I2C_BUS_MONITOR);
 464}
 465
 466static int axxia_i2c_get_sda(struct i2c_adapter *adap)
 467{
 468        struct axxia_i2c_dev *idev = i2c_get_adapdata(adap);
 469
 470        return !!(readl(idev->base + I2C_BUS_MONITOR) & BM_SDAS);
 471}
 472
 473static struct i2c_bus_recovery_info axxia_i2c_recovery_info = {
 474        .recover_bus = i2c_generic_scl_recovery,
 475        .get_scl = axxia_i2c_get_scl,
 476        .set_scl = axxia_i2c_set_scl,
 477        .get_sda = axxia_i2c_get_sda,
 478};
 479
 480static u32 axxia_i2c_func(struct i2c_adapter *adap)
 481{
 482        u32 caps = (I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
 483                    I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA);
 484        return caps;
 485}
 486
 487static const struct i2c_algorithm axxia_i2c_algo = {
 488        .master_xfer = axxia_i2c_xfer,
 489        .functionality = axxia_i2c_func,
 490};
 491
 492static struct i2c_adapter_quirks axxia_i2c_quirks = {
 493        .max_read_len = 255,
 494        .max_write_len = 255,
 495};
 496
 497static int axxia_i2c_probe(struct platform_device *pdev)
 498{
 499        struct device_node *np = pdev->dev.of_node;
 500        struct axxia_i2c_dev *idev = NULL;
 501        struct resource *res;
 502        void __iomem *base;
 503        int irq;
 504        int ret = 0;
 505
 506        idev = devm_kzalloc(&pdev->dev, sizeof(*idev), GFP_KERNEL);
 507        if (!idev)
 508                return -ENOMEM;
 509
 510        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 511        base = devm_ioremap_resource(&pdev->dev, res);
 512        if (IS_ERR(base))
 513                return PTR_ERR(base);
 514
 515        irq = platform_get_irq(pdev, 0);
 516        if (irq < 0) {
 517                dev_err(&pdev->dev, "missing interrupt resource\n");
 518                return irq;
 519        }
 520
 521        idev->i2c_clk = devm_clk_get(&pdev->dev, "i2c");
 522        if (IS_ERR(idev->i2c_clk)) {
 523                dev_err(&pdev->dev, "missing clock\n");
 524                return PTR_ERR(idev->i2c_clk);
 525        }
 526
 527        idev->base = base;
 528        idev->dev = &pdev->dev;
 529        init_completion(&idev->msg_complete);
 530
 531        of_property_read_u32(np, "clock-frequency", &idev->bus_clk_rate);
 532        if (idev->bus_clk_rate == 0)
 533                idev->bus_clk_rate = 100000;    /* default clock rate */
 534
 535        ret = axxia_i2c_init(idev);
 536        if (ret) {
 537                dev_err(&pdev->dev, "failed to initialize\n");
 538                return ret;
 539        }
 540
 541        ret = devm_request_irq(&pdev->dev, irq, axxia_i2c_isr, 0,
 542                               pdev->name, idev);
 543        if (ret) {
 544                dev_err(&pdev->dev, "failed to claim IRQ%d\n", irq);
 545                return ret;
 546        }
 547
 548        clk_prepare_enable(idev->i2c_clk);
 549
 550        i2c_set_adapdata(&idev->adapter, idev);
 551        strlcpy(idev->adapter.name, pdev->name, sizeof(idev->adapter.name));
 552        idev->adapter.owner = THIS_MODULE;
 553        idev->adapter.algo = &axxia_i2c_algo;
 554        idev->adapter.bus_recovery_info = &axxia_i2c_recovery_info;
 555        idev->adapter.quirks = &axxia_i2c_quirks;
 556        idev->adapter.dev.parent = &pdev->dev;
 557        idev->adapter.dev.of_node = pdev->dev.of_node;
 558
 559        platform_set_drvdata(pdev, idev);
 560
 561        ret = i2c_add_adapter(&idev->adapter);
 562        if (ret) {
 563                dev_err(&pdev->dev, "failed to add adapter\n");
 564                return ret;
 565        }
 566
 567        return 0;
 568}
 569
 570static int axxia_i2c_remove(struct platform_device *pdev)
 571{
 572        struct axxia_i2c_dev *idev = platform_get_drvdata(pdev);
 573
 574        clk_disable_unprepare(idev->i2c_clk);
 575        i2c_del_adapter(&idev->adapter);
 576
 577        return 0;
 578}
 579
 580/* Match table for of_platform binding */
 581static const struct of_device_id axxia_i2c_of_match[] = {
 582        { .compatible = "lsi,api2c", },
 583        {},
 584};
 585
 586MODULE_DEVICE_TABLE(of, axxia_i2c_of_match);
 587
 588static struct platform_driver axxia_i2c_driver = {
 589        .probe = axxia_i2c_probe,
 590        .remove = axxia_i2c_remove,
 591        .driver = {
 592                .name = "axxia-i2c",
 593                .of_match_table = axxia_i2c_of_match,
 594        },
 595};
 596
 597module_platform_driver(axxia_i2c_driver);
 598
 599MODULE_DESCRIPTION("Axxia I2C Bus driver");
 600MODULE_AUTHOR("Anders Berg <anders.berg@lsi.com>");
 601MODULE_LICENSE("GPL v2");
 602