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23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/delay.h>
26#include <linux/i2c.h>
27#include <linux/clk.h>
28#include <linux/errno.h>
29#include <linux/sched.h>
30#include <linux/err.h>
31#include <linux/interrupt.h>
32#include <linux/platform_device.h>
33#include <linux/io.h>
34#include <linux/slab.h>
35#include <linux/cpufreq.h>
36#include <linux/gpio.h>
37#include <linux/of_device.h>
38#include <linux/platform_data/i2c-davinci.h>
39
40
41
42#define DAVINCI_I2C_TIMEOUT (1*HZ)
43#define DAVINCI_I2C_MAX_TRIES 2
44#define DAVINCI_I2C_OWN_ADDRESS 0x08
45#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_SCD | \
46 DAVINCI_I2C_IMR_ARDY | \
47 DAVINCI_I2C_IMR_NACK | \
48 DAVINCI_I2C_IMR_AL)
49
50#define DAVINCI_I2C_OAR_REG 0x00
51#define DAVINCI_I2C_IMR_REG 0x04
52#define DAVINCI_I2C_STR_REG 0x08
53#define DAVINCI_I2C_CLKL_REG 0x0c
54#define DAVINCI_I2C_CLKH_REG 0x10
55#define DAVINCI_I2C_CNT_REG 0x14
56#define DAVINCI_I2C_DRR_REG 0x18
57#define DAVINCI_I2C_SAR_REG 0x1c
58#define DAVINCI_I2C_DXR_REG 0x20
59#define DAVINCI_I2C_MDR_REG 0x24
60#define DAVINCI_I2C_IVR_REG 0x28
61#define DAVINCI_I2C_EMDR_REG 0x2c
62#define DAVINCI_I2C_PSC_REG 0x30
63#define DAVINCI_I2C_FUNC_REG 0x48
64#define DAVINCI_I2C_DIR_REG 0x4c
65#define DAVINCI_I2C_DIN_REG 0x50
66#define DAVINCI_I2C_DOUT_REG 0x54
67#define DAVINCI_I2C_DSET_REG 0x58
68#define DAVINCI_I2C_DCLR_REG 0x5c
69
70#define DAVINCI_I2C_IVR_AAS 0x07
71#define DAVINCI_I2C_IVR_SCD 0x06
72#define DAVINCI_I2C_IVR_XRDY 0x05
73#define DAVINCI_I2C_IVR_RDR 0x04
74#define DAVINCI_I2C_IVR_ARDY 0x03
75#define DAVINCI_I2C_IVR_NACK 0x02
76#define DAVINCI_I2C_IVR_AL 0x01
77
78#define DAVINCI_I2C_STR_BB BIT(12)
79#define DAVINCI_I2C_STR_RSFULL BIT(11)
80#define DAVINCI_I2C_STR_SCD BIT(5)
81#define DAVINCI_I2C_STR_ARDY BIT(2)
82#define DAVINCI_I2C_STR_NACK BIT(1)
83#define DAVINCI_I2C_STR_AL BIT(0)
84
85#define DAVINCI_I2C_MDR_NACK BIT(15)
86#define DAVINCI_I2C_MDR_STT BIT(13)
87#define DAVINCI_I2C_MDR_STP BIT(11)
88#define DAVINCI_I2C_MDR_MST BIT(10)
89#define DAVINCI_I2C_MDR_TRX BIT(9)
90#define DAVINCI_I2C_MDR_XA BIT(8)
91#define DAVINCI_I2C_MDR_RM BIT(7)
92#define DAVINCI_I2C_MDR_IRS BIT(5)
93
94#define DAVINCI_I2C_IMR_AAS BIT(6)
95#define DAVINCI_I2C_IMR_SCD BIT(5)
96#define DAVINCI_I2C_IMR_XRDY BIT(4)
97#define DAVINCI_I2C_IMR_RRDY BIT(3)
98#define DAVINCI_I2C_IMR_ARDY BIT(2)
99#define DAVINCI_I2C_IMR_NACK BIT(1)
100#define DAVINCI_I2C_IMR_AL BIT(0)
101
102
103#define DAVINCI_I2C_FUNC_PFUNC0 BIT(0)
104
105
106#define DAVINCI_I2C_DIR_PDIR0 BIT(0)
107
108#define DAVINCI_I2C_DIR_PDIR1 BIT(1)
109
110
111#define DAVINCI_I2C_DIN_PDIN0 BIT(0)
112
113#define DAVINCI_I2C_DIN_PDIN1 BIT(1)
114
115
116#define DAVINCI_I2C_DSET_PDSET0 BIT(0)
117
118#define DAVINCI_I2C_DSET_PDSET1 BIT(1)
119
120
121#define DAVINCI_I2C_DCLR_PDCLR0 BIT(0)
122
123#define DAVINCI_I2C_DCLR_PDCLR1 BIT(1)
124
125struct davinci_i2c_dev {
126 struct device *dev;
127 void __iomem *base;
128 struct completion cmd_complete;
129 struct clk *clk;
130 int cmd_err;
131 u8 *buf;
132 size_t buf_len;
133 int irq;
134 int stop;
135 u8 terminate;
136 struct i2c_adapter adapter;
137#ifdef CONFIG_CPU_FREQ
138 struct completion xfr_complete;
139 struct notifier_block freq_transition;
140#endif
141 struct davinci_i2c_platform_data *pdata;
142};
143
144
145static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = {
146 .bus_freq = 100,
147 .bus_delay = 0,
148};
149
150static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
151 int reg, u16 val)
152{
153 writew_relaxed(val, i2c_dev->base + reg);
154}
155
156static inline u16 davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
157{
158 return readw_relaxed(i2c_dev->base + reg);
159}
160
161static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
162 int val)
163{
164 u16 w;
165
166 w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
167 if (!val)
168 w &= ~DAVINCI_I2C_MDR_IRS;
169 else
170 w |= DAVINCI_I2C_MDR_IRS;
171
172 davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
173}
174
175static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
176{
177 struct davinci_i2c_platform_data *pdata = dev->pdata;
178 u16 psc;
179 u32 clk;
180 u32 d;
181 u32 clkh;
182 u32 clkl;
183 u32 input_clock = clk_get_rate(dev->clk);
184 struct device_node *of_node = dev->dev->of_node;
185
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211
212
213 psc = (input_clock / 12000000) - 1;
214 if ((input_clock / (psc + 1)) > 12000000)
215 psc++;
216 d = (psc >= 2) ? 5 : 7 - psc;
217
218 if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c"))
219 d = 6;
220
221 clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000));
222
223 if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000)
224 clk++;
225
226
227
228
229
230 if (pdata->bus_freq > 100)
231 clkl = (clk << 1) / 3;
232 else
233 clkl = (clk >> 1);
234
235
236
237
238 if (clk >= clkl + d) {
239 clkh = clk - clkl - d;
240 clkl -= d;
241 } else {
242 clkh = 0;
243 clkl = clk - (d << 1);
244 }
245
246 davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
247 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
248 davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
249
250 dev_dbg(dev->dev, "input_clock = %d, CLK = %d\n", input_clock, clk);
251}
252
253
254
255
256
257
258static int i2c_davinci_init(struct davinci_i2c_dev *dev)
259{
260 struct davinci_i2c_platform_data *pdata = dev->pdata;
261
262
263 davinci_i2c_reset_ctrl(dev, 0);
264
265
266 i2c_davinci_calc_clk_dividers(dev);
267
268
269
270
271 davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, DAVINCI_I2C_OWN_ADDRESS);
272
273 dev_dbg(dev->dev, "PSC = %d\n",
274 davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
275 dev_dbg(dev->dev, "CLKL = %d\n",
276 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
277 dev_dbg(dev->dev, "CLKH = %d\n",
278 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
279 dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n",
280 pdata->bus_freq, pdata->bus_delay);
281
282
283
284 davinci_i2c_reset_ctrl(dev, 1);
285
286
287 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
288
289 return 0;
290}
291
292
293
294
295
296static void davinci_i2c_prepare_recovery(struct i2c_adapter *adap)
297{
298 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
299
300
301 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, 0);
302
303
304 davinci_i2c_reset_ctrl(dev, 0);
305}
306
307static void davinci_i2c_unprepare_recovery(struct i2c_adapter *adap)
308{
309 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
310
311 i2c_davinci_init(dev);
312}
313
314static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = {
315 .recover_bus = i2c_generic_gpio_recovery,
316 .prepare_recovery = davinci_i2c_prepare_recovery,
317 .unprepare_recovery = davinci_i2c_unprepare_recovery,
318};
319
320static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val)
321{
322 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
323
324 if (val)
325 davinci_i2c_write_reg(dev, DAVINCI_I2C_DSET_REG,
326 DAVINCI_I2C_DSET_PDSET0);
327 else
328 davinci_i2c_write_reg(dev, DAVINCI_I2C_DCLR_REG,
329 DAVINCI_I2C_DCLR_PDCLR0);
330}
331
332static int davinci_i2c_get_scl(struct i2c_adapter *adap)
333{
334 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
335 int val;
336
337
338 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
339 return val & DAVINCI_I2C_DIN_PDIN0;
340}
341
342static int davinci_i2c_get_sda(struct i2c_adapter *adap)
343{
344 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
345 int val;
346
347
348 val = davinci_i2c_read_reg(dev, DAVINCI_I2C_DIN_REG);
349 return val & DAVINCI_I2C_DIN_PDIN1;
350}
351
352static void davinci_i2c_scl_prepare_recovery(struct i2c_adapter *adap)
353{
354 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
355
356 davinci_i2c_prepare_recovery(adap);
357
358
359 davinci_i2c_write_reg(dev, DAVINCI_I2C_DIR_REG, DAVINCI_I2C_DIR_PDIR0);
360
361
362 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG,
363 DAVINCI_I2C_FUNC_PFUNC0);
364}
365
366static void davinci_i2c_scl_unprepare_recovery(struct i2c_adapter *adap)
367{
368 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
369
370
371 davinci_i2c_write_reg(dev, DAVINCI_I2C_FUNC_REG, 0);
372
373 davinci_i2c_unprepare_recovery(adap);
374}
375
376static struct i2c_bus_recovery_info davinci_i2c_scl_recovery_info = {
377 .recover_bus = i2c_generic_scl_recovery,
378 .set_scl = davinci_i2c_set_scl,
379 .get_scl = davinci_i2c_get_scl,
380 .get_sda = davinci_i2c_get_sda,
381 .prepare_recovery = davinci_i2c_scl_prepare_recovery,
382 .unprepare_recovery = davinci_i2c_scl_unprepare_recovery,
383};
384
385
386
387
388static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev)
389{
390 unsigned long timeout = jiffies + dev->adapter.timeout;
391
392 do {
393 if (!(davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB))
394 return 0;
395 schedule_timeout_uninterruptible(1);
396 } while (time_before_eq(jiffies, timeout));
397
398 dev_warn(dev->dev, "timeout waiting for bus ready\n");
399 i2c_recover_bus(&dev->adapter);
400
401
402
403
404
405 if (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG) & DAVINCI_I2C_STR_BB)
406 return -EIO;
407
408 return 0;
409}
410
411
412
413
414
415static int
416i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
417{
418 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
419 struct davinci_i2c_platform_data *pdata = dev->pdata;
420 u32 flag;
421 u16 w;
422 unsigned long time_left;
423
424 if (msg->addr == DAVINCI_I2C_OWN_ADDRESS) {
425 dev_warn(dev->dev, "transfer to own address aborted\n");
426 return -EADDRNOTAVAIL;
427 }
428
429
430 if (pdata->bus_delay)
431 udelay(pdata->bus_delay);
432
433
434 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
435
436 dev->buf = msg->buf;
437 dev->buf_len = msg->len;
438 dev->stop = stop;
439
440 davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
441
442 reinit_completion(&dev->cmd_complete);
443 dev->cmd_err = 0;
444
445
446 flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
447
448
449 if (msg->flags & I2C_M_TEN)
450 flag |= DAVINCI_I2C_MDR_XA;
451 if (!(msg->flags & I2C_M_RD))
452 flag |= DAVINCI_I2C_MDR_TRX;
453 if (msg->len == 0)
454 flag |= DAVINCI_I2C_MDR_RM;
455
456
457 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
458 if (msg->flags & I2C_M_RD)
459 w |= DAVINCI_I2C_IMR_RRDY;
460 else
461 w |= DAVINCI_I2C_IMR_XRDY;
462 davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
463
464 dev->terminate = 0;
465
466
467
468
469
470
471 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
472
473
474
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476
477
478
479
480 if ((!(msg->flags & I2C_M_RD)) && dev->buf_len) {
481 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
482 dev->buf_len--;
483 }
484
485
486 flag |= DAVINCI_I2C_MDR_STT;
487 if (stop && msg->len != 0)
488 flag |= DAVINCI_I2C_MDR_STP;
489 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
490
491 time_left = wait_for_completion_timeout(&dev->cmd_complete,
492 dev->adapter.timeout);
493 if (!time_left) {
494 dev_err(dev->dev, "controller timed out\n");
495 i2c_recover_bus(adap);
496 dev->buf_len = 0;
497 return -ETIMEDOUT;
498 }
499 if (dev->buf_len) {
500
501
502
503 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
504 dev->buf_len);
505 dev->terminate = 1;
506 wmb();
507 dev->buf_len = 0;
508 return -EREMOTEIO;
509 }
510
511
512 if (likely(!dev->cmd_err))
513 return msg->len;
514
515
516 if (dev->cmd_err & DAVINCI_I2C_STR_AL) {
517 i2c_davinci_init(dev);
518 return -EIO;
519 }
520
521 if (dev->cmd_err & DAVINCI_I2C_STR_NACK) {
522 if (msg->flags & I2C_M_IGNORE_NAK)
523 return msg->len;
524 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
525 w |= DAVINCI_I2C_MDR_STP;
526 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
527 return -EREMOTEIO;
528 }
529 return -EIO;
530}
531
532
533
534
535static int
536i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
537{
538 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap);
539 int i;
540 int ret;
541
542 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
543
544 ret = i2c_davinci_wait_bus_not_busy(dev);
545 if (ret < 0) {
546 dev_warn(dev->dev, "timeout waiting for bus ready\n");
547 return ret;
548 }
549
550 for (i = 0; i < num; i++) {
551 ret = i2c_davinci_xfer_msg(adap, &msgs[i], (i == (num - 1)));
552 dev_dbg(dev->dev, "%s [%d/%d] ret: %d\n", __func__, i + 1, num,
553 ret);
554 if (ret < 0)
555 return ret;
556 }
557
558#ifdef CONFIG_CPU_FREQ
559 complete(&dev->xfr_complete);
560#endif
561
562 return num;
563}
564
565static u32 i2c_davinci_func(struct i2c_adapter *adap)
566{
567 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
568}
569
570static void terminate_read(struct davinci_i2c_dev *dev)
571{
572 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
573 w |= DAVINCI_I2C_MDR_NACK;
574 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
575
576
577 davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
578 if (!dev->terminate)
579 dev_err(dev->dev, "RDR IRQ while no data requested\n");
580}
581static void terminate_write(struct davinci_i2c_dev *dev)
582{
583 u16 w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
584 w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
585 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
586
587 if (!dev->terminate)
588 dev_dbg(dev->dev, "TDR IRQ while no data to send\n");
589}
590
591
592
593
594
595static irqreturn_t i2c_davinci_isr(int this_irq, void *dev_id)
596{
597 struct davinci_i2c_dev *dev = dev_id;
598 u32 stat;
599 int count = 0;
600 u16 w;
601
602 while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
603 dev_dbg(dev->dev, "%s: stat=0x%x\n", __func__, stat);
604 if (count++ == 100) {
605 dev_warn(dev->dev, "Too much work in one IRQ\n");
606 break;
607 }
608
609 switch (stat) {
610 case DAVINCI_I2C_IVR_AL:
611
612 dev->cmd_err |= DAVINCI_I2C_STR_AL;
613 dev->buf_len = 0;
614 complete(&dev->cmd_complete);
615 break;
616
617 case DAVINCI_I2C_IVR_NACK:
618 dev->cmd_err |= DAVINCI_I2C_STR_NACK;
619 dev->buf_len = 0;
620 complete(&dev->cmd_complete);
621 break;
622
623 case DAVINCI_I2C_IVR_ARDY:
624 davinci_i2c_write_reg(dev,
625 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
626 if (((dev->buf_len == 0) && (dev->stop != 0)) ||
627 (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
628 w = davinci_i2c_read_reg(dev,
629 DAVINCI_I2C_MDR_REG);
630 w |= DAVINCI_I2C_MDR_STP;
631 davinci_i2c_write_reg(dev,
632 DAVINCI_I2C_MDR_REG, w);
633 }
634 complete(&dev->cmd_complete);
635 break;
636
637 case DAVINCI_I2C_IVR_RDR:
638 if (dev->buf_len) {
639 *dev->buf++ =
640 davinci_i2c_read_reg(dev,
641 DAVINCI_I2C_DRR_REG);
642 dev->buf_len--;
643 if (dev->buf_len)
644 continue;
645
646 davinci_i2c_write_reg(dev,
647 DAVINCI_I2C_STR_REG,
648 DAVINCI_I2C_IMR_RRDY);
649 } else {
650
651 terminate_read(dev);
652 }
653 break;
654
655 case DAVINCI_I2C_IVR_XRDY:
656 if (dev->buf_len) {
657 davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
658 *dev->buf++);
659 dev->buf_len--;
660 if (dev->buf_len)
661 continue;
662
663 w = davinci_i2c_read_reg(dev,
664 DAVINCI_I2C_IMR_REG);
665 w &= ~DAVINCI_I2C_IMR_XRDY;
666 davinci_i2c_write_reg(dev,
667 DAVINCI_I2C_IMR_REG,
668 w);
669 } else {
670
671 terminate_write(dev);
672 }
673 break;
674
675 case DAVINCI_I2C_IVR_SCD:
676 davinci_i2c_write_reg(dev,
677 DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
678 complete(&dev->cmd_complete);
679 break;
680
681 case DAVINCI_I2C_IVR_AAS:
682 dev_dbg(dev->dev, "Address as slave interrupt\n");
683 break;
684
685 default:
686 dev_warn(dev->dev, "Unrecognized irq stat %d\n", stat);
687 break;
688 }
689 }
690
691 return count ? IRQ_HANDLED : IRQ_NONE;
692}
693
694#ifdef CONFIG_CPU_FREQ
695static int i2c_davinci_cpufreq_transition(struct notifier_block *nb,
696 unsigned long val, void *data)
697{
698 struct davinci_i2c_dev *dev;
699
700 dev = container_of(nb, struct davinci_i2c_dev, freq_transition);
701 if (val == CPUFREQ_PRECHANGE) {
702 wait_for_completion(&dev->xfr_complete);
703 davinci_i2c_reset_ctrl(dev, 0);
704 } else if (val == CPUFREQ_POSTCHANGE) {
705 i2c_davinci_calc_clk_dividers(dev);
706 davinci_i2c_reset_ctrl(dev, 1);
707 }
708
709 return 0;
710}
711
712static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
713{
714 dev->freq_transition.notifier_call = i2c_davinci_cpufreq_transition;
715
716 return cpufreq_register_notifier(&dev->freq_transition,
717 CPUFREQ_TRANSITION_NOTIFIER);
718}
719
720static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
721{
722 cpufreq_unregister_notifier(&dev->freq_transition,
723 CPUFREQ_TRANSITION_NOTIFIER);
724}
725#else
726static inline int i2c_davinci_cpufreq_register(struct davinci_i2c_dev *dev)
727{
728 return 0;
729}
730
731static inline void i2c_davinci_cpufreq_deregister(struct davinci_i2c_dev *dev)
732{
733}
734#endif
735
736static struct i2c_algorithm i2c_davinci_algo = {
737 .master_xfer = i2c_davinci_xfer,
738 .functionality = i2c_davinci_func,
739};
740
741static const struct of_device_id davinci_i2c_of_match[] = {
742 {.compatible = "ti,davinci-i2c", },
743 {.compatible = "ti,keystone-i2c", },
744 {},
745};
746MODULE_DEVICE_TABLE(of, davinci_i2c_of_match);
747
748static int davinci_i2c_probe(struct platform_device *pdev)
749{
750 struct davinci_i2c_dev *dev;
751 struct i2c_adapter *adap;
752 struct resource *mem;
753 int r, irq;
754
755 irq = platform_get_irq(pdev, 0);
756 if (irq <= 0) {
757 if (!irq)
758 irq = -ENXIO;
759 if (irq != -EPROBE_DEFER)
760 dev_err(&pdev->dev,
761 "can't get irq resource ret=%d\n", irq);
762 return irq;
763 }
764
765 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
766 GFP_KERNEL);
767 if (!dev) {
768 dev_err(&pdev->dev, "Memory allocation failed\n");
769 return -ENOMEM;
770 }
771
772 init_completion(&dev->cmd_complete);
773#ifdef CONFIG_CPU_FREQ
774 init_completion(&dev->xfr_complete);
775#endif
776 dev->dev = &pdev->dev;
777 dev->irq = irq;
778 dev->pdata = dev_get_platdata(&pdev->dev);
779 platform_set_drvdata(pdev, dev);
780
781 if (!dev->pdata && pdev->dev.of_node) {
782 u32 prop;
783
784 dev->pdata = devm_kzalloc(&pdev->dev,
785 sizeof(struct davinci_i2c_platform_data), GFP_KERNEL);
786 if (!dev->pdata)
787 return -ENOMEM;
788
789 memcpy(dev->pdata, &davinci_i2c_platform_data_default,
790 sizeof(struct davinci_i2c_platform_data));
791 if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
792 &prop))
793 dev->pdata->bus_freq = prop / 1000;
794
795 dev->pdata->has_pfunc =
796 of_property_read_bool(pdev->dev.of_node,
797 "ti,has-pfunc");
798 } else if (!dev->pdata) {
799 dev->pdata = &davinci_i2c_platform_data_default;
800 }
801
802 dev->clk = devm_clk_get(&pdev->dev, NULL);
803 if (IS_ERR(dev->clk))
804 return -ENODEV;
805 clk_prepare_enable(dev->clk);
806
807 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
808 dev->base = devm_ioremap_resource(&pdev->dev, mem);
809 if (IS_ERR(dev->base)) {
810 r = PTR_ERR(dev->base);
811 goto err_unuse_clocks;
812 }
813
814 i2c_davinci_init(dev);
815
816 r = devm_request_irq(&pdev->dev, dev->irq, i2c_davinci_isr, 0,
817 pdev->name, dev);
818 if (r) {
819 dev_err(&pdev->dev, "failure requesting irq %i\n", dev->irq);
820 goto err_unuse_clocks;
821 }
822
823 r = i2c_davinci_cpufreq_register(dev);
824 if (r) {
825 dev_err(&pdev->dev, "failed to register cpufreq\n");
826 goto err_unuse_clocks;
827 }
828
829 adap = &dev->adapter;
830 i2c_set_adapdata(adap, dev);
831 adap->owner = THIS_MODULE;
832 adap->class = I2C_CLASS_DEPRECATED;
833 strlcpy(adap->name, "DaVinci I2C adapter", sizeof(adap->name));
834 adap->algo = &i2c_davinci_algo;
835 adap->dev.parent = &pdev->dev;
836 adap->timeout = DAVINCI_I2C_TIMEOUT;
837 adap->dev.of_node = pdev->dev.of_node;
838
839 if (dev->pdata->has_pfunc)
840 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info;
841 else if (dev->pdata->scl_pin) {
842 adap->bus_recovery_info = &davinci_i2c_gpio_recovery_info;
843 adap->bus_recovery_info->scl_gpio = dev->pdata->scl_pin;
844 adap->bus_recovery_info->sda_gpio = dev->pdata->sda_pin;
845 }
846
847 adap->nr = pdev->id;
848 r = i2c_add_numbered_adapter(adap);
849 if (r) {
850 dev_err(&pdev->dev, "failure adding adapter\n");
851 goto err_unuse_clocks;
852 }
853
854 return 0;
855
856err_unuse_clocks:
857 clk_disable_unprepare(dev->clk);
858 dev->clk = NULL;
859 return r;
860}
861
862static int davinci_i2c_remove(struct platform_device *pdev)
863{
864 struct davinci_i2c_dev *dev = platform_get_drvdata(pdev);
865
866 i2c_davinci_cpufreq_deregister(dev);
867
868 i2c_del_adapter(&dev->adapter);
869
870 clk_disable_unprepare(dev->clk);
871 dev->clk = NULL;
872
873 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, 0);
874
875 return 0;
876}
877
878#ifdef CONFIG_PM
879static int davinci_i2c_suspend(struct device *dev)
880{
881 struct platform_device *pdev = to_platform_device(dev);
882 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
883
884
885 davinci_i2c_reset_ctrl(i2c_dev, 0);
886 clk_disable_unprepare(i2c_dev->clk);
887
888 return 0;
889}
890
891static int davinci_i2c_resume(struct device *dev)
892{
893 struct platform_device *pdev = to_platform_device(dev);
894 struct davinci_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
895
896 clk_prepare_enable(i2c_dev->clk);
897
898 davinci_i2c_reset_ctrl(i2c_dev, 1);
899
900 return 0;
901}
902
903static const struct dev_pm_ops davinci_i2c_pm = {
904 .suspend = davinci_i2c_suspend,
905 .resume = davinci_i2c_resume,
906};
907
908#define davinci_i2c_pm_ops (&davinci_i2c_pm)
909#else
910#define davinci_i2c_pm_ops NULL
911#endif
912
913
914MODULE_ALIAS("platform:i2c_davinci");
915
916static struct platform_driver davinci_i2c_driver = {
917 .probe = davinci_i2c_probe,
918 .remove = davinci_i2c_remove,
919 .driver = {
920 .name = "i2c_davinci",
921 .pm = davinci_i2c_pm_ops,
922 .of_match_table = davinci_i2c_of_match,
923 },
924};
925
926
927static int __init davinci_i2c_init_driver(void)
928{
929 return platform_driver_register(&davinci_i2c_driver);
930}
931subsys_initcall(davinci_i2c_init_driver);
932
933static void __exit davinci_i2c_exit_driver(void)
934{
935 platform_driver_unregister(&davinci_i2c_driver);
936}
937module_exit(davinci_i2c_exit_driver);
938
939MODULE_AUTHOR("Texas Instruments India");
940MODULE_DESCRIPTION("TI DaVinci I2C bus adapter");
941MODULE_LICENSE("GPL");
942