LXR linux/drivers/i2c/busses/i2c-sh

   1/*
   2 * SuperH Mobile I2C Controller
   3 *
   4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
   5 *
   6 * Copyright (C) 2008 Magnus Damm
   7 *
   8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
   9 * Copyright (c) 2006 Carlos Munoz <carlos@kenati.com>
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 */
  20
  21#include <linux/clk.h>
  22#include <linux/delay.h>
  23#include <linux/dmaengine.h>
  24#include <linux/dma-mapping.h>
  25#include <linux/err.h>
  26#include <linux/i2c.h>
  27#include <linux/i2c/i2c-sh_mobile.h>
  28#include <linux/init.h>
  29#include <linux/interrupt.h>
  30#include <linux/io.h>
  31#include <linux/kernel.h>
  32#include <linux/module.h>
  33#include <linux/of_device.h>
  34#include <linux/platform_device.h>
  35#include <linux/pm_runtime.h>
  36#include <linux/slab.h>
  37
  38/* Transmit operation:                                                      */
  39/*                                                                          */
  40/* 0 byte transmit                                                          */
  41/* BUS:     S     A8     ACK   P(*)                                         */
  42/* IRQ:       DTE   WAIT                                                    */
  43/* ICIC:                                                                    */
  44/* ICCR: 0x94 0x90                                                          */
  45/* ICDR:      A8                                                            */
  46/*                                                                          */
  47/* 1 byte transmit                                                          */
  48/* BUS:     S     A8     ACK   D8(1)   ACK   P(*)                           */
  49/* IRQ:       DTE   WAIT         WAIT                                       */
  50/* ICIC:      -DTE                                                          */
  51/* ICCR: 0x94       0x90                                                    */
  52/* ICDR:      A8    D8(1)                                                   */
  53/*                                                                          */
  54/* 2 byte transmit                                                          */
  55/* BUS:     S     A8     ACK   D8(1)   ACK   D8(2)   ACK   P(*)             */
  56/* IRQ:       DTE   WAIT         WAIT          WAIT                         */
  57/* ICIC:      -DTE                                                          */
  58/* ICCR: 0x94                    0x90                                       */
  59/* ICDR:      A8    D8(1)        D8(2)                                      */
  60/*                                                                          */
  61/* 3 bytes or more, +---------+ gets repeated                               */
  62/*                                                                          */
  63/*                                                                          */
  64/* Receive operation:                                                       */
  65/*                                                                          */
  66/* 0 byte receive - not supported since slave may hold SDA low              */
  67/*                                                                          */
  68/* 1 byte receive       [TX] | [RX]                                         */
  69/* BUS:     S     A8     ACK | D8(1)   ACK   P(*)                           */
  70/* IRQ:       DTE   WAIT     |   WAIT     DTE                               */
  71/* ICIC:      -DTE           |   +DTE                                       */
  72/* ICCR: 0x94       0x81     |   0xc0                                       */
  73/* ICDR:      A8             |            D8(1)                             */
  74/*                                                                          */
  75/* 2 byte receive        [TX]| [RX]                                         */
  76/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   P(*)             */
  77/* IRQ:       DTE   WAIT     |   WAIT          WAIT     DTE                 */
  78/* ICIC:      -DTE           |                 +DTE                         */
  79/* ICCR: 0x94       0x81     |                 0xc0                         */
  80/* ICDR:      A8             |                 D8(1)    D8(2)               */
  81/*                                                                          */
  82/* 3 byte receive       [TX] | [RX]                                     (*) */
  83/* BUS:     S     A8     ACK | D8(1)   ACK   D8(2)   ACK   D8(3)   ACK    P */
  84/* IRQ:       DTE   WAIT     |   WAIT          WAIT         WAIT      DTE   */
  85/* ICIC:      -DTE           |                              +DTE            */
  86/* ICCR: 0x94       0x81     |                              0xc0            */
  87/* ICDR:      A8             |                 D8(1)        D8(2)     D8(3) */
  88/*                                                                          */
  89/* 4 bytes or more, this part is repeated    +---------+                    */
  90/*                                                                          */
  91/*                                                                          */
  92/* Interrupt order and BUSY flag                                            */
  93/*     ___                                                 _                */
  94/* SDA ___\___XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXAAAAAAAAA___/                 */
  95/* SCL      \_/1\_/2\_/3\_/4\_/5\_/6\_/7\_/8\___/9\_____/                   */
  96/*                                                                          */
  97/*        S   D7  D6  D5  D4  D3  D2  D1  D0              P(*)              */
  98/*                                           ___                            */
  99/* WAIT IRQ ________________________________/   \___________                */
 100/* TACK IRQ ____________________________________/   \_______                */
 101/* DTE  IRQ __________________________________________/   \_                */
 102/* AL   IRQ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX                */
 103/*         _______________________________________________                  */
 104/* BUSY __/                                               \_                */
 105/*                                                                          */
 106/* (*) The STOP condition is only sent by the master at the end of the last */
 107/* I2C message or if the I2C_M_STOP flag is set. Similarly, the BUSY bit is */
 108/* only cleared after the STOP condition, so, between messages we have to   */
 109/* poll for the DTE bit.                                                    */
 110/*                                                                          */
 111
 112enum sh_mobile_i2c_op {
 113        OP_START = 0,
 114        OP_TX_FIRST,
 115        OP_TX,
 116        OP_TX_STOP,
 117        OP_TX_STOP_DATA,
 118        OP_TX_TO_RX,
 119        OP_RX,
 120        OP_RX_STOP,
 121        OP_RX_STOP_DATA,
 122};
 123
 124struct sh_mobile_i2c_data {
 125        struct device *dev;
 126        void __iomem *reg;
 127        struct i2c_adapter adap;
 128        unsigned long bus_speed;
 129        unsigned int clks_per_count;
 130        struct clk *clk;
 131        u_int8_t icic;
 132        u_int8_t flags;
 133        u_int16_t iccl;
 134        u_int16_t icch;
 135
 136        spinlock_t lock;
 137        wait_queue_head_t wait;
 138        struct i2c_msg *msg;
 139        int pos;
 140        int sr;
 141        bool send_stop;
 142        bool stop_after_dma;
 143
 144        struct resource *res;
 145        struct dma_chan *dma_tx;
 146        struct dma_chan *dma_rx;
 147        struct scatterlist sg;
 148        enum dma_data_direction dma_direction;
 149};
 150
 151struct sh_mobile_dt_config {
 152        int clks_per_count;
 153        void (*setup)(struct sh_mobile_i2c_data *pd);
 154};
 155
 156#define IIC_FLAG_HAS_ICIC67     (1 << 0)
 157
 158#define STANDARD_MODE           100000
 159#define FAST_MODE               400000
 160
 161/* Register offsets */
 162#define ICDR                    0x00
 163#define ICCR                    0x04
 164#define ICSR                    0x08
 165#define ICIC                    0x0c
 166#define ICCL                    0x10
 167#define ICCH                    0x14
 168#define ICSTART                 0x70
 169
 170/* Register bits */
 171#define ICCR_ICE                0x80
 172#define ICCR_RACK               0x40
 173#define ICCR_TRS                0x10
 174#define ICCR_BBSY               0x04
 175#define ICCR_SCP                0x01
 176
 177#define ICSR_SCLM               0x80
 178#define ICSR_SDAM               0x40
 179#define SW_DONE                 0x20
 180#define ICSR_BUSY               0x10
 181#define ICSR_AL                 0x08
 182#define ICSR_TACK               0x04
 183#define ICSR_WAIT               0x02
 184#define ICSR_DTE                0x01
 185
 186#define ICIC_ICCLB8             0x80
 187#define ICIC_ICCHB8             0x40
 188#define ICIC_TDMAE              0x20
 189#define ICIC_RDMAE              0x10
 190#define ICIC_ALE                0x08
 191#define ICIC_TACKE              0x04
 192#define ICIC_WAITE              0x02
 193#define ICIC_DTEE               0x01
 194
 195#define ICSTART_ICSTART         0x10
 196
 197static void iic_wr(struct sh_mobile_i2c_data *pd, int offs, unsigned char data)
 198{
 199        if (offs == ICIC)
 200                data |= pd->icic;
 201
 202        iowrite8(data, pd->reg + offs);
 203}
 204
 205static unsigned char iic_rd(struct sh_mobile_i2c_data *pd, int offs)
 206{
 207        return ioread8(pd->reg + offs);
 208}
 209
 210static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
 211                        unsigned char set, unsigned char clr)
 212{
 213        iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
 214}
 215
 216static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf)
 217{
 218        /*
 219         * Conditional expression:
 220         *   ICCL >= COUNT_CLK * (tLOW + tf)
 221         *
 222         * SH-Mobile IIC hardware starts counting the LOW period of
 223         * the SCL signal (tLOW) as soon as it pulls the SCL line.
 224         * In order to meet the tLOW timing spec, we need to take into
 225         * account the fall time of SCL signal (tf).  Default tf value
 226         * should be 0.3 us, for safety.
 227         */
 228        return (((count_khz * (tLOW + tf)) + 5000) / 10000);
 229}
 230
 231static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf)
 232{
 233        /*
 234         * Conditional expression:
 235         *   ICCH >= COUNT_CLK * (tHIGH + tf)
 236         *
 237         * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
 238         * and can ignore it.  SH-Mobile IIC controller starts counting
 239         * the HIGH period of the SCL signal (tHIGH) after the SCL input
 240         * voltage increases at VIH.
 241         *
 242         * Afterward it turned out calculating ICCH using only tHIGH spec
 243         * will result in violation of the tHD;STA timing spec.  We need
 244         * to take into account the fall time of SDA signal (tf) at START
 245         * condition, in order to meet both tHIGH and tHD;STA specs.
 246         */
 247        return (((count_khz * (tHIGH + tf)) + 5000) / 10000);
 248}
 249
 250static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
 251{
 252        unsigned long i2c_clk_khz;
 253        u32 tHIGH, tLOW, tf;
 254        uint16_t max_val;
 255
 256        /* Get clock rate after clock is enabled */
 257        clk_prepare_enable(pd->clk);
 258        i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
 259        clk_disable_unprepare(pd->clk);
 260        i2c_clk_khz /= pd->clks_per_count;
 261
 262        if (pd->bus_speed == STANDARD_MODE) {
 263                tLOW    = 47;   /* tLOW = 4.7 us */
 264                tHIGH   = 40;   /* tHD;STA = tHIGH = 4.0 us */
 265                tf      = 3;    /* tf = 0.3 us */
 266        } else if (pd->bus_speed == FAST_MODE) {
 267                tLOW    = 13;   /* tLOW = 1.3 us */
 268                tHIGH   = 6;    /* tHD;STA = tHIGH = 0.6 us */
 269                tf      = 3;    /* tf = 0.3 us */
 270        } else {
 271                dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
 272                        pd->bus_speed);
 273                return -EINVAL;
 274        }
 275
 276        pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf);
 277        pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf);
 278
 279        max_val = pd->flags & IIC_FLAG_HAS_ICIC67 ? 0x1ff : 0xff;
 280        if (pd->iccl > max_val || pd->icch > max_val) {
 281                dev_err(pd->dev, "timing values out of range: L/H=0x%x/0x%x\n",
 282                        pd->iccl, pd->icch);
 283                return -EINVAL;
 284        }
 285
 286        /* one more bit of ICCL in ICIC */
 287        if (pd->iccl & 0x100)
 288                pd->icic |= ICIC_ICCLB8;
 289        else
 290                pd->icic &= ~ICIC_ICCLB8;
 291
 292        /* one more bit of ICCH in ICIC */
 293        if (pd->icch & 0x100)
 294                pd->icic |= ICIC_ICCHB8;
 295        else
 296                pd->icic &= ~ICIC_ICCHB8;
 297
 298        dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
 299        return 0;
 300}
 301
 302static void activate_ch(struct sh_mobile_i2c_data *pd)
 303{
 304        /* Wake up device and enable clock */
 305        pm_runtime_get_sync(pd->dev);
 306        clk_prepare_enable(pd->clk);
 307
 308        /* Enable channel and configure rx ack */
 309        iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 310
 311        /* Mask all interrupts */
 312        iic_wr(pd, ICIC, 0);
 313
 314        /* Set the clock */
 315        iic_wr(pd, ICCL, pd->iccl & 0xff);
 316        iic_wr(pd, ICCH, pd->icch & 0xff);
 317}
 318
 319static void deactivate_ch(struct sh_mobile_i2c_data *pd)
 320{
 321        /* Clear/disable interrupts */
 322        iic_wr(pd, ICSR, 0);
 323        iic_wr(pd, ICIC, 0);
 324
 325        /* Disable channel */
 326        iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 327
 328        /* Disable clock and mark device as idle */
 329        clk_disable_unprepare(pd->clk);
 330        pm_runtime_put_sync(pd->dev);
 331}
 332
 333static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
 334                            enum sh_mobile_i2c_op op, unsigned char data)
 335{
 336        unsigned char ret = 0;
 337        unsigned long flags;
 338
 339        dev_dbg(pd->dev, "op %d, data in 0x%02x\n", op, data);
 340
 341        spin_lock_irqsave(&pd->lock, flags);
 342
 343        switch (op) {
 344        case OP_START: /* issue start and trigger DTE interrupt */
 345                iic_wr(pd, ICCR, ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 346                break;
 347        case OP_TX_FIRST: /* disable DTE interrupt and write data */
 348                iic_wr(pd, ICIC, ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 349                iic_wr(pd, ICDR, data);
 350                break;
 351        case OP_TX: /* write data */
 352                iic_wr(pd, ICDR, data);
 353                break;
 354        case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
 355                iic_wr(pd, ICDR, data);
 356                /* fallthrough */
 357        case OP_TX_STOP: /* issue a stop */
 358                iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
 359                                               : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
 360                break;
 361        case OP_TX_TO_RX: /* select read mode */
 362                iic_wr(pd, ICCR, ICCR_ICE | ICCR_SCP);
 363                break;
 364        case OP_RX: /* just read data */
 365                ret = iic_rd(pd, ICDR);
 366                break;
 367        case OP_RX_STOP: /* enable DTE interrupt, issue stop */
 368                iic_wr(pd, ICIC,
 369                       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 370                iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 371                break;
 372        case OP_RX_STOP_DATA: /* enable DTE interrupt, read data, issue stop */
 373                iic_wr(pd, ICIC,
 374                       ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 375                ret = iic_rd(pd, ICDR);
 376                iic_wr(pd, ICCR, ICCR_ICE | ICCR_RACK);
 377                break;
 378        }
 379
 380        spin_unlock_irqrestore(&pd->lock, flags);
 381
 382        dev_dbg(pd->dev, "op %d, data out 0x%02x\n", op, ret);
 383        return ret;
 384}
 385
 386static bool sh_mobile_i2c_is_first_byte(struct sh_mobile_i2c_data *pd)
 387{
 388        return pd->pos == -1;
 389}
 390
 391static bool sh_mobile_i2c_is_last_byte(struct sh_mobile_i2c_data *pd)
 392{
 393        return pd->pos == pd->msg->len - 1;
 394}
 395
 396static void sh_mobile_i2c_get_data(struct sh_mobile_i2c_data *pd,
 397                                   unsigned char *buf)
 398{
 399        switch (pd->pos) {
 400        case -1:
 401                *buf = (pd->msg->addr & 0x7f) << 1;
 402                *buf |= (pd->msg->flags & I2C_M_RD) ? 1 : 0;
 403                break;
 404        default:
 405                *buf = pd->msg->buf[pd->pos];
 406        }
 407}
 408
 409static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
 410{
 411        unsigned char data;
 412
 413        if (pd->pos == pd->msg->len) {
 414                /* Send stop if we haven't yet (DMA case) */
 415                if (pd->send_stop && pd->stop_after_dma)
 416                        i2c_op(pd, OP_TX_STOP, 0);
 417                return 1;
 418        }
 419
 420        sh_mobile_i2c_get_data(pd, &data);
 421
 422        if (sh_mobile_i2c_is_last_byte(pd))
 423                i2c_op(pd, OP_TX_STOP_DATA, data);
 424        else if (sh_mobile_i2c_is_first_byte(pd))
 425                i2c_op(pd, OP_TX_FIRST, data);
 426        else
 427                i2c_op(pd, OP_TX, data);
 428
 429        pd->pos++;
 430        return 0;
 431}
 432
 433static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
 434{
 435        unsigned char data;
 436        int real_pos;
 437
 438        do {
 439                if (pd->pos <= -1) {
 440                        sh_mobile_i2c_get_data(pd, &data);
 441
 442                        if (sh_mobile_i2c_is_first_byte(pd))
 443                                i2c_op(pd, OP_TX_FIRST, data);
 444                        else
 445                                i2c_op(pd, OP_TX, data);
 446                        break;
 447                }
 448
 449                if (pd->pos == 0) {
 450                        i2c_op(pd, OP_TX_TO_RX, 0);
 451                        break;
 452                }
 453
 454                real_pos = pd->pos - 2;
 455
 456                if (pd->pos == pd->msg->len) {
 457                        if (pd->stop_after_dma) {
 458                                /* Simulate PIO end condition after DMA transfer */
 459                                i2c_op(pd, OP_RX_STOP, 0);
 460                                pd->pos++;
 461                                break;
 462                        }
 463
 464                        if (real_pos < 0) {
 465                                i2c_op(pd, OP_RX_STOP, 0);
 466                                break;
 467                        }
 468                        data = i2c_op(pd, OP_RX_STOP_DATA, 0);
 469                } else
 470                        data = i2c_op(pd, OP_RX, 0);
 471
 472                if (real_pos >= 0)
 473                        pd->msg->buf[real_pos] = data;
 474        } while (0);
 475
 476        pd->pos++;
 477        return pd->pos == (pd->msg->len + 2);
 478}
 479
 480static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
 481{
 482        struct sh_mobile_i2c_data *pd = dev_id;
 483        unsigned char sr;
 484        int wakeup = 0;
 485
 486        sr = iic_rd(pd, ICSR);
 487        pd->sr |= sr; /* remember state */
 488
 489        dev_dbg(pd->dev, "i2c_isr 0x%02x 0x%02x %s %d %d!\n", sr, pd->sr,
 490               (pd->msg->flags & I2C_M_RD) ? "read" : "write",
 491               pd->pos, pd->msg->len);
 492
 493        /* Kick off TxDMA after preface was done */
 494        if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
 495                iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
 496        else if (sr & (ICSR_AL | ICSR_TACK))
 497                /* don't interrupt transaction - continue to issue stop */
 498                iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
 499        else if (pd->msg->flags & I2C_M_RD)
 500                wakeup = sh_mobile_i2c_isr_rx(pd);
 501        else
 502                wakeup = sh_mobile_i2c_isr_tx(pd);
 503
 504        /* Kick off RxDMA after preface was done */
 505        if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
 506                iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
 507
 508        if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
 509                iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
 510
 511        if (wakeup) {
 512                pd->sr |= SW_DONE;
 513                wake_up(&pd->wait);
 514        }
 515
 516        /* defeat write posting to avoid spurious WAIT interrupts */
 517        iic_rd(pd, ICSR);
 518
 519        return IRQ_HANDLED;
 520}
 521
 522static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
 523{
 524        struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
 525                                ? pd->dma_rx : pd->dma_tx;
 526
 527        dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
 528                         pd->msg->len, pd->dma_direction);
 529
 530        pd->dma_direction = DMA_NONE;
 531}
 532
 533static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
 534{
 535        if (pd->dma_direction == DMA_NONE)
 536                return;
 537        else if (pd->dma_direction == DMA_FROM_DEVICE)
 538                dmaengine_terminate_all(pd->dma_rx);
 539        else if (pd->dma_direction == DMA_TO_DEVICE)
 540                dmaengine_terminate_all(pd->dma_tx);
 541
 542        sh_mobile_i2c_dma_unmap(pd);
 543}
 544
 545static void sh_mobile_i2c_dma_callback(void *data)
 546{
 547        struct sh_mobile_i2c_data *pd = data;
 548
 549        sh_mobile_i2c_dma_unmap(pd);
 550        pd->pos = pd->msg->len;
 551        pd->stop_after_dma = true;
 552
 553        iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
 554}
 555
 556static struct dma_chan *sh_mobile_i2c_request_dma_chan(struct device *dev,
 557                                enum dma_transfer_direction dir, dma_addr_t port_addr)
 558{
 559        struct dma_chan *chan;
 560        struct dma_slave_config cfg;
 561        char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
 562        int ret;
 563
 564        chan = dma_request_slave_channel_reason(dev, chan_name);
 565        if (IS_ERR(chan)) {
 566                ret = PTR_ERR(chan);
 567                dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
 568                return chan;
 569        }
 570
 571        memset(&cfg, 0, sizeof(cfg));
 572        cfg.direction = dir;
 573        if (dir == DMA_MEM_TO_DEV) {
 574                cfg.dst_addr = port_addr;
 575                cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 576        } else {
 577                cfg.src_addr = port_addr;
 578                cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 579        }
 580
 581        ret = dmaengine_slave_config(chan, &cfg);
 582        if (ret) {
 583                dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
 584                dma_release_channel(chan);
 585                return ERR_PTR(ret);
 586        }
 587
 588        dev_dbg(dev, "got DMA channel for %s\n", chan_name);
 589        return chan;
 590}
 591
 592static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
 593{
 594        bool read = pd->msg->flags & I2C_M_RD;
 595        enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
 596        struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
 597        struct dma_async_tx_descriptor *txdesc;
 598        dma_addr_t dma_addr;
 599        dma_cookie_t cookie;
 600
 601        if (PTR_ERR(chan) == -EPROBE_DEFER) {
 602                if (read)
 603                        chan = pd->dma_rx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
 604                                                                           pd->res->start + ICDR);
 605                else
 606                        chan = pd->dma_tx = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
 607                                                                           pd->res->start + ICDR);
 608        }
 609
 610        if (IS_ERR(chan))
 611                return;
 612
 613        dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
 614        if (dma_mapping_error(pd->dev, dma_addr)) {
 615                dev_dbg(pd->dev, "dma map failed, using PIO\n");
 616                return;
 617        }
 618
 619        sg_dma_len(&pd->sg) = pd->msg->len;
 620        sg_dma_address(&pd->sg) = dma_addr;
 621
 622        pd->dma_direction = dir;
 623
 624        txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
 625                                         read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
 626                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 627        if (!txdesc) {
 628                dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
 629                sh_mobile_i2c_cleanup_dma(pd);
 630                return;
 631        }
 632
 633        txdesc->callback = sh_mobile_i2c_dma_callback;
 634        txdesc->callback_param = pd;
 635
 636        cookie = dmaengine_submit(txdesc);
 637        if (dma_submit_error(cookie)) {
 638                dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
 639                sh_mobile_i2c_cleanup_dma(pd);
 640                return;
 641        }
 642
 643        dma_async_issue_pending(chan);
 644}
 645
 646static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
 647                    bool do_init)
 648{
 649        if (usr_msg->len == 0 && (usr_msg->flags & I2C_M_RD)) {
 650                dev_err(pd->dev, "Unsupported zero length i2c read\n");
 651                return -EOPNOTSUPP;
 652        }
 653
 654        if (do_init) {
 655                /* Initialize channel registers */
 656                iic_set_clr(pd, ICCR, 0, ICCR_ICE);
 657
 658                /* Enable channel and configure rx ack */
 659                iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 660
 661                /* Set the clock */
 662                iic_wr(pd, ICCL, pd->iccl & 0xff);
 663                iic_wr(pd, ICCH, pd->icch & 0xff);
 664        }
 665
 666        pd->msg = usr_msg;
 667        pd->pos = -1;
 668        pd->sr = 0;
 669
 670        if (pd->msg->len > 8)
 671                sh_mobile_i2c_xfer_dma(pd);
 672
 673        /* Enable all interrupts to begin with */
 674        iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
 675        return 0;
 676}
 677
 678static int poll_dte(struct sh_mobile_i2c_data *pd)
 679{
 680        int i;
 681
 682        for (i = 1000; i; i--) {
 683                u_int8_t val = iic_rd(pd, ICSR);
 684
 685                if (val & ICSR_DTE)
 686                        break;
 687
 688                if (val & ICSR_TACK)
 689                        return -ENXIO;
 690
 691                udelay(10);
 692        }
 693
 694        return i ? 0 : -ETIMEDOUT;
 695}
 696
 697static int poll_busy(struct sh_mobile_i2c_data *pd)
 698{
 699        int i;
 700
 701        for (i = 1000; i; i--) {
 702                u_int8_t val = iic_rd(pd, ICSR);
 703
 704                dev_dbg(pd->dev, "val 0x%02x pd->sr 0x%02x\n", val, pd->sr);
 705
 706                /* the interrupt handler may wake us up before the
 707                 * transfer is finished, so poll the hardware
 708                 * until we're done.
 709                 */
 710                if (!(val & ICSR_BUSY)) {
 711                        /* handle missing acknowledge and arbitration lost */
 712                        val |= pd->sr;
 713                        if (val & ICSR_TACK)
 714                                return -ENXIO;
 715                        if (val & ICSR_AL)
 716                                return -EAGAIN;
 717                        break;
 718                }
 719
 720                udelay(10);
 721        }
 722
 723        return i ? 0 : -ETIMEDOUT;
 724}
 725
 726static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
 727                              struct i2c_msg *msgs,
 728                              int num)
 729{
 730        struct sh_mobile_i2c_data *pd = i2c_get_adapdata(adapter);
 731        struct i2c_msg  *msg;
 732        int err = 0;
 733        int i;
 734        long timeout;
 735
 736        activate_ch(pd);
 737
 738        /* Process all messages */
 739        for (i = 0; i < num; i++) {
 740                bool do_start = pd->send_stop || !i;
 741                msg = &msgs[i];
 742                pd->send_stop = i == num - 1 || msg->flags & I2C_M_STOP;
 743                pd->stop_after_dma = false;
 744
 745                err = start_ch(pd, msg, do_start);
 746                if (err)
 747                        break;
 748
 749                if (do_start)
 750                        i2c_op(pd, OP_START, 0);
 751
 752                /* The interrupt handler takes care of the rest... */
 753                timeout = wait_event_timeout(pd->wait,
 754                                       pd->sr & (ICSR_TACK | SW_DONE),
 755                                       adapter->timeout);
 756                if (!timeout) {
 757                        dev_err(pd->dev, "Transfer request timed out\n");
 758                        if (pd->dma_direction != DMA_NONE)
 759                                sh_mobile_i2c_cleanup_dma(pd);
 760
 761                        err = -ETIMEDOUT;
 762                        break;
 763                }
 764
 765                if (pd->send_stop)
 766                        err = poll_busy(pd);
 767                else
 768                        err = poll_dte(pd);
 769                if (err < 0)
 770                        break;
 771        }
 772
 773        deactivate_ch(pd);
 774
 775        if (!err)
 776                err = num;
 777        return err;
 778}
 779
 780static u32 sh_mobile_i2c_func(struct i2c_adapter *adapter)
 781{
 782        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
 783}
 784
 785static struct i2c_algorithm sh_mobile_i2c_algorithm = {
 786        .functionality  = sh_mobile_i2c_func,
 787        .master_xfer    = sh_mobile_i2c_xfer,
 788};
 789
 790/*
 791 * r8a7740 chip has lasting errata on I2C I/O pad reset.
 792 * this is work-around for it.
 793 */
 794static void sh_mobile_i2c_r8a7740_workaround(struct sh_mobile_i2c_data *pd)
 795{
 796        iic_set_clr(pd, ICCR, ICCR_ICE, 0);
 797        iic_rd(pd, ICCR); /* dummy read */
 798
 799        iic_set_clr(pd, ICSTART, ICSTART_ICSTART, 0);
 800        iic_rd(pd, ICSTART); /* dummy read */
 801
 802        udelay(10);
 803
 804        iic_wr(pd, ICCR, ICCR_SCP);
 805        iic_wr(pd, ICSTART, 0);
 806
 807        udelay(10);
 808
 809        iic_wr(pd, ICCR, ICCR_TRS);
 810        udelay(10);
 811        iic_wr(pd, ICCR, 0);
 812        udelay(10);
 813        iic_wr(pd, ICCR, ICCR_TRS);
 814        udelay(10);
 815}
 816
 817static const struct sh_mobile_dt_config default_dt_config = {
 818        .clks_per_count = 1,
 819};
 820
 821static const struct sh_mobile_dt_config fast_clock_dt_config = {
 822        .clks_per_count = 2,
 823};
 824
 825static const struct sh_mobile_dt_config r8a7740_dt_config = {
 826        .clks_per_count = 1,
 827        .setup = sh_mobile_i2c_r8a7740_workaround,
 828};
 829
 830static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
 831        { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
 832        { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
 833        { .compatible = "renesas,iic-r8a7740", .data = &r8a7740_dt_config },
 834        { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
 835        { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
 836        { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
 837        { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
 838        { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
 839        { .compatible = "renesas,iic-r8a7795", .data = &fast_clock_dt_config },
 840        { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
 841        {},
 842};
 843MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
 844
 845static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
 846{
 847        if (!IS_ERR(pd->dma_tx)) {
 848                dma_release_channel(pd->dma_tx);
 849                pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 850        }
 851
 852        if (!IS_ERR(pd->dma_rx)) {
 853                dma_release_channel(pd->dma_rx);
 854                pd->dma_rx = ERR_PTR(-EPROBE_DEFER);
 855        }
 856}
 857
 858static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
 859{
 860        struct resource *res;
 861        resource_size_t n;
 862        int k = 0, ret;
 863
 864        while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
 865                for (n = res->start; n <= res->end; n++) {
 866                        ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
 867                                          0, dev_name(&dev->dev), pd);
 868                        if (ret) {
 869                                dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
 870                                return ret;
 871                        }
 872                }
 873                k++;
 874        }
 875
 876        return k > 0 ? 0 : -ENOENT;
 877}
 878
 879static int sh_mobile_i2c_probe(struct platform_device *dev)
 880{
 881        struct i2c_sh_mobile_platform_data *pdata = dev_get_platdata(&dev->dev);
 882        struct sh_mobile_i2c_data *pd;
 883        struct i2c_adapter *adap;
 884        struct resource *res;
 885        int ret;
 886        u32 bus_speed;
 887
 888        pd = devm_kzalloc(&dev->dev, sizeof(struct sh_mobile_i2c_data), GFP_KERNEL);
 889        if (!pd)
 890                return -ENOMEM;
 891
 892        pd->clk = devm_clk_get(&dev->dev, NULL);
 893        if (IS_ERR(pd->clk)) {
 894                dev_err(&dev->dev, "cannot get clock\n");
 895                return PTR_ERR(pd->clk);
 896        }
 897
 898        ret = sh_mobile_i2c_hook_irqs(dev, pd);
 899        if (ret)
 900                return ret;
 901
 902        pd->dev = &dev->dev;
 903        platform_set_drvdata(dev, pd);
 904
 905        res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 906
 907        pd->res = res;
 908        pd->reg = devm_ioremap_resource(&dev->dev, res);
 909        if (IS_ERR(pd->reg))
 910                return PTR_ERR(pd->reg);
 911
 912        /* Use platform data bus speed or STANDARD_MODE */
 913        ret = of_property_read_u32(dev->dev.of_node, "clock-frequency", &bus_speed);
 914        pd->bus_speed = ret ? STANDARD_MODE : bus_speed;
 915
 916        pd->clks_per_count = 1;
 917
 918        if (dev->dev.of_node) {
 919                const struct of_device_id *match;
 920
 921                match = of_match_device(sh_mobile_i2c_dt_ids, &dev->dev);
 922                if (match) {
 923                        const struct sh_mobile_dt_config *config;
 924
 925                        config = match->data;
 926                        pd->clks_per_count = config->clks_per_count;
 927
 928                        if (config->setup)
 929                                config->setup(pd);
 930                }
 931        } else {
 932                if (pdata && pdata->bus_speed)
 933                        pd->bus_speed = pdata->bus_speed;
 934                if (pdata && pdata->clks_per_count)
 935                        pd->clks_per_count = pdata->clks_per_count;
 936        }
 937
 938        /* The IIC blocks on SH-Mobile ARM processors
 939         * come with two new bits in ICIC.
 940         */
 941        if (resource_size(res) > 0x17)
 942                pd->flags |= IIC_FLAG_HAS_ICIC67;
 943
 944        ret = sh_mobile_i2c_init(pd);
 945        if (ret)
 946                return ret;
 947
 948        /* Init DMA */
 949        sg_init_table(&pd->sg, 1);
 950        pd->dma_direction = DMA_NONE;
 951        pd->dma_rx = pd->dma_tx = ERR_PTR(-EPROBE_DEFER);
 952
 953        /* Enable Runtime PM for this device.
 954         *
 955         * Also tell the Runtime PM core to ignore children
 956         * for this device since it is valid for us to suspend
 957         * this I2C master driver even though the slave devices
 958         * on the I2C bus may not be suspended.
 959         *
 960         * The state of the I2C hardware bus is unaffected by
 961         * the Runtime PM state.
 962         */
 963        pm_suspend_ignore_children(&dev->dev, true);
 964        pm_runtime_enable(&dev->dev);
 965
 966        /* setup the private data */
 967        adap = &pd->adap;
 968        i2c_set_adapdata(adap, pd);
 969
 970        adap->owner = THIS_MODULE;
 971        adap->algo = &sh_mobile_i2c_algorithm;
 972        adap->dev.parent = &dev->dev;
 973        adap->retries = 5;
 974        adap->nr = dev->id;
 975        adap->dev.of_node = dev->dev.of_node;
 976
 977        strlcpy(adap->name, dev->name, sizeof(adap->name));
 978
 979        spin_lock_init(&pd->lock);
 980        init_waitqueue_head(&pd->wait);
 981
 982        ret = i2c_add_numbered_adapter(adap);
 983        if (ret < 0) {
 984                sh_mobile_i2c_release_dma(pd);
 985                dev_err(&dev->dev, "cannot add numbered adapter\n");
 986                return ret;
 987        }
 988
 989        dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz\n", adap->nr, pd->bus_speed);
 990
 991        return 0;
 992}
 993
 994static int sh_mobile_i2c_remove(struct platform_device *dev)
 995{
 996        struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
 997
 998        i2c_del_adapter(&pd->adap);
 999        sh_mobile_i2c_release_dma(pd);
1000        pm_runtime_disable(&dev->dev);

1001        return 0;
1002}
1003
1004static int sh_mobile_i2c_runtime_nop(struct device *dev)
1005{
1006        /* Runtime PM callback shared between ->runtime_suspend()
1007         * and ->runtime_resume(). Simply returns success.
1008         *
1009         * This driver re-initializes all registers after
1010         * pm_runtime_get_sync() anyway so there is no need
1011         * to save and restore registers here.
1012         */
1013        return 0;
1014}
1015
1016static const struct dev_pm_ops sh_mobile_i2c_dev_pm_ops = {
1017        .runtime_suspend = sh_mobile_i2c_runtime_nop,
1018        .runtime_resume = sh_mobile_i2c_runtime_nop,
1019};
1020
1021static struct platform_driver sh_mobile_i2c_driver = {
1022        .driver         = {
1023                .name           = "i2c-sh_mobile",
1024                .pm             = &sh_mobile_i2c_dev_pm_ops,
1025                .of_match_table = sh_mobile_i2c_dt_ids,
1026        },
1027        .probe          = sh_mobile_i2c_probe,
1028        .remove         = sh_mobile_i2c_remove,
1029};
1030
1031static int __init sh_mobile_i2c_adap_init(void)
1032{
1033        return platform_driver_register(&sh_mobile_i2c_driver);
1034}
1035subsys_initcall(sh_mobile_i2c_adap_init);
1036
1037static void __exit sh_mobile_i2c_adap_exit(void)
1038{
1039        platform_driver_unregister(&sh_mobile_i2c_driver);
1040}
1041module_exit(sh_mobile_i2c_adap_exit);
1042
1043MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
1044MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
1045MODULE_LICENSE("GPL v2");
1046MODULE_ALIAS("platform:i2c-sh_mobile");
1047