linux/drivers/input/serio/at32psif.c
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   1/*
   2 * Copyright (C) 2007 Atmel Corporation
   3 *
   4 * Driver for the AT32AP700X PS/2 controller (PSIF).
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of the GNU General Public License version 2 as published
   8 * by the Free Software Foundation.
   9 */
  10#include <linux/kernel.h>
  11#include <linux/module.h>
  12#include <linux/device.h>
  13#include <linux/init.h>
  14#include <linux/serio.h>
  15#include <linux/interrupt.h>
  16#include <linux/delay.h>
  17#include <linux/err.h>
  18#include <linux/io.h>
  19#include <linux/clk.h>
  20#include <linux/platform_device.h>
  21#include <linux/slab.h>
  22
  23/* PSIF register offsets */
  24#define PSIF_CR                         0x00
  25#define PSIF_RHR                        0x04
  26#define PSIF_THR                        0x08
  27#define PSIF_SR                         0x10
  28#define PSIF_IER                        0x14
  29#define PSIF_IDR                        0x18
  30#define PSIF_IMR                        0x1c
  31#define PSIF_PSR                        0x24
  32
  33/* Bitfields in control register. */
  34#define PSIF_CR_RXDIS_OFFSET            1
  35#define PSIF_CR_RXDIS_SIZE              1
  36#define PSIF_CR_RXEN_OFFSET             0
  37#define PSIF_CR_RXEN_SIZE               1
  38#define PSIF_CR_SWRST_OFFSET            15
  39#define PSIF_CR_SWRST_SIZE              1
  40#define PSIF_CR_TXDIS_OFFSET            9
  41#define PSIF_CR_TXDIS_SIZE              1
  42#define PSIF_CR_TXEN_OFFSET             8
  43#define PSIF_CR_TXEN_SIZE               1
  44
  45/* Bitfields in interrupt disable, enable, mask and status register. */
  46#define PSIF_NACK_OFFSET                8
  47#define PSIF_NACK_SIZE                  1
  48#define PSIF_OVRUN_OFFSET               5
  49#define PSIF_OVRUN_SIZE                 1
  50#define PSIF_PARITY_OFFSET              9
  51#define PSIF_PARITY_SIZE                1
  52#define PSIF_RXRDY_OFFSET               4
  53#define PSIF_RXRDY_SIZE                 1
  54#define PSIF_TXEMPTY_OFFSET             1
  55#define PSIF_TXEMPTY_SIZE               1
  56#define PSIF_TXRDY_OFFSET               0
  57#define PSIF_TXRDY_SIZE                 1
  58
  59/* Bitfields in prescale register. */
  60#define PSIF_PSR_PRSCV_OFFSET           0
  61#define PSIF_PSR_PRSCV_SIZE             12
  62
  63/* Bitfields in receive hold register. */
  64#define PSIF_RHR_RXDATA_OFFSET          0
  65#define PSIF_RHR_RXDATA_SIZE            8
  66
  67/* Bitfields in transmit hold register. */
  68#define PSIF_THR_TXDATA_OFFSET          0
  69#define PSIF_THR_TXDATA_SIZE            8
  70
  71/* Bit manipulation macros */
  72#define PSIF_BIT(name)                                  \
  73        (1 << PSIF_##name##_OFFSET)
  74
  75#define PSIF_BF(name, value)                            \
  76        (((value) & ((1 << PSIF_##name##_SIZE) - 1))    \
  77         << PSIF_##name##_OFFSET)
  78
  79#define PSIF_BFEXT(name, value)                         \
  80        (((value) >> PSIF_##name##_OFFSET)              \
  81         & ((1 << PSIF_##name##_SIZE) - 1))
  82
  83#define PSIF_BFINS(name, value, old)                    \
  84        (((old) & ~(((1 << PSIF_##name##_SIZE) - 1)     \
  85                    << PSIF_##name##_OFFSET))           \
  86         | PSIF_BF(name, value))
  87
  88/* Register access macros */
  89#define psif_readl(port, reg)                           \
  90        __raw_readl((port)->regs + PSIF_##reg)
  91
  92#define psif_writel(port, reg, value)                   \
  93        __raw_writel((value), (port)->regs + PSIF_##reg)
  94
  95struct psif {
  96        struct platform_device  *pdev;
  97        struct clk              *pclk;
  98        struct serio            *io;
  99        void __iomem            *regs;
 100        unsigned int            irq;
 101        /* Prevent concurrent writes to PSIF THR. */
 102        spinlock_t              lock;
 103        bool                    open;
 104};
 105
 106static irqreturn_t psif_interrupt(int irq, void *_ptr)
 107{
 108        struct psif *psif = _ptr;
 109        int retval = IRQ_NONE;
 110        unsigned int io_flags = 0;
 111        unsigned long status;
 112
 113        status = psif_readl(psif, SR);
 114
 115        if (status & PSIF_BIT(RXRDY)) {
 116                unsigned char val = (unsigned char) psif_readl(psif, RHR);
 117
 118                if (status & PSIF_BIT(PARITY))
 119                        io_flags |= SERIO_PARITY;
 120                if (status & PSIF_BIT(OVRUN))
 121                        dev_err(&psif->pdev->dev, "overrun read error\n");
 122
 123                serio_interrupt(psif->io, val, io_flags);
 124
 125                retval = IRQ_HANDLED;
 126        }
 127
 128        return retval;
 129}
 130
 131static int psif_write(struct serio *io, unsigned char val)
 132{
 133        struct psif *psif = io->port_data;
 134        unsigned long flags;
 135        int timeout = 10;
 136        int retval = 0;
 137
 138        spin_lock_irqsave(&psif->lock, flags);
 139
 140        while (!(psif_readl(psif, SR) & PSIF_BIT(TXEMPTY)) && timeout--)
 141                udelay(50);
 142
 143        if (timeout >= 0) {
 144                psif_writel(psif, THR, val);
 145        } else {
 146                dev_dbg(&psif->pdev->dev, "timeout writing to THR\n");
 147                retval = -EBUSY;
 148        }
 149
 150        spin_unlock_irqrestore(&psif->lock, flags);
 151
 152        return retval;
 153}
 154
 155static int psif_open(struct serio *io)
 156{
 157        struct psif *psif = io->port_data;
 158        int retval;
 159
 160        retval = clk_enable(psif->pclk);
 161        if (retval)
 162                goto out;
 163
 164        psif_writel(psif, CR, PSIF_BIT(CR_TXEN) | PSIF_BIT(CR_RXEN));
 165        psif_writel(psif, IER, PSIF_BIT(RXRDY));
 166
 167        psif->open = true;
 168out:
 169        return retval;
 170}
 171
 172static void psif_close(struct serio *io)
 173{
 174        struct psif *psif = io->port_data;
 175
 176        psif->open = false;
 177
 178        psif_writel(psif, IDR, ~0UL);
 179        psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
 180
 181        clk_disable(psif->pclk);
 182}
 183
 184static void psif_set_prescaler(struct psif *psif)
 185{
 186        unsigned long prscv;
 187        unsigned long rate = clk_get_rate(psif->pclk);
 188
 189        /* PRSCV = Pulse length (100 us) * PSIF module frequency. */
 190        prscv = 100 * (rate / 1000000UL);
 191
 192        if (prscv > ((1<<PSIF_PSR_PRSCV_SIZE) - 1)) {
 193                prscv = (1<<PSIF_PSR_PRSCV_SIZE) - 1;
 194                dev_dbg(&psif->pdev->dev, "pclk too fast, "
 195                                "prescaler set to max\n");
 196        }
 197
 198        clk_enable(psif->pclk);
 199        psif_writel(psif, PSR, prscv);
 200        clk_disable(psif->pclk);
 201}
 202
 203static int __init psif_probe(struct platform_device *pdev)
 204{
 205        struct resource *regs;
 206        struct psif *psif;
 207        struct serio *io;
 208        struct clk *pclk;
 209        int irq;
 210        int ret;
 211
 212        psif = kzalloc(sizeof(struct psif), GFP_KERNEL);
 213        if (!psif) {
 214                dev_dbg(&pdev->dev, "out of memory\n");
 215                ret = -ENOMEM;
 216                goto out;
 217        }
 218        psif->pdev = pdev;
 219
 220        io = kzalloc(sizeof(struct serio), GFP_KERNEL);
 221        if (!io) {
 222                dev_dbg(&pdev->dev, "out of memory\n");
 223                ret = -ENOMEM;
 224                goto out_free_psif;
 225        }
 226        psif->io = io;
 227
 228        regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 229        if (!regs) {
 230                dev_dbg(&pdev->dev, "no mmio resources defined\n");
 231                ret = -ENOMEM;
 232                goto out_free_io;
 233        }
 234
 235        psif->regs = ioremap(regs->start, resource_size(regs));
 236        if (!psif->regs) {
 237                ret = -ENOMEM;
 238                dev_dbg(&pdev->dev, "could not map I/O memory\n");
 239                goto out_free_io;
 240        }
 241
 242        pclk = clk_get(&pdev->dev, "pclk");
 243        if (IS_ERR(pclk)) {
 244                dev_dbg(&pdev->dev, "could not get peripheral clock\n");
 245                ret = PTR_ERR(pclk);
 246                goto out_iounmap;
 247        }
 248        psif->pclk = pclk;
 249
 250        /* Reset the PSIF to enter at a known state. */
 251        ret = clk_enable(pclk);
 252        if (ret) {
 253                dev_dbg(&pdev->dev, "could not enable pclk\n");
 254                goto out_put_clk;
 255        }
 256        psif_writel(psif, CR, PSIF_BIT(CR_SWRST));
 257        clk_disable(pclk);
 258
 259        irq = platform_get_irq(pdev, 0);
 260        if (irq < 0) {
 261                dev_dbg(&pdev->dev, "could not get irq\n");
 262                ret = -ENXIO;
 263                goto out_put_clk;
 264        }
 265        ret = request_irq(irq, psif_interrupt, IRQF_SHARED, "at32psif", psif);
 266        if (ret) {
 267                dev_dbg(&pdev->dev, "could not request irq %d\n", irq);
 268                goto out_put_clk;
 269        }
 270        psif->irq = irq;
 271
 272        io->id.type     = SERIO_8042;
 273        io->write       = psif_write;
 274        io->open        = psif_open;
 275        io->close       = psif_close;
 276        snprintf(io->name, sizeof(io->name), "AVR32 PS/2 port%d", pdev->id);
 277        snprintf(io->phys, sizeof(io->phys), "at32psif/serio%d", pdev->id);
 278        io->port_data   = psif;
 279        io->dev.parent  = &pdev->dev;
 280
 281        psif_set_prescaler(psif);
 282
 283        spin_lock_init(&psif->lock);
 284        serio_register_port(psif->io);
 285        platform_set_drvdata(pdev, psif);
 286
 287        dev_info(&pdev->dev, "Atmel AVR32 PSIF PS/2 driver on 0x%08x irq %d\n",
 288                        (int)psif->regs, psif->irq);
 289
 290        return 0;
 291
 292out_put_clk:
 293        clk_put(psif->pclk);
 294out_iounmap:
 295        iounmap(psif->regs);
 296out_free_io:
 297        kfree(io);
 298out_free_psif:
 299        kfree(psif);
 300out:
 301        return ret;
 302}
 303
 304static int __exit psif_remove(struct platform_device *pdev)
 305{
 306        struct psif *psif = platform_get_drvdata(pdev);
 307
 308        psif_writel(psif, IDR, ~0UL);
 309        psif_writel(psif, CR, PSIF_BIT(CR_TXDIS) | PSIF_BIT(CR_RXDIS));
 310
 311        serio_unregister_port(psif->io);
 312        iounmap(psif->regs);
 313        free_irq(psif->irq, psif);
 314        clk_put(psif->pclk);
 315        kfree(psif);
 316
 317        return 0;
 318}
 319
 320#ifdef CONFIG_PM_SLEEP
 321static int psif_suspend(struct device *dev)
 322{
 323        struct platform_device *pdev = to_platform_device(dev);
 324        struct psif *psif = platform_get_drvdata(pdev);
 325
 326        if (psif->open) {
 327                psif_writel(psif, CR, PSIF_BIT(CR_RXDIS) | PSIF_BIT(CR_TXDIS));
 328                clk_disable(psif->pclk);
 329        }
 330
 331        return 0;
 332}
 333
 334static int psif_resume(struct device *dev)
 335{
 336        struct platform_device *pdev = to_platform_device(dev);
 337        struct psif *psif = platform_get_drvdata(pdev);
 338
 339        if (psif->open) {
 340                clk_enable(psif->pclk);
 341                psif_set_prescaler(psif);
 342                psif_writel(psif, CR, PSIF_BIT(CR_RXEN) | PSIF_BIT(CR_TXEN));
 343        }
 344
 345        return 0;
 346}
 347#endif
 348
 349static SIMPLE_DEV_PM_OPS(psif_pm_ops, psif_suspend, psif_resume);
 350
 351static struct platform_driver psif_driver = {
 352        .remove         = __exit_p(psif_remove),
 353        .driver         = {
 354                .name   = "atmel_psif",
 355                .pm     = &psif_pm_ops,
 356        },
 357};
 358
 359module_platform_driver_probe(psif_driver, psif_probe);
 360
 361MODULE_AUTHOR("Hans-Christian Egtvedt <egtvedt@samfundet.no>");
 362MODULE_DESCRIPTION("Atmel AVR32 PSIF PS/2 driver");
 363MODULE_LICENSE("GPL");
 364