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22#include <linux/slab.h>
23#include <linux/module.h>
24#include <linux/dvb/frontend.h>
25#include <linux/types.h>
26#include "ascot2e.h"
27#include "dvb_frontend.h"
28
29#define MAX_WRITE_REGSIZE 10
30
31enum ascot2e_state {
32 STATE_UNKNOWN,
33 STATE_SLEEP,
34 STATE_ACTIVE
35};
36
37struct ascot2e_priv {
38 u32 frequency;
39 u8 i2c_address;
40 struct i2c_adapter *i2c;
41 enum ascot2e_state state;
42 void *set_tuner_data;
43 int (*set_tuner)(void *, int);
44};
45
46enum ascot2e_tv_system_t {
47 ASCOT2E_DTV_DVBT_5,
48 ASCOT2E_DTV_DVBT_6,
49 ASCOT2E_DTV_DVBT_7,
50 ASCOT2E_DTV_DVBT_8,
51 ASCOT2E_DTV_DVBT2_1_7,
52 ASCOT2E_DTV_DVBT2_5,
53 ASCOT2E_DTV_DVBT2_6,
54 ASCOT2E_DTV_DVBT2_7,
55 ASCOT2E_DTV_DVBT2_8,
56 ASCOT2E_DTV_DVBC_6,
57 ASCOT2E_DTV_DVBC_8,
58 ASCOT2E_DTV_DVBC2_6,
59 ASCOT2E_DTV_DVBC2_8,
60 ASCOT2E_DTV_UNKNOWN
61};
62
63struct ascot2e_band_sett {
64 u8 if_out_sel;
65 u8 agc_sel;
66 u8 mix_oll;
67 u8 rf_gain;
68 u8 if_bpf_gc;
69 u8 fif_offset;
70 u8 bw_offset;
71 u8 bw;
72 u8 rf_oldet;
73 u8 if_bpf_f0;
74};
75
76#define ASCOT2E_AUTO 0xff
77#define ASCOT2E_OFFSET(ofs) ((u8)(ofs) & 0x1F)
78#define ASCOT2E_BW_6 0x00
79#define ASCOT2E_BW_7 0x01
80#define ASCOT2E_BW_8 0x02
81#define ASCOT2E_BW_1_7 0x03
82
83static struct ascot2e_band_sett ascot2e_sett[] = {
84 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
85 ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 },
86 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
87 ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 },
88 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
89 ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7, 0x0B, 0x00 },
90 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
91 ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8, 0x0B, 0x00 },
92 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
93 ASCOT2E_OFFSET(-10), ASCOT2E_OFFSET(-16), ASCOT2E_BW_1_7, 0x0B, 0x00 },
94 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
95 ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 },
96 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
97 ASCOT2E_OFFSET(-8), ASCOT2E_OFFSET(-6), ASCOT2E_BW_6, 0x0B, 0x00 },
98 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
99 ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_7, 0x0B, 0x00 },
100 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x06,
101 ASCOT2E_OFFSET(-4), ASCOT2E_OFFSET(-2), ASCOT2E_BW_8, 0x0B, 0x00 },
102 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03,
103 ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-8), ASCOT2E_BW_6, 0x09, 0x00 },
104 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x02, ASCOT2E_AUTO, 0x03,
105 ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(-1), ASCOT2E_BW_8, 0x09, 0x00 },
106 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01,
107 ASCOT2E_OFFSET(-6), ASCOT2E_OFFSET(-4), ASCOT2E_BW_6, 0x09, 0x00 },
108 { ASCOT2E_AUTO, ASCOT2E_AUTO, 0x03, ASCOT2E_AUTO, 0x01,
109 ASCOT2E_OFFSET(-2), ASCOT2E_OFFSET(2), ASCOT2E_BW_8, 0x09, 0x00 }
110};
111
112static void ascot2e_i2c_debug(struct ascot2e_priv *priv,
113 u8 reg, u8 write, const u8 *data, u32 len)
114{
115 dev_dbg(&priv->i2c->dev, "ascot2e: I2C %s reg 0x%02x size %d\n",
116 (write == 0 ? "read" : "write"), reg, len);
117 print_hex_dump_bytes("ascot2e: I2C data: ",
118 DUMP_PREFIX_OFFSET, data, len);
119}
120
121static int ascot2e_write_regs(struct ascot2e_priv *priv,
122 u8 reg, const u8 *data, u32 len)
123{
124 int ret;
125 u8 buf[MAX_WRITE_REGSIZE + 1];
126 struct i2c_msg msg[1] = {
127 {
128 .addr = priv->i2c_address,
129 .flags = 0,
130 .len = len + 1,
131 .buf = buf,
132 }
133 };
134
135 if (len + 1 >= sizeof(buf)) {
136 dev_warn(&priv->i2c->dev,"wr reg=%04x: len=%d is too big!\n",
137 reg, len + 1);
138 return -E2BIG;
139 }
140
141 ascot2e_i2c_debug(priv, reg, 1, data, len);
142 buf[0] = reg;
143 memcpy(&buf[1], data, len);
144 ret = i2c_transfer(priv->i2c, msg, 1);
145 if (ret >= 0 && ret != 1)
146 ret = -EREMOTEIO;
147 if (ret < 0) {
148 dev_warn(&priv->i2c->dev,
149 "%s: i2c wr failed=%d reg=%02x len=%d\n",
150 KBUILD_MODNAME, ret, reg, len);
151 return ret;
152 }
153 return 0;
154}
155
156static int ascot2e_write_reg(struct ascot2e_priv *priv, u8 reg, u8 val)
157{
158 return ascot2e_write_regs(priv, reg, &val, 1);
159}
160
161static int ascot2e_read_regs(struct ascot2e_priv *priv,
162 u8 reg, u8 *val, u32 len)
163{
164 int ret;
165 struct i2c_msg msg[2] = {
166 {
167 .addr = priv->i2c_address,
168 .flags = 0,
169 .len = 1,
170 .buf = ®,
171 }, {
172 .addr = priv->i2c_address,
173 .flags = I2C_M_RD,
174 .len = len,
175 .buf = val,
176 }
177 };
178
179 ret = i2c_transfer(priv->i2c, &msg[0], 1);
180 if (ret >= 0 && ret != 1)
181 ret = -EREMOTEIO;
182 if (ret < 0) {
183 dev_warn(&priv->i2c->dev,
184 "%s: I2C rw failed=%d addr=%02x reg=%02x\n",
185 KBUILD_MODNAME, ret, priv->i2c_address, reg);
186 return ret;
187 }
188 ret = i2c_transfer(priv->i2c, &msg[1], 1);
189 if (ret >= 0 && ret != 1)
190 ret = -EREMOTEIO;
191 if (ret < 0) {
192 dev_warn(&priv->i2c->dev,
193 "%s: i2c rd failed=%d addr=%02x reg=%02x\n",
194 KBUILD_MODNAME, ret, priv->i2c_address, reg);
195 return ret;
196 }
197 ascot2e_i2c_debug(priv, reg, 0, val, len);
198 return 0;
199}
200
201static int ascot2e_read_reg(struct ascot2e_priv *priv, u8 reg, u8 *val)
202{
203 return ascot2e_read_regs(priv, reg, val, 1);
204}
205
206static int ascot2e_set_reg_bits(struct ascot2e_priv *priv,
207 u8 reg, u8 data, u8 mask)
208{
209 int res;
210 u8 rdata;
211
212 if (mask != 0xff) {
213 res = ascot2e_read_reg(priv, reg, &rdata);
214 if (res != 0)
215 return res;
216 data = ((data & mask) | (rdata & (mask ^ 0xFF)));
217 }
218 return ascot2e_write_reg(priv, reg, data);
219}
220
221static int ascot2e_enter_power_save(struct ascot2e_priv *priv)
222{
223 u8 data[2];
224
225 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
226 if (priv->state == STATE_SLEEP)
227 return 0;
228 data[0] = 0x00;
229 data[1] = 0x04;
230 ascot2e_write_regs(priv, 0x14, data, 2);
231 ascot2e_write_reg(priv, 0x50, 0x01);
232 priv->state = STATE_SLEEP;
233 return 0;
234}
235
236static int ascot2e_leave_power_save(struct ascot2e_priv *priv)
237{
238 u8 data[2] = { 0xFB, 0x0F };
239
240 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
241 if (priv->state == STATE_ACTIVE)
242 return 0;
243 ascot2e_write_regs(priv, 0x14, data, 2);
244 ascot2e_write_reg(priv, 0x50, 0x00);
245 priv->state = STATE_ACTIVE;
246 return 0;
247}
248
249static int ascot2e_init(struct dvb_frontend *fe)
250{
251 struct ascot2e_priv *priv = fe->tuner_priv;
252
253 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
254 return ascot2e_leave_power_save(priv);
255}
256
257static int ascot2e_release(struct dvb_frontend *fe)
258{
259 struct ascot2e_priv *priv = fe->tuner_priv;
260
261 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
262 kfree(fe->tuner_priv);
263 fe->tuner_priv = NULL;
264 return 0;
265}
266
267static int ascot2e_sleep(struct dvb_frontend *fe)
268{
269 struct ascot2e_priv *priv = fe->tuner_priv;
270
271 dev_dbg(&priv->i2c->dev, "%s()\n", __func__);
272 ascot2e_enter_power_save(priv);
273 return 0;
274}
275
276static enum ascot2e_tv_system_t ascot2e_get_tv_system(struct dvb_frontend *fe)
277{
278 enum ascot2e_tv_system_t system = ASCOT2E_DTV_UNKNOWN;
279 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
280 struct ascot2e_priv *priv = fe->tuner_priv;
281
282 if (p->delivery_system == SYS_DVBT) {
283 if (p->bandwidth_hz <= 5000000)
284 system = ASCOT2E_DTV_DVBT_5;
285 else if (p->bandwidth_hz <= 6000000)
286 system = ASCOT2E_DTV_DVBT_6;
287 else if (p->bandwidth_hz <= 7000000)
288 system = ASCOT2E_DTV_DVBT_7;
289 else if (p->bandwidth_hz <= 8000000)
290 system = ASCOT2E_DTV_DVBT_8;
291 else {
292 system = ASCOT2E_DTV_DVBT_8;
293 p->bandwidth_hz = 8000000;
294 }
295 } else if (p->delivery_system == SYS_DVBT2) {
296 if (p->bandwidth_hz <= 5000000)
297 system = ASCOT2E_DTV_DVBT2_5;
298 else if (p->bandwidth_hz <= 6000000)
299 system = ASCOT2E_DTV_DVBT2_6;
300 else if (p->bandwidth_hz <= 7000000)
301 system = ASCOT2E_DTV_DVBT2_7;
302 else if (p->bandwidth_hz <= 8000000)
303 system = ASCOT2E_DTV_DVBT2_8;
304 else {
305 system = ASCOT2E_DTV_DVBT2_8;
306 p->bandwidth_hz = 8000000;
307 }
308 } else if (p->delivery_system == SYS_DVBC_ANNEX_A) {
309 if (p->bandwidth_hz <= 6000000)
310 system = ASCOT2E_DTV_DVBC_6;
311 else if (p->bandwidth_hz <= 8000000)
312 system = ASCOT2E_DTV_DVBC_8;
313 }
314 dev_dbg(&priv->i2c->dev,
315 "%s(): ASCOT2E DTV system %d (delsys %d, bandwidth %d)\n",
316 __func__, (int)system, p->delivery_system, p->bandwidth_hz);
317 return system;
318}
319
320static int ascot2e_set_params(struct dvb_frontend *fe)
321{
322 u8 data[10];
323 u32 frequency;
324 enum ascot2e_tv_system_t tv_system;
325 struct dtv_frontend_properties *p = &fe->dtv_property_cache;
326 struct ascot2e_priv *priv = fe->tuner_priv;
327
328 dev_dbg(&priv->i2c->dev, "%s(): tune frequency %dkHz\n",
329 __func__, p->frequency / 1000);
330 tv_system = ascot2e_get_tv_system(fe);
331
332 if (tv_system == ASCOT2E_DTV_UNKNOWN) {
333 dev_dbg(&priv->i2c->dev, "%s(): unknown DTV system\n",
334 __func__);
335 return -EINVAL;
336 }
337 if (priv->set_tuner)
338 priv->set_tuner(priv->set_tuner_data, 1);
339 frequency = roundup(p->frequency / 1000, 25);
340 if (priv->state == STATE_SLEEP)
341 ascot2e_leave_power_save(priv);
342
343
344 data[0] = 0x00;
345 if (ascot2e_sett[tv_system].agc_sel != ASCOT2E_AUTO) {
346
347 data[0] |= (u8)(
348 (ascot2e_sett[tv_system].agc_sel & 0x03) << 3);
349 }
350 if (ascot2e_sett[tv_system].if_out_sel != ASCOT2E_AUTO) {
351
352 data[0] |= (u8)(
353 (ascot2e_sett[tv_system].if_out_sel & 0x01) << 2);
354 }
355
356 ascot2e_set_reg_bits(priv, 0x05, data[0], 0x1c);
357
358
359 if (tv_system == ASCOT2E_DTV_DVBC_6 ||
360 tv_system == ASCOT2E_DTV_DVBC_8) {
361
362 data[0] = (frequency > 500000) ? 16 : 32;
363 } else {
364
365 data[0] = (frequency > 500000) ? 2 : 4;
366 }
367
368 data[1] = 0x04;
369
370 if (tv_system == ASCOT2E_DTV_DVBC_6 ||
371 tv_system == ASCOT2E_DTV_DVBC_8) {
372 data[2] = 18;
373 data[3] = 120;
374 data[4] = 20;
375 } else {
376 data[2] = 48;
377 data[3] = 10;
378 data[4] = 30;
379 }
380
381 if (tv_system == ASCOT2E_DTV_DVBC_6 ||
382 tv_system == ASCOT2E_DTV_DVBC_8)
383 data[5] = (frequency > 500000) ? 0x08 : 0x0c;
384 else
385 data[5] = (frequency > 500000) ? 0x30 : 0x38;
386
387 data[6] = ascot2e_sett[tv_system].mix_oll;
388
389 if (ascot2e_sett[tv_system].rf_gain == ASCOT2E_AUTO) {
390
391 ascot2e_write_reg(priv, 0x4E, 0x01);
392
393 data[7] = 0x00;
394 } else {
395
396 ascot2e_write_reg(priv, 0x4E, 0x00);
397 data[7] = ascot2e_sett[tv_system].rf_gain;
398 }
399
400 data[8] = (u8)((ascot2e_sett[tv_system].fif_offset << 3) |
401 (ascot2e_sett[tv_system].if_bpf_gc & 0x07));
402
403 data[9] = ascot2e_sett[tv_system].bw_offset;
404 ascot2e_write_regs(priv, 0x06, data, 10);
405
406
407
408
409
410 if (tv_system == ASCOT2E_DTV_DVBC_6 ||
411 tv_system == ASCOT2E_DTV_DVBC_8) {
412 data[0] = 0x0F;
413 data[1] = 0x00;
414 data[2] = 0x01;
415 } else {
416 data[0] = 0x0F;
417 data[1] = 0x00;
418 data[2] = 0x03;
419 }
420 ascot2e_write_regs(priv, 0x45, data, 3);
421
422
423 data[0] = ascot2e_sett[tv_system].rf_oldet;
424
425 data[1] = ascot2e_sett[tv_system].if_bpf_f0;
426 ascot2e_write_regs(priv, 0x49, data, 2);
427
428
429
430
431
432
433 ascot2e_set_reg_bits(priv, 0x0c, 0x90, 0xb0);
434
435 data[0] = 0xc4;
436 data[1] = 0x40;
437 ascot2e_write_regs(priv, 0x03, data, 2);
438
439 data[0] = (u8)(frequency & 0xFF);
440 data[1] = (u8)((frequency >> 8) & 0xFF);
441 data[2] = (u8)((frequency >> 16) & 0x0F);
442
443 data[2] |= (u8)(ascot2e_sett[tv_system].bw << 4);
444 data[3] = 0xFF;
445 data[4] = 0xFF;
446
447 ascot2e_write_regs(priv, 0x10, data, 5);
448 msleep(50);
449
450 ascot2e_write_reg(priv, 0x04, 0x00);
451
452 ascot2e_write_reg(priv, 0x03, 0xC0);
453
454 ascot2e_set_reg_bits(priv, 0x0C, 0x00, 0x30);
455 priv->frequency = frequency;
456 return 0;
457}
458
459static int ascot2e_get_frequency(struct dvb_frontend *fe, u32 *frequency)
460{
461 struct ascot2e_priv *priv = fe->tuner_priv;
462
463 *frequency = priv->frequency * 1000;
464 return 0;
465}
466
467static struct dvb_tuner_ops ascot2e_tuner_ops = {
468 .info = {
469 .name = "Sony ASCOT2E",
470 .frequency_min = 1000000,
471 .frequency_max = 1200000000,
472 .frequency_step = 25000,
473 },
474 .init = ascot2e_init,
475 .release = ascot2e_release,
476 .sleep = ascot2e_sleep,
477 .set_params = ascot2e_set_params,
478 .get_frequency = ascot2e_get_frequency,
479};
480
481struct dvb_frontend *ascot2e_attach(struct dvb_frontend *fe,
482 const struct ascot2e_config *config,
483 struct i2c_adapter *i2c)
484{
485 u8 data[4];
486 struct ascot2e_priv *priv = NULL;
487
488 priv = kzalloc(sizeof(struct ascot2e_priv), GFP_KERNEL);
489 if (priv == NULL)
490 return NULL;
491 priv->i2c_address = (config->i2c_address >> 1);
492 priv->i2c = i2c;
493 priv->set_tuner_data = config->set_tuner_priv;
494 priv->set_tuner = config->set_tuner_callback;
495
496 if (fe->ops.i2c_gate_ctrl)
497 fe->ops.i2c_gate_ctrl(fe, 1);
498
499
500 data[0] = 16;
501
502 data[1] = 0x06;
503
504 data[2] = 0xC4;
505 data[3] = 0x40;
506 ascot2e_write_regs(priv, 0x01, data, 4);
507
508 data[0] = 0x10;
509 data[1] = 0x3F;
510 data[2] = 0x25;
511 ascot2e_write_regs(priv, 0x22, data, 3);
512
513 ascot2e_write_reg(priv, 0x28, 0x1e);
514
515 ascot2e_write_reg(priv, 0x59, 0x04);
516
517 msleep(80);
518
519 ascot2e_write_reg(priv, 0x4c, 0x01);
520
521 ascot2e_write_reg(priv, 0x07, 0x04);
522
523 ascot2e_write_reg(priv, 0x04, 0x00);
524
525 ascot2e_write_reg(priv, 0x03, 0xc0);
526
527 data[0] = 0x00;
528 data[1] = 0x04;
529 ascot2e_write_regs(priv, 0x14, data, 2);
530 ascot2e_write_reg(priv, 0x50, 0x01);
531 priv->state = STATE_SLEEP;
532
533 if (fe->ops.i2c_gate_ctrl)
534 fe->ops.i2c_gate_ctrl(fe, 0);
535
536 memcpy(&fe->ops.tuner_ops, &ascot2e_tuner_ops,
537 sizeof(struct dvb_tuner_ops));
538 fe->tuner_priv = priv;
539 dev_info(&priv->i2c->dev,
540 "Sony ASCOT2E attached on addr=%x at I2C adapter %p\n",
541 priv->i2c_address, priv->i2c);
542 return fe;
543}
544EXPORT_SYMBOL(ascot2e_attach);
545
546MODULE_DESCRIPTION("Sony ASCOT2E terr/cab tuner driver");
547MODULE_AUTHOR("info@netup.ru");
548MODULE_LICENSE("GPL");
549
