1/* 2 * Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates. 3 * All rights reserved. 4 * 5 * This program is free software; you may redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; version 2 of the License. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 16 * SOFTWARE. 17 */ 18 19#ifndef M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H 20#define M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H 21 22/******************************************************************* 23 * Register Block 24 * M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_VHD_REGMAP 25 *******************************************************************/ 26struct m00233_video_measure_regmap { 27 uint32_t irq_status; /* Reg 0x0000 */ 28 /* The vertical counter starts on rising edge of vsync */ 29 uint32_t vsync_time; /* Reg 0x0004 */ 30 uint32_t vback_porch; /* Reg 0x0008 */ 31 uint32_t vactive_area; /* Reg 0x000c */ 32 uint32_t vfront_porch; /* Reg 0x0010 */ 33 /* The horizontal counter starts on rising edge of hsync. */ 34 uint32_t hsync_time; /* Reg 0x0014 */ 35 uint32_t hback_porch; /* Reg 0x0018 */ 36 uint32_t hactive_area; /* Reg 0x001c */ 37 uint32_t hfront_porch; /* Reg 0x0020 */ 38 uint32_t control; /* Reg 0x0024, Default=0x0 */ 39 uint32_t irq_triggers; /* Reg 0x0028, Default=0xff */ 40 /* Value is given in number of register bus clock periods between */ 41 /* falling and rising edge of hsync. Must be non-zero. */ 42 uint32_t hsync_timeout_val; /* Reg 0x002c, Default=0x1fff */ 43 uint32_t status; /* Reg 0x0030 */ 44}; 45 46#define M00233_VIDEO_MEASURE_REG_IRQ_STATUS_OFST 0 47#define M00233_VIDEO_MEASURE_REG_VSYNC_TIME_OFST 4 48#define M00233_VIDEO_MEASURE_REG_VBACK_PORCH_OFST 8 49#define M00233_VIDEO_MEASURE_REG_VACTIVE_AREA_OFST 12 50#define M00233_VIDEO_MEASURE_REG_VFRONT_PORCH_OFST 16 51#define M00233_VIDEO_MEASURE_REG_HSYNC_TIME_OFST 20 52#define M00233_VIDEO_MEASURE_REG_HBACK_PORCH_OFST 24 53#define M00233_VIDEO_MEASURE_REG_HACTIVE_AREA_OFST 28 54#define M00233_VIDEO_MEASURE_REG_HFRONT_PORCH_OFST 32 55#define M00233_VIDEO_MEASURE_REG_CONTROL_OFST 36 56#define M00233_VIDEO_MEASURE_REG_IRQ_TRIGGERS_OFST 40 57#define M00233_VIDEO_MEASURE_REG_HSYNC_TIMEOUT_VAL_OFST 44 58#define M00233_VIDEO_MEASURE_REG_STATUS_OFST 48 59 60/******************************************************************* 61 * Bit Mask for register 62 * M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_VHD_BITMAP 63 *******************************************************************/ 64/* irq_status [7:0] */ 65#define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST (0) 66#define M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VSYNC_TIME_OFST) 67#define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST (1) 68#define M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VBACK_PORCH_OFST) 69#define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST (2) 70#define M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VACTIVE_AREA_OFST) 71#define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST (3) 72#define M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_VFRONT_PORCH_OFST) 73#define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST (4) 74#define M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HSYNC_TIME_OFST) 75#define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST (5) 76#define M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HBACK_PORCH_OFST) 77#define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST (6) 78#define M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HACTIVE_AREA_OFST) 79#define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST (7) 80#define M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_MSK (0x1 << M00233_IRQ_STATUS_BITMAP_HFRONT_PORCH_OFST) 81/* control [4:0] */ 82#define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST (0) 83#define M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK (0x1 << M00233_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST) 84#define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST (1) 85#define M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK (0x1 << M00233_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST) 86#define M00233_CONTROL_BITMAP_ENABLE_MEASURE_OFST (2) 87#define M00233_CONTROL_BITMAP_ENABLE_MEASURE_MSK (0x1 << M00233_CONTROL_BITMAP_ENABLE_MEASURE_OFST) 88#define M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_OFST (3) 89#define M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_MSK (0x1 << M00233_CONTROL_BITMAP_ENABLE_INTERRUPT_OFST) 90#define M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_OFST (4) 91#define M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_MSK (0x1 << M00233_CONTROL_BITMAP_UPDATE_ON_HSYNC_OFST) 92/* irq_triggers [7:0] */ 93#define M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_OFST (0) 94#define M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VSYNC_TIME_OFST) 95#define M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_OFST (1) 96#define M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VBACK_PORCH_OFST) 97#define M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_OFST (2) 98#define M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VACTIVE_AREA_OFST) 99#define M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_OFST (3) 100#define M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_VFRONT_PORCH_OFST) 101#define M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_OFST (4) 102#define M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HSYNC_TIME_OFST) 103#define M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_OFST (5) 104#define M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HBACK_PORCH_OFST) 105#define M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_OFST (6) 106#define M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HACTIVE_AREA_OFST) 107#define M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_OFST (7) 108#define M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_MSK (0x1 << M00233_IRQ_TRIGGERS_BITMAP_HFRONT_PORCH_OFST) 109/* status [1:0] */ 110#define M00233_STATUS_BITMAP_HSYNC_TIMEOUT_OFST (0) 111#define M00233_STATUS_BITMAP_HSYNC_TIMEOUT_MSK (0x1 << M00233_STATUS_BITMAP_HSYNC_TIMEOUT_OFST) 112#define M00233_STATUS_BITMAP_INIT_DONE_OFST (1) 113#define M00233_STATUS_BITMAP_INIT_DONE_MSK (0x1 << M00233_STATUS_BITMAP_INIT_DONE_OFST) 114 115#endif /*M00233_VIDEO_MEASURE_MEMMAP_PACKAGE_H*/ 116