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16#ifndef S5P_MFC_COMMON_H_
17#define S5P_MFC_COMMON_H_
18
19#include <linux/platform_device.h>
20#include <linux/videodev2.h>
21#include <media/v4l2-ctrls.h>
22#include <media/v4l2-device.h>
23#include <media/v4l2-ioctl.h>
24#include <media/videobuf2-v4l2.h>
25#include "regs-mfc.h"
26#include "regs-mfc-v8.h"
27
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30
31
32#define DST_QUEUE_OFF_BASE (1 << 30)
33
34#define MFC_BANK1_ALLOC_CTX 0
35#define MFC_BANK2_ALLOC_CTX 1
36
37#define MFC_BANK1_ALIGN_ORDER 13
38#define MFC_BANK2_ALIGN_ORDER 13
39#define MFC_BASE_ALIGN_ORDER 17
40
41#define MFC_FW_MAX_VERSIONS 2
42
43#include <media/videobuf2-dma-contig.h>
44
45static inline dma_addr_t s5p_mfc_mem_cookie(void *a, void *b)
46{
47
48 dma_addr_t *paddr = vb2_dma_contig_memops.cookie(b);
49
50 return *paddr;
51}
52
53
54#define MFC_MAX_EXTRA_DPB 5
55#define MFC_MAX_BUFFERS 32
56#define MFC_NUM_CONTEXTS 4
57
58#define MFC_INT_TIMEOUT 2000
59
60#define MFC_BW_TIMEOUT 500
61
62#define MFC_WATCHDOG_INTERVAL 1000
63
64#define MFC_WATCHDOG_CNT 10
65#define MFC_NO_INSTANCE_SET -1
66#define MFC_ENC_CAP_PLANE_COUNT 1
67#define MFC_ENC_OUT_PLANE_COUNT 2
68#define STUFF_BYTE 4
69#define MFC_MAX_CTRLS 77
70
71#define S5P_MFC_CODEC_NONE -1
72#define S5P_MFC_CODEC_H264_DEC 0
73#define S5P_MFC_CODEC_H264_MVC_DEC 1
74#define S5P_MFC_CODEC_VC1_DEC 2
75#define S5P_MFC_CODEC_MPEG4_DEC 3
76#define S5P_MFC_CODEC_MPEG2_DEC 4
77#define S5P_MFC_CODEC_H263_DEC 5
78#define S5P_MFC_CODEC_VC1RCV_DEC 6
79#define S5P_MFC_CODEC_VP8_DEC 7
80
81#define S5P_MFC_CODEC_H264_ENC 20
82#define S5P_MFC_CODEC_H264_MVC_ENC 21
83#define S5P_MFC_CODEC_MPEG4_ENC 22
84#define S5P_MFC_CODEC_H263_ENC 23
85#define S5P_MFC_CODEC_VP8_ENC 24
86
87#define S5P_MFC_R2H_CMD_EMPTY 0
88#define S5P_MFC_R2H_CMD_SYS_INIT_RET 1
89#define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET 2
90#define S5P_MFC_R2H_CMD_SEQ_DONE_RET 3
91#define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET 4
92#define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET 6
93#define S5P_MFC_R2H_CMD_SLEEP_RET 7
94#define S5P_MFC_R2H_CMD_WAKEUP_RET 8
95#define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET 9
96#define S5P_MFC_R2H_CMD_DPB_FLUSH_RET 10
97#define S5P_MFC_R2H_CMD_NAL_ABORT_RET 11
98#define S5P_MFC_R2H_CMD_FW_STATUS_RET 12
99#define S5P_MFC_R2H_CMD_FRAME_DONE_RET 13
100#define S5P_MFC_R2H_CMD_FIELD_DONE_RET 14
101#define S5P_MFC_R2H_CMD_SLICE_DONE_RET 15
102#define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET 16
103#define S5P_MFC_R2H_CMD_ERR_RET 32
104
105#define mfc_read(dev, offset) readl(dev->regs_base + (offset))
106#define mfc_write(dev, data, offset) writel((data), dev->regs_base + \
107 (offset))
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111
112enum s5p_mfc_fmt_type {
113 MFC_FMT_DEC,
114 MFC_FMT_ENC,
115 MFC_FMT_RAW,
116};
117
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119
120
121enum s5p_mfc_inst_type {
122 MFCINST_INVALID,
123 MFCINST_DECODER,
124 MFCINST_ENCODER,
125};
126
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128
129
130enum s5p_mfc_inst_state {
131 MFCINST_FREE = 0,
132 MFCINST_INIT = 100,
133 MFCINST_GOT_INST,
134 MFCINST_HEAD_PARSED,
135 MFCINST_HEAD_PRODUCED,
136 MFCINST_BUFS_SET,
137 MFCINST_RUNNING,
138 MFCINST_FINISHING,
139 MFCINST_FINISHED,
140 MFCINST_RETURN_INST,
141 MFCINST_ERROR,
142 MFCINST_ABORT,
143 MFCINST_FLUSH,
144 MFCINST_RES_CHANGE_INIT,
145 MFCINST_RES_CHANGE_FLUSH,
146 MFCINST_RES_CHANGE_END,
147};
148
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150
151
152enum s5p_mfc_queue_state {
153 QUEUE_FREE,
154 QUEUE_BUFS_REQUESTED,
155 QUEUE_BUFS_QUERIED,
156 QUEUE_BUFS_MMAPED,
157};
158
159
160
161
162enum s5p_mfc_decode_arg {
163 MFC_DEC_FRAME,
164 MFC_DEC_LAST_FRAME,
165 MFC_DEC_RES_CHANGE,
166};
167
168enum s5p_mfc_fw_ver {
169 MFC_FW_V1,
170 MFC_FW_V2,
171};
172
173#define MFC_BUF_FLAG_USED (1 << 0)
174#define MFC_BUF_FLAG_EOS (1 << 1)
175
176struct s5p_mfc_ctx;
177
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179
180
181struct s5p_mfc_buf {
182 struct vb2_v4l2_buffer *b;
183 struct list_head list;
184 union {
185 struct {
186 size_t luma;
187 size_t chroma;
188 } raw;
189 size_t stream;
190 } cookie;
191 int flags;
192};
193
194
195
196
197struct s5p_mfc_pm {
198 struct clk *clock;
199 struct clk *clock_gate;
200 atomic_t power;
201 struct device *device;
202};
203
204struct s5p_mfc_buf_size_v5 {
205 unsigned int h264_ctx;
206 unsigned int non_h264_ctx;
207 unsigned int dsc;
208 unsigned int shm;
209};
210
211struct s5p_mfc_buf_size_v6 {
212 unsigned int dev_ctx;
213 unsigned int h264_dec_ctx;
214 unsigned int other_dec_ctx;
215 unsigned int h264_enc_ctx;
216 unsigned int other_enc_ctx;
217};
218
219struct s5p_mfc_buf_size {
220 unsigned int fw;
221 unsigned int cpb;
222 void *priv;
223};
224
225struct s5p_mfc_buf_align {
226 unsigned int base;
227};
228
229struct s5p_mfc_variant {
230 unsigned int version;
231 unsigned int port_num;
232 u32 version_bit;
233 struct s5p_mfc_buf_size *buf_size;
234 struct s5p_mfc_buf_align *buf_align;
235 char *fw_name[MFC_FW_MAX_VERSIONS];
236};
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245
246struct s5p_mfc_priv_buf {
247 unsigned long ofs;
248 void *virt;
249 dma_addr_t dma;
250 size_t size;
251};
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297struct s5p_mfc_dev {
298 struct v4l2_device v4l2_dev;
299 struct video_device *vfd_dec;
300 struct video_device *vfd_enc;
301 struct platform_device *plat_dev;
302 struct device *mem_dev_l;
303 struct device *mem_dev_r;
304 void __iomem *regs_base;
305 int irq;
306 struct v4l2_ctrl_handler dec_ctrl_handler;
307 struct v4l2_ctrl_handler enc_ctrl_handler;
308 struct s5p_mfc_pm pm;
309 struct s5p_mfc_variant *variant;
310 int num_inst;
311 spinlock_t irqlock;
312 spinlock_t condlock;
313
314 struct mutex mfc_mutex;
315 int int_cond;
316 int int_type;
317 unsigned int int_err;
318 wait_queue_head_t queue;
319 size_t fw_size;
320 void *fw_virt_addr;
321 dma_addr_t bank1;
322 dma_addr_t bank2;
323 unsigned long hw_lock;
324 struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
325 int curr_ctx;
326 unsigned long ctx_work_bits;
327 atomic_t watchdog_cnt;
328 struct timer_list watchdog_timer;
329 struct workqueue_struct *watchdog_workqueue;
330 struct work_struct watchdog_work;
331 void *alloc_ctx[2];
332 unsigned long enter_suspend;
333
334 struct s5p_mfc_priv_buf ctx_buf;
335 int warn_start;
336 struct s5p_mfc_hw_ops *mfc_ops;
337 struct s5p_mfc_hw_cmds *mfc_cmds;
338 const struct s5p_mfc_regs *mfc_regs;
339 enum s5p_mfc_fw_ver fw_ver;
340 bool risc_on;
341};
342
343
344
345
346struct s5p_mfc_h264_enc_params {
347 enum v4l2_mpeg_video_h264_profile profile;
348 enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
349 s8 loop_filter_alpha;
350 s8 loop_filter_beta;
351 enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
352 u8 max_ref_pic;
353 u8 num_ref_pic_4p;
354 int _8x8_transform;
355 int rc_mb_dark;
356 int rc_mb_smooth;
357 int rc_mb_static;
358 int rc_mb_activity;
359 int vui_sar;
360 u8 vui_sar_idc;
361 u16 vui_ext_sar_width;
362 u16 vui_ext_sar_height;
363 int open_gop;
364 u16 open_gop_size;
365 u8 rc_frame_qp;
366 u8 rc_min_qp;
367 u8 rc_max_qp;
368 u8 rc_p_frame_qp;
369 u8 rc_b_frame_qp;
370 enum v4l2_mpeg_video_h264_level level_v4l2;
371 int level;
372 u16 cpb_size;
373 int interlace;
374 u8 hier_qp;
375 u8 hier_qp_type;
376 u8 hier_qp_layer;
377 u8 hier_qp_layer_qp[7];
378 u8 sei_frame_packing;
379 u8 sei_fp_curr_frame_0;
380 u8 sei_fp_arrangement_type;
381
382 u8 fmo;
383 u8 fmo_map_type;
384 u8 fmo_slice_grp;
385 u8 fmo_chg_dir;
386 u32 fmo_chg_rate;
387 u32 fmo_run_len[4];
388 u8 aso;
389 u32 aso_slice_order[8];
390};
391
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393
394
395struct s5p_mfc_mpeg4_enc_params {
396
397 enum v4l2_mpeg_video_mpeg4_profile profile;
398 int quarter_pixel;
399
400 u16 vop_time_res;
401 u16 vop_frm_delta;
402 u8 rc_frame_qp;
403 u8 rc_min_qp;
404 u8 rc_max_qp;
405 u8 rc_p_frame_qp;
406 u8 rc_b_frame_qp;
407 enum v4l2_mpeg_video_mpeg4_level level_v4l2;
408 int level;
409};
410
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412
413
414struct s5p_mfc_vp8_enc_params {
415 u8 imd_4x4;
416 enum v4l2_vp8_num_partitions num_partitions;
417 enum v4l2_vp8_num_ref_frames num_ref;
418 u8 filter_level;
419 u8 filter_sharpness;
420 u32 golden_frame_ref_period;
421 enum v4l2_vp8_golden_frame_sel golden_frame_sel;
422 u8 hier_layer;
423 u8 hier_layer_qp[3];
424 u8 rc_min_qp;
425 u8 rc_max_qp;
426 u8 rc_frame_qp;
427 u8 rc_p_frame_qp;
428 u8 profile;
429};
430
431
432
433
434struct s5p_mfc_enc_params {
435 u16 width;
436 u16 height;
437 u32 mv_h_range;
438 u32 mv_v_range;
439
440 u16 gop_size;
441 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
442 u16 slice_mb;
443 u32 slice_bit;
444 u16 intra_refresh_mb;
445 int pad;
446 u8 pad_luma;
447 u8 pad_cb;
448 u8 pad_cr;
449 int rc_frame;
450 int rc_mb;
451 u32 rc_bitrate;
452 u16 rc_reaction_coeff;
453 u16 vbv_size;
454 u32 vbv_delay;
455
456 enum v4l2_mpeg_video_header_mode seq_hdr_mode;
457 enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
458 int fixed_target_bit;
459
460 u8 num_b_frame;
461 u32 rc_framerate_num;
462 u32 rc_framerate_denom;
463
464 struct {
465 struct s5p_mfc_h264_enc_params h264;
466 struct s5p_mfc_mpeg4_enc_params mpeg4;
467 struct s5p_mfc_vp8_enc_params vp8;
468 } codec;
469
470};
471
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474
475struct s5p_mfc_codec_ops {
476
477 int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
478 int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
479
480 int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
481 int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
482};
483
484#define call_cop(c, op, args...) \
485 (((c)->c_ops->op) ? \
486 ((c)->c_ops->op(args)) : 0)
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563struct s5p_mfc_ctx {
564 struct s5p_mfc_dev *dev;
565 struct v4l2_fh fh;
566
567 int num;
568
569 int int_cond;
570 int int_type;
571 unsigned int int_err;
572 wait_queue_head_t queue;
573
574 struct s5p_mfc_fmt *src_fmt;
575 struct s5p_mfc_fmt *dst_fmt;
576
577 struct vb2_queue vq_src;
578 struct vb2_queue vq_dst;
579
580 struct list_head src_queue;
581 struct list_head dst_queue;
582
583 unsigned int src_queue_cnt;
584 unsigned int dst_queue_cnt;
585
586 enum s5p_mfc_inst_type type;
587 enum s5p_mfc_inst_state state;
588 int inst_no;
589
590
591 int img_width;
592 int img_height;
593 int buf_width;
594 int buf_height;
595
596 int luma_size;
597 int chroma_size;
598 int mv_size;
599
600 unsigned long consumed_stream;
601
602 unsigned int dpb_flush_flag;
603 unsigned int head_processed;
604
605 struct s5p_mfc_priv_buf bank1;
606 struct s5p_mfc_priv_buf bank2;
607
608 enum s5p_mfc_queue_state capture_state;
609 enum s5p_mfc_queue_state output_state;
610
611 struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
612 int src_bufs_cnt;
613 struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
614 int dst_bufs_cnt;
615
616 unsigned int sequence;
617 unsigned long dec_dst_flag;
618 size_t dec_src_buf_size;
619
620
621 int codec_mode;
622 int slice_interface;
623 int loop_filter_mpeg4;
624 int display_delay;
625 int display_delay_enable;
626 int after_packed_pb;
627 int sei_fp_parse;
628
629 int pb_count;
630 int total_dpb_count;
631 int mv_count;
632
633 struct s5p_mfc_priv_buf ctx;
634 struct s5p_mfc_priv_buf dsc;
635 struct s5p_mfc_priv_buf shm;
636
637 struct s5p_mfc_enc_params enc_params;
638
639 size_t enc_dst_buf_size;
640 size_t luma_dpb_size;
641 size_t chroma_dpb_size;
642 size_t me_buffer_size;
643 size_t tmv_buffer_size;
644
645 enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
646
647 struct list_head ref_queue;
648 unsigned int ref_queue_cnt;
649
650 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
651 union {
652 unsigned int mb;
653 unsigned int bits;
654 } slice_size;
655
656 const struct s5p_mfc_codec_ops *c_ops;
657
658 struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
659 struct v4l2_ctrl_handler ctrl_handler;
660 unsigned int frame_tag;
661 size_t scratch_buf_size;
662};
663
664
665
666
667
668struct s5p_mfc_fmt {
669 char *name;
670 u32 fourcc;
671 u32 codec_mode;
672 enum s5p_mfc_fmt_type type;
673 u32 num_planes;
674 u32 versions;
675};
676
677
678
679
680
681struct mfc_control {
682 __u32 id;
683 enum v4l2_ctrl_type type;
684 __u8 name[32];
685 __s32 minimum;
686 __s32 maximum;
687 __s32 step;
688 __u32 menu_skip_mask;
689 __s32 default_value;
690 __u32 flags;
691 __u32 reserved[2];
692 __u8 is_volatile;
693};
694
695
696#define s5p_mfc_hw_call(f, op, args...) \
697 ((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
698
699#define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
700#define ctrl_to_ctx(__ctrl) \
701 container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
702
703void clear_work_bit(struct s5p_mfc_ctx *ctx);
704void set_work_bit(struct s5p_mfc_ctx *ctx);
705void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
706void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
707int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
708void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
709
710#define HAS_PORTNUM(dev) (dev ? (dev->variant ? \
711 (dev->variant->port_num ? 1 : 0) : 0) : 0)
712#define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0)
713#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0)
714#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0)
715#define IS_MFCV8(dev) (dev->variant->version >= 0x80 ? 1 : 0)
716
717#define MFC_V5_BIT BIT(0)
718#define MFC_V6_BIT BIT(1)
719#define MFC_V7_BIT BIT(2)
720#define MFC_V8_BIT BIT(3)
721
722
723#endif
724