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10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/of_device.h>
16#include <linux/regmap.h>
17#include <media/rc-core.h>
18
19#define IR_ENABLE 0x00
20#define IR_CONFIG 0x04
21#define CNT_LEADS 0x08
22#define CNT_LEADE 0x0c
23#define CNT_SLEADE 0x10
24#define CNT0_B 0x14
25#define CNT1_B 0x18
26#define IR_BUSY 0x1c
27#define IR_DATAH 0x20
28#define IR_DATAL 0x24
29#define IR_INTM 0x28
30#define IR_INTS 0x2c
31#define IR_INTC 0x30
32#define IR_START 0x34
33
34
35#define INTMS_SYMBRCV (BIT(24) | BIT(8))
36#define INTMS_TIMEOUT (BIT(25) | BIT(9))
37#define INTMS_OVERFLOW (BIT(26) | BIT(10))
38#define INT_CLR_OVERFLOW BIT(18)
39#define INT_CLR_TIMEOUT BIT(17)
40#define INT_CLR_RCV BIT(16)
41#define INT_CLR_RCVTIMEOUT (BIT(16) | BIT(17))
42
43#define IR_CLK 0x48
44#define IR_CLK_ENABLE BIT(4)
45#define IR_CLK_RESET BIT(5)
46
47#define IR_CFG_WIDTH_MASK 0xffff
48#define IR_CFG_WIDTH_SHIFT 16
49#define IR_CFG_FORMAT_MASK 0x3
50#define IR_CFG_FORMAT_SHIFT 14
51#define IR_CFG_INT_LEVEL_MASK 0x3f
52#define IR_CFG_INT_LEVEL_SHIFT 8
53
54#define IR_CFG_MODE_RAW BIT(7)
55#define IR_CFG_FREQ_MASK 0x7f
56#define IR_CFG_FREQ_SHIFT 0
57#define IR_CFG_INT_THRESHOLD 1
58
59#define IR_CFG_SYMBOL_FMT 0
60#define IR_CFG_SYMBOL_MAXWIDTH 0x3e80
61
62#define IR_HIX5HD2_NAME "hix5hd2-ir"
63
64struct hix5hd2_ir_priv {
65 int irq;
66 void __iomem *base;
67 struct device *dev;
68 struct rc_dev *rdev;
69 struct regmap *regmap;
70 struct clk *clock;
71 unsigned long rate;
72};
73
74static void hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on)
75{
76 u32 val;
77
78 regmap_read(dev->regmap, IR_CLK, &val);
79 if (on) {
80 val &= ~IR_CLK_RESET;
81 val |= IR_CLK_ENABLE;
82 } else {
83 val &= ~IR_CLK_ENABLE;
84 val |= IR_CLK_RESET;
85 }
86 regmap_write(dev->regmap, IR_CLK, val);
87}
88
89static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
90{
91 int timeout = 10000;
92 u32 val, rate;
93
94 writel_relaxed(0x01, priv->base + IR_ENABLE);
95 while (readl_relaxed(priv->base + IR_BUSY)) {
96 if (timeout--) {
97 udelay(1);
98 } else {
99 dev_err(priv->dev, "IR_BUSY timeout\n");
100 return -ETIMEDOUT;
101 }
102 }
103
104
105 rate = DIV_ROUND_CLOSEST(priv->rate, 1000000);
106 val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT;
107 val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT;
108 val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK
109 << IR_CFG_INT_LEVEL_SHIFT;
110 val |= IR_CFG_MODE_RAW;
111 val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT;
112 writel_relaxed(val, priv->base + IR_CONFIG);
113
114 writel_relaxed(0x00, priv->base + IR_INTM);
115
116 writel_relaxed(0x01, priv->base + IR_START);
117 return 0;
118}
119
120static int hix5hd2_ir_open(struct rc_dev *rdev)
121{
122 struct hix5hd2_ir_priv *priv = rdev->priv;
123
124 hix5hd2_ir_enable(priv, true);
125 return hix5hd2_ir_config(priv);
126}
127
128static void hix5hd2_ir_close(struct rc_dev *rdev)
129{
130 struct hix5hd2_ir_priv *priv = rdev->priv;
131
132 hix5hd2_ir_enable(priv, false);
133}
134
135static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
136{
137 u32 symb_num, symb_val, symb_time;
138 u32 data_l, data_h;
139 u32 irq_sr, i;
140 struct hix5hd2_ir_priv *priv = data;
141
142 irq_sr = readl_relaxed(priv->base + IR_INTS);
143 if (irq_sr & INTMS_OVERFLOW) {
144
145
146
147
148
149 ir_raw_event_reset(priv->rdev);
150 symb_num = readl_relaxed(priv->base + IR_DATAH);
151 for (i = 0; i < symb_num; i++)
152 readl_relaxed(priv->base + IR_DATAL);
153
154 writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);
155 dev_info(priv->dev, "overflow, level=%d\n",
156 IR_CFG_INT_THRESHOLD);
157 }
158
159 if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) {
160 DEFINE_IR_RAW_EVENT(ev);
161
162 symb_num = readl_relaxed(priv->base + IR_DATAH);
163 for (i = 0; i < symb_num; i++) {
164 symb_val = readl_relaxed(priv->base + IR_DATAL);
165 data_l = ((symb_val & 0xffff) * 10);
166 data_h = ((symb_val >> 16) & 0xffff) * 10;
167 symb_time = (data_l + data_h) / 10;
168
169 ev.duration = US_TO_NS(data_l);
170 ev.pulse = true;
171 ir_raw_event_store(priv->rdev, &ev);
172
173 if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) {
174 ev.duration = US_TO_NS(data_h);
175 ev.pulse = false;
176 ir_raw_event_store(priv->rdev, &ev);
177 } else {
178 ir_raw_event_set_idle(priv->rdev, true);
179 }
180 }
181
182 if (irq_sr & INTMS_SYMBRCV)
183 writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);
184 if (irq_sr & INTMS_TIMEOUT)
185 writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);
186 }
187
188
189 ir_raw_event_handle(priv->rdev);
190 return IRQ_HANDLED;
191}
192
193static int hix5hd2_ir_probe(struct platform_device *pdev)
194{
195 struct rc_dev *rdev;
196 struct device *dev = &pdev->dev;
197 struct resource *res;
198 struct hix5hd2_ir_priv *priv;
199 struct device_node *node = pdev->dev.of_node;
200 const char *map_name;
201 int ret;
202
203 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
204 if (!priv)
205 return -ENOMEM;
206
207 priv->regmap = syscon_regmap_lookup_by_phandle(node,
208 "hisilicon,power-syscon");
209 if (IS_ERR(priv->regmap)) {
210 dev_err(dev, "no power-reg\n");
211 return -EINVAL;
212 }
213
214 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
215 priv->base = devm_ioremap_resource(dev, res);
216 if (IS_ERR(priv->base))
217 return PTR_ERR(priv->base);
218
219 priv->irq = platform_get_irq(pdev, 0);
220 if (priv->irq < 0) {
221 dev_err(dev, "irq can not get\n");
222 return priv->irq;
223 }
224
225 rdev = rc_allocate_device();
226 if (!rdev)
227 return -ENOMEM;
228
229 priv->clock = devm_clk_get(dev, NULL);
230 if (IS_ERR(priv->clock)) {
231 dev_err(dev, "clock not found\n");
232 ret = PTR_ERR(priv->clock);
233 goto err;
234 }
235 clk_prepare_enable(priv->clock);
236 priv->rate = clk_get_rate(priv->clock);
237
238 rdev->driver_type = RC_DRIVER_IR_RAW;
239 rdev->allowed_protocols = RC_BIT_ALL;
240 rdev->priv = priv;
241 rdev->open = hix5hd2_ir_open;
242 rdev->close = hix5hd2_ir_close;
243 rdev->driver_name = IR_HIX5HD2_NAME;
244 map_name = of_get_property(node, "linux,rc-map-name", NULL);
245 rdev->map_name = map_name ?: RC_MAP_EMPTY;
246 rdev->input_name = IR_HIX5HD2_NAME;
247 rdev->input_phys = IR_HIX5HD2_NAME "/input0";
248 rdev->input_id.bustype = BUS_HOST;
249 rdev->input_id.vendor = 0x0001;
250 rdev->input_id.product = 0x0001;
251 rdev->input_id.version = 0x0100;
252 rdev->rx_resolution = US_TO_NS(10);
253 rdev->timeout = US_TO_NS(IR_CFG_SYMBOL_MAXWIDTH * 10);
254
255 ret = rc_register_device(rdev);
256 if (ret < 0)
257 goto clkerr;
258
259 if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt,
260 0, pdev->name, priv) < 0) {
261 dev_err(dev, "IRQ %d register failed\n", priv->irq);
262 ret = -EINVAL;
263 goto regerr;
264 }
265
266 priv->rdev = rdev;
267 priv->dev = dev;
268 platform_set_drvdata(pdev, priv);
269
270 return ret;
271
272regerr:
273 rc_unregister_device(rdev);
274 rdev = NULL;
275clkerr:
276 clk_disable_unprepare(priv->clock);
277err:
278 rc_free_device(rdev);
279 dev_err(dev, "Unable to register device (%d)\n", ret);
280 return ret;
281}
282
283static int hix5hd2_ir_remove(struct platform_device *pdev)
284{
285 struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev);
286
287 clk_disable_unprepare(priv->clock);
288 rc_unregister_device(priv->rdev);
289 return 0;
290}
291
292#ifdef CONFIG_PM_SLEEP
293static int hix5hd2_ir_suspend(struct device *dev)
294{
295 struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
296
297 clk_disable_unprepare(priv->clock);
298 hix5hd2_ir_enable(priv, false);
299
300 return 0;
301}
302
303static int hix5hd2_ir_resume(struct device *dev)
304{
305 struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
306
307 hix5hd2_ir_enable(priv, true);
308 clk_prepare_enable(priv->clock);
309
310 writel_relaxed(0x01, priv->base + IR_ENABLE);
311 writel_relaxed(0x00, priv->base + IR_INTM);
312 writel_relaxed(0xff, priv->base + IR_INTC);
313 writel_relaxed(0x01, priv->base + IR_START);
314
315 return 0;
316}
317#endif
318
319static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend,
320 hix5hd2_ir_resume);
321
322static const struct of_device_id hix5hd2_ir_table[] = {
323 { .compatible = "hisilicon,hix5hd2-ir", },
324 {},
325};
326MODULE_DEVICE_TABLE(of, hix5hd2_ir_table);
327
328static struct platform_driver hix5hd2_ir_driver = {
329 .driver = {
330 .name = IR_HIX5HD2_NAME,
331 .of_match_table = hix5hd2_ir_table,
332 .pm = &hix5hd2_ir_pm_ops,
333 },
334 .probe = hix5hd2_ir_probe,
335 .remove = hix5hd2_ir_remove,
336};
337
338module_platform_driver(hix5hd2_ir_driver);
339
340MODULE_DESCRIPTION("IR controller driver for hix5hd2 platforms");
341MODULE_AUTHOR("Guoxiong Yan <yanguoxiong@huawei.com>");
342MODULE_LICENSE("GPL v2");
343MODULE_ALIAS("platform:hix5hd2-ir");
344
