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21#include <linux/module.h>
22#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/errno.h>
25#include <linux/videodev2.h>
26#include <linux/v4l2-dv-timings.h>
27#include <media/v4l2-dv-timings.h>
28#include <linux/math64.h>
29
30MODULE_AUTHOR("Hans Verkuil");
31MODULE_DESCRIPTION("V4L2 DV Timings Helper Functions");
32MODULE_LICENSE("GPL");
33
34const struct v4l2_dv_timings v4l2_dv_timings_presets[] = {
35 V4L2_DV_BT_CEA_640X480P59_94,
36 V4L2_DV_BT_CEA_720X480I59_94,
37 V4L2_DV_BT_CEA_720X480P59_94,
38 V4L2_DV_BT_CEA_720X576I50,
39 V4L2_DV_BT_CEA_720X576P50,
40 V4L2_DV_BT_CEA_1280X720P24,
41 V4L2_DV_BT_CEA_1280X720P25,
42 V4L2_DV_BT_CEA_1280X720P30,
43 V4L2_DV_BT_CEA_1280X720P50,
44 V4L2_DV_BT_CEA_1280X720P60,
45 V4L2_DV_BT_CEA_1920X1080P24,
46 V4L2_DV_BT_CEA_1920X1080P25,
47 V4L2_DV_BT_CEA_1920X1080P30,
48 V4L2_DV_BT_CEA_1920X1080I50,
49 V4L2_DV_BT_CEA_1920X1080P50,
50 V4L2_DV_BT_CEA_1920X1080I60,
51 V4L2_DV_BT_CEA_1920X1080P60,
52 V4L2_DV_BT_DMT_640X350P85,
53 V4L2_DV_BT_DMT_640X400P85,
54 V4L2_DV_BT_DMT_720X400P85,
55 V4L2_DV_BT_DMT_640X480P72,
56 V4L2_DV_BT_DMT_640X480P75,
57 V4L2_DV_BT_DMT_640X480P85,
58 V4L2_DV_BT_DMT_800X600P56,
59 V4L2_DV_BT_DMT_800X600P60,
60 V4L2_DV_BT_DMT_800X600P72,
61 V4L2_DV_BT_DMT_800X600P75,
62 V4L2_DV_BT_DMT_800X600P85,
63 V4L2_DV_BT_DMT_800X600P120_RB,
64 V4L2_DV_BT_DMT_848X480P60,
65 V4L2_DV_BT_DMT_1024X768I43,
66 V4L2_DV_BT_DMT_1024X768P60,
67 V4L2_DV_BT_DMT_1024X768P70,
68 V4L2_DV_BT_DMT_1024X768P75,
69 V4L2_DV_BT_DMT_1024X768P85,
70 V4L2_DV_BT_DMT_1024X768P120_RB,
71 V4L2_DV_BT_DMT_1152X864P75,
72 V4L2_DV_BT_DMT_1280X768P60_RB,
73 V4L2_DV_BT_DMT_1280X768P60,
74 V4L2_DV_BT_DMT_1280X768P75,
75 V4L2_DV_BT_DMT_1280X768P85,
76 V4L2_DV_BT_DMT_1280X768P120_RB,
77 V4L2_DV_BT_DMT_1280X800P60_RB,
78 V4L2_DV_BT_DMT_1280X800P60,
79 V4L2_DV_BT_DMT_1280X800P75,
80 V4L2_DV_BT_DMT_1280X800P85,
81 V4L2_DV_BT_DMT_1280X800P120_RB,
82 V4L2_DV_BT_DMT_1280X960P60,
83 V4L2_DV_BT_DMT_1280X960P85,
84 V4L2_DV_BT_DMT_1280X960P120_RB,
85 V4L2_DV_BT_DMT_1280X1024P60,
86 V4L2_DV_BT_DMT_1280X1024P75,
87 V4L2_DV_BT_DMT_1280X1024P85,
88 V4L2_DV_BT_DMT_1280X1024P120_RB,
89 V4L2_DV_BT_DMT_1360X768P60,
90 V4L2_DV_BT_DMT_1360X768P120_RB,
91 V4L2_DV_BT_DMT_1366X768P60,
92 V4L2_DV_BT_DMT_1366X768P60_RB,
93 V4L2_DV_BT_DMT_1400X1050P60_RB,
94 V4L2_DV_BT_DMT_1400X1050P60,
95 V4L2_DV_BT_DMT_1400X1050P75,
96 V4L2_DV_BT_DMT_1400X1050P85,
97 V4L2_DV_BT_DMT_1400X1050P120_RB,
98 V4L2_DV_BT_DMT_1440X900P60_RB,
99 V4L2_DV_BT_DMT_1440X900P60,
100 V4L2_DV_BT_DMT_1440X900P75,
101 V4L2_DV_BT_DMT_1440X900P85,
102 V4L2_DV_BT_DMT_1440X900P120_RB,
103 V4L2_DV_BT_DMT_1600X900P60_RB,
104 V4L2_DV_BT_DMT_1600X1200P60,
105 V4L2_DV_BT_DMT_1600X1200P65,
106 V4L2_DV_BT_DMT_1600X1200P70,
107 V4L2_DV_BT_DMT_1600X1200P75,
108 V4L2_DV_BT_DMT_1600X1200P85,
109 V4L2_DV_BT_DMT_1600X1200P120_RB,
110 V4L2_DV_BT_DMT_1680X1050P60_RB,
111 V4L2_DV_BT_DMT_1680X1050P60,
112 V4L2_DV_BT_DMT_1680X1050P75,
113 V4L2_DV_BT_DMT_1680X1050P85,
114 V4L2_DV_BT_DMT_1680X1050P120_RB,
115 V4L2_DV_BT_DMT_1792X1344P60,
116 V4L2_DV_BT_DMT_1792X1344P75,
117 V4L2_DV_BT_DMT_1792X1344P120_RB,
118 V4L2_DV_BT_DMT_1856X1392P60,
119 V4L2_DV_BT_DMT_1856X1392P75,
120 V4L2_DV_BT_DMT_1856X1392P120_RB,
121 V4L2_DV_BT_DMT_1920X1200P60_RB,
122 V4L2_DV_BT_DMT_1920X1200P60,
123 V4L2_DV_BT_DMT_1920X1200P75,
124 V4L2_DV_BT_DMT_1920X1200P85,
125 V4L2_DV_BT_DMT_1920X1200P120_RB,
126 V4L2_DV_BT_DMT_1920X1440P60,
127 V4L2_DV_BT_DMT_1920X1440P75,
128 V4L2_DV_BT_DMT_1920X1440P120_RB,
129 V4L2_DV_BT_DMT_2048X1152P60_RB,
130 V4L2_DV_BT_DMT_2560X1600P60_RB,
131 V4L2_DV_BT_DMT_2560X1600P60,
132 V4L2_DV_BT_DMT_2560X1600P75,
133 V4L2_DV_BT_DMT_2560X1600P85,
134 V4L2_DV_BT_DMT_2560X1600P120_RB,
135 V4L2_DV_BT_CEA_3840X2160P24,
136 V4L2_DV_BT_CEA_3840X2160P25,
137 V4L2_DV_BT_CEA_3840X2160P30,
138 V4L2_DV_BT_CEA_3840X2160P50,
139 V4L2_DV_BT_CEA_3840X2160P60,
140 V4L2_DV_BT_CEA_4096X2160P24,
141 V4L2_DV_BT_CEA_4096X2160P25,
142 V4L2_DV_BT_CEA_4096X2160P30,
143 V4L2_DV_BT_CEA_4096X2160P50,
144 V4L2_DV_BT_DMT_4096X2160P59_94_RB,
145 V4L2_DV_BT_CEA_4096X2160P60,
146 { }
147};
148EXPORT_SYMBOL_GPL(v4l2_dv_timings_presets);
149
150bool v4l2_valid_dv_timings(const struct v4l2_dv_timings *t,
151 const struct v4l2_dv_timings_cap *dvcap,
152 v4l2_check_dv_timings_fnc fnc,
153 void *fnc_handle)
154{
155 const struct v4l2_bt_timings *bt = &t->bt;
156 const struct v4l2_bt_timings_cap *cap = &dvcap->bt;
157 u32 caps = cap->capabilities;
158
159 if (t->type != V4L2_DV_BT_656_1120)
160 return false;
161 if (t->type != dvcap->type ||
162 bt->height < cap->min_height ||
163 bt->height > cap->max_height ||
164 bt->width < cap->min_width ||
165 bt->width > cap->max_width ||
166 bt->pixelclock < cap->min_pixelclock ||
167 bt->pixelclock > cap->max_pixelclock ||
168 (!(caps & V4L2_DV_BT_CAP_CUSTOM) &&
169 cap->standards && bt->standards &&
170 !(bt->standards & cap->standards)) ||
171 (bt->interlaced && !(caps & V4L2_DV_BT_CAP_INTERLACED)) ||
172 (!bt->interlaced && !(caps & V4L2_DV_BT_CAP_PROGRESSIVE)))
173 return false;
174 return fnc == NULL || fnc(t, fnc_handle);
175}
176EXPORT_SYMBOL_GPL(v4l2_valid_dv_timings);
177
178int v4l2_enum_dv_timings_cap(struct v4l2_enum_dv_timings *t,
179 const struct v4l2_dv_timings_cap *cap,
180 v4l2_check_dv_timings_fnc fnc,
181 void *fnc_handle)
182{
183 u32 i, idx;
184
185 memset(t->reserved, 0, sizeof(t->reserved));
186 for (i = idx = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
187 if (v4l2_valid_dv_timings(v4l2_dv_timings_presets + i, cap,
188 fnc, fnc_handle) &&
189 idx++ == t->index) {
190 t->timings = v4l2_dv_timings_presets[i];
191 return 0;
192 }
193 }
194 return -EINVAL;
195}
196EXPORT_SYMBOL_GPL(v4l2_enum_dv_timings_cap);
197
198bool v4l2_find_dv_timings_cap(struct v4l2_dv_timings *t,
199 const struct v4l2_dv_timings_cap *cap,
200 unsigned pclock_delta,
201 v4l2_check_dv_timings_fnc fnc,
202 void *fnc_handle)
203{
204 int i;
205
206 if (!v4l2_valid_dv_timings(t, cap, fnc, fnc_handle))
207 return false;
208
209 for (i = 0; i < v4l2_dv_timings_presets[i].bt.width; i++) {
210 if (v4l2_valid_dv_timings(v4l2_dv_timings_presets + i, cap,
211 fnc, fnc_handle) &&
212 v4l2_match_dv_timings(t, v4l2_dv_timings_presets + i,
213 pclock_delta, false)) {
214 u32 flags = t->bt.flags & V4L2_DV_FL_REDUCED_FPS;
215
216 *t = v4l2_dv_timings_presets[i];
217 if (can_reduce_fps(&t->bt))
218 t->bt.flags |= flags;
219
220 return true;
221 }
222 }
223 return false;
224}
225EXPORT_SYMBOL_GPL(v4l2_find_dv_timings_cap);
226
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236
237bool v4l2_match_dv_timings(const struct v4l2_dv_timings *t1,
238 const struct v4l2_dv_timings *t2,
239 unsigned pclock_delta, bool match_reduced_fps)
240{
241 if (t1->type != t2->type || t1->type != V4L2_DV_BT_656_1120)
242 return false;
243 if (t1->bt.width == t2->bt.width &&
244 t1->bt.height == t2->bt.height &&
245 t1->bt.interlaced == t2->bt.interlaced &&
246 t1->bt.polarities == t2->bt.polarities &&
247 t1->bt.pixelclock >= t2->bt.pixelclock - pclock_delta &&
248 t1->bt.pixelclock <= t2->bt.pixelclock + pclock_delta &&
249 t1->bt.hfrontporch == t2->bt.hfrontporch &&
250 t1->bt.hsync == t2->bt.hsync &&
251 t1->bt.hbackporch == t2->bt.hbackporch &&
252 t1->bt.vfrontporch == t2->bt.vfrontporch &&
253 t1->bt.vsync == t2->bt.vsync &&
254 t1->bt.vbackporch == t2->bt.vbackporch &&
255 (!match_reduced_fps ||
256 (t1->bt.flags & V4L2_DV_FL_REDUCED_FPS) ==
257 (t2->bt.flags & V4L2_DV_FL_REDUCED_FPS)) &&
258 (!t1->bt.interlaced ||
259 (t1->bt.il_vfrontporch == t2->bt.il_vfrontporch &&
260 t1->bt.il_vsync == t2->bt.il_vsync &&
261 t1->bt.il_vbackporch == t2->bt.il_vbackporch)))
262 return true;
263 return false;
264}
265EXPORT_SYMBOL_GPL(v4l2_match_dv_timings);
266
267void v4l2_print_dv_timings(const char *dev_prefix, const char *prefix,
268 const struct v4l2_dv_timings *t, bool detailed)
269{
270 const struct v4l2_bt_timings *bt = &t->bt;
271 u32 htot, vtot;
272 u32 fps;
273
274 if (t->type != V4L2_DV_BT_656_1120)
275 return;
276
277 htot = V4L2_DV_BT_FRAME_WIDTH(bt);
278 vtot = V4L2_DV_BT_FRAME_HEIGHT(bt);
279 if (bt->interlaced)
280 vtot /= 2;
281
282 fps = (htot * vtot) > 0 ? div_u64((100 * (u64)bt->pixelclock),
283 (htot * vtot)) : 0;
284
285 if (prefix == NULL)
286 prefix = "";
287
288 pr_info("%s: %s%ux%u%s%u.%u (%ux%u)\n", dev_prefix, prefix,
289 bt->width, bt->height, bt->interlaced ? "i" : "p",
290 fps / 100, fps % 100, htot, vtot);
291
292 if (!detailed)
293 return;
294
295 pr_info("%s: horizontal: fp = %u, %ssync = %u, bp = %u\n",
296 dev_prefix, bt->hfrontporch,
297 (bt->polarities & V4L2_DV_HSYNC_POS_POL) ? "+" : "-",
298 bt->hsync, bt->hbackporch);
299 pr_info("%s: vertical: fp = %u, %ssync = %u, bp = %u\n",
300 dev_prefix, bt->vfrontporch,
301 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
302 bt->vsync, bt->vbackporch);
303 if (bt->interlaced)
304 pr_info("%s: vertical bottom field: fp = %u, %ssync = %u, bp = %u\n",
305 dev_prefix, bt->il_vfrontporch,
306 (bt->polarities & V4L2_DV_VSYNC_POS_POL) ? "+" : "-",
307 bt->il_vsync, bt->il_vbackporch);
308 pr_info("%s: pixelclock: %llu\n", dev_prefix, bt->pixelclock);
309 pr_info("%s: flags (0x%x):%s%s%s%s%s%s\n", dev_prefix, bt->flags,
310 (bt->flags & V4L2_DV_FL_REDUCED_BLANKING) ?
311 " REDUCED_BLANKING" : "",
312 ((bt->flags & V4L2_DV_FL_REDUCED_BLANKING) &&
313 bt->vsync == 8) ? " (V2)" : "",
314 (bt->flags & V4L2_DV_FL_CAN_REDUCE_FPS) ?
315 " CAN_REDUCE_FPS" : "",
316 (bt->flags & V4L2_DV_FL_REDUCED_FPS) ?
317 " REDUCED_FPS" : "",
318 (bt->flags & V4L2_DV_FL_HALF_LINE) ?
319 " HALF_LINE" : "",
320 (bt->flags & V4L2_DV_FL_IS_CE_VIDEO) ?
321 " CE_VIDEO" : "");
322 pr_info("%s: standards (0x%x):%s%s%s%s\n", dev_prefix, bt->standards,
323 (bt->standards & V4L2_DV_BT_STD_CEA861) ? " CEA" : "",
324 (bt->standards & V4L2_DV_BT_STD_DMT) ? " DMT" : "",
325 (bt->standards & V4L2_DV_BT_STD_CVT) ? " CVT" : "",
326 (bt->standards & V4L2_DV_BT_STD_GTF) ? " GTF" : "");
327}
328EXPORT_SYMBOL_GPL(v4l2_print_dv_timings);
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335
336#define CVT_PXL_CLK_GRAN 250000
337#define CVT_PXL_CLK_GRAN_RB_V2 1000
338
339
340#define CVT_MIN_V_BPORCH 7
341#define CVT_MIN_V_PORCH_RND 3
342#define CVT_MIN_VSYNC_BP 550
343#define CVT_HSYNC_PERCENT 8
344
345
346#define CVT_CELL_GRAN 8
347#define CVT_M 600
348#define CVT_C 40
349#define CVT_K 128
350#define CVT_J 20
351#define CVT_C_PRIME (((CVT_C - CVT_J) * CVT_K / 256) + CVT_J)
352#define CVT_M_PRIME (CVT_K * CVT_M / 256)
353
354
355#define CVT_RB_MIN_V_BPORCH 7
356#define CVT_RB_V_FPORCH 3
357#define CVT_RB_MIN_V_BLANK 460
358#define CVT_RB_H_SYNC 32
359#define CVT_RB_H_BLANK 160
360
361#define CVT_RB_V2_H_BLANK 80
362#define CVT_RB_MIN_V_FPORCH 3
363#define CVT_RB_V2_MIN_V_FPORCH 1
364#define CVT_RB_V_BPORCH 6
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382bool v4l2_detect_cvt(unsigned frame_height,
383 unsigned hfreq,
384 unsigned vsync,
385 unsigned active_width,
386 u32 polarities,
387 bool interlaced,
388 struct v4l2_dv_timings *fmt)
389{
390 int v_fp, v_bp, h_fp, h_bp, hsync;
391 int frame_width, image_height, image_width;
392 bool reduced_blanking;
393 bool rb_v2 = false;
394 unsigned pix_clk;
395
396 if (vsync < 4 || vsync > 8)
397 return false;
398
399 if (polarities == V4L2_DV_VSYNC_POS_POL)
400 reduced_blanking = false;
401 else if (polarities == V4L2_DV_HSYNC_POS_POL)
402 reduced_blanking = true;
403 else
404 return false;
405
406 if (reduced_blanking && vsync == 8)
407 rb_v2 = true;
408
409 if (rb_v2 && active_width == 0)
410 return false;
411
412 if (!rb_v2 && vsync > 7)
413 return false;
414
415 if (hfreq == 0)
416 return false;
417
418
419 if (reduced_blanking) {
420 if (rb_v2) {
421 v_bp = CVT_RB_V_BPORCH;
422 v_fp = (CVT_RB_MIN_V_BLANK * hfreq) / 1000000 + 1;
423 v_fp -= vsync + v_bp;
424
425 if (v_fp < CVT_RB_V2_MIN_V_FPORCH)
426 v_fp = CVT_RB_V2_MIN_V_FPORCH;
427 } else {
428 v_fp = CVT_RB_V_FPORCH;
429 v_bp = (CVT_RB_MIN_V_BLANK * hfreq) / 1000000 + 1;
430 v_bp -= vsync + v_fp;
431
432 if (v_bp < CVT_RB_MIN_V_BPORCH)
433 v_bp = CVT_RB_MIN_V_BPORCH;
434 }
435 } else {
436 v_fp = CVT_MIN_V_PORCH_RND;
437 v_bp = (CVT_MIN_VSYNC_BP * hfreq) / 1000000 + 1 - vsync;
438
439 if (v_bp < CVT_MIN_V_BPORCH)
440 v_bp = CVT_MIN_V_BPORCH;
441 }
442
443 if (interlaced)
444 image_height = (frame_height - 2 * v_fp - 2 * vsync - 2 * v_bp) & ~0x1;
445 else
446 image_height = (frame_height - v_fp - vsync - v_bp + 1) & ~0x1;
447
448 if (image_height < 0)
449 return false;
450
451
452 switch (vsync) {
453 case 4:
454 image_width = (image_height * 4) / 3;
455 break;
456 case 5:
457 image_width = (image_height * 16) / 9;
458 break;
459 case 6:
460 image_width = (image_height * 16) / 10;
461 break;
462 case 7:
463
464 if (image_height == 1024)
465 image_width = (image_height * 5) / 4;
466 else if (image_height == 768)
467 image_width = (image_height * 15) / 9;
468 else
469 return false;
470 break;
471 case 8:
472 image_width = active_width;
473 break;
474 default:
475 return false;
476 }
477
478 if (!rb_v2)
479 image_width = image_width & ~7;
480
481
482 if (reduced_blanking) {
483 int h_blank;
484 int clk_gran;
485
486 h_blank = rb_v2 ? CVT_RB_V2_H_BLANK : CVT_RB_H_BLANK;
487 clk_gran = rb_v2 ? CVT_PXL_CLK_GRAN_RB_V2 : CVT_PXL_CLK_GRAN;
488
489 pix_clk = (image_width + h_blank) * hfreq;
490 pix_clk = (pix_clk / clk_gran) * clk_gran;
491
492 h_bp = h_blank / 2;
493 hsync = CVT_RB_H_SYNC;
494 h_fp = h_blank - h_bp - hsync;
495
496 frame_width = image_width + h_blank;
497 } else {
498 unsigned ideal_duty_cycle_per_myriad =
499 100 * CVT_C_PRIME - (CVT_M_PRIME * 100000) / hfreq;
500 int h_blank;
501
502 if (ideal_duty_cycle_per_myriad < 2000)
503 ideal_duty_cycle_per_myriad = 2000;
504
505 h_blank = image_width * ideal_duty_cycle_per_myriad /
506 (10000 - ideal_duty_cycle_per_myriad);
507 h_blank = (h_blank / (2 * CVT_CELL_GRAN)) * 2 * CVT_CELL_GRAN;
508
509 pix_clk = (image_width + h_blank) * hfreq;
510 pix_clk = (pix_clk / CVT_PXL_CLK_GRAN) * CVT_PXL_CLK_GRAN;
511
512 h_bp = h_blank / 2;
513 frame_width = image_width + h_blank;
514
515 hsync = frame_width * CVT_HSYNC_PERCENT / 100;
516 hsync = (hsync / CVT_CELL_GRAN) * CVT_CELL_GRAN;
517 h_fp = h_blank - hsync - h_bp;
518 }
519
520 fmt->type = V4L2_DV_BT_656_1120;
521 fmt->bt.polarities = polarities;
522 fmt->bt.width = image_width;
523 fmt->bt.height = image_height;
524 fmt->bt.hfrontporch = h_fp;
525 fmt->bt.vfrontporch = v_fp;
526 fmt->bt.hsync = hsync;
527 fmt->bt.vsync = vsync;
528 fmt->bt.hbackporch = frame_width - image_width - h_fp - hsync;
529
530 if (!interlaced) {
531 fmt->bt.vbackporch = frame_height - image_height - v_fp - vsync;
532 fmt->bt.interlaced = V4L2_DV_PROGRESSIVE;
533 } else {
534 fmt->bt.vbackporch = (frame_height - image_height - 2 * v_fp -
535 2 * vsync) / 2;
536 fmt->bt.il_vbackporch = frame_height - image_height - 2 * v_fp -
537 2 * vsync - fmt->bt.vbackporch;
538 fmt->bt.il_vfrontporch = v_fp;
539 fmt->bt.il_vsync = vsync;
540 fmt->bt.flags |= V4L2_DV_FL_HALF_LINE;
541 fmt->bt.interlaced = V4L2_DV_INTERLACED;
542 }
543
544 fmt->bt.pixelclock = pix_clk;
545 fmt->bt.standards = V4L2_DV_BT_STD_CVT;
546
547 if (reduced_blanking)
548 fmt->bt.flags |= V4L2_DV_FL_REDUCED_BLANKING;
549
550 return true;
551}
552EXPORT_SYMBOL_GPL(v4l2_detect_cvt);
553
554
555
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557
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560#define GTF_PXL_CLK_GRAN 250000
561
562#define GTF_MIN_VSYNC_BP 550
563#define GTF_V_FP 1
564#define GTF_CELL_GRAN 8
565
566
567#define GTF_D_M 600
568#define GTF_D_C 40
569#define GTF_D_K 128
570#define GTF_D_J 20
571#define GTF_D_C_PRIME ((((GTF_D_C - GTF_D_J) * GTF_D_K) / 256) + GTF_D_J)
572#define GTF_D_M_PRIME ((GTF_D_K * GTF_D_M) / 256)
573
574
575#define GTF_S_M 3600
576#define GTF_S_C 40
577#define GTF_S_K 128
578#define GTF_S_J 35
579#define GTF_S_C_PRIME ((((GTF_S_C - GTF_S_J) * GTF_S_K) / 256) + GTF_S_J)
580#define GTF_S_M_PRIME ((GTF_S_K * GTF_S_M) / 256)
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600bool v4l2_detect_gtf(unsigned frame_height,
601 unsigned hfreq,
602 unsigned vsync,
603 u32 polarities,
604 bool interlaced,
605 struct v4l2_fract aspect,
606 struct v4l2_dv_timings *fmt)
607{
608 int pix_clk;
609 int v_fp, v_bp, h_fp, hsync;
610 int frame_width, image_height, image_width;
611 bool default_gtf;
612 int h_blank;
613
614 if (vsync != 3)
615 return false;
616
617 if (polarities == V4L2_DV_VSYNC_POS_POL)
618 default_gtf = true;
619 else if (polarities == V4L2_DV_HSYNC_POS_POL)
620 default_gtf = false;
621 else
622 return false;
623
624 if (hfreq == 0)
625 return false;
626
627
628 v_fp = GTF_V_FP;
629 v_bp = (GTF_MIN_VSYNC_BP * hfreq + 500000) / 1000000 - vsync;
630 if (interlaced)
631 image_height = (frame_height - 2 * v_fp - 2 * vsync - 2 * v_bp) & ~0x1;
632 else
633 image_height = (frame_height - v_fp - vsync - v_bp + 1) & ~0x1;
634
635 if (image_height < 0)
636 return false;
637
638 if (aspect.numerator == 0 || aspect.denominator == 0) {
639 aspect.numerator = 16;
640 aspect.denominator = 9;
641 }
642 image_width = ((image_height * aspect.numerator) / aspect.denominator);
643 image_width = (image_width + GTF_CELL_GRAN/2) & ~(GTF_CELL_GRAN - 1);
644
645
646 if (default_gtf) {
647 u64 num;
648 u32 den;
649
650 num = ((image_width * GTF_D_C_PRIME * (u64)hfreq) -
651 ((u64)image_width * GTF_D_M_PRIME * 1000));
652 den = (hfreq * (100 - GTF_D_C_PRIME) + GTF_D_M_PRIME * 1000) *
653 (2 * GTF_CELL_GRAN);
654 h_blank = div_u64((num + (den >> 1)), den);
655 h_blank *= (2 * GTF_CELL_GRAN);
656 } else {
657 u64 num;
658 u32 den;
659
660 num = ((image_width * GTF_S_C_PRIME * (u64)hfreq) -
661 ((u64)image_width * GTF_S_M_PRIME * 1000));
662 den = (hfreq * (100 - GTF_S_C_PRIME) + GTF_S_M_PRIME * 1000) *
663 (2 * GTF_CELL_GRAN);
664 h_blank = div_u64((num + (den >> 1)), den);
665 h_blank *= (2 * GTF_CELL_GRAN);
666 }
667
668 frame_width = image_width + h_blank;
669
670 pix_clk = (image_width + h_blank) * hfreq;
671 pix_clk = pix_clk / GTF_PXL_CLK_GRAN * GTF_PXL_CLK_GRAN;
672
673 hsync = (frame_width * 8 + 50) / 100;
674 hsync = ((hsync + GTF_CELL_GRAN / 2) / GTF_CELL_GRAN) * GTF_CELL_GRAN;
675
676 h_fp = h_blank / 2 - hsync;
677
678 fmt->type = V4L2_DV_BT_656_1120;
679 fmt->bt.polarities = polarities;
680 fmt->bt.width = image_width;
681 fmt->bt.height = image_height;
682 fmt->bt.hfrontporch = h_fp;
683 fmt->bt.vfrontporch = v_fp;
684 fmt->bt.hsync = hsync;
685 fmt->bt.vsync = vsync;
686 fmt->bt.hbackporch = frame_width - image_width - h_fp - hsync;
687
688 if (!interlaced) {
689 fmt->bt.vbackporch = frame_height - image_height - v_fp - vsync;
690 fmt->bt.interlaced = V4L2_DV_PROGRESSIVE;
691 } else {
692 fmt->bt.vbackporch = (frame_height - image_height - 2 * v_fp -
693 2 * vsync) / 2;
694 fmt->bt.il_vbackporch = frame_height - image_height - 2 * v_fp -
695 2 * vsync - fmt->bt.vbackporch;
696 fmt->bt.il_vfrontporch = v_fp;
697 fmt->bt.il_vsync = vsync;
698 fmt->bt.flags |= V4L2_DV_FL_HALF_LINE;
699 fmt->bt.interlaced = V4L2_DV_INTERLACED;
700 }
701
702 fmt->bt.pixelclock = pix_clk;
703 fmt->bt.standards = V4L2_DV_BT_STD_GTF;
704
705 if (!default_gtf)
706 fmt->bt.flags |= V4L2_DV_FL_REDUCED_BLANKING;
707
708 return true;
709}
710EXPORT_SYMBOL_GPL(v4l2_detect_gtf);
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719
720
721struct v4l2_fract v4l2_calc_aspect_ratio(u8 hor_landscape, u8 vert_portrait)
722{
723 struct v4l2_fract aspect = { 16, 9 };
724 u8 ratio;
725
726
727 if (!hor_landscape && !vert_portrait)
728 return aspect;
729
730 if (hor_landscape && vert_portrait) {
731 aspect.numerator = hor_landscape;
732 aspect.denominator = vert_portrait;
733 return aspect;
734 }
735
736
737 ratio = hor_landscape | vert_portrait;
738
739 if (ratio == 79) {
740 aspect.numerator = 16;
741 aspect.denominator = 9;
742 } else if (ratio == 34) {
743 aspect.numerator = 4;
744 aspect.denominator = 3;
745 } else if (ratio == 68) {
746 aspect.numerator = 15;
747 aspect.denominator = 9;
748 } else {
749 aspect.numerator = hor_landscape + 99;
750 aspect.denominator = 100;
751 }
752 if (hor_landscape)
753 return aspect;
754
755 swap(aspect.denominator, aspect.numerator);
756 return aspect;
757}
758EXPORT_SYMBOL_GPL(v4l2_calc_aspect_ratio);
759
