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11#include <linux/clk.h>
12#include <linux/delay.h>
13#include <linux/dma-mapping.h>
14#include <linux/interrupt.h>
15#include <linux/module.h>
16#include <linux/mtd/mtd.h>
17#include <linux/mtd/nand.h>
18#include <linux/mtd/partitions.h>
19#include <linux/of.h>
20#include <linux/of_mtd.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23
24#define DRIVER_NAME "arasan_nfc"
25#define EVNT_TIMEOUT 1000
26#define STATUS_TIMEOUT 2000
27#define ANFC_PM_TIMEOUT 1000
28
29#define PKT_OFST 0x00
30#define MEM_ADDR1_OFST 0x04
31#define MEM_ADDR2_OFST 0x08
32#define CMD_OFST 0x0C
33#define PROG_OFST 0x10
34#define INTR_STS_EN_OFST 0x14
35#define INTR_SIG_EN_OFST 0x18
36#define INTR_STS_OFST 0x1C
37#define READY_STS_OFST 0x20
38#define DMA_ADDR1_OFST 0x24
39#define FLASH_STS_OFST 0x28
40#define DATA_PORT_OFST 0x30
41#define ECC_OFST 0x34
42#define ECC_ERR_CNT_OFST 0x38
43#define ECC_SPR_CMD_OFST 0x3C
44#define ECC_ERR_CNT_1BIT_OFST 0x40
45#define ECC_ERR_CNT_2BIT_OFST 0x44
46#define DMA_ADDR0_OFST 0x50
47#define DATA_INTERFACE_REG 0x6C
48
49#define PKT_CNT_SHIFT 12
50
51#define ECC_ENABLE BIT(31)
52#define DMA_EN_MASK GENMASK(27, 26)
53#define DMA_ENABLE 0x2
54#define DMA_EN_SHIFT 26
55#define PAGE_SIZE_MASK GENMASK(25, 23)
56#define PAGE_SIZE_SHIFT 23
57#define PAGE_SIZE_512 0
58#define PAGE_SIZE_1K 5
59#define PAGE_SIZE_2K 1
60#define PAGE_SIZE_4K 2
61#define PAGE_SIZE_8K 3
62#define PAGE_SIZE_16K 4
63#define CMD2_SHIFT 8
64#define ADDR_CYCLES_SHIFT 28
65
66#define XFER_COMPLETE BIT(2)
67#define READ_READY BIT(1)
68#define WRITE_READY BIT(0)
69#define MBIT_ERROR BIT(3)
70#define ERR_INTRPT BIT(4)
71
72#define PROG_PGRD BIT(0)
73#define PROG_ERASE BIT(2)
74#define PROG_STATUS BIT(3)
75#define PROG_PGPROG BIT(4)
76#define PROG_RDID BIT(6)
77#define PROG_RDPARAM BIT(7)
78#define PROG_RST BIT(8)
79#define PROG_GET_FEATURE BIT(9)
80#define PROG_SET_FEATURE BIT(10)
81
82#define ONFI_STATUS_FAIL BIT(0)
83#define ONFI_STATUS_READY BIT(6)
84
85#define PG_ADDR_SHIFT 16
86#define BCH_MODE_SHIFT 25
87#define BCH_EN_SHIFT 27
88#define ECC_SIZE_SHIFT 16
89
90#define MEM_ADDR_MASK GENMASK(7, 0)
91#define BCH_MODE_MASK GENMASK(27, 25)
92
93#define CS_MASK GENMASK(31, 30)
94#define CS_SHIFT 30
95
96#define PAGE_ERR_CNT_MASK GENMASK(16, 8)
97#define PKT_ERR_CNT_MASK GENMASK(7, 0)
98
99#define NVDDR_MODE BIT(9)
100#define NVDDR_TIMING_MODE_SHIFT 3
101
102#define ONFI_ID_LEN 8
103#define TEMP_BUF_SIZE 512
104#define NVDDR_MODE_PACKET_SIZE 8
105#define SDR_MODE_PACKET_SIZE 4
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114
115struct anfc_ecc_matrix {
116 u32 pagesize;
117 u32 codeword_size;
118 u8 eccbits;
119 u8 bch;
120 u16 eccsize;
121};
122
123static const struct anfc_ecc_matrix ecc_matrix[] = {
124 {512, 512, 1, 0, 0x3},
125 {512, 512, 4, 1, 0x7},
126 {512, 512, 8, 1, 0xD},
127
128 {2048, 512, 1, 0, 0xC},
129 {2048, 512, 4, 1, 0x1A},
130 {2048, 512, 8, 1, 0x34},
131 {2048, 512, 12, 1, 0x4E},
132 {2048, 1024, 24, 1, 0x54},
133
134 {4096, 512, 1, 0, 0x18},
135 {4096, 512, 4, 1, 0x34},
136 {4096, 512, 8, 1, 0x68},
137 {4096, 512, 12, 1, 0x9C},
138 {4096, 1024, 24, 1, 0xA8},
139
140 {8192, 512, 1, 0, 0x30},
141 {8192, 512, 4, 1, 0x68},
142 {8192, 512, 8, 1, 0xD0},
143 {8192, 512, 12, 1, 0x138},
144 {8192, 1024, 24, 1, 0x150},
145
146 {16384, 512, 1, 0, 0x60},
147 {16384, 512, 4, 1, 0xD0},
148 {16384, 512, 8, 1, 0x1A0},
149 {16384, 512, 12, 1, 0x270},
150 {16384, 1024, 24, 1, 0x2A0}
151};
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178struct anfc {
179 struct nand_chip chip;
180 struct device *dev;
181
182 void __iomem *base;
183 int curr_cmd;
184 struct clk *clk_sys;
185 struct clk *clk_flash;
186
187 bool dma;
188 bool bch;
189 bool err;
190 bool iswriteoob;
191
192 u8 buf[TEMP_BUF_SIZE];
193
194 u16 raddr_cycles;
195 u16 caddr_cycles;
196
197 u32 irq;
198 u32 pktsize;
199 u32 bufshift;
200 u32 rdintrmask;
201 u32 num_cs;
202 u32 spktsize;
203
204 struct completion bufrdy;
205 struct completion xfercomp;
206 struct nand_ecclayout ecclayout;
207};
208
209static inline struct anfc *to_anfc(struct mtd_info *mtd)
210{
211 return container_of(mtd_to_nand(mtd), struct anfc, chip);
212}
213
214static u8 anfc_page(u32 pagesize)
215{
216 switch (pagesize) {
217 case 512:
218 return PAGE_SIZE_512;
219 case 2048:
220 return PAGE_SIZE_2K;
221 case 4096:
222 return PAGE_SIZE_4K;
223 case 8192:
224 return PAGE_SIZE_8K;
225 case 16384:
226 return PAGE_SIZE_16K;
227 case 1024:
228 return PAGE_SIZE_1K;
229 default:
230 break;
231 }
232
233 return 0;
234}
235
236static inline void anfc_enable_intrs(struct anfc *nfc, u32 val)
237{
238 writel(val, nfc->base + INTR_STS_EN_OFST);
239 writel(val, nfc->base + INTR_SIG_EN_OFST);
240}
241
242static int anfc_wait_for_event(struct anfc *nfc, u32 event)
243{
244 struct completion *comp;
245 int ret;
246
247 if (event == XFER_COMPLETE)
248 comp = &nfc->xfercomp;
249 else
250 comp = &nfc->bufrdy;
251
252 ret = wait_for_completion_timeout(comp, msecs_to_jiffies(EVNT_TIMEOUT));
253
254 return ret;
255}
256
257static inline void anfc_setpktszcnt(struct anfc *nfc, u32 pktsize,
258 u32 pktcount)
259{
260 writel(pktsize | (pktcount << PKT_CNT_SHIFT), nfc->base + PKT_OFST);
261}
262
263static inline void anfc_set_eccsparecmd(struct anfc *nfc, u8 cmd1, u8 cmd2)
264{
265 writel(cmd1 | (cmd2 << CMD2_SHIFT) |
266 (nfc->caddr_cycles << ADDR_CYCLES_SHIFT),
267 nfc->base + ECC_SPR_CMD_OFST);
268}
269
270static void anfc_setpagecoladdr(struct anfc *nfc, u32 page, u16 col)
271{
272 u32 val;
273
274 writel(col | (page << PG_ADDR_SHIFT), nfc->base + MEM_ADDR1_OFST);
275
276 val = readl(nfc->base + MEM_ADDR2_OFST);
277 val = (val & ~MEM_ADDR_MASK) |
278 ((page >> PG_ADDR_SHIFT) & MEM_ADDR_MASK);
279 writel(val, nfc->base + MEM_ADDR2_OFST);
280}
281
282static void anfc_prepare_cmd(struct anfc *nfc, u8 cmd1, u8 cmd2,
283 u8 dmamode, u32 pagesize, u8 addrcycles)
284{
285 u32 regval;
286
287 regval = cmd1 | (cmd2 << CMD2_SHIFT);
288 if (dmamode && nfc->dma)
289 regval |= DMA_ENABLE << DMA_EN_SHIFT;
290 if (addrcycles)
291 regval |= addrcycles << ADDR_CYCLES_SHIFT;
292 if (pagesize)
293 regval |= anfc_page(pagesize) << PAGE_SIZE_SHIFT;
294 writel(regval, nfc->base + CMD_OFST);
295}
296
297static int anfc_device_ready(struct mtd_info *mtd,
298 struct nand_chip *chip)
299{
300 u8 status;
301 unsigned long timeout = jiffies + STATUS_TIMEOUT;
302
303 do {
304 chip->cmdfunc(mtd, NAND_CMD_STATUS, 0, 0);
305 status = chip->read_byte(mtd);
306 if (status & ONFI_STATUS_READY) {
307 if (status & ONFI_STATUS_FAIL)
308 return NAND_STATUS_FAIL;
309 break;
310 }
311 cpu_relax();
312 } while (!time_after_eq(jiffies, timeout));
313
314 if (time_after_eq(jiffies, timeout)) {
315 pr_err("%s timed out\n", __func__);
316 return -ETIMEDOUT;
317 }
318
319 return 0;
320}
321
322static int anfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
323 int page)
324{
325 struct anfc *nfc = to_anfc(mtd);
326
327 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
328 if (nfc->dma)
329 nfc->rdintrmask = XFER_COMPLETE;
330 else
331 nfc->rdintrmask = READ_READY;
332 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
333
334 return 0;
335}
336
337static int anfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
338 int page)
339{
340 struct anfc *nfc = to_anfc(mtd);
341
342 nfc->iswriteoob = true;
343 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
344 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
345 nfc->iswriteoob = false;
346
347 return 0;
348}
349
350static void anfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
351{
352 u32 i, pktcount, buf_rd_cnt = 0, pktsize;
353 u32 *bufptr = (u32 *)buf;
354 struct anfc *nfc = to_anfc(mtd);
355 dma_addr_t paddr = 0;
356
357 if (nfc->curr_cmd == NAND_CMD_READ0) {
358 pktsize = nfc->pktsize;
359 if (mtd->writesize % pktsize)
360 pktcount = mtd->writesize / pktsize + 1;
361 else
362 pktcount = mtd->writesize / pktsize;
363 } else {
364 pktsize = len;
365 pktcount = 1;
366 }
367
368 anfc_setpktszcnt(nfc, pktsize, pktcount);
369
370 if (nfc->dma) {
371 paddr = dma_map_single(nfc->dev, buf, len, DMA_FROM_DEVICE);
372 if (dma_mapping_error(nfc->dev, paddr)) {
373 dev_err(nfc->dev, "Read buffer mapping error");
374 return;
375 }
376 writel(lower_32_bits(paddr), nfc->base + DMA_ADDR0_OFST);
377 writel(upper_32_bits(paddr), nfc->base + DMA_ADDR1_OFST);
378 anfc_enable_intrs(nfc, nfc->rdintrmask);
379 writel(PROG_PGRD, nfc->base + PROG_OFST);
380 anfc_wait_for_event(nfc, XFER_COMPLETE);
381 dma_unmap_single(nfc->dev, paddr, len, DMA_FROM_DEVICE);
382 return;
383 }
384
385 anfc_enable_intrs(nfc, nfc->rdintrmask);
386 writel(PROG_PGRD, nfc->base + PROG_OFST);
387
388 while (buf_rd_cnt < pktcount) {
389
390 anfc_wait_for_event(nfc, READ_READY);
391 buf_rd_cnt++;
392
393 if (buf_rd_cnt == pktcount)
394 anfc_enable_intrs(nfc, XFER_COMPLETE);
395
396 for (i = 0; i < pktsize / 4; i++)
397 bufptr[i] = readl(nfc->base + DATA_PORT_OFST);
398
399 bufptr += (pktsize / 4);
400
401 if (buf_rd_cnt < pktcount)
402 anfc_enable_intrs(nfc, nfc->rdintrmask);
403 }
404
405 anfc_wait_for_event(nfc, XFER_COMPLETE);
406}
407
408static void anfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
409{
410 u32 buf_wr_cnt = 0, pktcount = 1, i, pktsize;
411 u32 *bufptr = (u32 *)buf;
412 struct anfc *nfc = to_anfc(mtd);
413 dma_addr_t paddr = 0;
414
415 if (nfc->iswriteoob) {
416 pktsize = len;
417 pktcount = 1;
418 } else {
419 pktsize = nfc->pktsize;
420 pktcount = mtd->writesize / pktsize;
421 }
422
423 anfc_setpktszcnt(nfc, pktsize, pktcount);
424
425 if (nfc->dma) {
426 paddr = dma_map_single(nfc->dev, (void *)buf, len,
427 DMA_TO_DEVICE);
428 if (dma_mapping_error(nfc->dev, paddr)) {
429 dev_err(nfc->dev, "Write buffer mapping error");
430 return;
431 }
432 writel(lower_32_bits(paddr), nfc->base + DMA_ADDR0_OFST);
433 writel(upper_32_bits(paddr), nfc->base + DMA_ADDR1_OFST);
434 anfc_enable_intrs(nfc, XFER_COMPLETE);
435 writel(PROG_PGPROG, nfc->base + PROG_OFST);
436 anfc_wait_for_event(nfc, XFER_COMPLETE);
437 dma_unmap_single(nfc->dev, paddr, len, DMA_TO_DEVICE);
438 return;
439 }
440
441 anfc_enable_intrs(nfc, WRITE_READY);
442 writel(PROG_PGPROG, nfc->base + PROG_OFST);
443
444 while (buf_wr_cnt < pktcount) {
445 anfc_wait_for_event(nfc, WRITE_READY);
446
447 buf_wr_cnt++;
448 if (buf_wr_cnt == pktcount)
449 anfc_enable_intrs(nfc, XFER_COMPLETE);
450
451 for (i = 0; i < (pktsize / 4); i++)
452 writel(bufptr[i], nfc->base + DATA_PORT_OFST);
453
454 bufptr += (pktsize / 4);
455
456 if (buf_wr_cnt < pktcount)
457 anfc_enable_intrs(nfc, WRITE_READY);
458 }
459
460 anfc_wait_for_event(nfc, XFER_COMPLETE);
461}
462
463static int anfc_read_page_hwecc(struct mtd_info *mtd,
464 struct nand_chip *chip, uint8_t *buf,
465 int oob_required, int page)
466{
467 u32 val;
468 struct anfc *nfc = to_anfc(mtd);
469
470 anfc_set_eccsparecmd(nfc, NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART);
471
472 val = readl(nfc->base + CMD_OFST);
473 val = val | ECC_ENABLE;
474 writel(val, nfc->base + CMD_OFST);
475
476 if (nfc->dma)
477 nfc->rdintrmask = XFER_COMPLETE;
478 else
479 nfc->rdintrmask = READ_READY;
480
481 if (!nfc->bch)
482 nfc->rdintrmask = MBIT_ERROR;
483
484 chip->read_buf(mtd, buf, mtd->writesize);
485
486 val = readl(nfc->base + ECC_ERR_CNT_OFST);
487 if (nfc->bch) {
488 mtd->ecc_stats.corrected += val & PAGE_ERR_CNT_MASK;
489 } else {
490 val = readl(nfc->base + ECC_ERR_CNT_1BIT_OFST);
491 mtd->ecc_stats.corrected += val;
492 val = readl(nfc->base + ECC_ERR_CNT_2BIT_OFST);
493 mtd->ecc_stats.failed += val;
494
495 writel(0x0, nfc->base + ECC_ERR_CNT_1BIT_OFST);
496 writel(0x0, nfc->base + ECC_ERR_CNT_2BIT_OFST);
497 }
498 nfc->err = false;
499
500 if (oob_required)
501 chip->ecc.read_oob(mtd, chip, page);
502
503 return 0;
504}
505
506static int anfc_write_page_hwecc(struct mtd_info *mtd,
507 struct nand_chip *chip, const uint8_t *buf,
508 int oob_required, int page)
509{
510 u32 val, i;
511 struct anfc *nfc = to_anfc(mtd);
512 uint8_t *ecc_calc = chip->buffers->ecccalc;
513 uint32_t *eccpos = chip->ecc.layout->eccpos;
514
515 anfc_set_eccsparecmd(nfc, NAND_CMD_RNDIN, 0);
516
517 val = readl(nfc->base + CMD_OFST);
518 val = val | ECC_ENABLE;
519 writel(val, nfc->base + CMD_OFST);
520
521 chip->write_buf(mtd, buf, mtd->writesize);
522
523 if (oob_required) {
524 anfc_device_ready(mtd, chip);
525 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
526 if (nfc->dma)
527 nfc->rdintrmask = XFER_COMPLETE;
528 else
529 nfc->rdintrmask = READ_READY;
530 chip->read_buf(mtd, ecc_calc, mtd->oobsize);
531 for (i = 0; i < chip->ecc.total; i++)
532 chip->oob_poi[eccpos[i]] = ecc_calc[eccpos[i]];
533 chip->ecc.write_oob(mtd, chip, page);
534 }
535
536 return 0;
537}
538
539static u8 anfc_read_byte(struct mtd_info *mtd)
540{
541 struct anfc *nfc = to_anfc(mtd);
542
543 return nfc->buf[nfc->bufshift++];
544}
545
546static void anfc_writefifo(struct anfc *nfc, u32 prog, u32 size, u8 *buf)
547{
548 u32 i, *bufptr = (u32 *)buf;
549
550 anfc_enable_intrs(nfc, WRITE_READY);
551
552 writel(prog, nfc->base + PROG_OFST);
553 anfc_wait_for_event(nfc, WRITE_READY);
554
555 anfc_enable_intrs(nfc, XFER_COMPLETE);
556 for (i = 0; i < size / 4; i++)
557 writel(bufptr[i], nfc->base + DATA_PORT_OFST);
558
559 anfc_wait_for_event(nfc, XFER_COMPLETE);
560}
561
562static void anfc_readfifo(struct anfc *nfc, u32 prog, u32 size)
563{
564 u32 i, *bufptr = (u32 *)&nfc->buf[0];
565
566 anfc_enable_intrs(nfc, READ_READY);
567
568 writel(prog, nfc->base + PROG_OFST);
569 anfc_wait_for_event(nfc, READ_READY);
570
571 anfc_enable_intrs(nfc, XFER_COMPLETE);
572
573 for (i = 0; i < size / 4; i++)
574 bufptr[i] = readl(nfc->base + DATA_PORT_OFST);
575
576 anfc_wait_for_event(nfc, XFER_COMPLETE);
577}
578
579static int anfc_ecc_init(struct mtd_info *mtd,
580 struct nand_ecc_ctrl *ecc)
581{
582 u32 oob_index, i, ecc_addr, regval, bchmode = 0;
583 struct nand_chip *nand_chip = mtd_to_nand(mtd);
584 struct anfc *nfc = to_anfc(mtd);
585 int found = -1;
586
587 nand_chip->ecc.mode = NAND_ECC_HW;
588 nand_chip->ecc.read_page = anfc_read_page_hwecc;
589 nand_chip->ecc.write_page = anfc_write_page_hwecc;
590 nand_chip->ecc.write_oob = anfc_write_oob;
591 nand_chip->ecc.read_oob = anfc_read_oob;
592
593 for (i = 0; i < sizeof(ecc_matrix) / sizeof(struct anfc_ecc_matrix);
594 i++) {
595 if ((ecc_matrix[i].pagesize == mtd->writesize) &&
596 (ecc_matrix[i].codeword_size >= nand_chip->ecc_step_ds)) {
597 if (ecc_matrix[i].eccbits >=
598 nand_chip->ecc_strength_ds) {
599 found = i;
600 break;
601 }
602 found = i;
603 }
604 }
605
606 if (found < 0) {
607 dev_err(nfc->dev, "ECC scheme not supported");
608 return 1;
609 }
610 if (ecc_matrix[found].bch) {
611 switch (ecc_matrix[found].eccbits) {
612 case 12:
613 bchmode = 0x1;
614 break;
615 case 8:
616 bchmode = 0x2;
617 break;
618 case 4:
619 bchmode = 0x3;
620 break;
621 case 24:
622 bchmode = 0x4;
623 break;
624 default:
625 bchmode = 0x0;
626 }
627 }
628
629 nand_chip->ecc.strength = ecc_matrix[found].eccbits;
630 nand_chip->ecc.size = ecc_matrix[found].codeword_size;
631 nand_chip->ecc.steps = ecc_matrix[found].pagesize /
632 ecc_matrix[found].codeword_size;
633 nand_chip->ecc.bytes = ecc_matrix[found].eccsize /
634 nand_chip->ecc.steps;
635 nfc->ecclayout.eccbytes = ecc_matrix[found].eccsize;
636 nfc->bch = ecc_matrix[found].bch;
637 oob_index = mtd->oobsize - nfc->ecclayout.eccbytes;
638 ecc_addr = mtd->writesize + oob_index;
639
640 for (i = 0; i < nand_chip->ecc.size; i++)
641 nfc->ecclayout.eccpos[i] = oob_index + i;
642
643 nfc->ecclayout.oobfree->offset = 2;
644 nfc->ecclayout.oobfree->length = oob_index -
645 nfc->ecclayout.oobfree->offset;
646
647 nand_chip->ecc.layout = &nfc->ecclayout;
648 regval = ecc_addr | (ecc_matrix[found].eccsize << ECC_SIZE_SHIFT) |
649 (ecc_matrix[found].bch << BCH_EN_SHIFT);
650 writel(regval, nfc->base + ECC_OFST);
651
652 regval = readl(nfc->base + MEM_ADDR2_OFST);
653 regval = (regval & ~(BCH_MODE_MASK)) | (bchmode << BCH_MODE_SHIFT);
654 writel(regval, nfc->base + MEM_ADDR2_OFST);
655
656 if (nand_chip->ecc_step_ds >= 1024)
657 nfc->pktsize = 1024;
658 else
659 nfc->pktsize = 512;
660
661 return 0;
662}
663
664static void anfc_cmd_function(struct mtd_info *mtd,
665 unsigned int cmd, int column, int page_addr)
666{
667 struct anfc *nfc = to_anfc(mtd);
668 bool wait = false, read = false;
669 u32 addrcycles, prog;
670 u32 *bufptr = (u32 *)&nfc->buf[0];
671
672 nfc->bufshift = 0;
673 nfc->curr_cmd = cmd;
674
675 if (page_addr == -1)
676 page_addr = 0;
677 if (column == -1)
678 column = 0;
679
680 switch (cmd) {
681 case NAND_CMD_RESET:
682 anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 0);
683 prog = PROG_RST;
684 wait = true;
685 break;
686 case NAND_CMD_SEQIN:
687 addrcycles = nfc->raddr_cycles + nfc->caddr_cycles;
688 anfc_prepare_cmd(nfc, cmd, NAND_CMD_PAGEPROG, 1,
689 mtd->writesize, addrcycles);
690 anfc_setpagecoladdr(nfc, page_addr, column);
691 break;
692 case NAND_CMD_READOOB:
693 column += mtd->writesize;
694 case NAND_CMD_READ0:
695 case NAND_CMD_READ1:
696 addrcycles = nfc->raddr_cycles + nfc->caddr_cycles;
697 anfc_prepare_cmd(nfc, NAND_CMD_READ0, NAND_CMD_READSTART, 1,
698 mtd->writesize, addrcycles);
699 anfc_setpagecoladdr(nfc, page_addr, column);
700 break;
701 case NAND_CMD_RNDOUT:
702 anfc_prepare_cmd(nfc, cmd, NAND_CMD_RNDOUTSTART, 1,
703 mtd->writesize, 2);
704 anfc_setpagecoladdr(nfc, page_addr, column);
705 if (nfc->dma)
706 nfc->rdintrmask = XFER_COMPLETE;
707 else
708 nfc->rdintrmask = READ_READY;
709 break;
710 case NAND_CMD_PARAM:
711 anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 1);
712 anfc_setpagecoladdr(nfc, page_addr, column);
713 anfc_setpktszcnt(nfc, sizeof(struct nand_onfi_params), 1);
714 anfc_readfifo(nfc, PROG_RDPARAM,
715 sizeof(struct nand_onfi_params));
716 break;
717 case NAND_CMD_READID:
718 anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 1);
719 anfc_setpagecoladdr(nfc, page_addr, column);
720 anfc_setpktszcnt(nfc, ONFI_ID_LEN, 1);
721 anfc_readfifo(nfc, PROG_RDID, ONFI_ID_LEN);
722 break;
723 case NAND_CMD_ERASE1:
724 addrcycles = nfc->raddr_cycles;
725 prog = PROG_ERASE;
726 anfc_prepare_cmd(nfc, cmd, NAND_CMD_ERASE2, 0, 0, addrcycles);
727 column = page_addr & 0xffff;
728 page_addr = (page_addr >> PG_ADDR_SHIFT) & 0xffff;
729 anfc_setpagecoladdr(nfc, page_addr, column);
730 wait = true;
731 break;
732 case NAND_CMD_STATUS:
733 anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 0);
734 anfc_setpktszcnt(nfc, nfc->spktsize/4, 1);
735 anfc_setpagecoladdr(nfc, page_addr, column);
736 prog = PROG_STATUS;
737 wait = read = true;
738 break;
739 case NAND_CMD_GET_FEATURES:
740 anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 1);
741 anfc_setpagecoladdr(nfc, page_addr, column);
742 anfc_setpktszcnt(nfc, nfc->spktsize, 1);
743 anfc_readfifo(nfc, PROG_GET_FEATURE, 4);
744 break;
745 case NAND_CMD_SET_FEATURES:
746 anfc_prepare_cmd(nfc, cmd, 0, 0, 0, 1);
747 anfc_setpagecoladdr(nfc, page_addr, column);
748 anfc_setpktszcnt(nfc, nfc->spktsize, 1);
749 break;
750 default:
751 return;
752 }
753
754 if (wait) {
755 anfc_enable_intrs(nfc, XFER_COMPLETE);
756 writel(prog, nfc->base + PROG_OFST);
757 anfc_wait_for_event(nfc, XFER_COMPLETE);
758 }
759
760 if (read)
761 bufptr[0] = readl(nfc->base + FLASH_STS_OFST);
762}
763
764static void anfc_select_chip(struct mtd_info *mtd, int num)
765{
766 u32 val;
767 int ret;
768 struct anfc *nfc = to_anfc(mtd);
769
770 if (num == -1) {
771 pm_runtime_mark_last_busy(nfc->dev);
772 pm_runtime_put_autosuspend(nfc->dev);
773 return;
774 }
775
776 ret = pm_runtime_get_sync(nfc->dev);
777 if (ret < 0) {
778 dev_err(nfc->dev, "runtime_get_sync failed\n");
779 return;
780 }
781 val = readl(nfc->base + MEM_ADDR2_OFST);
782 val = (val & ~(CS_MASK)) | (num << CS_SHIFT);
783 writel(val, nfc->base + MEM_ADDR2_OFST);
784}
785
786static irqreturn_t anfc_irq_handler(int irq, void *ptr)
787{
788 struct anfc *nfc = ptr;
789 u32 regval = 0, status;
790
791 status = readl(nfc->base + INTR_STS_OFST);
792 if (status & XFER_COMPLETE) {
793 complete(&nfc->xfercomp);
794 regval |= XFER_COMPLETE;
795 }
796
797 if (status & READ_READY) {
798 complete(&nfc->bufrdy);
799 regval |= READ_READY;
800 }
801
802 if (status & WRITE_READY) {
803 complete(&nfc->bufrdy);
804 regval |= WRITE_READY;
805 }
806
807 if (status & MBIT_ERROR) {
808 nfc->err = true;
809 complete(&nfc->bufrdy);
810 regval |= MBIT_ERROR;
811 }
812
813 if (regval) {
814 writel(regval, nfc->base + INTR_STS_OFST);
815 writel(0, nfc->base + INTR_STS_EN_OFST);
816 writel(0, nfc->base + INTR_SIG_EN_OFST);
817
818 return IRQ_HANDLED;
819 }
820
821 return IRQ_NONE;
822}
823
824static int anfc_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
825 int addr, uint8_t *subfeature_param)
826{
827 int status;
828 struct anfc *nfc = to_anfc(mtd);
829
830 if (!chip->onfi_version || !(le16_to_cpu(chip->onfi_params.opt_cmd)
831 & ONFI_OPT_CMD_SET_GET_FEATURES))
832 return -EINVAL;
833
834 chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
835 anfc_writefifo(nfc, PROG_SET_FEATURE, nfc->spktsize, subfeature_param);
836
837 status = chip->waitfunc(mtd, chip);
838 if (status & NAND_STATUS_FAIL)
839 return -EIO;
840
841 return 0;
842}
843
844static int anfc_init_timing_mode(struct anfc *nfc)
845{
846 int mode, err;
847 unsigned int feature[2], regval, i;
848 struct nand_chip *chip = &nfc->chip;
849 struct mtd_info *mtd = nand_to_mtd(&nfc->chip);
850
851 memset(&feature[0], 0, NVDDR_MODE_PACKET_SIZE);
852 mode = onfi_get_sync_timing_mode(chip);
853
854 mode = mode & 0xFF;
855 if (!mode) {
856 mode = onfi_get_async_timing_mode(&nfc->chip);
857 mode = fls(mode) - 1;
858 regval = mode;
859 } else {
860 mode = fls(mode) - 1;
861 regval = NVDDR_MODE | mode << NVDDR_TIMING_MODE_SHIFT;
862 mode |= ONFI_DATA_INTERFACE_NVDDR;
863 }
864
865 feature[0] = mode;
866 for (i = 0; i < nfc->num_cs; i++) {
867 chip->select_chip(mtd, i);
868 err = chip->onfi_set_features(mtd, chip,
869 ONFI_FEATURE_ADDR_TIMING_MODE,
870 (uint8_t *)&feature[0]);
871 chip->select_chip(mtd, -1);
872 if (err)
873 return err;
874 }
875 writel(regval, nfc->base + DATA_INTERFACE_REG);
876
877 if (mode & ONFI_DATA_INTERFACE_NVDDR)
878 nfc->spktsize = NVDDR_MODE_PACKET_SIZE;
879
880 return 0;
881}
882
883static int anfc_probe(struct platform_device *pdev)
884{
885 struct anfc *nfc;
886 struct mtd_info *mtd;
887 struct nand_chip *nand_chip;
888 struct resource *res;
889 int err;
890
891 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
892 if (!nfc)
893 return -ENOMEM;
894
895 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
896 nfc->base = devm_ioremap_resource(&pdev->dev, res);
897 if (IS_ERR(nfc->base))
898 return PTR_ERR(nfc->base);
899
900 nand_chip = &nfc->chip;
901 nand_set_controller_data(nand_chip, nfc);
902 mtd = nand_to_mtd(nand_chip);
903 mtd->owner = THIS_MODULE;
904 mtd->name = DRIVER_NAME;
905 nfc->dev = &pdev->dev;
906 mtd->dev.parent = &pdev->dev;
907 nand_set_flash_node(nand_chip, pdev->dev.of_node);
908
909 nand_chip->cmdfunc = anfc_cmd_function;
910 nand_chip->waitfunc = anfc_device_ready;
911 nand_chip->chip_delay = 30;
912 nand_chip->read_buf = anfc_read_buf;
913 nand_chip->write_buf = anfc_write_buf;
914 nand_chip->read_byte = anfc_read_byte;
915 nand_chip->options = NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE;
916 nand_chip->bbt_options = NAND_BBT_USE_FLASH;
917 nand_chip->select_chip = anfc_select_chip;
918 nand_chip->onfi_set_features = anfc_onfi_set_features;
919 nfc->dma = of_property_read_bool(pdev->dev.of_node,
920 "arasan,has-mdma");
921 nfc->num_cs = 1;
922 of_property_read_u32(pdev->dev.of_node, "num-cs", &nfc->num_cs);
923 platform_set_drvdata(pdev, nfc);
924 init_completion(&nfc->bufrdy);
925 init_completion(&nfc->xfercomp);
926 nfc->irq = platform_get_irq(pdev, 0);
927 if (nfc->irq < 0) {
928 dev_err(&pdev->dev, "request_irq failed\n");
929 return -ENXIO;
930 }
931 err = devm_request_irq(&pdev->dev, nfc->irq, anfc_irq_handler,
932 0, "arasannfc", nfc);
933 if (err)
934 return err;
935 nfc->clk_sys = devm_clk_get(&pdev->dev, "clk_sys");
936 if (IS_ERR(nfc->clk_sys)) {
937 dev_err(&pdev->dev, "sys clock not found.\n");
938 return PTR_ERR(nfc->clk_sys);
939 }
940
941 nfc->clk_flash = devm_clk_get(&pdev->dev, "clk_flash");
942 if (IS_ERR(nfc->clk_flash)) {
943 dev_err(&pdev->dev, "flash clock not found.\n");
944 return PTR_ERR(nfc->clk_flash);
945 }
946
947 err = clk_prepare_enable(nfc->clk_sys);
948 if (err) {
949 dev_err(&pdev->dev, "Unable to enable sys clock.\n");
950 return err;
951 }
952
953 err = clk_prepare_enable(nfc->clk_flash);
954 if (err) {
955 dev_err(&pdev->dev, "Unable to enable flash clock.\n");
956 goto clk_dis_sys;
957 }
958
959 pm_runtime_set_autosuspend_delay(nfc->dev, ANFC_PM_TIMEOUT);
960 pm_runtime_use_autosuspend(nfc->dev);
961 pm_runtime_set_active(nfc->dev);
962 pm_runtime_enable(nfc->dev);
963
964 nfc->spktsize = SDR_MODE_PACKET_SIZE;
965 if (nand_scan_ident(mtd, nfc->num_cs, NULL)) {
966 err = -ENXIO;
967 dev_err(&pdev->dev, "nand_scan_ident for NAND failed\n");
968 goto clk_dis_all;
969 }
970 if (nand_chip->onfi_version) {
971 nfc->raddr_cycles = nand_chip->onfi_params.addr_cycles & 0xF;
972 nfc->caddr_cycles =
973 (nand_chip->onfi_params.addr_cycles >> 4) & 0xF;
974 } else {
975
976 nfc->raddr_cycles = nfc->caddr_cycles = 5;
977 }
978
979 if (anfc_init_timing_mode(nfc)) {
980 err = -ENXIO;
981 dev_err(&pdev->dev, "timing mode init failed\n");
982 goto clk_dis_all;
983 }
984
985 if (anfc_ecc_init(mtd, &nand_chip->ecc)) {
986 err = -ENXIO;
987 goto clk_dis_all;
988 }
989
990 if (nand_scan_tail(mtd)) {
991 err = -ENXIO;
992 dev_err(&pdev->dev, "nand_scan_tail for NAND failed\n");
993 goto clk_dis_all;
994 }
995
996 err = mtd_device_register(mtd, NULL, 0);
997 if (err)
998 goto clk_dis_all;
999
1000 pm_runtime_mark_last_busy(nfc->dev);
1001 pm_runtime_put_autosuspend(nfc->dev);
1002
1003 return err;
1004
1005clk_dis_all:
1006 pm_runtime_disable(&pdev->dev);
1007 pm_runtime_set_suspended(&pdev->dev);
1008 clk_disable_unprepare(nfc->clk_flash);
1009clk_dis_sys:
1010 clk_disable_unprepare(nfc->clk_sys);
1011
1012 return err;
1013}
1014
1015static int anfc_remove(struct platform_device *pdev)
1016{
1017 struct anfc *nfc = platform_get_drvdata(pdev);
1018 struct mtd_info *mtd = nand_to_mtd(&nfc->chip);
1019
1020 pm_runtime_disable(&pdev->dev);
1021 pm_runtime_set_suspended(&pdev->dev);
1022 pm_runtime_dont_use_autosuspend(&pdev->dev);
1023 clk_disable_unprepare(nfc->clk_sys);
1024 clk_disable_unprepare(nfc->clk_flash);
1025
1026 nand_release(mtd);
1027
1028 return 0;
1029}
1030
1031static const struct of_device_id anfc_ids[] = {
1032 { .compatible = "arasan,nfc-v3p10" },
1033 { }
1034};
1035MODULE_DEVICE_TABLE(of, anfc_ids);
1036static int anfc_suspend(struct device *dev)
1037{
1038 return pm_runtime_put_sync(dev);
1039}
1040
1041static int anfc_resume(struct device *dev)
1042{
1043 return pm_runtime_get_sync(dev);
1044}
1045
1046static int __maybe_unused anfc_runtime_suspend(struct device *dev)
1047{
1048 struct platform_device *pdev = to_platform_device(dev);
1049 struct anfc *nfc = platform_get_drvdata(pdev);
1050
1051 clk_disable(nfc->clk_sys);
1052 clk_disable(nfc->clk_flash);
1053
1054 return 0;
1055}
1056
1057static int __maybe_unused anfc_runtime_resume(struct device *dev)
1058{
1059 struct platform_device *pdev = to_platform_device(dev);
1060 struct anfc *nfc = platform_get_drvdata(pdev);
1061 int ret;
1062
1063 ret = clk_enable(nfc->clk_sys);
1064 if (ret) {
1065 dev_err(dev, "Cannot enable sys clock.\n");
1066 return ret;
1067 }
1068 ret = clk_enable(nfc->clk_flash);
1069 if (ret) {
1070 dev_err(dev, "Cannot enable flash clock.\n");
1071 clk_disable(nfc->clk_sys);
1072 return ret;
1073 }
1074
1075 return 0;
1076}
1077
1078static const struct dev_pm_ops anfc_pm_ops = {
1079 .resume = anfc_resume,
1080 .suspend = anfc_suspend,
1081 .runtime_resume = anfc_runtime_resume,
1082 .runtime_suspend = anfc_runtime_suspend,
1083};
1084
1085static struct platform_driver anfc_driver = {
1086 .driver = {
1087 .name = DRIVER_NAME,
1088 .of_match_table = anfc_ids,
1089 .pm = &anfc_pm_ops,
1090 },
1091 .probe = anfc_probe,
1092 .remove = anfc_remove,
1093};
1094module_platform_driver(anfc_driver);
1095
1096MODULE_LICENSE("GPL");
1097MODULE_AUTHOR("Xilinx, Inc");
1098MODULE_DESCRIPTION("Arasan NAND Flash Controller Driver");
1099
