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10
11#define DEBUG
12
13#include <linux/device.h>
14#undef DEBUG
15#include <linux/mtd/mtd.h>
16#include <linux/mtd/nand.h>
17#include <linux/mtd/partitions.h>
18#include <linux/rslib.h>
19#include <linux/pci.h>
20#include <linux/delay.h>
21#include <linux/interrupt.h>
22#include <linux/dma-mapping.h>
23#include <linux/slab.h>
24#include <linux/module.h>
25#include <asm/io.h>
26
27#define CAFE_NAND_CTRL1 0x00
28#define CAFE_NAND_CTRL2 0x04
29#define CAFE_NAND_CTRL3 0x08
30#define CAFE_NAND_STATUS 0x0c
31#define CAFE_NAND_IRQ 0x10
32#define CAFE_NAND_IRQ_MASK 0x14
33#define CAFE_NAND_DATA_LEN 0x18
34#define CAFE_NAND_ADDR1 0x1c
35#define CAFE_NAND_ADDR2 0x20
36#define CAFE_NAND_TIMING1 0x24
37#define CAFE_NAND_TIMING2 0x28
38#define CAFE_NAND_TIMING3 0x2c
39#define CAFE_NAND_NONMEM 0x30
40#define CAFE_NAND_ECC_RESULT 0x3C
41#define CAFE_NAND_DMA_CTRL 0x40
42#define CAFE_NAND_DMA_ADDR0 0x44
43#define CAFE_NAND_DMA_ADDR1 0x48
44#define CAFE_NAND_ECC_SYN01 0x50
45#define CAFE_NAND_ECC_SYN23 0x54
46#define CAFE_NAND_ECC_SYN45 0x58
47#define CAFE_NAND_ECC_SYN67 0x5c
48#define CAFE_NAND_READ_DATA 0x1000
49#define CAFE_NAND_WRITE_DATA 0x2000
50
51#define CAFE_GLOBAL_CTRL 0x3004
52#define CAFE_GLOBAL_IRQ 0x3008
53#define CAFE_GLOBAL_IRQ_MASK 0x300c
54#define CAFE_NAND_RESET 0x3034
55
56
57#define CTRL1_CHIPSELECT (1<<19)
58
59struct cafe_priv {
60 struct nand_chip nand;
61 struct pci_dev *pdev;
62 void __iomem *mmio;
63 struct rs_control *rs;
64 uint32_t ctl1;
65 uint32_t ctl2;
66 int datalen;
67 int nr_data;
68 int data_pos;
69 int page_addr;
70 dma_addr_t dmaaddr;
71 unsigned char *dmabuf;
72};
73
74static int usedma = 1;
75module_param(usedma, int, 0644);
76
77static int skipbbt = 0;
78module_param(skipbbt, int, 0644);
79
80static int debug = 0;
81module_param(debug, int, 0644);
82
83static int regdebug = 0;
84module_param(regdebug, int, 0644);
85
86static int checkecc = 1;
87module_param(checkecc, int, 0644);
88
89static unsigned int numtimings;
90static int timing[3];
91module_param_array(timing, int, &numtimings, 0644);
92
93static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
94
95
96#define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
97
98
99#define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
100#define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
101
102static int cafe_device_ready(struct mtd_info *mtd)
103{
104 struct nand_chip *chip = mtd_to_nand(mtd);
105 struct cafe_priv *cafe = nand_get_controller_data(chip);
106 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
107 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
108
109 cafe_writel(cafe, irqs, NAND_IRQ);
110
111 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
112 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
113 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
114
115 return result;
116}
117
118
119static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
120{
121 struct nand_chip *chip = mtd_to_nand(mtd);
122 struct cafe_priv *cafe = nand_get_controller_data(chip);
123
124 if (usedma)
125 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
126 else
127 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
128
129 cafe->datalen += len;
130
131 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
132 len, cafe->datalen);
133}
134
135static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
136{
137 struct nand_chip *chip = mtd_to_nand(mtd);
138 struct cafe_priv *cafe = nand_get_controller_data(chip);
139
140 if (usedma)
141 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
142 else
143 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
144
145 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
146 len, cafe->datalen);
147 cafe->datalen += len;
148}
149
150static uint8_t cafe_read_byte(struct mtd_info *mtd)
151{
152 struct nand_chip *chip = mtd_to_nand(mtd);
153 struct cafe_priv *cafe = nand_get_controller_data(chip);
154 uint8_t d;
155
156 cafe_read_buf(mtd, &d, 1);
157 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
158
159 return d;
160}
161
162static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
163 int column, int page_addr)
164{
165 struct nand_chip *chip = mtd_to_nand(mtd);
166 struct cafe_priv *cafe = nand_get_controller_data(chip);
167 int adrbytes = 0;
168 uint32_t ctl1;
169 uint32_t doneint = 0x80000000;
170
171 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
172 command, column, page_addr);
173
174 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
175
176 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
177 ctl1 = cafe->ctl1;
178 cafe->ctl2 &= ~(1<<30);
179 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
180 cafe->ctl1, cafe->nr_data);
181 goto do_command;
182 }
183
184 cafe_writel(cafe, 0, NAND_CTRL2);
185
186
187 if (mtd->writesize > 512 &&
188 command == NAND_CMD_READOOB) {
189 column += mtd->writesize;
190 command = NAND_CMD_READ0;
191 }
192
193
194
195
196 if (column != -1) {
197 cafe_writel(cafe, column, NAND_ADDR1);
198 adrbytes = 2;
199 if (page_addr != -1)
200 goto write_adr2;
201 } else if (page_addr != -1) {
202 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
203 page_addr >>= 16;
204 write_adr2:
205 cafe_writel(cafe, page_addr, NAND_ADDR2);
206 adrbytes += 2;
207 if (mtd->size > mtd->writesize << 16)
208 adrbytes++;
209 }
210
211 cafe->data_pos = cafe->datalen = 0;
212
213
214 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
215
216
217 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
218 ctl1 |= (1<<26);
219
220 cafe->datalen = 4;
221
222 adrbytes = 1;
223 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
224 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
225 ctl1 |= 1<<26;
226
227 cafe->datalen = mtd->writesize + mtd->oobsize - column;
228 } else if (command == NAND_CMD_SEQIN)
229 ctl1 |= 1<<25;
230
231
232 if (adrbytes)
233 ctl1 |= ((adrbytes-1)|8) << 27;
234
235 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
236
237
238 cafe->ctl1 = ctl1;
239 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
240 cafe->ctl1, cafe->datalen);
241 return;
242 }
243
244 if (command == NAND_CMD_RNDOUT)
245 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
246 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
247 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
248
249 do_command:
250 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
251 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
252
253
254 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
255 cafe_writel(cafe, 0x90000000, NAND_IRQ);
256 if (usedma && (ctl1 & (3<<25))) {
257 uint32_t dmactl = 0xc0000000 + cafe->datalen;
258
259 if (ctl1 & (1<<26)) {
260
261 dmactl |= (1<<29);
262
263
264 doneint = 0x10000000;
265 }
266 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
267 }
268 cafe->datalen = 0;
269
270 if (unlikely(regdebug)) {
271 int i;
272 printk("About to write command %08x to register 0\n", ctl1);
273 for (i=4; i< 0x5c; i+=4)
274 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
275 }
276
277 cafe_writel(cafe, ctl1, NAND_CTRL1);
278
279
280 ndelay(100);
281
282 if (1) {
283 int c;
284 uint32_t irqs;
285
286 for (c = 500000; c != 0; c--) {
287 irqs = cafe_readl(cafe, NAND_IRQ);
288 if (irqs & doneint)
289 break;
290 udelay(1);
291 if (!(c % 100000))
292 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
293 cpu_relax();
294 }
295 cafe_writel(cafe, doneint, NAND_IRQ);
296 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
297 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
298 }
299
300 WARN_ON(cafe->ctl2 & (1<<30));
301
302 switch (command) {
303
304 case NAND_CMD_CACHEDPROG:
305 case NAND_CMD_PAGEPROG:
306 case NAND_CMD_ERASE1:
307 case NAND_CMD_ERASE2:
308 case NAND_CMD_SEQIN:
309 case NAND_CMD_RNDIN:
310 case NAND_CMD_STATUS:
311 case NAND_CMD_RNDOUT:
312 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
313 return;
314 }
315 nand_wait_ready(mtd);
316 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
317}
318
319static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
320{
321 struct nand_chip *chip = mtd_to_nand(mtd);
322 struct cafe_priv *cafe = nand_get_controller_data(chip);
323
324 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
325
326
327
328 if (chipnr)
329 cafe->ctl1 |= CTRL1_CHIPSELECT;
330 else
331 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
332}
333
334static irqreturn_t cafe_nand_interrupt(int irq, void *id)
335{
336 struct mtd_info *mtd = id;
337 struct nand_chip *chip = mtd_to_nand(mtd);
338 struct cafe_priv *cafe = nand_get_controller_data(chip);
339 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
340 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
341 if (!irqs)
342 return IRQ_NONE;
343
344 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
345 return IRQ_HANDLED;
346}
347
348static void cafe_nand_bug(struct mtd_info *mtd)
349{
350 BUG();
351}
352
353static int cafe_nand_write_oob(struct mtd_info *mtd,
354 struct nand_chip *chip, int page)
355{
356 int status = 0;
357
358 chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
359 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
360 chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
361 status = chip->waitfunc(mtd, chip);
362
363 return status & NAND_STATUS_FAIL ? -EIO : 0;
364}
365
366
367static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
368 int page)
369{
370 chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
371 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
372 return 0;
373}
374
375
376
377
378
379
380
381
382
383
384static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
385 uint8_t *buf, int oob_required, int page)
386{
387 struct cafe_priv *cafe = nand_get_controller_data(chip);
388 unsigned int max_bitflips = 0;
389
390 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
391 cafe_readl(cafe, NAND_ECC_RESULT),
392 cafe_readl(cafe, NAND_ECC_SYN01));
393
394 chip->read_buf(mtd, buf, mtd->writesize);
395 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
396
397 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
398 unsigned short syn[8], pat[4];
399 int pos[4];
400 u8 *oob = chip->oob_poi;
401 int i, n;
402
403 for (i=0; i<8; i+=2) {
404 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
405 syn[i] = cafe->rs->index_of[tmp & 0xfff];
406 syn[i+1] = cafe->rs->index_of[(tmp >> 16) & 0xfff];
407 }
408
409 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
410 pat);
411
412 for (i = 0; i < n; i++) {
413 int p = pos[i];
414
415
416
417 if (p > 1374) {
418
419 n = -1374;
420 } else if (p == 0) {
421
422 if (pat[i] > 0xff)
423 n = -2048;
424 else
425 buf[0] ^= pat[i];
426 } else if (p == 1365) {
427 buf[2047] ^= pat[i] >> 4;
428 oob[0] ^= pat[i] << 4;
429 } else if (p > 1365) {
430 if ((p & 1) == 1) {
431 oob[3*p/2 - 2048] ^= pat[i] >> 4;
432 oob[3*p/2 - 2047] ^= pat[i] << 4;
433 } else {
434 oob[3*p/2 - 2049] ^= pat[i] >> 8;
435 oob[3*p/2 - 2048] ^= pat[i];
436 }
437 } else if ((p & 1) == 1) {
438 buf[3*p/2] ^= pat[i] >> 4;
439 buf[3*p/2 + 1] ^= pat[i] << 4;
440 } else {
441 buf[3*p/2 - 1] ^= pat[i] >> 8;
442 buf[3*p/2] ^= pat[i];
443 }
444 }
445
446 if (n < 0) {
447 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
448 cafe_readl(cafe, NAND_ADDR2) * 2048);
449 for (i = 0; i < 0x5c; i += 4)
450 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
451 mtd->ecc_stats.failed++;
452 } else {
453 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
454 mtd->ecc_stats.corrected += n;
455 max_bitflips = max_t(unsigned int, max_bitflips, n);
456 }
457 }
458
459 return max_bitflips;
460}
461
462static struct nand_ecclayout cafe_oobinfo_2048 = {
463 .eccbytes = 14,
464 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
465 .oobfree = {{14, 50}}
466};
467
468
469
470static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
471static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
472
473static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
474static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
475
476
477static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
478 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
479 | NAND_BBT_2BIT | NAND_BBT_VERSION,
480 .offs = 14,
481 .len = 4,
482 .veroffs = 18,
483 .maxblocks = 4,
484 .pattern = cafe_bbt_pattern_2048
485};
486
487static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
488 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
489 | NAND_BBT_2BIT | NAND_BBT_VERSION,
490 .offs = 14,
491 .len = 4,
492 .veroffs = 18,
493 .maxblocks = 4,
494 .pattern = cafe_mirror_pattern_2048
495};
496
497static struct nand_ecclayout cafe_oobinfo_512 = {
498 .eccbytes = 14,
499 .eccpos = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
500 .oobfree = {{14, 2}}
501};
502
503static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
504 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
505 | NAND_BBT_2BIT | NAND_BBT_VERSION,
506 .offs = 14,
507 .len = 1,
508 .veroffs = 15,
509 .maxblocks = 4,
510 .pattern = cafe_bbt_pattern_512
511};
512
513static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
514 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
515 | NAND_BBT_2BIT | NAND_BBT_VERSION,
516 .offs = 14,
517 .len = 1,
518 .veroffs = 15,
519 .maxblocks = 4,
520 .pattern = cafe_mirror_pattern_512
521};
522
523
524static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
525 struct nand_chip *chip,
526 const uint8_t *buf, int oob_required,
527 int page)
528{
529 struct cafe_priv *cafe = nand_get_controller_data(chip);
530
531 chip->write_buf(mtd, buf, mtd->writesize);
532 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
533
534
535 cafe->ctl2 |= (1<<30);
536
537 return 0;
538}
539
540static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
541{
542 return 0;
543}
544
545
546static unsigned short gf64_mul(u8 a, u8 b)
547{
548 u8 c;
549 unsigned int i;
550
551 c = 0;
552 for (i = 0; i < 6; i++) {
553 if (a & 1)
554 c ^= b;
555 a >>= 1;
556 b <<= 1;
557 if ((b & 0x40) != 0)
558 b ^= 0x43;
559 }
560
561 return c;
562}
563
564
565static u16 gf4096_mul(u16 a, u16 b)
566{
567 u8 ah, al, bh, bl, ch, cl;
568
569 ah = a >> 6;
570 al = a & 0x3f;
571 bh = b >> 6;
572 bl = b & 0x3f;
573
574 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
575 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
576
577 return (ch << 6) ^ cl;
578}
579
580static int cafe_mul(int x)
581{
582 if (x == 0)
583 return 1;
584 return gf4096_mul(x, 0xe01);
585}
586
587static int cafe_nand_probe(struct pci_dev *pdev,
588 const struct pci_device_id *ent)
589{
590 struct mtd_info *mtd;
591 struct cafe_priv *cafe;
592 uint32_t ctrl;
593 int err = 0;
594 int old_dma;
595 struct nand_buffers *nbuf;
596
597
598
599 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
600 return -ENODEV;
601
602 err = pci_enable_device(pdev);
603 if (err)
604 return err;
605
606 pci_set_master(pdev);
607
608 cafe = kzalloc(sizeof(*cafe), GFP_KERNEL);
609 if (!cafe)
610 return -ENOMEM;
611
612 mtd = nand_to_mtd(&cafe->nand);
613 mtd->dev.parent = &pdev->dev;
614 nand_set_controller_data(&cafe->nand, cafe);
615
616 cafe->pdev = pdev;
617 cafe->mmio = pci_iomap(pdev, 0, 0);
618 if (!cafe->mmio) {
619 dev_warn(&pdev->dev, "failed to iomap\n");
620 err = -ENOMEM;
621 goto out_free_mtd;
622 }
623
624 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
625 if (!cafe->rs) {
626 err = -ENOMEM;
627 goto out_ior;
628 }
629
630 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
631 cafe->nand.dev_ready = cafe_device_ready;
632 cafe->nand.read_byte = cafe_read_byte;
633 cafe->nand.read_buf = cafe_read_buf;
634 cafe->nand.write_buf = cafe_write_buf;
635 cafe->nand.select_chip = cafe_select_chip;
636
637 cafe->nand.chip_delay = 0;
638
639
640 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
641 cafe->nand.options = NAND_OWN_BUFFERS;
642
643 if (skipbbt) {
644 cafe->nand.options |= NAND_SKIP_BBTSCAN;
645 cafe->nand.block_bad = cafe_nand_block_bad;
646 }
647
648 if (numtimings && numtimings != 3) {
649 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
650 }
651
652 if (numtimings == 3) {
653 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
654 timing[0], timing[1], timing[2]);
655 } else {
656 timing[0] = cafe_readl(cafe, NAND_TIMING1);
657 timing[1] = cafe_readl(cafe, NAND_TIMING2);
658 timing[2] = cafe_readl(cafe, NAND_TIMING3);
659
660 if (timing[0] | timing[1] | timing[2]) {
661 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
662 timing[0], timing[1], timing[2]);
663 } else {
664 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
665 timing[0] = timing[1] = timing[2] = 0xffffffff;
666 }
667 }
668
669
670 cafe_writel(cafe, 1, NAND_RESET);
671 cafe_writel(cafe, 0, NAND_RESET);
672
673 cafe_writel(cafe, timing[0], NAND_TIMING1);
674 cafe_writel(cafe, timing[1], NAND_TIMING2);
675 cafe_writel(cafe, timing[2], NAND_TIMING3);
676
677 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
678 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
679 "CAFE NAND", mtd);
680 if (err) {
681 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
682 goto out_ior;
683 }
684
685
686 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
687 ctrl &= 0xffffeff0;
688 ctrl |= 0x00007000;
689 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
690 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
691 cafe_writel(cafe, 0, NAND_DMA_CTRL);
692
693 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
694 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
695
696
697 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
698 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
699 cafe_readl(cafe, GLOBAL_CTRL),
700 cafe_readl(cafe, GLOBAL_IRQ_MASK));
701
702
703 old_dma = usedma;
704 usedma = 0;
705
706
707 if (nand_scan_ident(mtd, 2, NULL)) {
708 err = -ENXIO;
709 goto out_irq;
710 }
711
712 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev,
713 2112 + sizeof(struct nand_buffers) +
714 mtd->writesize + mtd->oobsize,
715 &cafe->dmaaddr, GFP_KERNEL);
716 if (!cafe->dmabuf) {
717 err = -ENOMEM;
718 goto out_irq;
719 }
720 cafe->nand.buffers = nbuf = (void *)cafe->dmabuf + 2112;
721
722
723 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
724 if (sizeof(cafe->dmaaddr) > 4)
725
726 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
727 else
728 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
729
730 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
731 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
732
733
734 nbuf->ecccalc = NULL;
735 nbuf->ecccode = NULL;
736 nbuf->databuf = (uint8_t *)(nbuf + 1);
737
738
739 usedma = old_dma;
740
741 cafe->ctl2 = 1<<27;
742 if (mtd->writesize == 2048)
743 cafe->ctl2 |= 1<<29;
744
745
746 if (mtd->writesize == 2048) {
747 cafe->nand.ecc.layout = &cafe_oobinfo_2048;
748 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
749 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
750 } else if (mtd->writesize == 512) {
751 cafe->nand.ecc.layout = &cafe_oobinfo_512;
752 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
753 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
754 } else {
755 printk(KERN_WARNING "Unexpected NAND flash writesize %d. Aborting\n",
756 mtd->writesize);
757 goto out_free_dma;
758 }
759 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
760 cafe->nand.ecc.size = mtd->writesize;
761 cafe->nand.ecc.bytes = 14;
762 cafe->nand.ecc.strength = 4;
763 cafe->nand.ecc.hwctl = (void *)cafe_nand_bug;
764 cafe->nand.ecc.calculate = (void *)cafe_nand_bug;
765 cafe->nand.ecc.correct = (void *)cafe_nand_bug;
766 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
767 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
768 cafe->nand.ecc.read_page = cafe_nand_read_page;
769 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
770
771 err = nand_scan_tail(mtd);
772 if (err)
773 goto out_free_dma;
774
775 pci_set_drvdata(pdev, mtd);
776
777 mtd->name = "cafe_nand";
778 mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
779
780 goto out;
781
782 out_free_dma:
783 dma_free_coherent(&cafe->pdev->dev,
784 2112 + sizeof(struct nand_buffers) +
785 mtd->writesize + mtd->oobsize,
786 cafe->dmabuf, cafe->dmaaddr);
787 out_irq:
788
789 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
790 free_irq(pdev->irq, mtd);
791 out_ior:
792 pci_iounmap(pdev, cafe->mmio);
793 out_free_mtd:
794 kfree(cafe);
795 out:
796 return err;
797}
798
799static void cafe_nand_remove(struct pci_dev *pdev)
800{
801 struct mtd_info *mtd = pci_get_drvdata(pdev);
802 struct nand_chip *chip = mtd_to_nand(mtd);
803 struct cafe_priv *cafe = nand_get_controller_data(chip);
804
805
806 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
807 free_irq(pdev->irq, mtd);
808 nand_release(mtd);
809 free_rs(cafe->rs);
810 pci_iounmap(pdev, cafe->mmio);
811 dma_free_coherent(&cafe->pdev->dev,
812 2112 + sizeof(struct nand_buffers) +
813 mtd->writesize + mtd->oobsize,
814 cafe->dmabuf, cafe->dmaaddr);
815 kfree(cafe);
816}
817
818static const struct pci_device_id cafe_nand_tbl[] = {
819 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
820 PCI_ANY_ID, PCI_ANY_ID },
821 { }
822};
823
824MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
825
826static int cafe_nand_resume(struct pci_dev *pdev)
827{
828 uint32_t ctrl;
829 struct mtd_info *mtd = pci_get_drvdata(pdev);
830 struct nand_chip *chip = mtd_to_nand(mtd);
831 struct cafe_priv *cafe = nand_get_controller_data(chip);
832
833
834 cafe_writel(cafe, 1, NAND_RESET);
835 cafe_writel(cafe, 0, NAND_RESET);
836 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
837
838
839 cafe_writel(cafe, timing[0], NAND_TIMING1);
840 cafe_writel(cafe, timing[1], NAND_TIMING2);
841 cafe_writel(cafe, timing[2], NAND_TIMING3);
842
843
844 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
845 ctrl &= 0xffffeff0;
846 ctrl |= 0x00007000;
847 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
848 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
849 cafe_writel(cafe, 0, NAND_DMA_CTRL);
850 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
851 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
852
853
854 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
855 if (sizeof(cafe->dmaaddr) > 4)
856
857 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
858 else
859 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
860
861
862 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
863 return 0;
864}
865
866static struct pci_driver cafe_nand_pci_driver = {
867 .name = "CAFÉ NAND",
868 .id_table = cafe_nand_tbl,
869 .probe = cafe_nand_probe,
870 .remove = cafe_nand_remove,
871 .resume = cafe_nand_resume,
872};
873
874module_pci_driver(cafe_nand_pci_driver);
875
876MODULE_LICENSE("GPL");
877MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
878MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
879
