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22#ifndef __XGENE_ENET_MAIN_H__
23#define __XGENE_ENET_MAIN_H__
24
25#include <linux/acpi.h>
26#include <linux/clk.h>
27#include <linux/efi.h>
28#include <linux/irq.h>
29#include <linux/io.h>
30#include <linux/of_platform.h>
31#include <linux/of_net.h>
32#include <linux/of_mdio.h>
33#include <linux/module.h>
34#include <net/ip.h>
35#include <linux/prefetch.h>
36#include <linux/if_vlan.h>
37#include <linux/phy.h>
38#include "xgene_enet_hw.h"
39#include "xgene_enet_cle.h"
40#include "xgene_enet_ring2.h"
41
42#define XGENE_DRV_VERSION "v1.0"
43#define XGENE_ENET_MAX_MTU 1536
44#define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
45#define BUFLEN_16K (16 * 1024)
46#define NUM_PKT_BUF 64
47#define NUM_BUFPOOL 32
48#define MAX_EXP_BUFFS 256
49#define XGENE_ENET_MSS 1448
50#define XGENE_MIN_ENET_FRAME_SIZE 60
51
52#define XGENE_MAX_ENET_IRQ 16
53#define XGENE_NUM_RX_RING 8
54#define XGENE_NUM_TX_RING 8
55#define XGENE_NUM_TXC_RING 8
56
57#define START_CPU_BUFNUM_0 0
58#define START_ETH_BUFNUM_0 2
59#define START_BP_BUFNUM_0 0x22
60#define START_RING_NUM_0 8
61#define START_CPU_BUFNUM_1 12
62#define START_ETH_BUFNUM_1 10
63#define START_BP_BUFNUM_1 0x2A
64#define START_RING_NUM_1 264
65
66#define XG_START_CPU_BUFNUM_1 12
67#define XG_START_ETH_BUFNUM_1 2
68#define XG_START_BP_BUFNUM_1 0x22
69#define XG_START_RING_NUM_1 264
70
71#define X2_START_CPU_BUFNUM_0 0
72#define X2_START_ETH_BUFNUM_0 0
73#define X2_START_BP_BUFNUM_0 0x20
74#define X2_START_RING_NUM_0 0
75#define X2_START_CPU_BUFNUM_1 0xc
76#define X2_START_ETH_BUFNUM_1 0
77#define X2_START_BP_BUFNUM_1 0x20
78#define X2_START_RING_NUM_1 256
79
80#define IRQ_ID_SIZE 16
81
82#define PHY_POLL_LINK_ON (10 * HZ)
83#define PHY_POLL_LINK_OFF (PHY_POLL_LINK_ON / 5)
84
85enum xgene_enet_id {
86 XGENE_ENET1 = 1,
87 XGENE_ENET2
88};
89
90
91struct xgene_enet_desc_ring {
92 struct net_device *ndev;
93 u16 id;
94 u16 num;
95 u16 head;
96 u16 tail;
97 u16 exp_buf_tail;
98 u16 slots;
99 u16 irq;
100 char irq_name[IRQ_ID_SIZE];
101 u32 size;
102 u32 state[X2_NUM_RING_CONFIG];
103 void __iomem *cmd_base;
104 void __iomem *cmd;
105 dma_addr_t dma;
106 dma_addr_t irq_mbox_dma;
107 void *irq_mbox_addr;
108 u16 dst_ring_num;
109 u8 nbufpool;
110 u8 index;
111 struct sk_buff *(*rx_skb);
112 struct sk_buff *(*cp_skb);
113 dma_addr_t *frag_dma_addr;
114 enum xgene_enet_ring_cfgsize cfgsize;
115 struct xgene_enet_desc_ring *cp_ring;
116 struct xgene_enet_desc_ring *buf_pool;
117 struct napi_struct napi;
118 union {
119 void *desc_addr;
120 struct xgene_enet_raw_desc *raw_desc;
121 struct xgene_enet_raw_desc16 *raw_desc16;
122 };
123 __le64 *exp_bufs;
124 u64 tx_packets;
125 u64 tx_bytes;
126 u64 rx_packets;
127 u64 rx_bytes;
128 u64 rx_dropped;
129 u64 rx_errors;
130 u64 rx_length_errors;
131 u64 rx_crc_errors;
132 u64 rx_frame_errors;
133 u64 rx_fifo_errors;
134};
135
136struct xgene_mac_ops {
137 void (*init)(struct xgene_enet_pdata *pdata);
138 void (*reset)(struct xgene_enet_pdata *pdata);
139 void (*tx_enable)(struct xgene_enet_pdata *pdata);
140 void (*rx_enable)(struct xgene_enet_pdata *pdata);
141 void (*tx_disable)(struct xgene_enet_pdata *pdata);
142 void (*rx_disable)(struct xgene_enet_pdata *pdata);
143 void (*set_mac_addr)(struct xgene_enet_pdata *pdata);
144 void (*set_mss)(struct xgene_enet_pdata *pdata);
145 void (*link_state)(struct work_struct *work);
146};
147
148struct xgene_port_ops {
149 int (*reset)(struct xgene_enet_pdata *pdata);
150 void (*cle_bypass)(struct xgene_enet_pdata *pdata,
151 u32 dst_ring_num, u16 bufpool_id);
152 void (*shutdown)(struct xgene_enet_pdata *pdata);
153};
154
155struct xgene_ring_ops {
156 u8 num_ring_config;
157 u8 num_ring_id_shift;
158 struct xgene_enet_desc_ring * (*setup)(struct xgene_enet_desc_ring *);
159 void (*clear)(struct xgene_enet_desc_ring *);
160 void (*wr_cmd)(struct xgene_enet_desc_ring *, int);
161 u32 (*len)(struct xgene_enet_desc_ring *);
162 void (*coalesce)(struct xgene_enet_desc_ring *);
163};
164
165struct xgene_cle_ops {
166 int (*cle_init)(struct xgene_enet_pdata *pdata);
167};
168
169
170struct xgene_enet_pdata {
171 struct net_device *ndev;
172 struct mii_bus *mdio_bus;
173 struct phy_device *phy_dev;
174 int phy_speed;
175 struct clk *clk;
176 struct platform_device *pdev;
177 enum xgene_enet_id enet_id;
178 struct xgene_enet_desc_ring *tx_ring[XGENE_NUM_TX_RING];
179 struct xgene_enet_desc_ring *rx_ring[XGENE_NUM_RX_RING];
180 u16 tx_level[XGENE_NUM_TX_RING];
181 u16 txc_level[XGENE_NUM_TX_RING];
182 char *dev_name;
183 u32 rx_buff_cnt;
184 u32 tx_qcnt_hi;
185 u32 irqs[XGENE_MAX_ENET_IRQ];
186 u8 rxq_cnt;
187 u8 txq_cnt;
188 u8 cq_cnt;
189 void __iomem *eth_csr_addr;
190 void __iomem *eth_ring_if_addr;
191 void __iomem *eth_diag_csr_addr;
192 void __iomem *mcx_mac_addr;
193 void __iomem *mcx_mac_csr_addr;
194 void __iomem *base_addr;
195 void __iomem *ring_csr_addr;
196 void __iomem *ring_cmd_addr;
197 int phy_mode;
198 enum xgene_enet_rm rm;
199 struct xgene_enet_cle cle;
200 struct rtnl_link_stats64 stats;
201 const struct xgene_mac_ops *mac_ops;
202 const struct xgene_port_ops *port_ops;
203 struct xgene_ring_ops *ring_ops;
204 struct xgene_cle_ops *cle_ops;
205 struct delayed_work link_work;
206 u32 port_id;
207 u8 cpu_bufnum;
208 u8 eth_bufnum;
209 u8 bp_bufnum;
210 u16 ring_num;
211 u32 mss;
212 u8 tx_delay;
213 u8 rx_delay;
214};
215
216struct xgene_indirect_ctl {
217 void __iomem *addr;
218 void __iomem *ctl;
219 void __iomem *cmd;
220 void __iomem *cmd_done;
221};
222
223
224
225
226static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
227{
228 return (val & ((1ULL << len) - 1)) << pos;
229}
230
231#define SET_VAL(field, val) \
232 xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
233
234#define SET_BIT(field) \
235 xgene_enet_set_field_value(field ## _POS, 1, 1)
236
237
238
239
240static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
241{
242 return (src >> pos) & ((1ULL << len) - 1);
243}
244
245#define GET_VAL(field, src) \
246 xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
247
248#define GET_BIT(field, src) \
249 xgene_enet_get_field_value(field ## _POS, 1, src)
250
251static inline struct device *ndev_to_dev(struct net_device *ndev)
252{
253 return ndev->dev.parent;
254}
255
256static inline u16 xgene_enet_dst_ring_num(struct xgene_enet_desc_ring *ring)
257{
258 struct xgene_enet_pdata *pdata = netdev_priv(ring->ndev);
259
260 return ((u16)pdata->rm << 10) | ring->num;
261}
262
263void xgene_enet_set_ethtool_ops(struct net_device *netdev);
264
265#endif
266
