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35#ifndef ALX_HW_H_
36#define ALX_HW_H_
37#include <linux/types.h>
38#include <linux/mdio.h>
39#include <linux/pci.h>
40#include <linux/if_vlan.h>
41#include "reg.h"
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101struct alx_txd {
102 __le16 len;
103 __le16 vlan_tag;
104 __le32 word1;
105 union {
106 __le64 addr;
107 struct {
108 __le32 pkt_len;
109 __le32 resvd;
110 } l;
111 } adrl;
112} __packed;
113
114
115#define TPD_CXSUMSTART_MASK 0x00FF
116#define TPD_CXSUMSTART_SHIFT 0
117#define TPD_L4HDROFFSET_MASK 0x00FF
118#define TPD_L4HDROFFSET_SHIFT 0
119#define TPD_CXSUM_EN_MASK 0x0001
120#define TPD_CXSUM_EN_SHIFT 8
121#define TPD_IP_XSUM_MASK 0x0001
122#define TPD_IP_XSUM_SHIFT 9
123#define TPD_TCP_XSUM_MASK 0x0001
124#define TPD_TCP_XSUM_SHIFT 10
125#define TPD_UDP_XSUM_MASK 0x0001
126#define TPD_UDP_XSUM_SHIFT 11
127#define TPD_LSO_EN_MASK 0x0001
128#define TPD_LSO_EN_SHIFT 12
129#define TPD_LSO_V2_MASK 0x0001
130#define TPD_LSO_V2_SHIFT 13
131#define TPD_VLTAGGED_MASK 0x0001
132#define TPD_VLTAGGED_SHIFT 14
133#define TPD_INS_VLTAG_MASK 0x0001
134#define TPD_INS_VLTAG_SHIFT 15
135#define TPD_IPV4_MASK 0x0001
136#define TPD_IPV4_SHIFT 16
137#define TPD_ETHTYPE_MASK 0x0001
138#define TPD_ETHTYPE_SHIFT 17
139#define TPD_CXSUMOFFSET_MASK 0x00FF
140#define TPD_CXSUMOFFSET_SHIFT 18
141#define TPD_MSS_MASK 0x1FFF
142#define TPD_MSS_SHIFT 18
143#define TPD_EOP_MASK 0x0001
144#define TPD_EOP_SHIFT 31
145
146#define DESC_GET(_x, _name) ((_x) >> _name##SHIFT & _name##MASK)
147
148
149struct alx_rfd {
150 __le64 addr;
151
152
153
154} __packed;
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239struct alx_rrd {
240 __le32 word0;
241 __le32 rss_hash;
242 __le32 word2;
243 __le32 word3;
244} __packed;
245
246
247#define RRD_XSUM_MASK 0xFFFF
248#define RRD_XSUM_SHIFT 0
249#define RRD_NOR_MASK 0x000F
250#define RRD_NOR_SHIFT 16
251#define RRD_SI_MASK 0x0FFF
252#define RRD_SI_SHIFT 20
253
254
255#define RRD_VLTAG_MASK 0xFFFF
256#define RRD_VLTAG_SHIFT 0
257#define RRD_PID_MASK 0x00FF
258#define RRD_PID_SHIFT 16
259
260#define RRD_PID_NONIP 0
261
262#define RRD_PID_IPV4 1
263
264#define RRD_PID_IPV6TCP 2
265
266#define RRD_PID_IPV4TCP 3
267
268#define RRD_PID_IPV6UDP 4
269
270#define RRD_PID_IPV4UDP 5
271
272#define RRD_PID_IPV6 6
273
274#define RRD_PID_LLDP 7
275
276#define RRD_PID_1588 8
277#define RRD_RSSQ_MASK 0x0007
278#define RRD_RSSQ_SHIFT 25
279#define RRD_RSSALG_MASK 0x000F
280#define RRD_RSSALG_SHIFT 28
281#define RRD_RSSALG_TCPV6 0x1
282#define RRD_RSSALG_IPV6 0x2
283#define RRD_RSSALG_TCPV4 0x4
284#define RRD_RSSALG_IPV4 0x8
285
286
287#define RRD_PKTLEN_MASK 0x3FFF
288#define RRD_PKTLEN_SHIFT 0
289#define RRD_ERR_L4_MASK 0x0001
290#define RRD_ERR_L4_SHIFT 14
291#define RRD_ERR_IPV4_MASK 0x0001
292#define RRD_ERR_IPV4_SHIFT 15
293#define RRD_VLTAGGED_MASK 0x0001
294#define RRD_VLTAGGED_SHIFT 16
295#define RRD_OLD_PID_MASK 0x0007
296#define RRD_OLD_PID_SHIFT 17
297#define RRD_ERR_RES_MASK 0x0001
298#define RRD_ERR_RES_SHIFT 20
299#define RRD_ERR_FCS_MASK 0x0001
300#define RRD_ERR_FCS_SHIFT 21
301#define RRD_ERR_FAE_MASK 0x0001
302#define RRD_ERR_FAE_SHIFT 22
303#define RRD_ERR_TRUNC_MASK 0x0001
304#define RRD_ERR_TRUNC_SHIFT 23
305#define RRD_ERR_RUNT_MASK 0x0001
306#define RRD_ERR_RUNT_SHIFT 24
307#define RRD_ERR_ICMP_MASK 0x0001
308#define RRD_ERR_ICMP_SHIFT 25
309#define RRD_BCAST_MASK 0x0001
310#define RRD_BCAST_SHIFT 26
311#define RRD_MCAST_MASK 0x0001
312#define RRD_MCAST_SHIFT 27
313#define RRD_ETHTYPE_MASK 0x0001
314#define RRD_ETHTYPE_SHIFT 28
315#define RRD_ERR_FIFOV_MASK 0x0001
316#define RRD_ERR_FIFOV_SHIFT 29
317#define RRD_ERR_LEN_MASK 0x0001
318#define RRD_ERR_LEN_SHIFT 30
319#define RRD_UPDATED_MASK 0x0001
320#define RRD_UPDATED_SHIFT 31
321
322
323#define ALX_MAX_SETUP_LNK_CYCLE 50
324
325
326#define ALX_FC_RX 0x01
327#define ALX_FC_TX 0x02
328#define ALX_FC_ANEG 0x04
329
330
331#define ALX_SLEEP_WOL_PHY 0x00000001
332#define ALX_SLEEP_WOL_MAGIC 0x00000002
333#define ALX_SLEEP_CIFS 0x00000004
334#define ALX_SLEEP_ACTIVE (ALX_SLEEP_WOL_PHY | \
335 ALX_SLEEP_WOL_MAGIC | \
336 ALX_SLEEP_CIFS)
337
338
339#define ALX_RSS_HASH_TYPE_IPV4 0x1
340#define ALX_RSS_HASH_TYPE_IPV4_TCP 0x2
341#define ALX_RSS_HASH_TYPE_IPV6 0x4
342#define ALX_RSS_HASH_TYPE_IPV6_TCP 0x8
343#define ALX_RSS_HASH_TYPE_ALL (ALX_RSS_HASH_TYPE_IPV4 | \
344 ALX_RSS_HASH_TYPE_IPV4_TCP | \
345 ALX_RSS_HASH_TYPE_IPV6 | \
346 ALX_RSS_HASH_TYPE_IPV6_TCP)
347#define ALX_FRAME_PAD 16
348#define ALX_RAW_MTU(_mtu) (_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
349#define ALX_MAX_FRAME_LEN(_mtu) (ALIGN((ALX_RAW_MTU(_mtu) + ALX_FRAME_PAD), 8))
350#define ALX_DEF_RXBUF_SIZE ALX_MAX_FRAME_LEN(1500)
351#define ALX_MAX_JUMBO_PKT_SIZE (9*1024)
352#define ALX_MAX_TSO_PKT_SIZE (7*1024)
353#define ALX_MAX_FRAME_SIZE ALX_MAX_JUMBO_PKT_SIZE
354#define ALX_MIN_FRAME_SIZE (ETH_ZLEN + ETH_FCS_LEN + VLAN_HLEN)
355
356#define ALX_MAX_RX_QUEUES 8
357#define ALX_MAX_TX_QUEUES 4
358#define ALX_MAX_HANDLED_INTRS 5
359
360#define ALX_ISR_MISC (ALX_ISR_PCIE_LNKDOWN | \
361 ALX_ISR_DMAW | \
362 ALX_ISR_DMAR | \
363 ALX_ISR_SMB | \
364 ALX_ISR_MANU | \
365 ALX_ISR_TIMER)
366
367#define ALX_ISR_FATAL (ALX_ISR_PCIE_LNKDOWN | \
368 ALX_ISR_DMAW | ALX_ISR_DMAR)
369
370#define ALX_ISR_ALERT (ALX_ISR_RXF_OV | \
371 ALX_ISR_TXF_UR | \
372 ALX_ISR_RFD_UR)
373
374#define ALX_ISR_ALL_QUEUES (ALX_ISR_TX_Q0 | \
375 ALX_ISR_TX_Q1 | \
376 ALX_ISR_TX_Q2 | \
377 ALX_ISR_TX_Q3 | \
378 ALX_ISR_RX_Q0 | \
379 ALX_ISR_RX_Q1 | \
380 ALX_ISR_RX_Q2 | \
381 ALX_ISR_RX_Q3 | \
382 ALX_ISR_RX_Q4 | \
383 ALX_ISR_RX_Q5 | \
384 ALX_ISR_RX_Q6 | \
385 ALX_ISR_RX_Q7)
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393struct alx_hw_stats {
394
395 u64 rx_ok;
396 u64 rx_bcast;
397 u64 rx_mcast;
398 u64 rx_pause;
399 u64 rx_ctrl;
400 u64 rx_fcs_err;
401 u64 rx_len_err;
402 u64 rx_byte_cnt;
403 u64 rx_runt;
404 u64 rx_frag;
405 u64 rx_sz_64B;
406 u64 rx_sz_127B;
407 u64 rx_sz_255B;
408 u64 rx_sz_511B;
409 u64 rx_sz_1023B;
410 u64 rx_sz_1518B;
411 u64 rx_sz_max;
412 u64 rx_ov_sz;
413 u64 rx_ov_rxf;
414 u64 rx_ov_rrd;
415 u64 rx_align_err;
416 u64 rx_bc_byte_cnt;
417 u64 rx_mc_byte_cnt;
418 u64 rx_err_addr;
419
420
421 u64 tx_ok;
422 u64 tx_bcast;
423 u64 tx_mcast;
424 u64 tx_pause;
425 u64 tx_exc_defer;
426 u64 tx_ctrl;
427 u64 tx_defer;
428 u64 tx_byte_cnt;
429 u64 tx_sz_64B;
430 u64 tx_sz_127B;
431 u64 tx_sz_255B;
432 u64 tx_sz_511B;
433 u64 tx_sz_1023B;
434 u64 tx_sz_1518B;
435 u64 tx_sz_max;
436 u64 tx_single_col;
437 u64 tx_multi_col;
438 u64 tx_late_col;
439 u64 tx_abort_col;
440 u64 tx_underrun;
441
442
443 u64 tx_trd_eop;
444
445
446 u64 tx_len_err;
447 u64 tx_trunc;
448 u64 tx_bc_byte_cnt;
449 u64 tx_mc_byte_cnt;
450 u64 update;
451};
452
453
454
455#define ALX_MAX_MSIX_INTRS 16
456
457#define ALX_GET_FIELD(_data, _field) \
458 (((_data) >> _field ## _SHIFT) & _field ## _MASK)
459
460#define ALX_SET_FIELD(_data, _field, _value) do { \
461 (_data) &= ~(_field ## _MASK << _field ## _SHIFT); \
462 (_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\
463 } while (0)
464
465struct alx_hw {
466 struct pci_dev *pdev;
467 u8 __iomem *hw_addr;
468
469
470 u8 mac_addr[ETH_ALEN];
471 u8 perm_addr[ETH_ALEN];
472
473 u16 mtu;
474 u16 imt;
475 u8 dma_chnl;
476 u8 max_dma_chnl;
477
478 u32 ith_tpd;
479 u32 rx_ctrl;
480 u32 mc_hash[2];
481
482 u32 smb_timer;
483
484 int link_speed;
485 u8 duplex;
486
487
488 u8 flowctrl;
489 u32 adv_cfg;
490
491 spinlock_t mdio_lock;
492 struct mdio_if_info mdio;
493 u16 phy_id[2];
494
495
496 bool lnk_patch;
497
498
499 struct alx_hw_stats stats;
500};
501
502static inline int alx_hw_revision(struct alx_hw *hw)
503{
504 return hw->pdev->revision >> ALX_PCI_REVID_SHIFT;
505}
506
507static inline bool alx_hw_with_cr(struct alx_hw *hw)
508{
509 return hw->pdev->revision & 1;
510}
511
512static inline bool alx_hw_giga(struct alx_hw *hw)
513{
514 return hw->pdev->device & 1;
515}
516
517static inline void alx_write_mem8(struct alx_hw *hw, u32 reg, u8 val)
518{
519 writeb(val, hw->hw_addr + reg);
520}
521
522static inline void alx_write_mem16(struct alx_hw *hw, u32 reg, u16 val)
523{
524 writew(val, hw->hw_addr + reg);
525}
526
527static inline u16 alx_read_mem16(struct alx_hw *hw, u32 reg)
528{
529 return readw(hw->hw_addr + reg);
530}
531
532static inline void alx_write_mem32(struct alx_hw *hw, u32 reg, u32 val)
533{
534 writel(val, hw->hw_addr + reg);
535}
536
537static inline u32 alx_read_mem32(struct alx_hw *hw, u32 reg)
538{
539 return readl(hw->hw_addr + reg);
540}
541
542static inline void alx_post_write(struct alx_hw *hw)
543{
544 readl(hw->hw_addr);
545}
546
547int alx_get_perm_macaddr(struct alx_hw *hw, u8 *addr);
548void alx_reset_phy(struct alx_hw *hw);
549void alx_reset_pcie(struct alx_hw *hw);
550void alx_enable_aspm(struct alx_hw *hw, bool l0s_en, bool l1_en);
551int alx_setup_speed_duplex(struct alx_hw *hw, u32 ethadv, u8 flowctrl);
552void alx_post_phy_link(struct alx_hw *hw);
553int alx_read_phy_reg(struct alx_hw *hw, u16 reg, u16 *phy_data);
554int alx_write_phy_reg(struct alx_hw *hw, u16 reg, u16 phy_data);
555int alx_read_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 *pdata);
556int alx_write_phy_ext(struct alx_hw *hw, u8 dev, u16 reg, u16 data);
557int alx_read_phy_link(struct alx_hw *hw);
558int alx_clear_phy_intr(struct alx_hw *hw);
559void alx_cfg_mac_flowcontrol(struct alx_hw *hw, u8 fc);
560void alx_start_mac(struct alx_hw *hw);
561int alx_reset_mac(struct alx_hw *hw);
562void alx_set_macaddr(struct alx_hw *hw, const u8 *addr);
563bool alx_phy_configured(struct alx_hw *hw);
564void alx_configure_basic(struct alx_hw *hw);
565void alx_disable_rss(struct alx_hw *hw);
566bool alx_get_phy_info(struct alx_hw *hw);
567void alx_update_hw_stats(struct alx_hw *hw);
568
569static inline u32 alx_speed_to_ethadv(int speed, u8 duplex)
570{
571 if (speed == SPEED_1000 && duplex == DUPLEX_FULL)
572 return ADVERTISED_1000baseT_Full;
573 if (speed == SPEED_100 && duplex == DUPLEX_FULL)
574 return ADVERTISED_100baseT_Full;
575 if (speed == SPEED_100 && duplex== DUPLEX_HALF)
576 return ADVERTISED_100baseT_Half;
577 if (speed == SPEED_10 && duplex == DUPLEX_FULL)
578 return ADVERTISED_10baseT_Full;
579 if (speed == SPEED_10 && duplex == DUPLEX_HALF)
580 return ADVERTISED_10baseT_Half;
581 return 0;
582}
583
584#endif
585