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20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/ethtool.h>
23#include <linux/netdevice.h>
24#include <linux/types.h>
25#include <linux/sched.h>
26#include <linux/crc32.h>
27#include "bnx2x.h"
28#include "bnx2x_cmn.h"
29#include "bnx2x_dump.h"
30#include "bnx2x_init.h"
31
32
33
34
35
36#define MAX_QUEUE_NAME_LEN 4
37static const struct {
38 long offset;
39 int size;
40 char string[ETH_GSTRING_LEN];
41} bnx2x_q_stats_arr[] = {
42 { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
43 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
44 8, "[%s]: rx_ucast_packets" },
45 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
46 8, "[%s]: rx_mcast_packets" },
47 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
48 8, "[%s]: rx_bcast_packets" },
49 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
50 { Q_STATS_OFFSET32(rx_err_discard_pkt),
51 4, "[%s]: rx_phy_ip_err_discards"},
52 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
53 4, "[%s]: rx_skb_alloc_discard" },
54 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
55 { Q_STATS_OFFSET32(driver_xoff), 4, "[%s]: tx_exhaustion_events" },
56 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
57{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
58 8, "[%s]: tx_ucast_packets" },
59 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
60 8, "[%s]: tx_mcast_packets" },
61 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
62 8, "[%s]: tx_bcast_packets" },
63 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
64 8, "[%s]: tpa_aggregations" },
65 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
66 8, "[%s]: tpa_aggregated_frames"},
67 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
68 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
69 4, "[%s]: driver_filtered_tx_pkt" }
70};
71
72#define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
73
74static const struct {
75 long offset;
76 int size;
77 bool is_port_stat;
78 char string[ETH_GSTRING_LEN];
79} bnx2x_stats_arr[] = {
80 { STATS_OFFSET32(total_bytes_received_hi),
81 8, false, "rx_bytes" },
82 { STATS_OFFSET32(error_bytes_received_hi),
83 8, false, "rx_error_bytes" },
84 { STATS_OFFSET32(total_unicast_packets_received_hi),
85 8, false, "rx_ucast_packets" },
86 { STATS_OFFSET32(total_multicast_packets_received_hi),
87 8, false, "rx_mcast_packets" },
88 { STATS_OFFSET32(total_broadcast_packets_received_hi),
89 8, false, "rx_bcast_packets" },
90 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
91 8, true, "rx_crc_errors" },
92 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
93 8, true, "rx_align_errors" },
94 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
95 8, true, "rx_undersize_packets" },
96 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
97 8, true, "rx_oversize_packets" },
98{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
99 8, true, "rx_fragments" },
100 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
101 8, true, "rx_jabbers" },
102 { STATS_OFFSET32(no_buff_discard_hi),
103 8, false, "rx_discards" },
104 { STATS_OFFSET32(mac_filter_discard),
105 4, true, "rx_filtered_packets" },
106 { STATS_OFFSET32(mf_tag_discard),
107 4, true, "rx_mf_tag_discard" },
108 { STATS_OFFSET32(pfc_frames_received_hi),
109 8, true, "pfc_frames_received" },
110 { STATS_OFFSET32(pfc_frames_sent_hi),
111 8, true, "pfc_frames_sent" },
112 { STATS_OFFSET32(brb_drop_hi),
113 8, true, "rx_brb_discard" },
114 { STATS_OFFSET32(brb_truncate_hi),
115 8, true, "rx_brb_truncate" },
116 { STATS_OFFSET32(pause_frames_received_hi),
117 8, true, "rx_pause_frames" },
118 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
119 8, true, "rx_mac_ctrl_frames" },
120 { STATS_OFFSET32(nig_timer_max),
121 4, true, "rx_constant_pause_events" },
122{ STATS_OFFSET32(rx_err_discard_pkt),
123 4, false, "rx_phy_ip_err_discards"},
124 { STATS_OFFSET32(rx_skb_alloc_failed),
125 4, false, "rx_skb_alloc_discard" },
126 { STATS_OFFSET32(hw_csum_err),
127 4, false, "rx_csum_offload_errors" },
128 { STATS_OFFSET32(driver_xoff),
129 4, false, "tx_exhaustion_events" },
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, false, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, true, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, false, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, false, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, false, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, true, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, true, "tx_carrier_errors" },
144{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, true, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, true, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, true, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, true, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, true, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, true, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, true, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, true, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, true, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, true, "tx_256_to_511_byte_packets" },
164{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, true, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, true, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, true, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
171 8, true, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, false, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, false, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
177 8, false, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, false, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, false, "unrecoverable_errors" },
182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, false, "driver_filtered_tx_pkt" },
184 { STATS_OFFSET32(eee_tx_lpi),
185 4, true, "Tx LPI entry count"}
186};
187
188#define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
189
190static int bnx2x_get_port_type(struct bnx2x *bp)
191{
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217}
218
219static int bnx2x_get_vf_settings(struct net_device *dev,
220 struct ethtool_cmd *cmd)
221{
222 struct bnx2x *bp = netdev_priv(dev);
223
224 if (bp->state == BNX2X_STATE_OPEN) {
225 if (test_bit(BNX2X_LINK_REPORT_FD,
226 &bp->vf_link_vars.link_report_flags))
227 cmd->duplex = DUPLEX_FULL;
228 else
229 cmd->duplex = DUPLEX_HALF;
230
231 ethtool_cmd_speed_set(cmd, bp->vf_link_vars.line_speed);
232 } else {
233 cmd->duplex = DUPLEX_UNKNOWN;
234 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
235 }
236
237 cmd->port = PORT_OTHER;
238 cmd->phy_address = 0;
239 cmd->transceiver = XCVR_INTERNAL;
240 cmd->autoneg = AUTONEG_DISABLE;
241 cmd->maxtxpkt = 0;
242 cmd->maxrxpkt = 0;
243
244 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
245 " supported 0x%x advertising 0x%x speed %u\n"
246 " duplex %d port %d phy_address %d transceiver %d\n"
247 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
248 cmd->cmd, cmd->supported, cmd->advertising,
249 ethtool_cmd_speed(cmd),
250 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
251 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
252
253 return 0;
254}
255
256static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
257{
258 struct bnx2x *bp = netdev_priv(dev);
259 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
260 u32 media_type;
261
262
263 cmd->supported = bp->port.supported[cfg_idx] |
264 (bp->port.supported[cfg_idx ^ 1] &
265 (SUPPORTED_TP | SUPPORTED_FIBRE));
266 cmd->advertising = bp->port.advertising[cfg_idx];
267 media_type = bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type;
268 if (media_type == ETH_PHY_SFP_1G_FIBER) {
269 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
270 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
271 }
272
273 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
274 !(bp->flags & MF_FUNC_DIS)) {
275 cmd->duplex = bp->link_vars.duplex;
276
277 if (IS_MF(bp) && !BP_NOMCP(bp))
278 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
279 else
280 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
281 } else {
282 cmd->duplex = DUPLEX_UNKNOWN;
283 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
284 }
285
286 cmd->port = bnx2x_get_port_type(bp);
287
288 cmd->phy_address = bp->mdio.prtad;
289 cmd->transceiver = XCVR_INTERNAL;
290
291 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
292 cmd->autoneg = AUTONEG_ENABLE;
293 else
294 cmd->autoneg = AUTONEG_DISABLE;
295
296
297 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
298 u32 status = bp->link_vars.link_status;
299
300 cmd->lp_advertising |= ADVERTISED_Autoneg;
301 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
302 cmd->lp_advertising |= ADVERTISED_Pause;
303 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
304 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
305
306 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
307 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
308 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
309 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
310 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
311 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
312 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
313 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
314 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
315 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
316 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) {
317 if (media_type == ETH_PHY_KR) {
318 cmd->lp_advertising |=
319 ADVERTISED_1000baseKX_Full;
320 } else {
321 cmd->lp_advertising |=
322 ADVERTISED_1000baseT_Full;
323 }
324 }
325 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
326 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
327 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE) {
328 if (media_type == ETH_PHY_KR) {
329 cmd->lp_advertising |=
330 ADVERTISED_10000baseKR_Full;
331 } else {
332 cmd->lp_advertising |=
333 ADVERTISED_10000baseT_Full;
334 }
335 }
336 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
337 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
338 }
339
340 cmd->maxtxpkt = 0;
341 cmd->maxrxpkt = 0;
342
343 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
344 " supported 0x%x advertising 0x%x speed %u\n"
345 " duplex %d port %d phy_address %d transceiver %d\n"
346 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
347 cmd->cmd, cmd->supported, cmd->advertising,
348 ethtool_cmd_speed(cmd),
349 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
350 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
351
352 return 0;
353}
354
355static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
356{
357 struct bnx2x *bp = netdev_priv(dev);
358 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
359 u32 speed, phy_idx;
360
361 if (IS_MF_SD(bp))
362 return 0;
363
364 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
365 " supported 0x%x advertising 0x%x speed %u\n"
366 " duplex %d port %d phy_address %d transceiver %d\n"
367 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
368 cmd->cmd, cmd->supported, cmd->advertising,
369 ethtool_cmd_speed(cmd),
370 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
371 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
372
373 speed = ethtool_cmd_speed(cmd);
374
375
376 if (cmd->duplex == DUPLEX_UNKNOWN)
377 cmd->duplex = DUPLEX_FULL;
378
379 if (IS_MF_SI(bp)) {
380 u32 part;
381 u32 line_speed = bp->link_vars.line_speed;
382
383
384 if (!line_speed)
385 line_speed = 10000;
386
387 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
388 DP(BNX2X_MSG_ETHTOOL,
389 "To set speed BC %X or higher is required, please upgrade BC\n",
390 REQ_BC_VER_4_SET_MF_BW);
391 return -EINVAL;
392 }
393
394 part = (speed * 100) / line_speed;
395
396 if (line_speed < speed || !part) {
397 DP(BNX2X_MSG_ETHTOOL,
398 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
399 return -EINVAL;
400 }
401
402 if (bp->state != BNX2X_STATE_OPEN)
403
404 bp->pending_max = part;
405 else
406 bnx2x_update_max_mf_config(bp, part);
407
408 return 0;
409 }
410
411 cfg_idx = bnx2x_get_link_cfg_idx(bp);
412 old_multi_phy_config = bp->link_params.multi_phy_config;
413 if (cmd->port != bnx2x_get_port_type(bp)) {
414 switch (cmd->port) {
415 case PORT_TP:
416 if (!(bp->port.supported[0] & SUPPORTED_TP ||
417 bp->port.supported[1] & SUPPORTED_TP)) {
418 DP(BNX2X_MSG_ETHTOOL,
419 "Unsupported port type\n");
420 return -EINVAL;
421 }
422 bp->link_params.multi_phy_config &=
423 ~PORT_HW_CFG_PHY_SELECTION_MASK;
424 if (bp->link_params.multi_phy_config &
425 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
426 bp->link_params.multi_phy_config |=
427 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
428 else
429 bp->link_params.multi_phy_config |=
430 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
431 break;
432 case PORT_FIBRE:
433 case PORT_DA:
434 case PORT_NONE:
435 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
436 bp->port.supported[1] & SUPPORTED_FIBRE)) {
437 DP(BNX2X_MSG_ETHTOOL,
438 "Unsupported port type\n");
439 return -EINVAL;
440 }
441 bp->link_params.multi_phy_config &=
442 ~PORT_HW_CFG_PHY_SELECTION_MASK;
443 if (bp->link_params.multi_phy_config &
444 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
445 bp->link_params.multi_phy_config |=
446 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
447 else
448 bp->link_params.multi_phy_config |=
449 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
450 break;
451 default:
452 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
453 return -EINVAL;
454 }
455 }
456
457 new_multi_phy_config = bp->link_params.multi_phy_config;
458
459 cfg_idx = bnx2x_get_link_cfg_idx(bp);
460
461 bp->link_params.multi_phy_config = old_multi_phy_config;
462 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
463
464 if (cmd->autoneg == AUTONEG_ENABLE) {
465 u32 an_supported_speed = bp->port.supported[cfg_idx];
466 if (bp->link_params.phy[EXT_PHY1].type ==
467 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
468 an_supported_speed |= (SUPPORTED_100baseT_Half |
469 SUPPORTED_100baseT_Full);
470 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
471 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
472 return -EINVAL;
473 }
474
475
476 if (cmd->advertising & ~an_supported_speed) {
477 DP(BNX2X_MSG_ETHTOOL,
478 "Advertisement parameters are not supported\n");
479 return -EINVAL;
480 }
481
482 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
483 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
484 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
485 cmd->advertising);
486 if (cmd->advertising) {
487
488 bp->link_params.speed_cap_mask[cfg_idx] = 0;
489 if (cmd->advertising & ADVERTISED_10baseT_Half) {
490 bp->link_params.speed_cap_mask[cfg_idx] |=
491 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
492 }
493 if (cmd->advertising & ADVERTISED_10baseT_Full)
494 bp->link_params.speed_cap_mask[cfg_idx] |=
495 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
496
497 if (cmd->advertising & ADVERTISED_100baseT_Full)
498 bp->link_params.speed_cap_mask[cfg_idx] |=
499 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
500
501 if (cmd->advertising & ADVERTISED_100baseT_Half) {
502 bp->link_params.speed_cap_mask[cfg_idx] |=
503 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
504 }
505 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
506 bp->link_params.speed_cap_mask[cfg_idx] |=
507 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
508 }
509 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
510 ADVERTISED_1000baseKX_Full))
511 bp->link_params.speed_cap_mask[cfg_idx] |=
512 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
513
514 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
515 ADVERTISED_10000baseKX4_Full |
516 ADVERTISED_10000baseKR_Full))
517 bp->link_params.speed_cap_mask[cfg_idx] |=
518 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
519
520 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
521 bp->link_params.speed_cap_mask[cfg_idx] |=
522 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
523 }
524 } else {
525
526 switch (speed) {
527 case SPEED_10:
528 if (cmd->duplex == DUPLEX_FULL) {
529 if (!(bp->port.supported[cfg_idx] &
530 SUPPORTED_10baseT_Full)) {
531 DP(BNX2X_MSG_ETHTOOL,
532 "10M full not supported\n");
533 return -EINVAL;
534 }
535
536 advertising = (ADVERTISED_10baseT_Full |
537 ADVERTISED_TP);
538 } else {
539 if (!(bp->port.supported[cfg_idx] &
540 SUPPORTED_10baseT_Half)) {
541 DP(BNX2X_MSG_ETHTOOL,
542 "10M half not supported\n");
543 return -EINVAL;
544 }
545
546 advertising = (ADVERTISED_10baseT_Half |
547 ADVERTISED_TP);
548 }
549 break;
550
551 case SPEED_100:
552 if (cmd->duplex == DUPLEX_FULL) {
553 if (!(bp->port.supported[cfg_idx] &
554 SUPPORTED_100baseT_Full)) {
555 DP(BNX2X_MSG_ETHTOOL,
556 "100M full not supported\n");
557 return -EINVAL;
558 }
559
560 advertising = (ADVERTISED_100baseT_Full |
561 ADVERTISED_TP);
562 } else {
563 if (!(bp->port.supported[cfg_idx] &
564 SUPPORTED_100baseT_Half)) {
565 DP(BNX2X_MSG_ETHTOOL,
566 "100M half not supported\n");
567 return -EINVAL;
568 }
569
570 advertising = (ADVERTISED_100baseT_Half |
571 ADVERTISED_TP);
572 }
573 break;
574
575 case SPEED_1000:
576 if (cmd->duplex != DUPLEX_FULL) {
577 DP(BNX2X_MSG_ETHTOOL,
578 "1G half not supported\n");
579 return -EINVAL;
580 }
581
582 if (bp->port.supported[cfg_idx] &
583 SUPPORTED_1000baseT_Full) {
584 advertising = (ADVERTISED_1000baseT_Full |
585 ADVERTISED_TP);
586
587 } else if (bp->port.supported[cfg_idx] &
588 SUPPORTED_1000baseKX_Full) {
589 advertising = ADVERTISED_1000baseKX_Full;
590 } else {
591 DP(BNX2X_MSG_ETHTOOL,
592 "1G full not supported\n");
593 return -EINVAL;
594 }
595
596 break;
597
598 case SPEED_2500:
599 if (cmd->duplex != DUPLEX_FULL) {
600 DP(BNX2X_MSG_ETHTOOL,
601 "2.5G half not supported\n");
602 return -EINVAL;
603 }
604
605 if (!(bp->port.supported[cfg_idx]
606 & SUPPORTED_2500baseX_Full)) {
607 DP(BNX2X_MSG_ETHTOOL,
608 "2.5G full not supported\n");
609 return -EINVAL;
610 }
611
612 advertising = (ADVERTISED_2500baseX_Full |
613 ADVERTISED_TP);
614 break;
615
616 case SPEED_10000:
617 if (cmd->duplex != DUPLEX_FULL) {
618 DP(BNX2X_MSG_ETHTOOL,
619 "10G half not supported\n");
620 return -EINVAL;
621 }
622 phy_idx = bnx2x_get_cur_phy_idx(bp);
623 if ((bp->port.supported[cfg_idx] &
624 SUPPORTED_10000baseT_Full) &&
625 (bp->link_params.phy[phy_idx].media_type !=
626 ETH_PHY_SFP_1G_FIBER)) {
627 advertising = (ADVERTISED_10000baseT_Full |
628 ADVERTISED_FIBRE);
629 } else if (bp->port.supported[cfg_idx] &
630 SUPPORTED_10000baseKR_Full) {
631 advertising = (ADVERTISED_10000baseKR_Full |
632 ADVERTISED_FIBRE);
633 } else {
634 DP(BNX2X_MSG_ETHTOOL,
635 "10G full not supported\n");
636 return -EINVAL;
637 }
638
639 break;
640
641 default:
642 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
643 return -EINVAL;
644 }
645
646 bp->link_params.req_line_speed[cfg_idx] = speed;
647 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
648 bp->port.advertising[cfg_idx] = advertising;
649 }
650
651 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
652 " req_duplex %d advertising 0x%x\n",
653 bp->link_params.req_line_speed[cfg_idx],
654 bp->link_params.req_duplex[cfg_idx],
655 bp->port.advertising[cfg_idx]);
656
657
658 bp->link_params.multi_phy_config = new_multi_phy_config;
659 if (netif_running(dev)) {
660 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
661 bnx2x_force_link_reset(bp);
662 bnx2x_link_set(bp);
663 }
664
665 return 0;
666}
667
668#define DUMP_ALL_PRESETS 0x1FFF
669#define DUMP_MAX_PRESETS 13
670
671static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
672{
673 if (CHIP_IS_E1(bp))
674 return dump_num_registers[0][preset-1];
675 else if (CHIP_IS_E1H(bp))
676 return dump_num_registers[1][preset-1];
677 else if (CHIP_IS_E2(bp))
678 return dump_num_registers[2][preset-1];
679 else if (CHIP_IS_E3A0(bp))
680 return dump_num_registers[3][preset-1];
681 else if (CHIP_IS_E3B0(bp))
682 return dump_num_registers[4][preset-1];
683 else
684 return 0;
685}
686
687static int __bnx2x_get_regs_len(struct bnx2x *bp)
688{
689 u32 preset_idx;
690 int regdump_len = 0;
691
692
693 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
694 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
695
696 return regdump_len;
697}
698
699static int bnx2x_get_regs_len(struct net_device *dev)
700{
701 struct bnx2x *bp = netdev_priv(dev);
702 int regdump_len = 0;
703
704 if (IS_VF(bp))
705 return 0;
706
707 regdump_len = __bnx2x_get_regs_len(bp);
708 regdump_len *= 4;
709 regdump_len += sizeof(struct dump_header);
710
711 return regdump_len;
712}
713
714#define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
715#define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
716#define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
717#define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
718#define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
719
720#define IS_REG_IN_PRESET(presets, idx) \
721 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
722
723
724static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
725{
726 if (CHIP_IS_E2(bp))
727 return page_vals_e2;
728 else if (CHIP_IS_E3(bp))
729 return page_vals_e3;
730 else
731 return NULL;
732}
733
734static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
735{
736 if (CHIP_IS_E2(bp))
737 return PAGE_MODE_VALUES_E2;
738 else if (CHIP_IS_E3(bp))
739 return PAGE_MODE_VALUES_E3;
740 else
741 return 0;
742}
743
744static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
745{
746 if (CHIP_IS_E2(bp))
747 return page_write_regs_e2;
748 else if (CHIP_IS_E3(bp))
749 return page_write_regs_e3;
750 else
751 return NULL;
752}
753
754static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
755{
756 if (CHIP_IS_E2(bp))
757 return PAGE_WRITE_REGS_E2;
758 else if (CHIP_IS_E3(bp))
759 return PAGE_WRITE_REGS_E3;
760 else
761 return 0;
762}
763
764static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
765{
766 if (CHIP_IS_E2(bp))
767 return page_read_regs_e2;
768 else if (CHIP_IS_E3(bp))
769 return page_read_regs_e3;
770 else
771 return NULL;
772}
773
774static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
775{
776 if (CHIP_IS_E2(bp))
777 return PAGE_READ_REGS_E2;
778 else if (CHIP_IS_E3(bp))
779 return PAGE_READ_REGS_E3;
780 else
781 return 0;
782}
783
784static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
785 const struct reg_addr *reg_info)
786{
787 if (CHIP_IS_E1(bp))
788 return IS_E1_REG(reg_info->chips);
789 else if (CHIP_IS_E1H(bp))
790 return IS_E1H_REG(reg_info->chips);
791 else if (CHIP_IS_E2(bp))
792 return IS_E2_REG(reg_info->chips);
793 else if (CHIP_IS_E3A0(bp))
794 return IS_E3A0_REG(reg_info->chips);
795 else if (CHIP_IS_E3B0(bp))
796 return IS_E3B0_REG(reg_info->chips);
797 else
798 return false;
799}
800
801static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
802 const struct wreg_addr *wreg_info)
803{
804 if (CHIP_IS_E1(bp))
805 return IS_E1_REG(wreg_info->chips);
806 else if (CHIP_IS_E1H(bp))
807 return IS_E1H_REG(wreg_info->chips);
808 else if (CHIP_IS_E2(bp))
809 return IS_E2_REG(wreg_info->chips);
810 else if (CHIP_IS_E3A0(bp))
811 return IS_E3A0_REG(wreg_info->chips);
812 else if (CHIP_IS_E3B0(bp))
813 return IS_E3B0_REG(wreg_info->chips);
814 else
815 return false;
816}
817
818
819
820
821
822
823
824
825
826
827
828
829static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
830{
831 u32 i, j, k, n;
832
833
834 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
835
836 int num_pages = __bnx2x_get_page_reg_num(bp);
837
838 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
839
840 int write_num = __bnx2x_get_page_write_num(bp);
841
842 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
843
844 int read_num = __bnx2x_get_page_read_num(bp);
845 u32 addr, size;
846
847 for (i = 0; i < num_pages; i++) {
848 for (j = 0; j < write_num; j++) {
849 REG_WR(bp, write_addr[j], page_addr[i]);
850
851 for (k = 0; k < read_num; k++) {
852 if (IS_REG_IN_PRESET(read_addr[k].presets,
853 preset)) {
854 size = read_addr[k].size;
855 for (n = 0; n < size; n++) {
856 addr = read_addr[k].addr + n*4;
857 *p++ = REG_RD(bp, addr);
858 }
859 }
860 }
861 }
862 }
863}
864
865static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
866{
867 u32 i, j, addr;
868 const struct wreg_addr *wreg_addr_p = NULL;
869
870 if (CHIP_IS_E1(bp))
871 wreg_addr_p = &wreg_addr_e1;
872 else if (CHIP_IS_E1H(bp))
873 wreg_addr_p = &wreg_addr_e1h;
874 else if (CHIP_IS_E2(bp))
875 wreg_addr_p = &wreg_addr_e2;
876 else if (CHIP_IS_E3A0(bp))
877 wreg_addr_p = &wreg_addr_e3;
878 else if (CHIP_IS_E3B0(bp))
879 wreg_addr_p = &wreg_addr_e3b0;
880
881
882 for (i = 0; i < IDLE_REGS_COUNT; i++) {
883 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
884 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
885 for (j = 0; j < idle_reg_addrs[i].size; j++)
886 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
887 }
888 }
889
890
891 for (i = 0; i < REGS_COUNT; i++) {
892 if (bnx2x_is_reg_in_chip(bp, ®_addrs[i]) &&
893 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
894 for (j = 0; j < reg_addrs[i].size; j++)
895 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
896 }
897 }
898
899
900 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
901 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
902 for (i = 0; i < wreg_addr_p->size; i++) {
903 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
904
905
906
907
908 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
909 addr = *(wreg_addr_p->read_regs);
910 *p++ = REG_RD(bp, addr + j*4);
911 }
912 }
913 }
914
915
916 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
917
918 bnx2x_read_pages_regs(bp, p, preset);
919 }
920
921 return 0;
922}
923
924static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
925{
926 u32 preset_idx;
927
928
929 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
930
931 if ((preset_idx == 2) ||
932 (preset_idx == 5) ||
933 (preset_idx == 8) ||
934 (preset_idx == 11))
935 continue;
936 __bnx2x_get_preset_regs(bp, p, preset_idx);
937 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
938 }
939}
940
941static void bnx2x_get_regs(struct net_device *dev,
942 struct ethtool_regs *regs, void *_p)
943{
944 u32 *p = _p;
945 struct bnx2x *bp = netdev_priv(dev);
946 struct dump_header dump_hdr = {0};
947
948 regs->version = 2;
949 memset(p, 0, regs->len);
950
951 if (!netif_running(bp->dev))
952 return;
953
954
955
956
957
958
959 bnx2x_disable_blocks_parity(bp);
960
961 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
962 dump_hdr.preset = DUMP_ALL_PRESETS;
963 dump_hdr.version = BNX2X_DUMP_VERSION;
964
965
966 if (CHIP_IS_E1(bp)) {
967 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
968 } else if (CHIP_IS_E1H(bp)) {
969 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
970 } else if (CHIP_IS_E2(bp)) {
971 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
972 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
973 } else if (CHIP_IS_E3A0(bp)) {
974 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
975 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
976 } else if (CHIP_IS_E3B0(bp)) {
977 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
978 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
979 }
980
981 memcpy(p, &dump_hdr, sizeof(struct dump_header));
982 p += dump_hdr.header_size + 1;
983
984
985
986
987 BNX2X_ERR("Generating register dump. Might trigger harmless GRC timeouts\n");
988
989
990 __bnx2x_get_regs(bp, p);
991
992
993 bnx2x_clear_blocks_parity(bp);
994 bnx2x_enable_blocks_parity(bp);
995}
996
997static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
998{
999 struct bnx2x *bp = netdev_priv(dev);
1000 int regdump_len = 0;
1001
1002 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
1003 regdump_len *= 4;
1004 regdump_len += sizeof(struct dump_header);
1005
1006 return regdump_len;
1007}
1008
1009static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
1010{
1011 struct bnx2x *bp = netdev_priv(dev);
1012
1013
1014 if (val->flag < 1 || val->flag > DUMP_MAX_PRESETS)
1015 return -EINVAL;
1016
1017 bp->dump_preset_idx = val->flag;
1018 return 0;
1019}
1020
1021static int bnx2x_get_dump_flag(struct net_device *dev,
1022 struct ethtool_dump *dump)
1023{
1024 struct bnx2x *bp = netdev_priv(dev);
1025
1026 dump->version = BNX2X_DUMP_VERSION;
1027 dump->flag = bp->dump_preset_idx;
1028
1029 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
1030 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
1031 bp->dump_preset_idx, dump->len);
1032 return 0;
1033}
1034
1035static int bnx2x_get_dump_data(struct net_device *dev,
1036 struct ethtool_dump *dump,
1037 void *buffer)
1038{
1039 u32 *p = buffer;
1040 struct bnx2x *bp = netdev_priv(dev);
1041 struct dump_header dump_hdr = {0};
1042
1043
1044
1045
1046
1047
1048 bnx2x_disable_blocks_parity(bp);
1049
1050 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1051 dump_hdr.preset = bp->dump_preset_idx;
1052 dump_hdr.version = BNX2X_DUMP_VERSION;
1053
1054 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1055
1056
1057 if (CHIP_IS_E1(bp)) {
1058 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1059 } else if (CHIP_IS_E1H(bp)) {
1060 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1061 } else if (CHIP_IS_E2(bp)) {
1062 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1063 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1064 } else if (CHIP_IS_E3A0(bp)) {
1065 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1066 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1067 } else if (CHIP_IS_E3B0(bp)) {
1068 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1069 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1070 }
1071
1072 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1073 p += dump_hdr.header_size + 1;
1074
1075
1076 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1077
1078
1079 bnx2x_clear_blocks_parity(bp);
1080 bnx2x_enable_blocks_parity(bp);
1081
1082 return 0;
1083}
1084
1085static void bnx2x_get_drvinfo(struct net_device *dev,
1086 struct ethtool_drvinfo *info)
1087{
1088 struct bnx2x *bp = netdev_priv(dev);
1089
1090 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1091 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1092
1093 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1094
1095 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1096}
1097
1098static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1099{
1100 struct bnx2x *bp = netdev_priv(dev);
1101
1102 if (bp->flags & NO_WOL_FLAG) {
1103 wol->supported = 0;
1104 wol->wolopts = 0;
1105 } else {
1106 wol->supported = WAKE_MAGIC;
1107 if (bp->wol)
1108 wol->wolopts = WAKE_MAGIC;
1109 else
1110 wol->wolopts = 0;
1111 }
1112 memset(&wol->sopass, 0, sizeof(wol->sopass));
1113}
1114
1115static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1116{
1117 struct bnx2x *bp = netdev_priv(dev);
1118
1119 if (wol->wolopts & ~WAKE_MAGIC) {
1120 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1121 return -EINVAL;
1122 }
1123
1124 if (wol->wolopts & WAKE_MAGIC) {
1125 if (bp->flags & NO_WOL_FLAG) {
1126 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1127 return -EINVAL;
1128 }
1129 bp->wol = 1;
1130 } else
1131 bp->wol = 0;
1132
1133 if (SHMEM2_HAS(bp, curr_cfg))
1134 SHMEM2_WR(bp, curr_cfg, CURR_CFG_MET_OS);
1135
1136 return 0;
1137}
1138
1139static u32 bnx2x_get_msglevel(struct net_device *dev)
1140{
1141 struct bnx2x *bp = netdev_priv(dev);
1142
1143 return bp->msg_enable;
1144}
1145
1146static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1147{
1148 struct bnx2x *bp = netdev_priv(dev);
1149
1150 if (capable(CAP_NET_ADMIN)) {
1151
1152 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1153 bnx2x_fw_dump_lvl(bp, KERN_INFO);
1154 bp->msg_enable = level;
1155 }
1156}
1157
1158static int bnx2x_nway_reset(struct net_device *dev)
1159{
1160 struct bnx2x *bp = netdev_priv(dev);
1161
1162 if (!bp->port.pmf)
1163 return 0;
1164
1165 if (netif_running(dev)) {
1166 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1167 bnx2x_force_link_reset(bp);
1168 bnx2x_link_set(bp);
1169 }
1170
1171 return 0;
1172}
1173
1174static u32 bnx2x_get_link(struct net_device *dev)
1175{
1176 struct bnx2x *bp = netdev_priv(dev);
1177
1178 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1179 return 0;
1180
1181 if (IS_VF(bp))
1182 return !test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1183 &bp->vf_link_vars.link_report_flags);
1184
1185 return bp->link_vars.link_up;
1186}
1187
1188static int bnx2x_get_eeprom_len(struct net_device *dev)
1189{
1190 struct bnx2x *bp = netdev_priv(dev);
1191
1192 return bp->common.flash_size;
1193}
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1209{
1210 int port = BP_PORT(bp);
1211 int count, i;
1212 u32 val;
1213
1214
1215 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1216
1217
1218 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1219 if (CHIP_REV_IS_SLOW(bp))
1220 count *= 100;
1221
1222
1223 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1224 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1225
1226 for (i = 0; i < count*10; i++) {
1227 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1228 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1229 break;
1230
1231 udelay(5);
1232 }
1233
1234 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1235 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1236 "cannot get access to nvram interface\n");
1237 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1238 return -EBUSY;
1239 }
1240
1241 return 0;
1242}
1243
1244static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1245{
1246 int port = BP_PORT(bp);
1247 int count, i;
1248 u32 val;
1249
1250
1251 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1252 if (CHIP_REV_IS_SLOW(bp))
1253 count *= 100;
1254
1255
1256 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1257 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1258
1259 for (i = 0; i < count*10; i++) {
1260 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1261 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1262 break;
1263
1264 udelay(5);
1265 }
1266
1267 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1268 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1269 "cannot free access to nvram interface\n");
1270 return -EBUSY;
1271 }
1272
1273
1274 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1275 return 0;
1276}
1277
1278static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1279{
1280 u32 val;
1281
1282 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1283
1284
1285 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1286 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1287 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1288}
1289
1290static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1291{
1292 u32 val;
1293
1294 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1295
1296
1297 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1298 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1299 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1300}
1301
1302static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1303 u32 cmd_flags)
1304{
1305 int count, i, rc;
1306 u32 val;
1307
1308
1309 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1310
1311
1312 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1313
1314
1315 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1316 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1317
1318
1319 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1320
1321
1322 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1323 if (CHIP_REV_IS_SLOW(bp))
1324 count *= 100;
1325
1326
1327 *ret_val = 0;
1328 rc = -EBUSY;
1329 for (i = 0; i < count; i++) {
1330 udelay(5);
1331 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1332
1333 if (val & MCPR_NVM_COMMAND_DONE) {
1334 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1335
1336
1337
1338
1339 *ret_val = cpu_to_be32(val);
1340 rc = 0;
1341 break;
1342 }
1343 }
1344 if (rc == -EBUSY)
1345 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1346 "nvram read timeout expired\n");
1347 return rc;
1348}
1349
1350int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1351 int buf_size)
1352{
1353 int rc;
1354 u32 cmd_flags;
1355 __be32 val;
1356
1357 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1358 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1359 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1360 offset, buf_size);
1361 return -EINVAL;
1362 }
1363
1364 if (offset + buf_size > bp->common.flash_size) {
1365 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1366 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1367 offset, buf_size, bp->common.flash_size);
1368 return -EINVAL;
1369 }
1370
1371
1372 rc = bnx2x_acquire_nvram_lock(bp);
1373 if (rc)
1374 return rc;
1375
1376
1377 bnx2x_enable_nvram_access(bp);
1378
1379
1380 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1381 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1382 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1383 memcpy(ret_buf, &val, 4);
1384
1385
1386 offset += sizeof(u32);
1387 ret_buf += sizeof(u32);
1388 buf_size -= sizeof(u32);
1389 cmd_flags = 0;
1390 }
1391
1392 if (rc == 0) {
1393 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1394 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1395 memcpy(ret_buf, &val, 4);
1396 }
1397
1398
1399 bnx2x_disable_nvram_access(bp);
1400 bnx2x_release_nvram_lock(bp);
1401
1402 return rc;
1403}
1404
1405static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1406 int buf_size)
1407{
1408 int rc;
1409
1410 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1411
1412 if (!rc) {
1413 __be32 *be = (__be32 *)buf;
1414
1415 while ((buf_size -= 4) >= 0)
1416 *buf++ = be32_to_cpu(*be++);
1417 }
1418
1419 return rc;
1420}
1421
1422static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1423{
1424 int rc = 1;
1425 u16 pm = 0;
1426 struct net_device *dev = pci_get_drvdata(bp->pdev);
1427
1428 if (bp->pdev->pm_cap)
1429 rc = pci_read_config_word(bp->pdev,
1430 bp->pdev->pm_cap + PCI_PM_CTRL, &pm);
1431
1432 if ((rc && !netif_running(dev)) ||
1433 (!rc && ((pm & PCI_PM_CTRL_STATE_MASK) != (__force u16)PCI_D0)))
1434 return false;
1435
1436 return true;
1437}
1438
1439static int bnx2x_get_eeprom(struct net_device *dev,
1440 struct ethtool_eeprom *eeprom, u8 *eebuf)
1441{
1442 struct bnx2x *bp = netdev_priv(dev);
1443
1444 if (!bnx2x_is_nvm_accessible(bp)) {
1445 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1446 "cannot access eeprom when the interface is down\n");
1447 return -EAGAIN;
1448 }
1449
1450 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1451 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1452 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1453 eeprom->len, eeprom->len);
1454
1455
1456
1457 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1458}
1459
1460static int bnx2x_get_module_eeprom(struct net_device *dev,
1461 struct ethtool_eeprom *ee,
1462 u8 *data)
1463{
1464 struct bnx2x *bp = netdev_priv(dev);
1465 int rc = -EINVAL, phy_idx;
1466 u8 *user_data = data;
1467 unsigned int start_addr = ee->offset, xfer_size = 0;
1468
1469 if (!bnx2x_is_nvm_accessible(bp)) {
1470 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1471 "cannot access eeprom when the interface is down\n");
1472 return -EAGAIN;
1473 }
1474
1475 phy_idx = bnx2x_get_cur_phy_idx(bp);
1476
1477
1478 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1479
1480 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1481 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1482 else
1483 xfer_size = ee->len;
1484 bnx2x_acquire_phy_lock(bp);
1485 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1486 &bp->link_params,
1487 I2C_DEV_ADDR_A0,
1488 start_addr,
1489 xfer_size,
1490 user_data);
1491 bnx2x_release_phy_lock(bp);
1492 if (rc) {
1493 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1494
1495 return -EINVAL;
1496 }
1497 user_data += xfer_size;
1498 start_addr += xfer_size;
1499 }
1500
1501
1502 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1503 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1504 xfer_size = ee->len - xfer_size;
1505
1506 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1507 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1508 start_addr -= ETH_MODULE_SFF_8079_LEN;
1509 bnx2x_acquire_phy_lock(bp);
1510 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1511 &bp->link_params,
1512 I2C_DEV_ADDR_A2,
1513 start_addr,
1514 xfer_size,
1515 user_data);
1516 bnx2x_release_phy_lock(bp);
1517 if (rc) {
1518 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1519 return -EINVAL;
1520 }
1521 }
1522 return rc;
1523}
1524
1525static int bnx2x_get_module_info(struct net_device *dev,
1526 struct ethtool_modinfo *modinfo)
1527{
1528 struct bnx2x *bp = netdev_priv(dev);
1529 int phy_idx, rc;
1530 u8 sff8472_comp, diag_type;
1531
1532 if (!bnx2x_is_nvm_accessible(bp)) {
1533 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1534 "cannot access eeprom when the interface is down\n");
1535 return -EAGAIN;
1536 }
1537 phy_idx = bnx2x_get_cur_phy_idx(bp);
1538 bnx2x_acquire_phy_lock(bp);
1539 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1540 &bp->link_params,
1541 I2C_DEV_ADDR_A0,
1542 SFP_EEPROM_SFF_8472_COMP_ADDR,
1543 SFP_EEPROM_SFF_8472_COMP_SIZE,
1544 &sff8472_comp);
1545 bnx2x_release_phy_lock(bp);
1546 if (rc) {
1547 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1548 return -EINVAL;
1549 }
1550
1551 bnx2x_acquire_phy_lock(bp);
1552 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1553 &bp->link_params,
1554 I2C_DEV_ADDR_A0,
1555 SFP_EEPROM_DIAG_TYPE_ADDR,
1556 SFP_EEPROM_DIAG_TYPE_SIZE,
1557 &diag_type);
1558 bnx2x_release_phy_lock(bp);
1559 if (rc) {
1560 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1561 return -EINVAL;
1562 }
1563
1564 if (!sff8472_comp ||
1565 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1566 modinfo->type = ETH_MODULE_SFF_8079;
1567 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1568 } else {
1569 modinfo->type = ETH_MODULE_SFF_8472;
1570 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1571 }
1572 return 0;
1573}
1574
1575static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1576 u32 cmd_flags)
1577{
1578 int count, i, rc;
1579
1580
1581 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1582
1583
1584 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1585
1586
1587 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1588
1589
1590 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1591 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1592
1593
1594 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1595
1596
1597 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1598 if (CHIP_REV_IS_SLOW(bp))
1599 count *= 100;
1600
1601
1602 rc = -EBUSY;
1603 for (i = 0; i < count; i++) {
1604 udelay(5);
1605 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1606 if (val & MCPR_NVM_COMMAND_DONE) {
1607 rc = 0;
1608 break;
1609 }
1610 }
1611
1612 if (rc == -EBUSY)
1613 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1614 "nvram write timeout expired\n");
1615 return rc;
1616}
1617
1618#define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1619
1620static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1621 int buf_size)
1622{
1623 int rc;
1624 u32 cmd_flags, align_offset, val;
1625 __be32 val_be;
1626
1627 if (offset + buf_size > bp->common.flash_size) {
1628 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1629 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1630 offset, buf_size, bp->common.flash_size);
1631 return -EINVAL;
1632 }
1633
1634
1635 rc = bnx2x_acquire_nvram_lock(bp);
1636 if (rc)
1637 return rc;
1638
1639
1640 bnx2x_enable_nvram_access(bp);
1641
1642 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1643 align_offset = (offset & ~0x03);
1644 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1645
1646 if (rc == 0) {
1647
1648
1649
1650 val = be32_to_cpu(val_be);
1651
1652 val &= ~le32_to_cpu((__force __le32)
1653 (0xff << BYTE_OFFSET(offset)));
1654 val |= le32_to_cpu((__force __le32)
1655 (*data_buf << BYTE_OFFSET(offset)));
1656
1657 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1658 cmd_flags);
1659 }
1660
1661
1662 bnx2x_disable_nvram_access(bp);
1663 bnx2x_release_nvram_lock(bp);
1664
1665 return rc;
1666}
1667
1668static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1669 int buf_size)
1670{
1671 int rc;
1672 u32 cmd_flags;
1673 u32 val;
1674 u32 written_so_far;
1675
1676 if (buf_size == 1)
1677 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1678
1679 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1680 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1681 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1682 offset, buf_size);
1683 return -EINVAL;
1684 }
1685
1686 if (offset + buf_size > bp->common.flash_size) {
1687 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1688 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1689 offset, buf_size, bp->common.flash_size);
1690 return -EINVAL;
1691 }
1692
1693
1694 rc = bnx2x_acquire_nvram_lock(bp);
1695 if (rc)
1696 return rc;
1697
1698
1699 bnx2x_enable_nvram_access(bp);
1700
1701 written_so_far = 0;
1702 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1703 while ((written_so_far < buf_size) && (rc == 0)) {
1704 if (written_so_far == (buf_size - sizeof(u32)))
1705 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1706 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1707 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1708 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1709 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1710
1711 memcpy(&val, data_buf, 4);
1712
1713
1714
1715
1716
1717
1718
1719 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1720
1721
1722 offset += sizeof(u32);
1723 data_buf += sizeof(u32);
1724 written_so_far += sizeof(u32);
1725
1726
1727
1728
1729 if ((cmd_flags & MCPR_NVM_COMMAND_LAST) &&
1730 (written_so_far < buf_size)) {
1731 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1732 "Releasing NVM lock after offset 0x%x\n",
1733 (u32)(offset - sizeof(u32)));
1734 bnx2x_release_nvram_lock(bp);
1735 usleep_range(1000, 2000);
1736 rc = bnx2x_acquire_nvram_lock(bp);
1737 if (rc)
1738 return rc;
1739 }
1740
1741 cmd_flags = 0;
1742 }
1743
1744
1745 bnx2x_disable_nvram_access(bp);
1746 bnx2x_release_nvram_lock(bp);
1747
1748 return rc;
1749}
1750
1751static int bnx2x_set_eeprom(struct net_device *dev,
1752 struct ethtool_eeprom *eeprom, u8 *eebuf)
1753{
1754 struct bnx2x *bp = netdev_priv(dev);
1755 int port = BP_PORT(bp);
1756 int rc = 0;
1757 u32 ext_phy_config;
1758
1759 if (!bnx2x_is_nvm_accessible(bp)) {
1760 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1761 "cannot access eeprom when the interface is down\n");
1762 return -EAGAIN;
1763 }
1764
1765 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1766 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1767 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1768 eeprom->len, eeprom->len);
1769
1770
1771
1772
1773 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1774 !bp->port.pmf) {
1775 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1776 "wrong magic or interface is not pmf\n");
1777 return -EINVAL;
1778 }
1779
1780 ext_phy_config =
1781 SHMEM_RD(bp,
1782 dev_info.port_hw_config[port].external_phy_config);
1783
1784 if (eeprom->magic == 0x50485950) {
1785
1786 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1787
1788 bnx2x_acquire_phy_lock(bp);
1789 rc |= bnx2x_link_reset(&bp->link_params,
1790 &bp->link_vars, 0);
1791 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1792 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1793 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1794 MISC_REGISTERS_GPIO_HIGH, port);
1795 bnx2x_release_phy_lock(bp);
1796 bnx2x_link_report(bp);
1797
1798 } else if (eeprom->magic == 0x50485952) {
1799
1800 if (bp->state == BNX2X_STATE_OPEN) {
1801 bnx2x_acquire_phy_lock(bp);
1802 rc |= bnx2x_link_reset(&bp->link_params,
1803 &bp->link_vars, 1);
1804
1805 rc |= bnx2x_phy_init(&bp->link_params,
1806 &bp->link_vars);
1807 bnx2x_release_phy_lock(bp);
1808 bnx2x_calc_fc_adv(bp);
1809 }
1810 } else if (eeprom->magic == 0x53985943) {
1811
1812 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1813 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1814
1815
1816 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1817 MISC_REGISTERS_GPIO_LOW, port);
1818
1819 bnx2x_acquire_phy_lock(bp);
1820
1821 bnx2x_sfx7101_sp_sw_reset(bp,
1822 &bp->link_params.phy[EXT_PHY1]);
1823
1824
1825 msleep(500);
1826 bnx2x_ext_phy_hw_reset(bp, port);
1827 msleep(500);
1828 bnx2x_release_phy_lock(bp);
1829 }
1830 } else
1831 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1832
1833 return rc;
1834}
1835
1836static int bnx2x_get_coalesce(struct net_device *dev,
1837 struct ethtool_coalesce *coal)
1838{
1839 struct bnx2x *bp = netdev_priv(dev);
1840
1841 memset(coal, 0, sizeof(struct ethtool_coalesce));
1842
1843 coal->rx_coalesce_usecs = bp->rx_ticks;
1844 coal->tx_coalesce_usecs = bp->tx_ticks;
1845
1846 return 0;
1847}
1848
1849static int bnx2x_set_coalesce(struct net_device *dev,
1850 struct ethtool_coalesce *coal)
1851{
1852 struct bnx2x *bp = netdev_priv(dev);
1853
1854 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1855 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1856 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1857
1858 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1859 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1860 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1861
1862 if (netif_running(dev))
1863 bnx2x_update_coalesce(bp);
1864
1865 return 0;
1866}
1867
1868static void bnx2x_get_ringparam(struct net_device *dev,
1869 struct ethtool_ringparam *ering)
1870{
1871 struct bnx2x *bp = netdev_priv(dev);
1872
1873 ering->rx_max_pending = MAX_RX_AVAIL;
1874
1875 if (bp->rx_ring_size)
1876 ering->rx_pending = bp->rx_ring_size;
1877 else
1878 ering->rx_pending = MAX_RX_AVAIL;
1879
1880 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1881 ering->tx_pending = bp->tx_ring_size;
1882}
1883
1884static int bnx2x_set_ringparam(struct net_device *dev,
1885 struct ethtool_ringparam *ering)
1886{
1887 struct bnx2x *bp = netdev_priv(dev);
1888
1889 DP(BNX2X_MSG_ETHTOOL,
1890 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1891 ering->rx_pending, ering->tx_pending);
1892
1893 if (pci_num_vf(bp->pdev)) {
1894 DP(BNX2X_MSG_IOV,
1895 "VFs are enabled, can not change ring parameters\n");
1896 return -EPERM;
1897 }
1898
1899 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1900 DP(BNX2X_MSG_ETHTOOL,
1901 "Handling parity error recovery. Try again later\n");
1902 return -EAGAIN;
1903 }
1904
1905 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1906 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1907 MIN_RX_SIZE_TPA)) ||
1908 (ering->tx_pending > (IS_MF_STORAGE_ONLY(bp) ? 0 : MAX_TX_AVAIL)) ||
1909 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1910 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1911 return -EINVAL;
1912 }
1913
1914 bp->rx_ring_size = ering->rx_pending;
1915 bp->tx_ring_size = ering->tx_pending;
1916
1917 return bnx2x_reload_if_running(dev);
1918}
1919
1920static void bnx2x_get_pauseparam(struct net_device *dev,
1921 struct ethtool_pauseparam *epause)
1922{
1923 struct bnx2x *bp = netdev_priv(dev);
1924 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1925 int cfg_reg;
1926
1927 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1928 BNX2X_FLOW_CTRL_AUTO);
1929
1930 if (!epause->autoneg)
1931 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1932 else
1933 cfg_reg = bp->link_params.req_fc_auto_adv;
1934
1935 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1936 BNX2X_FLOW_CTRL_RX);
1937 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1938 BNX2X_FLOW_CTRL_TX);
1939
1940 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1941 " autoneg %d rx_pause %d tx_pause %d\n",
1942 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1943}
1944
1945static int bnx2x_set_pauseparam(struct net_device *dev,
1946 struct ethtool_pauseparam *epause)
1947{
1948 struct bnx2x *bp = netdev_priv(dev);
1949 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1950 if (IS_MF(bp))
1951 return 0;
1952
1953 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1954 " autoneg %d rx_pause %d tx_pause %d\n",
1955 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1956
1957 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1958
1959 if (epause->rx_pause)
1960 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1961
1962 if (epause->tx_pause)
1963 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1964
1965 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1966 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1967
1968 if (epause->autoneg) {
1969 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1970 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1971 return -EINVAL;
1972 }
1973
1974 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1975 bp->link_params.req_flow_ctrl[cfg_idx] =
1976 BNX2X_FLOW_CTRL_AUTO;
1977 }
1978 bp->link_params.req_fc_auto_adv = 0;
1979 if (epause->rx_pause)
1980 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1981
1982 if (epause->tx_pause)
1983 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1984
1985 if (!bp->link_params.req_fc_auto_adv)
1986 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1987 }
1988
1989 DP(BNX2X_MSG_ETHTOOL,
1990 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1991
1992 if (netif_running(dev)) {
1993 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1994 bnx2x_force_link_reset(bp);
1995 bnx2x_link_set(bp);
1996 }
1997
1998 return 0;
1999}
2000
2001static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
2002 "register_test (offline) ",
2003 "memory_test (offline) ",
2004 "int_loopback_test (offline)",
2005 "ext_loopback_test (offline)",
2006 "nvram_test (online) ",
2007 "interrupt_test (online) ",
2008 "link_test (online) "
2009};
2010
2011enum {
2012 BNX2X_PRI_FLAG_ISCSI,
2013 BNX2X_PRI_FLAG_FCOE,
2014 BNX2X_PRI_FLAG_STORAGE,
2015 BNX2X_PRI_FLAG_LEN,
2016};
2017
2018static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
2019 "iSCSI offload support",
2020 "FCoE offload support",
2021 "Storage only interface"
2022};
2023
2024static u32 bnx2x_eee_to_adv(u32 eee_adv)
2025{
2026 u32 modes = 0;
2027
2028 if (eee_adv & SHMEM_EEE_100M_ADV)
2029 modes |= ADVERTISED_100baseT_Full;
2030 if (eee_adv & SHMEM_EEE_1G_ADV)
2031 modes |= ADVERTISED_1000baseT_Full;
2032 if (eee_adv & SHMEM_EEE_10G_ADV)
2033 modes |= ADVERTISED_10000baseT_Full;
2034
2035 return modes;
2036}
2037
2038static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
2039{
2040 u32 eee_adv = 0;
2041 if (modes & ADVERTISED_100baseT_Full)
2042 eee_adv |= SHMEM_EEE_100M_ADV;
2043 if (modes & ADVERTISED_1000baseT_Full)
2044 eee_adv |= SHMEM_EEE_1G_ADV;
2045 if (modes & ADVERTISED_10000baseT_Full)
2046 eee_adv |= SHMEM_EEE_10G_ADV;
2047
2048 return eee_adv << shift;
2049}
2050
2051static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
2052{
2053 struct bnx2x *bp = netdev_priv(dev);
2054 u32 eee_cfg;
2055
2056 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2057 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2058 return -EOPNOTSUPP;
2059 }
2060
2061 eee_cfg = bp->link_vars.eee_status;
2062
2063 edata->supported =
2064 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
2065 SHMEM_EEE_SUPPORTED_SHIFT);
2066
2067 edata->advertised =
2068 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
2069 SHMEM_EEE_ADV_STATUS_SHIFT);
2070 edata->lp_advertised =
2071 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2072 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2073
2074
2075 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2076
2077 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2078 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2079 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2080
2081 return 0;
2082}
2083
2084static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2085{
2086 struct bnx2x *bp = netdev_priv(dev);
2087 u32 eee_cfg;
2088 u32 advertised;
2089
2090 if (IS_MF(bp))
2091 return 0;
2092
2093 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2094 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2095 return -EOPNOTSUPP;
2096 }
2097
2098 eee_cfg = bp->link_vars.eee_status;
2099
2100 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2101 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2102 return -EOPNOTSUPP;
2103 }
2104
2105 advertised = bnx2x_adv_to_eee(edata->advertised,
2106 SHMEM_EEE_ADV_STATUS_SHIFT);
2107 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2108 DP(BNX2X_MSG_ETHTOOL,
2109 "Direct manipulation of EEE advertisement is not supported\n");
2110 return -EINVAL;
2111 }
2112
2113 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2114 DP(BNX2X_MSG_ETHTOOL,
2115 "Maximal Tx Lpi timer supported is %x(u)\n",
2116 EEE_MODE_TIMER_MASK);
2117 return -EINVAL;
2118 }
2119 if (edata->tx_lpi_enabled &&
2120 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2121 DP(BNX2X_MSG_ETHTOOL,
2122 "Minimal Tx Lpi timer supported is %d(u)\n",
2123 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2124 return -EINVAL;
2125 }
2126
2127
2128 if (edata->eee_enabled)
2129 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2130 else
2131 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2132
2133 if (edata->tx_lpi_enabled)
2134 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2135 else
2136 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2137
2138 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2139 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2140 EEE_MODE_TIMER_MASK) |
2141 EEE_MODE_OVERRIDE_NVRAM |
2142 EEE_MODE_OUTPUT_TIME;
2143
2144
2145 if (netif_running(dev)) {
2146 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2147 bnx2x_force_link_reset(bp);
2148 bnx2x_link_set(bp);
2149 }
2150
2151 return 0;
2152}
2153
2154enum {
2155 BNX2X_CHIP_E1_OFST = 0,
2156 BNX2X_CHIP_E1H_OFST,
2157 BNX2X_CHIP_E2_OFST,
2158 BNX2X_CHIP_E3_OFST,
2159 BNX2X_CHIP_E3B0_OFST,
2160 BNX2X_CHIP_MAX_OFST
2161};
2162
2163#define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2164#define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2165#define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2166#define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2167#define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2168
2169#define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2170#define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2171
2172static int bnx2x_test_registers(struct bnx2x *bp)
2173{
2174 int idx, i, rc = -ENODEV;
2175 u32 wr_val = 0, hw;
2176 int port = BP_PORT(bp);
2177 static const struct {
2178 u32 hw;
2179 u32 offset0;
2180 u32 offset1;
2181 u32 mask;
2182 } reg_tbl[] = {
2183 { BNX2X_CHIP_MASK_ALL,
2184 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2185 { BNX2X_CHIP_MASK_ALL,
2186 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2187 { BNX2X_CHIP_MASK_E1X,
2188 HC_REG_AGG_INT_0, 4, 0x000003ff },
2189 { BNX2X_CHIP_MASK_ALL,
2190 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2191 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2192 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2193 { BNX2X_CHIP_MASK_E3B0,
2194 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2195 { BNX2X_CHIP_MASK_ALL,
2196 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2197 { BNX2X_CHIP_MASK_ALL,
2198 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2199 { BNX2X_CHIP_MASK_ALL,
2200 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2201 { BNX2X_CHIP_MASK_ALL,
2202 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2203 { BNX2X_CHIP_MASK_ALL,
2204 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2205 { BNX2X_CHIP_MASK_ALL,
2206 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2207 { BNX2X_CHIP_MASK_ALL,
2208 QM_REG_CONNNUM_0, 4, 0x000fffff },
2209 { BNX2X_CHIP_MASK_ALL,
2210 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2211 { BNX2X_CHIP_MASK_ALL,
2212 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2213 { BNX2X_CHIP_MASK_ALL,
2214 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2215 { BNX2X_CHIP_MASK_ALL,
2216 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2217 { BNX2X_CHIP_MASK_ALL,
2218 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2219 { BNX2X_CHIP_MASK_ALL,
2220 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2221 { BNX2X_CHIP_MASK_ALL,
2222 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2223 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2224 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2225 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2226 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2227 { BNX2X_CHIP_MASK_ALL,
2228 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2229 { BNX2X_CHIP_MASK_ALL,
2230 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2231 { BNX2X_CHIP_MASK_ALL,
2232 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2233 { BNX2X_CHIP_MASK_ALL,
2234 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2235 { BNX2X_CHIP_MASK_ALL,
2236 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2237 { BNX2X_CHIP_MASK_ALL,
2238 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2239 { BNX2X_CHIP_MASK_ALL,
2240 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2241 { BNX2X_CHIP_MASK_ALL,
2242 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2243 { BNX2X_CHIP_MASK_ALL,
2244 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2245 { BNX2X_CHIP_MASK_ALL,
2246 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2247 { BNX2X_CHIP_MASK_ALL,
2248 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2249 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2250 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2251 { BNX2X_CHIP_MASK_ALL,
2252 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2253 { BNX2X_CHIP_MASK_ALL,
2254 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2255 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2256 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2257 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2258 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2259
2260 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2261 };
2262
2263 if (!bnx2x_is_nvm_accessible(bp)) {
2264 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2265 "cannot access eeprom when the interface is down\n");
2266 return rc;
2267 }
2268
2269 if (CHIP_IS_E1(bp))
2270 hw = BNX2X_CHIP_MASK_E1;
2271 else if (CHIP_IS_E1H(bp))
2272 hw = BNX2X_CHIP_MASK_E1H;
2273 else if (CHIP_IS_E2(bp))
2274 hw = BNX2X_CHIP_MASK_E2;
2275 else if (CHIP_IS_E3B0(bp))
2276 hw = BNX2X_CHIP_MASK_E3B0;
2277 else
2278 hw = BNX2X_CHIP_MASK_E3;
2279
2280
2281
2282
2283 for (idx = 0; idx < 2; idx++) {
2284
2285 switch (idx) {
2286 case 0:
2287 wr_val = 0;
2288 break;
2289 case 1:
2290 wr_val = 0xffffffff;
2291 break;
2292 }
2293
2294 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2295 u32 offset, mask, save_val, val;
2296 if (!(hw & reg_tbl[i].hw))
2297 continue;
2298
2299 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2300 mask = reg_tbl[i].mask;
2301
2302 save_val = REG_RD(bp, offset);
2303
2304 REG_WR(bp, offset, wr_val & mask);
2305
2306 val = REG_RD(bp, offset);
2307
2308
2309 REG_WR(bp, offset, save_val);
2310
2311
2312 if ((val & mask) != (wr_val & mask)) {
2313 DP(BNX2X_MSG_ETHTOOL,
2314 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2315 offset, val, wr_val, mask);
2316 goto test_reg_exit;
2317 }
2318 }
2319 }
2320
2321 rc = 0;
2322
2323test_reg_exit:
2324 return rc;
2325}
2326
2327static int bnx2x_test_memory(struct bnx2x *bp)
2328{
2329 int i, j, rc = -ENODEV;
2330 u32 val, index;
2331 static const struct {
2332 u32 offset;
2333 int size;
2334 } mem_tbl[] = {
2335 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2336 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2337 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2338 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2339 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2340 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2341 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2342
2343 { 0xffffffff, 0 }
2344 };
2345
2346 static const struct {
2347 char *name;
2348 u32 offset;
2349 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2350 } prty_tbl[] = {
2351 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2352 {0x3ffc0, 0, 0, 0} },
2353 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2354 {0x2, 0x2, 0, 0} },
2355 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2356 {0, 0, 0, 0} },
2357 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2358 {0x3ffc0, 0, 0, 0} },
2359 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2360 {0x3ffc0, 0, 0, 0} },
2361 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2362 {0x3ffc1, 0, 0, 0} },
2363
2364 { NULL, 0xffffffff, {0, 0, 0, 0} }
2365 };
2366
2367 if (!bnx2x_is_nvm_accessible(bp)) {
2368 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2369 "cannot access eeprom when the interface is down\n");
2370 return rc;
2371 }
2372
2373 if (CHIP_IS_E1(bp))
2374 index = BNX2X_CHIP_E1_OFST;
2375 else if (CHIP_IS_E1H(bp))
2376 index = BNX2X_CHIP_E1H_OFST;
2377 else if (CHIP_IS_E2(bp))
2378 index = BNX2X_CHIP_E2_OFST;
2379 else
2380 index = BNX2X_CHIP_E3_OFST;
2381
2382
2383 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2384 val = REG_RD(bp, prty_tbl[i].offset);
2385 if (val & ~(prty_tbl[i].hw_mask[index])) {
2386 DP(BNX2X_MSG_ETHTOOL,
2387 "%s is 0x%x\n", prty_tbl[i].name, val);
2388 goto test_mem_exit;
2389 }
2390 }
2391
2392
2393 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2394 for (j = 0; j < mem_tbl[i].size; j++)
2395 REG_RD(bp, mem_tbl[i].offset + j*4);
2396
2397
2398 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2399 val = REG_RD(bp, prty_tbl[i].offset);
2400 if (val & ~(prty_tbl[i].hw_mask[index])) {
2401 DP(BNX2X_MSG_ETHTOOL,
2402 "%s is 0x%x\n", prty_tbl[i].name, val);
2403 goto test_mem_exit;
2404 }
2405 }
2406
2407 rc = 0;
2408
2409test_mem_exit:
2410 return rc;
2411}
2412
2413static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2414{
2415 int cnt = 1400;
2416
2417 if (link_up) {
2418 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2419 msleep(20);
2420
2421 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2422 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2423
2424 cnt = 1400;
2425 while (!bp->link_vars.link_up && cnt--)
2426 msleep(20);
2427
2428 if (cnt <= 0 && !bp->link_vars.link_up)
2429 DP(BNX2X_MSG_ETHTOOL,
2430 "Timeout waiting for link init\n");
2431 }
2432}
2433
2434static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2435{
2436 unsigned int pkt_size, num_pkts, i;
2437 struct sk_buff *skb;
2438 unsigned char *packet;
2439 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2440 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2441 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2442 u16 tx_start_idx, tx_idx;
2443 u16 rx_start_idx, rx_idx;
2444 u16 pkt_prod, bd_prod;
2445 struct sw_tx_bd *tx_buf;
2446 struct eth_tx_start_bd *tx_start_bd;
2447 dma_addr_t mapping;
2448 union eth_rx_cqe *cqe;
2449 u8 cqe_fp_flags, cqe_fp_type;
2450 struct sw_rx_bd *rx_buf;
2451 u16 len;
2452 int rc = -ENODEV;
2453 u8 *data;
2454 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2455 txdata->txq_index);
2456
2457
2458 switch (loopback_mode) {
2459 case BNX2X_PHY_LOOPBACK:
2460 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2461 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2462 return -EINVAL;
2463 }
2464 break;
2465 case BNX2X_MAC_LOOPBACK:
2466 if (CHIP_IS_E3(bp)) {
2467 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2468 if (bp->port.supported[cfg_idx] &
2469 (SUPPORTED_10000baseT_Full |
2470 SUPPORTED_20000baseMLD2_Full |
2471 SUPPORTED_20000baseKR2_Full))
2472 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2473 else
2474 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2475 } else
2476 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2477
2478 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2479 break;
2480 case BNX2X_EXT_LOOPBACK:
2481 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2482 DP(BNX2X_MSG_ETHTOOL,
2483 "Can't configure external loopback\n");
2484 return -EINVAL;
2485 }
2486 break;
2487 default:
2488 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2489 return -EINVAL;
2490 }
2491
2492
2493 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2494 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2495 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2496 if (!skb) {
2497 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2498 rc = -ENOMEM;
2499 goto test_loopback_exit;
2500 }
2501 packet = skb_put(skb, pkt_size);
2502 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2503 eth_zero_addr(packet + ETH_ALEN);
2504 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2505 for (i = ETH_HLEN; i < pkt_size; i++)
2506 packet[i] = (unsigned char) (i & 0xff);
2507 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2508 skb_headlen(skb), DMA_TO_DEVICE);
2509 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2510 rc = -ENOMEM;
2511 dev_kfree_skb(skb);
2512 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2513 goto test_loopback_exit;
2514 }
2515
2516
2517 num_pkts = 0;
2518 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2519 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2520
2521 netdev_tx_sent_queue(txq, skb->len);
2522
2523 pkt_prod = txdata->tx_pkt_prod++;
2524 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2525 tx_buf->first_bd = txdata->tx_bd_prod;
2526 tx_buf->skb = skb;
2527 tx_buf->flags = 0;
2528
2529 bd_prod = TX_BD(txdata->tx_bd_prod);
2530 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2531 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2532 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2533 tx_start_bd->nbd = cpu_to_le16(2);
2534 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2535 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2536 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2537 SET_FLAG(tx_start_bd->general_data,
2538 ETH_TX_START_BD_HDR_NBDS,
2539 1);
2540 SET_FLAG(tx_start_bd->general_data,
2541 ETH_TX_START_BD_PARSE_NBDS,
2542 0);
2543
2544
2545 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2546
2547 if (CHIP_IS_E1x(bp)) {
2548 u16 global_data = 0;
2549 struct eth_tx_parse_bd_e1x *pbd_e1x =
2550 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2551 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2552 SET_FLAG(global_data,
2553 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2554 pbd_e1x->global_data = cpu_to_le16(global_data);
2555 } else {
2556 u32 parsing_data = 0;
2557 struct eth_tx_parse_bd_e2 *pbd_e2 =
2558 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2559 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2560 SET_FLAG(parsing_data,
2561 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2562 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2563 }
2564 wmb();
2565
2566 txdata->tx_db.data.prod += 2;
2567 barrier();
2568 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2569
2570 mmiowb();
2571 barrier();
2572
2573 num_pkts++;
2574 txdata->tx_bd_prod += 2;
2575
2576 udelay(100);
2577
2578 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2579 if (tx_idx != tx_start_idx + num_pkts)
2580 goto test_loopback_exit;
2581
2582
2583
2584
2585
2586 if (bp->common.int_block == INT_BLOCK_IGU) {
2587
2588
2589
2590
2591 local_bh_disable();
2592 bnx2x_tx_int(bp, txdata);
2593 local_bh_enable();
2594 }
2595
2596 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2597 if (rx_idx != rx_start_idx + num_pkts)
2598 goto test_loopback_exit;
2599
2600 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2601 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2602 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2603 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2604 goto test_loopback_rx_exit;
2605
2606 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2607 if (len != pkt_size)
2608 goto test_loopback_rx_exit;
2609
2610 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2611 dma_sync_single_for_cpu(&bp->pdev->dev,
2612 dma_unmap_addr(rx_buf, mapping),
2613 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2614 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2615 for (i = ETH_HLEN; i < pkt_size; i++)
2616 if (*(data + i) != (unsigned char) (i & 0xff))
2617 goto test_loopback_rx_exit;
2618
2619 rc = 0;
2620
2621test_loopback_rx_exit:
2622
2623 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2624 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2625 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2626 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2627
2628
2629 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2630 fp_rx->rx_sge_prod);
2631
2632test_loopback_exit:
2633 bp->link_params.loopback_mode = LOOPBACK_NONE;
2634
2635 return rc;
2636}
2637
2638static int bnx2x_test_loopback(struct bnx2x *bp)
2639{
2640 int rc = 0, res;
2641
2642 if (BP_NOMCP(bp))
2643 return rc;
2644
2645 if (!netif_running(bp->dev))
2646 return BNX2X_LOOPBACK_FAILED;
2647
2648 bnx2x_netif_stop(bp, 1);
2649 bnx2x_acquire_phy_lock(bp);
2650
2651 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2652 if (res) {
2653 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
2654 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2655 }
2656
2657 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2658 if (res) {
2659 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
2660 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2661 }
2662
2663 bnx2x_release_phy_lock(bp);
2664 bnx2x_netif_start(bp);
2665
2666 return rc;
2667}
2668
2669static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2670{
2671 int rc;
2672 u8 is_serdes =
2673 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2674
2675 if (BP_NOMCP(bp))
2676 return -ENODEV;
2677
2678 if (!netif_running(bp->dev))
2679 return BNX2X_EXT_LOOPBACK_FAILED;
2680
2681 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2682 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2683 if (rc) {
2684 DP(BNX2X_MSG_ETHTOOL,
2685 "Can't perform self-test, nic_load (for external lb) failed\n");
2686 return -ENODEV;
2687 }
2688 bnx2x_wait_for_link(bp, 1, is_serdes);
2689
2690 bnx2x_netif_stop(bp, 1);
2691
2692 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2693 if (rc)
2694 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2695
2696 bnx2x_netif_start(bp);
2697
2698 return rc;
2699}
2700
2701struct code_entry {
2702 u32 sram_start_addr;
2703 u32 code_attribute;
2704#define CODE_IMAGE_TYPE_MASK 0xf0800003
2705#define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2706#define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2707#define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2708 u32 nvm_start_addr;
2709};
2710
2711#define CODE_ENTRY_MAX 16
2712#define CODE_ENTRY_EXTENDED_DIR_IDX 15
2713#define MAX_IMAGES_IN_EXTENDED_DIR 64
2714#define NVRAM_DIR_OFFSET 0x14
2715
2716#define EXTENDED_DIR_EXISTS(code) \
2717 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2718 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2719
2720#define CRC32_RESIDUAL 0xdebb20e3
2721#define CRC_BUFF_SIZE 256
2722
2723static int bnx2x_nvram_crc(struct bnx2x *bp,
2724 int offset,
2725 int size,
2726 u8 *buff)
2727{
2728 u32 crc = ~0;
2729 int rc = 0, done = 0;
2730
2731 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2732 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2733
2734 while (done < size) {
2735 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2736
2737 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2738
2739 if (rc)
2740 return rc;
2741
2742 crc = crc32_le(crc, buff, count);
2743 done += count;
2744 }
2745
2746 if (crc != CRC32_RESIDUAL)
2747 rc = -EINVAL;
2748
2749 return rc;
2750}
2751
2752static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2753 struct code_entry *entry,
2754 u8 *buff)
2755{
2756 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2757 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2758 int rc;
2759
2760
2761 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2762 return 0;
2763
2764 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2765 if (rc)
2766 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2767 "image %x has failed crc test (rc %d)\n", type, rc);
2768
2769 return rc;
2770}
2771
2772static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2773{
2774 int rc;
2775 struct code_entry entry;
2776
2777 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2778 if (rc)
2779 return rc;
2780
2781 return bnx2x_test_nvram_dir(bp, &entry, buff);
2782}
2783
2784static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2785{
2786 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2787 struct code_entry entry;
2788 int i;
2789
2790 rc = bnx2x_nvram_read32(bp,
2791 dir_offset +
2792 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2793 (u32 *)&entry, sizeof(entry));
2794 if (rc)
2795 return rc;
2796
2797 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2798 return 0;
2799
2800 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2801 &cnt, sizeof(u32));
2802 if (rc)
2803 return rc;
2804
2805 dir_offset = entry.nvm_start_addr + 8;
2806
2807 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2808 rc = bnx2x_test_dir_entry(bp, dir_offset +
2809 sizeof(struct code_entry) * i,
2810 buff);
2811 if (rc)
2812 return rc;
2813 }
2814
2815 return 0;
2816}
2817
2818static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2819{
2820 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2821 int i;
2822
2823 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2824
2825 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2826 rc = bnx2x_test_dir_entry(bp, dir_offset +
2827 sizeof(struct code_entry) * i,
2828 buff);
2829 if (rc)
2830 return rc;
2831 }
2832
2833 return bnx2x_test_nvram_ext_dirs(bp, buff);
2834}
2835
2836struct crc_pair {
2837 int offset;
2838 int size;
2839};
2840
2841static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2842 const struct crc_pair *nvram_tbl, u8 *buf)
2843{
2844 int i;
2845
2846 for (i = 0; nvram_tbl[i].size; i++) {
2847 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2848 nvram_tbl[i].size, buf);
2849 if (rc) {
2850 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2851 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2852 i, rc);
2853 return rc;
2854 }
2855 }
2856
2857 return 0;
2858}
2859
2860static int bnx2x_test_nvram(struct bnx2x *bp)
2861{
2862 const struct crc_pair nvram_tbl[] = {
2863 { 0, 0x14 },
2864 { 0x14, 0xec },
2865 { 0x100, 0x350 },
2866 { 0x450, 0xf0 },
2867 { 0x640, 0x64 },
2868 { 0x708, 0x70 },
2869 { 0, 0 }
2870 };
2871 const struct crc_pair nvram_tbl2[] = {
2872 { 0x7e8, 0x350 },
2873 { 0xb38, 0xf0 },
2874 { 0, 0 }
2875 };
2876
2877 u8 *buf;
2878 int rc;
2879 u32 magic;
2880
2881 if (BP_NOMCP(bp))
2882 return 0;
2883
2884 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2885 if (!buf) {
2886 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2887 rc = -ENOMEM;
2888 goto test_nvram_exit;
2889 }
2890
2891 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2892 if (rc) {
2893 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2894 "magic value read (rc %d)\n", rc);
2895 goto test_nvram_exit;
2896 }
2897
2898 if (magic != 0x669955aa) {
2899 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2900 "wrong magic value (0x%08x)\n", magic);
2901 rc = -ENODEV;
2902 goto test_nvram_exit;
2903 }
2904
2905 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2906 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2907 if (rc)
2908 goto test_nvram_exit;
2909
2910 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2911 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2912 SHARED_HW_CFG_HIDE_PORT1;
2913
2914 if (!hide) {
2915 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2916 "Port 1 CRC test-set\n");
2917 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2918 if (rc)
2919 goto test_nvram_exit;
2920 }
2921 }
2922
2923 rc = bnx2x_test_nvram_dirs(bp, buf);
2924
2925test_nvram_exit:
2926 kfree(buf);
2927 return rc;
2928}
2929
2930
2931static int bnx2x_test_intr(struct bnx2x *bp)
2932{
2933 struct bnx2x_queue_state_params params = {NULL};
2934
2935 if (!netif_running(bp->dev)) {
2936 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2937 "cannot access eeprom when the interface is down\n");
2938 return -ENODEV;
2939 }
2940
2941 params.q_obj = &bp->sp_objs->q_obj;
2942 params.cmd = BNX2X_Q_CMD_EMPTY;
2943
2944 __set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags);
2945
2946 return bnx2x_queue_state_change(bp, ¶ms);
2947}
2948
2949static void bnx2x_self_test(struct net_device *dev,
2950 struct ethtool_test *etest, u64 *buf)
2951{
2952 struct bnx2x *bp = netdev_priv(dev);
2953 u8 is_serdes, link_up;
2954 int rc, cnt = 0;
2955
2956 if (pci_num_vf(bp->pdev)) {
2957 DP(BNX2X_MSG_IOV,
2958 "VFs are enabled, can not perform self test\n");
2959 return;
2960 }
2961
2962 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2963 netdev_err(bp->dev,
2964 "Handling parity error recovery. Try again later\n");
2965 etest->flags |= ETH_TEST_FL_FAILED;
2966 return;
2967 }
2968
2969 DP(BNX2X_MSG_ETHTOOL,
2970 "Self-test command parameters: offline = %d, external_lb = %d\n",
2971 (etest->flags & ETH_TEST_FL_OFFLINE),
2972 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2973
2974 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2975
2976 if (bnx2x_test_nvram(bp) != 0) {
2977 if (!IS_MF(bp))
2978 buf[4] = 1;
2979 else
2980 buf[0] = 1;
2981 etest->flags |= ETH_TEST_FL_FAILED;
2982 }
2983
2984 if (!netif_running(dev)) {
2985 DP(BNX2X_MSG_ETHTOOL, "Interface is down\n");
2986 return;
2987 }
2988
2989 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2990 link_up = bp->link_vars.link_up;
2991
2992 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2993 int port = BP_PORT(bp);
2994 u32 val;
2995
2996
2997 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2998
2999 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
3000
3001 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3002 rc = bnx2x_nic_load(bp, LOAD_DIAG);
3003 if (rc) {
3004 etest->flags |= ETH_TEST_FL_FAILED;
3005 DP(BNX2X_MSG_ETHTOOL,
3006 "Can't perform self-test, nic_load (for offline) failed\n");
3007 return;
3008 }
3009
3010
3011 bnx2x_wait_for_link(bp, 1, is_serdes);
3012
3013 if (bnx2x_test_registers(bp) != 0) {
3014 buf[0] = 1;
3015 etest->flags |= ETH_TEST_FL_FAILED;
3016 }
3017 if (bnx2x_test_memory(bp) != 0) {
3018 buf[1] = 1;
3019 etest->flags |= ETH_TEST_FL_FAILED;
3020 }
3021
3022 buf[2] = bnx2x_test_loopback(bp);
3023 if (buf[2] != 0)
3024 etest->flags |= ETH_TEST_FL_FAILED;
3025
3026 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
3027 buf[3] = bnx2x_test_ext_loopback(bp);
3028 if (buf[3] != 0)
3029 etest->flags |= ETH_TEST_FL_FAILED;
3030 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
3031 }
3032
3033 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
3034
3035
3036 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
3037 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
3038 if (rc) {
3039 etest->flags |= ETH_TEST_FL_FAILED;
3040 DP(BNX2X_MSG_ETHTOOL,
3041 "Can't perform self-test, nic_load (for online) failed\n");
3042 return;
3043 }
3044
3045 bnx2x_wait_for_link(bp, link_up, is_serdes);
3046 }
3047
3048 if (bnx2x_test_intr(bp) != 0) {
3049 if (!IS_MF(bp))
3050 buf[5] = 1;
3051 else
3052 buf[1] = 1;
3053 etest->flags |= ETH_TEST_FL_FAILED;
3054 }
3055
3056 if (link_up) {
3057 cnt = 100;
3058 while (bnx2x_link_test(bp, is_serdes) && --cnt)
3059 msleep(20);
3060 }
3061
3062 if (!cnt) {
3063 if (!IS_MF(bp))
3064 buf[6] = 1;
3065 else
3066 buf[2] = 1;
3067 etest->flags |= ETH_TEST_FL_FAILED;
3068 }
3069}
3070
3071#define IS_PORT_STAT(i) (bnx2x_stats_arr[i].is_port_stat)
3072#define HIDE_PORT_STAT(bp) IS_VF(bp)
3073
3074
3075
3076
3077static int bnx2x_num_stat_queues(struct bnx2x *bp)
3078{
3079 return BNX2X_NUM_ETH_QUEUES(bp);
3080}
3081
3082static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3083{
3084 struct bnx2x *bp = netdev_priv(dev);
3085 int i, num_strings = 0;
3086
3087 switch (stringset) {
3088 case ETH_SS_STATS:
3089 if (is_multi(bp)) {
3090 num_strings = bnx2x_num_stat_queues(bp) *
3091 BNX2X_NUM_Q_STATS;
3092 } else
3093 num_strings = 0;
3094 if (HIDE_PORT_STAT(bp)) {
3095 for (i = 0; i < BNX2X_NUM_STATS; i++)
3096 if (!IS_PORT_STAT(i))
3097 num_strings++;
3098 } else
3099 num_strings += BNX2X_NUM_STATS;
3100
3101 return num_strings;
3102
3103 case ETH_SS_TEST:
3104 return BNX2X_NUM_TESTS(bp);
3105
3106 case ETH_SS_PRIV_FLAGS:
3107 return BNX2X_PRI_FLAG_LEN;
3108
3109 default:
3110 return -EINVAL;
3111 }
3112}
3113
3114static u32 bnx2x_get_private_flags(struct net_device *dev)
3115{
3116 struct bnx2x *bp = netdev_priv(dev);
3117 u32 flags = 0;
3118
3119 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3120 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3121 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3122
3123 return flags;
3124}
3125
3126static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3127{
3128 struct bnx2x *bp = netdev_priv(dev);
3129 int i, j, k, start;
3130 char queue_name[MAX_QUEUE_NAME_LEN+1];
3131
3132 switch (stringset) {
3133 case ETH_SS_STATS:
3134 k = 0;
3135 if (is_multi(bp)) {
3136 for_each_eth_queue(bp, i) {
3137 memset(queue_name, 0, sizeof(queue_name));
3138 sprintf(queue_name, "%d", i);
3139 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3140 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3141 ETH_GSTRING_LEN,
3142 bnx2x_q_stats_arr[j].string,
3143 queue_name);
3144 k += BNX2X_NUM_Q_STATS;
3145 }
3146 }
3147
3148 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3149 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3150 continue;
3151 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3152 bnx2x_stats_arr[i].string);
3153 j++;
3154 }
3155
3156 break;
3157
3158 case ETH_SS_TEST:
3159
3160 if (!IS_MF(bp))
3161 start = 0;
3162 else
3163 start = 4;
3164 memcpy(buf, bnx2x_tests_str_arr + start,
3165 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3166 break;
3167
3168 case ETH_SS_PRIV_FLAGS:
3169 memcpy(buf, bnx2x_private_arr,
3170 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3171 break;
3172 }
3173}
3174
3175static void bnx2x_get_ethtool_stats(struct net_device *dev,
3176 struct ethtool_stats *stats, u64 *buf)
3177{
3178 struct bnx2x *bp = netdev_priv(dev);
3179 u32 *hw_stats, *offset;
3180 int i, j, k = 0;
3181
3182 if (is_multi(bp)) {
3183 for_each_eth_queue(bp, i) {
3184 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3185 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3186 if (bnx2x_q_stats_arr[j].size == 0) {
3187
3188 buf[k + j] = 0;
3189 continue;
3190 }
3191 offset = (hw_stats +
3192 bnx2x_q_stats_arr[j].offset);
3193 if (bnx2x_q_stats_arr[j].size == 4) {
3194
3195 buf[k + j] = (u64) *offset;
3196 continue;
3197 }
3198
3199 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3200 }
3201 k += BNX2X_NUM_Q_STATS;
3202 }
3203 }
3204
3205 hw_stats = (u32 *)&bp->eth_stats;
3206 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3207 if (HIDE_PORT_STAT(bp) && IS_PORT_STAT(i))
3208 continue;
3209 if (bnx2x_stats_arr[i].size == 0) {
3210
3211 buf[k + j] = 0;
3212 j++;
3213 continue;
3214 }
3215 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3216 if (bnx2x_stats_arr[i].size == 4) {
3217
3218 buf[k + j] = (u64) *offset;
3219 j++;
3220 continue;
3221 }
3222
3223 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3224 j++;
3225 }
3226}
3227
3228static int bnx2x_set_phys_id(struct net_device *dev,
3229 enum ethtool_phys_id_state state)
3230{
3231 struct bnx2x *bp = netdev_priv(dev);
3232
3233 if (!bnx2x_is_nvm_accessible(bp)) {
3234 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3235 "cannot access eeprom when the interface is down\n");
3236 return -EAGAIN;
3237 }
3238
3239 switch (state) {
3240 case ETHTOOL_ID_ACTIVE:
3241 return 1;
3242
3243 case ETHTOOL_ID_ON:
3244 bnx2x_acquire_phy_lock(bp);
3245 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3246 LED_MODE_ON, SPEED_1000);
3247 bnx2x_release_phy_lock(bp);
3248 break;
3249
3250 case ETHTOOL_ID_OFF:
3251 bnx2x_acquire_phy_lock(bp);
3252 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3253 LED_MODE_FRONT_PANEL_OFF, 0);
3254 bnx2x_release_phy_lock(bp);
3255 break;
3256
3257 case ETHTOOL_ID_INACTIVE:
3258 bnx2x_acquire_phy_lock(bp);
3259 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3260 LED_MODE_OPER,
3261 bp->link_vars.line_speed);
3262 bnx2x_release_phy_lock(bp);
3263 }
3264
3265 return 0;
3266}
3267
3268static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3269{
3270 switch (info->flow_type) {
3271 case TCP_V4_FLOW:
3272 case TCP_V6_FLOW:
3273 info->data = RXH_IP_SRC | RXH_IP_DST |
3274 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3275 break;
3276 case UDP_V4_FLOW:
3277 if (bp->rss_conf_obj.udp_rss_v4)
3278 info->data = RXH_IP_SRC | RXH_IP_DST |
3279 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3280 else
3281 info->data = RXH_IP_SRC | RXH_IP_DST;
3282 break;
3283 case UDP_V6_FLOW:
3284 if (bp->rss_conf_obj.udp_rss_v6)
3285 info->data = RXH_IP_SRC | RXH_IP_DST |
3286 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3287 else
3288 info->data = RXH_IP_SRC | RXH_IP_DST;
3289 break;
3290 case IPV4_FLOW:
3291 case IPV6_FLOW:
3292 info->data = RXH_IP_SRC | RXH_IP_DST;
3293 break;
3294 default:
3295 info->data = 0;
3296 break;
3297 }
3298
3299 return 0;
3300}
3301
3302static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3303 u32 *rules __always_unused)
3304{
3305 struct bnx2x *bp = netdev_priv(dev);
3306
3307 switch (info->cmd) {
3308 case ETHTOOL_GRXRINGS:
3309 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3310 return 0;
3311 case ETHTOOL_GRXFH:
3312 return bnx2x_get_rss_flags(bp, info);
3313 default:
3314 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3315 return -EOPNOTSUPP;
3316 }
3317}
3318
3319static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3320{
3321 int udp_rss_requested;
3322
3323 DP(BNX2X_MSG_ETHTOOL,
3324 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3325 info->flow_type, info->data);
3326
3327 switch (info->flow_type) {
3328 case TCP_V4_FLOW:
3329 case TCP_V6_FLOW:
3330
3331 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3332 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3333 DP(BNX2X_MSG_ETHTOOL,
3334 "Command parameters not supported\n");
3335 return -EINVAL;
3336 }
3337 return 0;
3338
3339 case UDP_V4_FLOW:
3340 case UDP_V6_FLOW:
3341
3342 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3343 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3344 udp_rss_requested = 1;
3345 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3346 udp_rss_requested = 0;
3347 else
3348 return -EINVAL;
3349
3350 if (CHIP_IS_E1x(bp) && udp_rss_requested) {
3351 DP(BNX2X_MSG_ETHTOOL,
3352 "57710, 57711 boards don't support RSS according to UDP 4-tuple\n");
3353 return -EINVAL;
3354 }
3355
3356 if ((info->flow_type == UDP_V4_FLOW) &&
3357 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3358 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3359 DP(BNX2X_MSG_ETHTOOL,
3360 "rss re-configured, UDP 4-tupple %s\n",
3361 udp_rss_requested ? "enabled" : "disabled");
3362 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3363 } else if ((info->flow_type == UDP_V6_FLOW) &&
3364 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3365 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3366 DP(BNX2X_MSG_ETHTOOL,
3367 "rss re-configured, UDP 4-tupple %s\n",
3368 udp_rss_requested ? "enabled" : "disabled");
3369 return bnx2x_rss(bp, &bp->rss_conf_obj, false, true);
3370 }
3371 return 0;
3372
3373 case IPV4_FLOW:
3374 case IPV6_FLOW:
3375
3376 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3377 DP(BNX2X_MSG_ETHTOOL,
3378 "Command parameters not supported\n");
3379 return -EINVAL;
3380 }
3381 return 0;
3382
3383 case SCTP_V4_FLOW:
3384 case AH_ESP_V4_FLOW:
3385 case AH_V4_FLOW:
3386 case ESP_V4_FLOW:
3387 case SCTP_V6_FLOW:
3388 case AH_ESP_V6_FLOW:
3389 case AH_V6_FLOW:
3390 case ESP_V6_FLOW:
3391 case IP_USER_FLOW:
3392 case ETHER_FLOW:
3393
3394 if (info->data) {
3395 DP(BNX2X_MSG_ETHTOOL,
3396 "Command parameters not supported\n");
3397 return -EINVAL;
3398 }
3399 return 0;
3400
3401 default:
3402 return -EINVAL;
3403 }
3404}
3405
3406static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3407{
3408 struct bnx2x *bp = netdev_priv(dev);
3409
3410 switch (info->cmd) {
3411 case ETHTOOL_SRXFH:
3412 return bnx2x_set_rss_flags(bp, info);
3413 default:
3414 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3415 return -EOPNOTSUPP;
3416 }
3417}
3418
3419static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3420{
3421 return T_ETH_INDIRECTION_TABLE_SIZE;
3422}
3423
3424static int bnx2x_get_rxfh(struct net_device *dev, u32 *indir, u8 *key,
3425 u8 *hfunc)
3426{
3427 struct bnx2x *bp = netdev_priv(dev);
3428 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3429 size_t i;
3430
3431 if (hfunc)
3432 *hfunc = ETH_RSS_HASH_TOP;
3433 if (!indir)
3434 return 0;
3435
3436
3437 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447
3448 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3449 indir[i] = ind_table[i] - bp->fp->cl_id;
3450
3451 return 0;
3452}
3453
3454static int bnx2x_set_rxfh(struct net_device *dev, const u32 *indir,
3455 const u8 *key, const u8 hfunc)
3456{
3457 struct bnx2x *bp = netdev_priv(dev);
3458 size_t i;
3459
3460
3461
3462
3463 if (key ||
3464 (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP))
3465 return -EOPNOTSUPP;
3466
3467 if (!indir)
3468 return 0;
3469
3470 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3471
3472
3473
3474
3475
3476
3477
3478
3479
3480 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3481 }
3482
3483 return bnx2x_config_rss_eth(bp, false);
3484}
3485
3486
3487
3488
3489
3490
3491
3492static void bnx2x_get_channels(struct net_device *dev,
3493 struct ethtool_channels *channels)
3494{
3495 struct bnx2x *bp = netdev_priv(dev);
3496
3497 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3498 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3499}
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3510{
3511 bnx2x_disable_msi(bp);
3512 bp->num_ethernet_queues = num_rss;
3513 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3514 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3515 bnx2x_set_int_mode(bp);
3516}
3517
3518
3519
3520
3521
3522
3523
3524static int bnx2x_set_channels(struct net_device *dev,
3525 struct ethtool_channels *channels)
3526{
3527 struct bnx2x *bp = netdev_priv(dev);
3528
3529 DP(BNX2X_MSG_ETHTOOL,
3530 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3531 channels->rx_count, channels->tx_count, channels->other_count,
3532 channels->combined_count);
3533
3534 if (pci_num_vf(bp->pdev)) {
3535 DP(BNX2X_MSG_IOV, "VFs are enabled, can not set channels\n");
3536 return -EPERM;
3537 }
3538
3539
3540
3541
3542 if (channels->rx_count || channels->tx_count || channels->other_count
3543 || (channels->combined_count == 0) ||
3544 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3545 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3546 return -EINVAL;
3547 }
3548
3549
3550 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3551 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3552 return 0;
3553 }
3554
3555
3556
3557
3558
3559 if (unlikely(!netif_running(dev))) {
3560 bnx2x_change_num_queues(bp, channels->combined_count);
3561 return 0;
3562 }
3563 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3564 bnx2x_change_num_queues(bp, channels->combined_count);
3565 return bnx2x_nic_load(bp, LOAD_NORMAL);
3566}
3567
3568static int bnx2x_get_ts_info(struct net_device *dev,
3569 struct ethtool_ts_info *info)
3570{
3571 struct bnx2x *bp = netdev_priv(dev);
3572
3573 if (bp->flags & PTP_SUPPORTED) {
3574 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
3575 SOF_TIMESTAMPING_RX_SOFTWARE |
3576 SOF_TIMESTAMPING_SOFTWARE |
3577 SOF_TIMESTAMPING_TX_HARDWARE |
3578 SOF_TIMESTAMPING_RX_HARDWARE |
3579 SOF_TIMESTAMPING_RAW_HARDWARE;
3580
3581 if (bp->ptp_clock)
3582 info->phc_index = ptp_clock_index(bp->ptp_clock);
3583 else
3584 info->phc_index = -1;
3585
3586 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
3587 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
3588 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
3589 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
3590
3591 info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
3592
3593 return 0;
3594 }
3595
3596 return ethtool_op_get_ts_info(dev, info);
3597}
3598
3599static const struct ethtool_ops bnx2x_ethtool_ops = {
3600 .get_settings = bnx2x_get_settings,
3601 .set_settings = bnx2x_set_settings,
3602 .get_drvinfo = bnx2x_get_drvinfo,
3603 .get_regs_len = bnx2x_get_regs_len,
3604 .get_regs = bnx2x_get_regs,
3605 .get_dump_flag = bnx2x_get_dump_flag,
3606 .get_dump_data = bnx2x_get_dump_data,
3607 .set_dump = bnx2x_set_dump,
3608 .get_wol = bnx2x_get_wol,
3609 .set_wol = bnx2x_set_wol,
3610 .get_msglevel = bnx2x_get_msglevel,
3611 .set_msglevel = bnx2x_set_msglevel,
3612 .nway_reset = bnx2x_nway_reset,
3613 .get_link = bnx2x_get_link,
3614 .get_eeprom_len = bnx2x_get_eeprom_len,
3615 .get_eeprom = bnx2x_get_eeprom,
3616 .set_eeprom = bnx2x_set_eeprom,
3617 .get_coalesce = bnx2x_get_coalesce,
3618 .set_coalesce = bnx2x_set_coalesce,
3619 .get_ringparam = bnx2x_get_ringparam,
3620 .set_ringparam = bnx2x_set_ringparam,
3621 .get_pauseparam = bnx2x_get_pauseparam,
3622 .set_pauseparam = bnx2x_set_pauseparam,
3623 .self_test = bnx2x_self_test,
3624 .get_sset_count = bnx2x_get_sset_count,
3625 .get_priv_flags = bnx2x_get_private_flags,
3626 .get_strings = bnx2x_get_strings,
3627 .set_phys_id = bnx2x_set_phys_id,
3628 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3629 .get_rxnfc = bnx2x_get_rxnfc,
3630 .set_rxnfc = bnx2x_set_rxnfc,
3631 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3632 .get_rxfh = bnx2x_get_rxfh,
3633 .set_rxfh = bnx2x_set_rxfh,
3634 .get_channels = bnx2x_get_channels,
3635 .set_channels = bnx2x_set_channels,
3636 .get_module_info = bnx2x_get_module_info,
3637 .get_module_eeprom = bnx2x_get_module_eeprom,
3638 .get_eee = bnx2x_get_eee,
3639 .set_eee = bnx2x_set_eee,
3640 .get_ts_info = bnx2x_get_ts_info,
3641};
3642
3643static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3644 .get_settings = bnx2x_get_vf_settings,
3645 .get_drvinfo = bnx2x_get_drvinfo,
3646 .get_msglevel = bnx2x_get_msglevel,
3647 .set_msglevel = bnx2x_set_msglevel,
3648 .get_link = bnx2x_get_link,
3649 .get_coalesce = bnx2x_get_coalesce,
3650 .get_ringparam = bnx2x_get_ringparam,
3651 .set_ringparam = bnx2x_set_ringparam,
3652 .get_sset_count = bnx2x_get_sset_count,
3653 .get_strings = bnx2x_get_strings,
3654 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3655 .get_rxnfc = bnx2x_get_rxnfc,
3656 .set_rxnfc = bnx2x_set_rxnfc,
3657 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3658 .get_rxfh = bnx2x_get_rxfh,
3659 .set_rxfh = bnx2x_set_rxfh,
3660 .get_channels = bnx2x_get_channels,
3661 .set_channels = bnx2x_set_channels,
3662};
3663
3664void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3665{
3666 netdev->ethtool_ops = (IS_PF(bp)) ?
3667 &bnx2x_ethtool_ops : &bnx2x_vf_ethtool_ops;
3668}
3669
