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34
35
36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38#include <linux/module.h>
39#include <linux/moduleparam.h>
40#include <linux/init.h>
41#include <linux/pci.h>
42#include <linux/dma-mapping.h>
43#include <linux/netdevice.h>
44#include <linux/etherdevice.h>
45#include <linux/debugfs.h>
46#include <linux/ethtool.h>
47#include <linux/mdio.h>
48
49#include "t4vf_common.h"
50#include "t4vf_defs.h"
51
52#include "../cxgb4/t4_regs.h"
53#include "../cxgb4/t4_msg.h"
54
55
56
57
58#define DRV_VERSION "2.0.0-ko"
59#define DRV_DESC "Chelsio T4/T5/T6 Virtual Function (VF) Network Driver"
60
61
62
63
64
65
66
67
68
69#define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
70 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
71 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
72
73static int dflt_msg_enable = DFLT_MSG_ENABLE;
74
75module_param(dflt_msg_enable, int, 0644);
76MODULE_PARM_DESC(dflt_msg_enable,
77 "default adapter ethtool message level bitmap");
78
79
80
81
82
83
84
85
86
87
88
89
90
91#define MSI_MSIX 2
92#define MSI_MSI 1
93#define MSI_DEFAULT MSI_MSIX
94
95static int msi = MSI_DEFAULT;
96
97module_param(msi, int, 0644);
98MODULE_PARM_DESC(msi, "whether to use MSI-X or MSI");
99
100
101
102
103
104
105enum {
106 MAX_TXQ_ENTRIES = 16384,
107 MAX_RSPQ_ENTRIES = 16384,
108 MAX_RX_BUFFERS = 16384,
109
110 MIN_TXQ_ENTRIES = 32,
111 MIN_RSPQ_ENTRIES = 128,
112 MIN_FL_ENTRIES = 16,
113
114
115
116
117
118
119
120
121
122
123
124 EQ_UNIT = SGE_EQ_IDXSIZE,
125 FL_PER_EQ_UNIT = EQ_UNIT / sizeof(__be64),
126 MIN_FL_RESID = FL_PER_EQ_UNIT,
127};
128
129
130
131
132
133
134static struct dentry *cxgb4vf_debugfs_root;
135
136
137
138
139
140
141
142
143
144void t4vf_os_link_changed(struct adapter *adapter, int pidx, int link_ok)
145{
146 struct net_device *dev = adapter->port[pidx];
147
148
149
150
151
152 if (!netif_running(dev) || link_ok == netif_carrier_ok(dev))
153 return;
154
155
156
157
158
159 if (link_ok) {
160 const char *s;
161 const char *fc;
162 const struct port_info *pi = netdev_priv(dev);
163
164 netif_carrier_on(dev);
165
166 switch (pi->link_cfg.speed) {
167 case 40000:
168 s = "40Gbps";
169 break;
170
171 case 10000:
172 s = "10Gbps";
173 break;
174
175 case 1000:
176 s = "1000Mbps";
177 break;
178
179 case 100:
180 s = "100Mbps";
181 break;
182
183 default:
184 s = "unknown";
185 break;
186 }
187
188 switch (pi->link_cfg.fc) {
189 case PAUSE_RX:
190 fc = "RX";
191 break;
192
193 case PAUSE_TX:
194 fc = "TX";
195 break;
196
197 case PAUSE_RX|PAUSE_TX:
198 fc = "RX/TX";
199 break;
200
201 default:
202 fc = "no";
203 break;
204 }
205
206 netdev_info(dev, "link up, %s, full-duplex, %s PAUSE\n", s, fc);
207 } else {
208 netif_carrier_off(dev);
209 netdev_info(dev, "link down\n");
210 }
211}
212
213
214
215
216
217void t4vf_os_portmod_changed(struct adapter *adapter, int pidx)
218{
219 static const char * const mod_str[] = {
220 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
221 };
222 const struct net_device *dev = adapter->port[pidx];
223 const struct port_info *pi = netdev_priv(dev);
224
225 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
226 dev_info(adapter->pdev_dev, "%s: port module unplugged\n",
227 dev->name);
228 else if (pi->mod_type < ARRAY_SIZE(mod_str))
229 dev_info(adapter->pdev_dev, "%s: %s port module inserted\n",
230 dev->name, mod_str[pi->mod_type]);
231 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
232 dev_info(adapter->pdev_dev, "%s: unsupported optical port "
233 "module inserted\n", dev->name);
234 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
235 dev_info(adapter->pdev_dev, "%s: unknown port module inserted,"
236 "forcing TWINAX\n", dev->name);
237 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR)
238 dev_info(adapter->pdev_dev, "%s: transceiver module error\n",
239 dev->name);
240 else
241 dev_info(adapter->pdev_dev, "%s: unknown module type %d "
242 "inserted\n", dev->name, pi->mod_type);
243}
244
245
246
247
248
249
250
251
252
253
254
255
256
257static int link_start(struct net_device *dev)
258{
259 int ret;
260 struct port_info *pi = netdev_priv(dev);
261
262
263
264
265
266 ret = t4vf_set_rxmode(pi->adapter, pi->viid, dev->mtu, -1, -1, -1, 1,
267 true);
268 if (ret == 0) {
269 ret = t4vf_change_mac(pi->adapter, pi->viid,
270 pi->xact_addr_filt, dev->dev_addr, true);
271 if (ret >= 0) {
272 pi->xact_addr_filt = ret;
273 ret = 0;
274 }
275 }
276
277
278
279
280
281
282 if (ret == 0)
283 ret = t4vf_enable_vi(pi->adapter, pi->viid, true, true);
284 return ret;
285}
286
287
288
289
290static void name_msix_vecs(struct adapter *adapter)
291{
292 int namelen = sizeof(adapter->msix_info[0].desc) - 1;
293 int pidx;
294
295
296
297
298 snprintf(adapter->msix_info[MSIX_FW].desc, namelen,
299 "%s-FWeventq", adapter->name);
300 adapter->msix_info[MSIX_FW].desc[namelen] = 0;
301
302
303
304
305 for_each_port(adapter, pidx) {
306 struct net_device *dev = adapter->port[pidx];
307 const struct port_info *pi = netdev_priv(dev);
308 int qs, msi;
309
310 for (qs = 0, msi = MSIX_IQFLINT; qs < pi->nqsets; qs++, msi++) {
311 snprintf(adapter->msix_info[msi].desc, namelen,
312 "%s-%d", dev->name, qs);
313 adapter->msix_info[msi].desc[namelen] = 0;
314 }
315 }
316}
317
318
319
320
321static int request_msix_queue_irqs(struct adapter *adapter)
322{
323 struct sge *s = &adapter->sge;
324 int rxq, msi, err;
325
326
327
328
329 err = request_irq(adapter->msix_info[MSIX_FW].vec, t4vf_sge_intr_msix,
330 0, adapter->msix_info[MSIX_FW].desc, &s->fw_evtq);
331 if (err)
332 return err;
333
334
335
336
337 msi = MSIX_IQFLINT;
338 for_each_ethrxq(s, rxq) {
339 err = request_irq(adapter->msix_info[msi].vec,
340 t4vf_sge_intr_msix, 0,
341 adapter->msix_info[msi].desc,
342 &s->ethrxq[rxq].rspq);
343 if (err)
344 goto err_free_irqs;
345 msi++;
346 }
347 return 0;
348
349err_free_irqs:
350 while (--rxq >= 0)
351 free_irq(adapter->msix_info[--msi].vec, &s->ethrxq[rxq].rspq);
352 free_irq(adapter->msix_info[MSIX_FW].vec, &s->fw_evtq);
353 return err;
354}
355
356
357
358
359static void free_msix_queue_irqs(struct adapter *adapter)
360{
361 struct sge *s = &adapter->sge;
362 int rxq, msi;
363
364 free_irq(adapter->msix_info[MSIX_FW].vec, &s->fw_evtq);
365 msi = MSIX_IQFLINT;
366 for_each_ethrxq(s, rxq)
367 free_irq(adapter->msix_info[msi++].vec,
368 &s->ethrxq[rxq].rspq);
369}
370
371
372
373
374static void qenable(struct sge_rspq *rspq)
375{
376 napi_enable(&rspq->napi);
377
378
379
380
381
382 t4_write_reg(rspq->adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
383 CIDXINC_V(0) |
384 SEINTARM_V(rspq->intr_params) |
385 INGRESSQID_V(rspq->cntxt_id));
386}
387
388
389
390
391static void enable_rx(struct adapter *adapter)
392{
393 int rxq;
394 struct sge *s = &adapter->sge;
395
396 for_each_ethrxq(s, rxq)
397 qenable(&s->ethrxq[rxq].rspq);
398 qenable(&s->fw_evtq);
399
400
401
402
403
404 if (adapter->flags & USING_MSI)
405 t4_write_reg(adapter, T4VF_SGE_BASE_ADDR + SGE_VF_GTS,
406 CIDXINC_V(0) |
407 SEINTARM_V(s->intrq.intr_params) |
408 INGRESSQID_V(s->intrq.cntxt_id));
409
410}
411
412
413
414
415static void quiesce_rx(struct adapter *adapter)
416{
417 struct sge *s = &adapter->sge;
418 int rxq;
419
420 for_each_ethrxq(s, rxq)
421 napi_disable(&s->ethrxq[rxq].rspq.napi);
422 napi_disable(&s->fw_evtq.napi);
423}
424
425
426
427
428static int fwevtq_handler(struct sge_rspq *rspq, const __be64 *rsp,
429 const struct pkt_gl *gl)
430{
431
432
433
434 struct adapter *adapter = rspq->adapter;
435 u8 opcode = ((const struct rss_header *)rsp)->opcode;
436 void *cpl = (void *)(rsp + 1);
437
438 switch (opcode) {
439 case CPL_FW6_MSG: {
440
441
442
443 const struct cpl_fw6_msg *fw_msg = cpl;
444 if (fw_msg->type == FW6_TYPE_CMD_RPL)
445 t4vf_handle_fw_rpl(adapter, fw_msg->data);
446 break;
447 }
448
449 case CPL_FW4_MSG: {
450
451
452 const struct cpl_sge_egr_update *p = (void *)(rsp + 3);
453 opcode = CPL_OPCODE_G(ntohl(p->opcode_qid));
454 if (opcode != CPL_SGE_EGR_UPDATE) {
455 dev_err(adapter->pdev_dev, "unexpected FW4/CPL %#x on FW event queue\n"
456 , opcode);
457 break;
458 }
459 cpl = (void *)p;
460
461 }
462
463 case CPL_SGE_EGR_UPDATE: {
464
465
466
467
468
469
470
471
472
473 const struct cpl_sge_egr_update *p = cpl;
474 unsigned int qid = EGR_QID_G(be32_to_cpu(p->opcode_qid));
475 struct sge *s = &adapter->sge;
476 struct sge_txq *tq;
477 struct sge_eth_txq *txq;
478 unsigned int eq_idx;
479
480
481
482
483
484
485
486
487 eq_idx = EQ_IDX(s, qid);
488 if (unlikely(eq_idx >= MAX_EGRQ)) {
489 dev_err(adapter->pdev_dev,
490 "Egress Update QID %d out of range\n", qid);
491 break;
492 }
493 tq = s->egr_map[eq_idx];
494 if (unlikely(tq == NULL)) {
495 dev_err(adapter->pdev_dev,
496 "Egress Update QID %d TXQ=NULL\n", qid);
497 break;
498 }
499 txq = container_of(tq, struct sge_eth_txq, q);
500 if (unlikely(tq->abs_id != qid)) {
501 dev_err(adapter->pdev_dev,
502 "Egress Update QID %d refers to TXQ %d\n",
503 qid, tq->abs_id);
504 break;
505 }
506
507
508
509
510
511 txq->q.restarts++;
512 netif_tx_wake_queue(txq->txq);
513 break;
514 }
515
516 default:
517 dev_err(adapter->pdev_dev,
518 "unexpected CPL %#x on FW event queue\n", opcode);
519 }
520
521 return 0;
522}
523
524
525
526
527
528
529static int setup_sge_queues(struct adapter *adapter)
530{
531 struct sge *s = &adapter->sge;
532 int err, pidx, msix;
533
534
535
536
537
538 bitmap_zero(s->starving_fl, MAX_EGRQ);
539
540
541
542
543
544
545
546
547
548 if (adapter->flags & USING_MSI) {
549 err = t4vf_sge_alloc_rxq(adapter, &s->intrq, false,
550 adapter->port[0], 0, NULL, NULL);
551 if (err)
552 goto err_free_queues;
553 }
554
555
556
557
558 err = t4vf_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->port[0],
559 MSIX_FW, NULL, fwevtq_handler);
560 if (err)
561 goto err_free_queues;
562
563
564
565
566
567
568
569 msix = MSIX_IQFLINT;
570 for_each_port(adapter, pidx) {
571 struct net_device *dev = adapter->port[pidx];
572 struct port_info *pi = netdev_priv(dev);
573 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset];
574 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset];
575 int qs;
576
577 for (qs = 0; qs < pi->nqsets; qs++, rxq++, txq++) {
578 err = t4vf_sge_alloc_rxq(adapter, &rxq->rspq, false,
579 dev, msix++,
580 &rxq->fl, t4vf_ethrx_handler);
581 if (err)
582 goto err_free_queues;
583
584 err = t4vf_sge_alloc_eth_txq(adapter, txq, dev,
585 netdev_get_tx_queue(dev, qs),
586 s->fw_evtq.cntxt_id);
587 if (err)
588 goto err_free_queues;
589
590 rxq->rspq.idx = qs;
591 memset(&rxq->stats, 0, sizeof(rxq->stats));
592 }
593 }
594
595
596
597
598 s->egr_base = s->ethtxq[0].q.abs_id - s->ethtxq[0].q.cntxt_id;
599 s->ingr_base = s->ethrxq[0].rspq.abs_id - s->ethrxq[0].rspq.cntxt_id;
600 IQ_MAP(s, s->fw_evtq.abs_id) = &s->fw_evtq;
601 for_each_port(adapter, pidx) {
602 struct net_device *dev = adapter->port[pidx];
603 struct port_info *pi = netdev_priv(dev);
604 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset];
605 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset];
606 int qs;
607
608 for (qs = 0; qs < pi->nqsets; qs++, rxq++, txq++) {
609 IQ_MAP(s, rxq->rspq.abs_id) = &rxq->rspq;
610 EQ_MAP(s, txq->q.abs_id) = &txq->q;
611
612
613
614
615
616
617
618
619
620
621 rxq->fl.abs_id = rxq->fl.cntxt_id + s->egr_base;
622 EQ_MAP(s, rxq->fl.abs_id) = &rxq->fl;
623 }
624 }
625 return 0;
626
627err_free_queues:
628 t4vf_free_sge_resources(adapter);
629 return err;
630}
631
632
633
634
635
636
637
638
639
640static int setup_rss(struct adapter *adapter)
641{
642 int pidx;
643
644 for_each_port(adapter, pidx) {
645 struct port_info *pi = adap2pinfo(adapter, pidx);
646 struct sge_eth_rxq *rxq = &adapter->sge.ethrxq[pi->first_qset];
647 u16 rss[MAX_PORT_QSETS];
648 int qs, err;
649
650 for (qs = 0; qs < pi->nqsets; qs++)
651 rss[qs] = rxq[qs].rspq.abs_id;
652
653 err = t4vf_config_rss_range(adapter, pi->viid,
654 0, pi->rss_size, rss, pi->nqsets);
655 if (err)
656 return err;
657
658
659
660
661 switch (adapter->params.rss.mode) {
662 case FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL:
663
664
665
666
667
668
669
670 if (!adapter->params.rss.u.basicvirtual.tnlalllookup) {
671 union rss_vi_config config;
672 err = t4vf_read_rss_vi_config(adapter,
673 pi->viid,
674 &config);
675 if (err)
676 return err;
677 config.basicvirtual.defaultq =
678 rxq[0].rspq.abs_id;
679 err = t4vf_write_rss_vi_config(adapter,
680 pi->viid,
681 &config);
682 if (err)
683 return err;
684 }
685 break;
686 }
687 }
688
689 return 0;
690}
691
692
693
694
695
696
697
698
699static int adapter_up(struct adapter *adapter)
700{
701 int err;
702
703
704
705
706
707
708 if ((adapter->flags & FULL_INIT_DONE) == 0) {
709 err = setup_sge_queues(adapter);
710 if (err)
711 return err;
712 err = setup_rss(adapter);
713 if (err) {
714 t4vf_free_sge_resources(adapter);
715 return err;
716 }
717
718 if (adapter->flags & USING_MSIX)
719 name_msix_vecs(adapter);
720 adapter->flags |= FULL_INIT_DONE;
721 }
722
723
724
725
726 BUG_ON((adapter->flags & (USING_MSIX|USING_MSI)) == 0);
727 if (adapter->flags & USING_MSIX)
728 err = request_msix_queue_irqs(adapter);
729 else
730 err = request_irq(adapter->pdev->irq,
731 t4vf_intr_handler(adapter), 0,
732 adapter->name, adapter);
733 if (err) {
734 dev_err(adapter->pdev_dev, "request_irq failed, err %d\n",
735 err);
736 return err;
737 }
738
739
740
741
742 enable_rx(adapter);
743 t4vf_sge_start(adapter);
744
745
746 INIT_LIST_HEAD(&adapter->mac_hlist);
747 return 0;
748}
749
750
751
752
753
754
755static void adapter_down(struct adapter *adapter)
756{
757
758
759
760 if (adapter->flags & USING_MSIX)
761 free_msix_queue_irqs(adapter);
762 else
763 free_irq(adapter->pdev->irq, adapter);
764
765
766
767
768 quiesce_rx(adapter);
769}
770
771
772
773
774static int cxgb4vf_open(struct net_device *dev)
775{
776 int err;
777 struct port_info *pi = netdev_priv(dev);
778 struct adapter *adapter = pi->adapter;
779
780
781
782
783
784 if (adapter->open_device_map == 0) {
785 err = adapter_up(adapter);
786 if (err)
787 return err;
788 }
789
790
791
792
793 err = link_start(dev);
794 if (err)
795 goto err_unwind;
796
797 netif_tx_start_all_queues(dev);
798 set_bit(pi->port_id, &adapter->open_device_map);
799 return 0;
800
801err_unwind:
802 if (adapter->open_device_map == 0)
803 adapter_down(adapter);
804 return err;
805}
806
807
808
809
810
811static int cxgb4vf_stop(struct net_device *dev)
812{
813 struct port_info *pi = netdev_priv(dev);
814 struct adapter *adapter = pi->adapter;
815
816 netif_tx_stop_all_queues(dev);
817 netif_carrier_off(dev);
818 t4vf_enable_vi(adapter, pi->viid, false, false);
819 pi->link_cfg.link_ok = 0;
820
821 clear_bit(pi->port_id, &adapter->open_device_map);
822 if (adapter->open_device_map == 0)
823 adapter_down(adapter);
824 return 0;
825}
826
827
828
829
830static struct net_device_stats *cxgb4vf_get_stats(struct net_device *dev)
831{
832 struct t4vf_port_stats stats;
833 struct port_info *pi = netdev2pinfo(dev);
834 struct adapter *adapter = pi->adapter;
835 struct net_device_stats *ns = &dev->stats;
836 int err;
837
838 spin_lock(&adapter->stats_lock);
839 err = t4vf_get_port_stats(adapter, pi->pidx, &stats);
840 spin_unlock(&adapter->stats_lock);
841
842 memset(ns, 0, sizeof(*ns));
843 if (err)
844 return ns;
845
846 ns->tx_bytes = (stats.tx_bcast_bytes + stats.tx_mcast_bytes +
847 stats.tx_ucast_bytes + stats.tx_offload_bytes);
848 ns->tx_packets = (stats.tx_bcast_frames + stats.tx_mcast_frames +
849 stats.tx_ucast_frames + stats.tx_offload_frames);
850 ns->rx_bytes = (stats.rx_bcast_bytes + stats.rx_mcast_bytes +
851 stats.rx_ucast_bytes);
852 ns->rx_packets = (stats.rx_bcast_frames + stats.rx_mcast_frames +
853 stats.rx_ucast_frames);
854 ns->multicast = stats.rx_mcast_frames;
855 ns->tx_errors = stats.tx_drop_frames;
856 ns->rx_errors = stats.rx_err_frames;
857
858 return ns;
859}
860
861static inline int cxgb4vf_set_addr_hash(struct port_info *pi)
862{
863 struct adapter *adapter = pi->adapter;
864 u64 vec = 0;
865 bool ucast = false;
866 struct hash_mac_addr *entry;
867
868
869 list_for_each_entry(entry, &adapter->mac_hlist, list) {
870 ucast |= is_unicast_ether_addr(entry->addr);
871 vec |= (1ULL << hash_mac_addr(entry->addr));
872 }
873 return t4vf_set_addr_hash(adapter, pi->viid, ucast, vec, false);
874}
875
876static int cxgb4vf_mac_sync(struct net_device *netdev, const u8 *mac_addr)
877{
878 struct port_info *pi = netdev_priv(netdev);
879 struct adapter *adapter = pi->adapter;
880 int ret;
881 u64 mhash = 0;
882 u64 uhash = 0;
883 bool free = false;
884 bool ucast = is_unicast_ether_addr(mac_addr);
885 const u8 *maclist[1] = {mac_addr};
886 struct hash_mac_addr *new_entry;
887
888 ret = t4vf_alloc_mac_filt(adapter, pi->viid, free, 1, maclist,
889 NULL, ucast ? &uhash : &mhash, false);
890 if (ret < 0)
891 goto out;
892
893
894
895
896 if (uhash || mhash) {
897 new_entry = kzalloc(sizeof(*new_entry), GFP_ATOMIC);
898 if (!new_entry)
899 return -ENOMEM;
900 ether_addr_copy(new_entry->addr, mac_addr);
901 list_add_tail(&new_entry->list, &adapter->mac_hlist);
902 ret = cxgb4vf_set_addr_hash(pi);
903 }
904out:
905 return ret < 0 ? ret : 0;
906}
907
908static int cxgb4vf_mac_unsync(struct net_device *netdev, const u8 *mac_addr)
909{
910 struct port_info *pi = netdev_priv(netdev);
911 struct adapter *adapter = pi->adapter;
912 int ret;
913 const u8 *maclist[1] = {mac_addr};
914 struct hash_mac_addr *entry, *tmp;
915
916
917
918
919 list_for_each_entry_safe(entry, tmp, &adapter->mac_hlist, list) {
920 if (ether_addr_equal(entry->addr, mac_addr)) {
921 list_del(&entry->list);
922 kfree(entry);
923 return cxgb4vf_set_addr_hash(pi);
924 }
925 }
926
927 ret = t4vf_free_mac_filt(adapter, pi->viid, 1, maclist, false);
928 return ret < 0 ? -EINVAL : 0;
929}
930
931
932
933
934
935static int set_rxmode(struct net_device *dev, int mtu, bool sleep_ok)
936{
937 struct port_info *pi = netdev_priv(dev);
938
939 if (!(dev->flags & IFF_PROMISC)) {
940 __dev_uc_sync(dev, cxgb4vf_mac_sync, cxgb4vf_mac_unsync);
941 if (!(dev->flags & IFF_ALLMULTI))
942 __dev_mc_sync(dev, cxgb4vf_mac_sync,
943 cxgb4vf_mac_unsync);
944 }
945 return t4vf_set_rxmode(pi->adapter, pi->viid, -1,
946 (dev->flags & IFF_PROMISC) != 0,
947 (dev->flags & IFF_ALLMULTI) != 0,
948 1, -1, sleep_ok);
949}
950
951
952
953
954static void cxgb4vf_set_rxmode(struct net_device *dev)
955{
956
957 set_rxmode(dev, -1, false);
958}
959
960
961
962
963
964static int closest_timer(const struct sge *s, int us)
965{
966 int i, timer_idx = 0, min_delta = INT_MAX;
967
968 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) {
969 int delta = us - s->timer_val[i];
970 if (delta < 0)
971 delta = -delta;
972 if (delta < min_delta) {
973 min_delta = delta;
974 timer_idx = i;
975 }
976 }
977 return timer_idx;
978}
979
980static int closest_thres(const struct sge *s, int thres)
981{
982 int i, delta, pktcnt_idx = 0, min_delta = INT_MAX;
983
984 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) {
985 delta = thres - s->counter_val[i];
986 if (delta < 0)
987 delta = -delta;
988 if (delta < min_delta) {
989 min_delta = delta;
990 pktcnt_idx = i;
991 }
992 }
993 return pktcnt_idx;
994}
995
996
997
998
999static unsigned int qtimer_val(const struct adapter *adapter,
1000 const struct sge_rspq *rspq)
1001{
1002 unsigned int timer_idx = QINTR_TIMER_IDX_G(rspq->intr_params);
1003
1004 return timer_idx < SGE_NTIMERS
1005 ? adapter->sge.timer_val[timer_idx]
1006 : 0;
1007}
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020static int set_rxq_intr_params(struct adapter *adapter, struct sge_rspq *rspq,
1021 unsigned int us, unsigned int cnt)
1022{
1023 unsigned int timer_idx;
1024
1025
1026
1027
1028
1029 if ((us | cnt) == 0)
1030 cnt = 1;
1031
1032
1033
1034
1035
1036
1037
1038 if (cnt) {
1039 int err;
1040 u32 v, pktcnt_idx;
1041
1042 pktcnt_idx = closest_thres(&adapter->sge, cnt);
1043 if (rspq->desc && rspq->pktcnt_idx != pktcnt_idx) {
1044 v = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DMAQ) |
1045 FW_PARAMS_PARAM_X_V(
1046 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) |
1047 FW_PARAMS_PARAM_YZ_V(rspq->cntxt_id);
1048 err = t4vf_set_params(adapter, 1, &v, &pktcnt_idx);
1049 if (err)
1050 return err;
1051 }
1052 rspq->pktcnt_idx = pktcnt_idx;
1053 }
1054
1055
1056
1057
1058
1059 timer_idx = (us == 0
1060 ? SGE_TIMER_RSTRT_CNTR
1061 : closest_timer(&adapter->sge, us));
1062
1063
1064
1065
1066
1067 rspq->intr_params = (QINTR_TIMER_IDX_V(timer_idx) |
1068 QINTR_CNT_EN_V(cnt > 0));
1069 return 0;
1070}
1071
1072
1073
1074
1075
1076
1077static inline unsigned int mk_adap_vers(const struct adapter *adapter)
1078{
1079
1080
1081
1082 return CHELSIO_CHIP_VERSION(adapter->params.chip) | (0x3f << 10);
1083}
1084
1085
1086
1087
1088static int cxgb4vf_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1089{
1090 int ret = 0;
1091
1092 switch (cmd) {
1093
1094
1095
1096
1097
1098
1099 default:
1100 ret = -EOPNOTSUPP;
1101 break;
1102 }
1103 return ret;
1104}
1105
1106
1107
1108
1109static int cxgb4vf_change_mtu(struct net_device *dev, int new_mtu)
1110{
1111 int ret;
1112 struct port_info *pi = netdev_priv(dev);
1113
1114
1115 if (new_mtu < 81)
1116 return -EINVAL;
1117
1118 ret = t4vf_set_rxmode(pi->adapter, pi->viid, new_mtu,
1119 -1, -1, -1, -1, true);
1120 if (!ret)
1121 dev->mtu = new_mtu;
1122 return ret;
1123}
1124
1125static netdev_features_t cxgb4vf_fix_features(struct net_device *dev,
1126 netdev_features_t features)
1127{
1128
1129
1130
1131
1132 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1133 features |= NETIF_F_HW_VLAN_CTAG_TX;
1134 else
1135 features &= ~NETIF_F_HW_VLAN_CTAG_TX;
1136
1137 return features;
1138}
1139
1140static int cxgb4vf_set_features(struct net_device *dev,
1141 netdev_features_t features)
1142{
1143 struct port_info *pi = netdev_priv(dev);
1144 netdev_features_t changed = dev->features ^ features;
1145
1146 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1147 t4vf_set_rxmode(pi->adapter, pi->viid, -1, -1, -1, -1,
1148 features & NETIF_F_HW_VLAN_CTAG_TX, 0);
1149
1150 return 0;
1151}
1152
1153
1154
1155
1156static int cxgb4vf_set_mac_addr(struct net_device *dev, void *_addr)
1157{
1158 int ret;
1159 struct sockaddr *addr = _addr;
1160 struct port_info *pi = netdev_priv(dev);
1161
1162 if (!is_valid_ether_addr(addr->sa_data))
1163 return -EADDRNOTAVAIL;
1164
1165 ret = t4vf_change_mac(pi->adapter, pi->viid, pi->xact_addr_filt,
1166 addr->sa_data, true);
1167 if (ret < 0)
1168 return ret;
1169
1170 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1171 pi->xact_addr_filt = ret;
1172 return 0;
1173}
1174
1175#ifdef CONFIG_NET_POLL_CONTROLLER
1176
1177
1178
1179
1180static void cxgb4vf_poll_controller(struct net_device *dev)
1181{
1182 struct port_info *pi = netdev_priv(dev);
1183 struct adapter *adapter = pi->adapter;
1184
1185 if (adapter->flags & USING_MSIX) {
1186 struct sge_eth_rxq *rxq;
1187 int nqsets;
1188
1189 rxq = &adapter->sge.ethrxq[pi->first_qset];
1190 for (nqsets = pi->nqsets; nqsets; nqsets--) {
1191 t4vf_sge_intr_msix(0, &rxq->rspq);
1192 rxq++;
1193 }
1194 } else
1195 t4vf_intr_handler(adapter)(0, adapter);
1196}
1197#endif
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207static unsigned int t4vf_from_fw_linkcaps(enum fw_port_type type,
1208 unsigned int caps)
1209{
1210 unsigned int v = 0;
1211
1212 if (type == FW_PORT_TYPE_BT_SGMII || type == FW_PORT_TYPE_BT_XFI ||
1213 type == FW_PORT_TYPE_BT_XAUI) {
1214 v |= SUPPORTED_TP;
1215 if (caps & FW_PORT_CAP_SPEED_100M)
1216 v |= SUPPORTED_100baseT_Full;
1217 if (caps & FW_PORT_CAP_SPEED_1G)
1218 v |= SUPPORTED_1000baseT_Full;
1219 if (caps & FW_PORT_CAP_SPEED_10G)
1220 v |= SUPPORTED_10000baseT_Full;
1221 } else if (type == FW_PORT_TYPE_KX4 || type == FW_PORT_TYPE_KX) {
1222 v |= SUPPORTED_Backplane;
1223 if (caps & FW_PORT_CAP_SPEED_1G)
1224 v |= SUPPORTED_1000baseKX_Full;
1225 if (caps & FW_PORT_CAP_SPEED_10G)
1226 v |= SUPPORTED_10000baseKX4_Full;
1227 } else if (type == FW_PORT_TYPE_KR)
1228 v |= SUPPORTED_Backplane | SUPPORTED_10000baseKR_Full;
1229 else if (type == FW_PORT_TYPE_BP_AP)
1230 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
1231 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full;
1232 else if (type == FW_PORT_TYPE_BP4_AP)
1233 v |= SUPPORTED_Backplane | SUPPORTED_10000baseR_FEC |
1234 SUPPORTED_10000baseKR_Full | SUPPORTED_1000baseKX_Full |
1235 SUPPORTED_10000baseKX4_Full;
1236 else if (type == FW_PORT_TYPE_FIBER_XFI ||
1237 type == FW_PORT_TYPE_FIBER_XAUI ||
1238 type == FW_PORT_TYPE_SFP ||
1239 type == FW_PORT_TYPE_QSFP_10G ||
1240 type == FW_PORT_TYPE_QSA) {
1241 v |= SUPPORTED_FIBRE;
1242 if (caps & FW_PORT_CAP_SPEED_1G)
1243 v |= SUPPORTED_1000baseT_Full;
1244 if (caps & FW_PORT_CAP_SPEED_10G)
1245 v |= SUPPORTED_10000baseT_Full;
1246 } else if (type == FW_PORT_TYPE_BP40_BA ||
1247 type == FW_PORT_TYPE_QSFP) {
1248 v |= SUPPORTED_40000baseSR4_Full;
1249 v |= SUPPORTED_FIBRE;
1250 }
1251
1252 if (caps & FW_PORT_CAP_ANEG)
1253 v |= SUPPORTED_Autoneg;
1254 return v;
1255}
1256
1257static int cxgb4vf_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1258{
1259 const struct port_info *p = netdev_priv(dev);
1260
1261 if (p->port_type == FW_PORT_TYPE_BT_SGMII ||
1262 p->port_type == FW_PORT_TYPE_BT_XFI ||
1263 p->port_type == FW_PORT_TYPE_BT_XAUI)
1264 cmd->port = PORT_TP;
1265 else if (p->port_type == FW_PORT_TYPE_FIBER_XFI ||
1266 p->port_type == FW_PORT_TYPE_FIBER_XAUI)
1267 cmd->port = PORT_FIBRE;
1268 else if (p->port_type == FW_PORT_TYPE_SFP ||
1269 p->port_type == FW_PORT_TYPE_QSFP_10G ||
1270 p->port_type == FW_PORT_TYPE_QSA ||
1271 p->port_type == FW_PORT_TYPE_QSFP) {
1272 if (p->mod_type == FW_PORT_MOD_TYPE_LR ||
1273 p->mod_type == FW_PORT_MOD_TYPE_SR ||
1274 p->mod_type == FW_PORT_MOD_TYPE_ER ||
1275 p->mod_type == FW_PORT_MOD_TYPE_LRM)
1276 cmd->port = PORT_FIBRE;
1277 else if (p->mod_type == FW_PORT_MOD_TYPE_TWINAX_PASSIVE ||
1278 p->mod_type == FW_PORT_MOD_TYPE_TWINAX_ACTIVE)
1279 cmd->port = PORT_DA;
1280 else
1281 cmd->port = PORT_OTHER;
1282 } else
1283 cmd->port = PORT_OTHER;
1284
1285 if (p->mdio_addr >= 0) {
1286 cmd->phy_address = p->mdio_addr;
1287 cmd->transceiver = XCVR_EXTERNAL;
1288 cmd->mdio_support = p->port_type == FW_PORT_TYPE_BT_SGMII ?
1289 MDIO_SUPPORTS_C22 : MDIO_SUPPORTS_C45;
1290 } else {
1291 cmd->phy_address = 0;
1292 cmd->transceiver = XCVR_INTERNAL;
1293 cmd->mdio_support = 0;
1294 }
1295
1296 cmd->supported = t4vf_from_fw_linkcaps(p->port_type,
1297 p->link_cfg.supported);
1298 cmd->advertising = t4vf_from_fw_linkcaps(p->port_type,
1299 p->link_cfg.advertising);
1300 ethtool_cmd_speed_set(cmd,
1301 netif_carrier_ok(dev) ? p->link_cfg.speed : 0);
1302 cmd->duplex = DUPLEX_FULL;
1303 cmd->autoneg = p->link_cfg.autoneg;
1304 cmd->maxtxpkt = 0;
1305 cmd->maxrxpkt = 0;
1306 return 0;
1307}
1308
1309
1310
1311
1312static void cxgb4vf_get_drvinfo(struct net_device *dev,
1313 struct ethtool_drvinfo *drvinfo)
1314{
1315 struct adapter *adapter = netdev2adap(dev);
1316
1317 strlcpy(drvinfo->driver, KBUILD_MODNAME, sizeof(drvinfo->driver));
1318 strlcpy(drvinfo->version, DRV_VERSION, sizeof(drvinfo->version));
1319 strlcpy(drvinfo->bus_info, pci_name(to_pci_dev(dev->dev.parent)),
1320 sizeof(drvinfo->bus_info));
1321 snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version),
1322 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1323 FW_HDR_FW_VER_MAJOR_G(adapter->params.dev.fwrev),
1324 FW_HDR_FW_VER_MINOR_G(adapter->params.dev.fwrev),
1325 FW_HDR_FW_VER_MICRO_G(adapter->params.dev.fwrev),
1326 FW_HDR_FW_VER_BUILD_G(adapter->params.dev.fwrev),
1327 FW_HDR_FW_VER_MAJOR_G(adapter->params.dev.tprev),
1328 FW_HDR_FW_VER_MINOR_G(adapter->params.dev.tprev),
1329 FW_HDR_FW_VER_MICRO_G(adapter->params.dev.tprev),
1330 FW_HDR_FW_VER_BUILD_G(adapter->params.dev.tprev));
1331}
1332
1333
1334
1335
1336static u32 cxgb4vf_get_msglevel(struct net_device *dev)
1337{
1338 return netdev2adap(dev)->msg_enable;
1339}
1340
1341
1342
1343
1344static void cxgb4vf_set_msglevel(struct net_device *dev, u32 msglevel)
1345{
1346 netdev2adap(dev)->msg_enable = msglevel;
1347}
1348
1349
1350
1351
1352
1353
1354
1355static void cxgb4vf_get_ringparam(struct net_device *dev,
1356 struct ethtool_ringparam *rp)
1357{
1358 const struct port_info *pi = netdev_priv(dev);
1359 const struct sge *s = &pi->adapter->sge;
1360
1361 rp->rx_max_pending = MAX_RX_BUFFERS;
1362 rp->rx_mini_max_pending = MAX_RSPQ_ENTRIES;
1363 rp->rx_jumbo_max_pending = 0;
1364 rp->tx_max_pending = MAX_TXQ_ENTRIES;
1365
1366 rp->rx_pending = s->ethrxq[pi->first_qset].fl.size - MIN_FL_RESID;
1367 rp->rx_mini_pending = s->ethrxq[pi->first_qset].rspq.size;
1368 rp->rx_jumbo_pending = 0;
1369 rp->tx_pending = s->ethtxq[pi->first_qset].q.size;
1370}
1371
1372
1373
1374
1375
1376
1377
1378static int cxgb4vf_set_ringparam(struct net_device *dev,
1379 struct ethtool_ringparam *rp)
1380{
1381 const struct port_info *pi = netdev_priv(dev);
1382 struct adapter *adapter = pi->adapter;
1383 struct sge *s = &adapter->sge;
1384 int qs;
1385
1386 if (rp->rx_pending > MAX_RX_BUFFERS ||
1387 rp->rx_jumbo_pending ||
1388 rp->tx_pending > MAX_TXQ_ENTRIES ||
1389 rp->rx_mini_pending > MAX_RSPQ_ENTRIES ||
1390 rp->rx_mini_pending < MIN_RSPQ_ENTRIES ||
1391 rp->rx_pending < MIN_FL_ENTRIES ||
1392 rp->tx_pending < MIN_TXQ_ENTRIES)
1393 return -EINVAL;
1394
1395 if (adapter->flags & FULL_INIT_DONE)
1396 return -EBUSY;
1397
1398 for (qs = pi->first_qset; qs < pi->first_qset + pi->nqsets; qs++) {
1399 s->ethrxq[qs].fl.size = rp->rx_pending + MIN_FL_RESID;
1400 s->ethrxq[qs].rspq.size = rp->rx_mini_pending;
1401 s->ethtxq[qs].q.size = rp->tx_pending;
1402 }
1403 return 0;
1404}
1405
1406
1407
1408
1409
1410
1411static int cxgb4vf_get_coalesce(struct net_device *dev,
1412 struct ethtool_coalesce *coalesce)
1413{
1414 const struct port_info *pi = netdev_priv(dev);
1415 const struct adapter *adapter = pi->adapter;
1416 const struct sge_rspq *rspq = &adapter->sge.ethrxq[pi->first_qset].rspq;
1417
1418 coalesce->rx_coalesce_usecs = qtimer_val(adapter, rspq);
1419 coalesce->rx_max_coalesced_frames =
1420 ((rspq->intr_params & QINTR_CNT_EN_F)
1421 ? adapter->sge.counter_val[rspq->pktcnt_idx]
1422 : 0);
1423 return 0;
1424}
1425
1426
1427
1428
1429
1430
1431static int cxgb4vf_set_coalesce(struct net_device *dev,
1432 struct ethtool_coalesce *coalesce)
1433{
1434 const struct port_info *pi = netdev_priv(dev);
1435 struct adapter *adapter = pi->adapter;
1436
1437 return set_rxq_intr_params(adapter,
1438 &adapter->sge.ethrxq[pi->first_qset].rspq,
1439 coalesce->rx_coalesce_usecs,
1440 coalesce->rx_max_coalesced_frames);
1441}
1442
1443
1444
1445
1446static void cxgb4vf_get_pauseparam(struct net_device *dev,
1447 struct ethtool_pauseparam *pauseparam)
1448{
1449 struct port_info *pi = netdev_priv(dev);
1450
1451 pauseparam->autoneg = (pi->link_cfg.requested_fc & PAUSE_AUTONEG) != 0;
1452 pauseparam->rx_pause = (pi->link_cfg.fc & PAUSE_RX) != 0;
1453 pauseparam->tx_pause = (pi->link_cfg.fc & PAUSE_TX) != 0;
1454}
1455
1456
1457
1458
1459static int cxgb4vf_phys_id(struct net_device *dev,
1460 enum ethtool_phys_id_state state)
1461{
1462 unsigned int val;
1463 struct port_info *pi = netdev_priv(dev);
1464
1465 if (state == ETHTOOL_ID_ACTIVE)
1466 val = 0xffff;
1467 else if (state == ETHTOOL_ID_INACTIVE)
1468 val = 0;
1469 else
1470 return -EINVAL;
1471
1472 return t4vf_identify_port(pi->adapter, pi->viid, val);
1473}
1474
1475
1476
1477
1478struct queue_port_stats {
1479 u64 tso;
1480 u64 tx_csum;
1481 u64 rx_csum;
1482 u64 vlan_ex;
1483 u64 vlan_ins;
1484 u64 lro_pkts;
1485 u64 lro_merged;
1486};
1487
1488
1489
1490
1491
1492
1493static const char stats_strings[][ETH_GSTRING_LEN] = {
1494
1495
1496
1497 "TxBroadcastBytes ",
1498 "TxBroadcastFrames ",
1499 "TxMulticastBytes ",
1500 "TxMulticastFrames ",
1501 "TxUnicastBytes ",
1502 "TxUnicastFrames ",
1503 "TxDroppedFrames ",
1504 "TxOffloadBytes ",
1505 "TxOffloadFrames ",
1506 "RxBroadcastBytes ",
1507 "RxBroadcastFrames ",
1508 "RxMulticastBytes ",
1509 "RxMulticastFrames ",
1510 "RxUnicastBytes ",
1511 "RxUnicastFrames ",
1512 "RxErrorFrames ",
1513
1514
1515
1516
1517
1518 "TSO ",
1519 "TxCsumOffload ",
1520 "RxCsumGood ",
1521 "VLANextractions ",
1522 "VLANinsertions ",
1523 "GROPackets ",
1524 "GROMerged ",
1525};
1526
1527
1528
1529
1530static int cxgb4vf_get_sset_count(struct net_device *dev, int sset)
1531{
1532 switch (sset) {
1533 case ETH_SS_STATS:
1534 return ARRAY_SIZE(stats_strings);
1535 default:
1536 return -EOPNOTSUPP;
1537 }
1538
1539}
1540
1541
1542
1543
1544static void cxgb4vf_get_strings(struct net_device *dev,
1545 u32 sset,
1546 u8 *data)
1547{
1548 switch (sset) {
1549 case ETH_SS_STATS:
1550 memcpy(data, stats_strings, sizeof(stats_strings));
1551 break;
1552 }
1553}
1554
1555
1556
1557
1558
1559static void collect_sge_port_stats(const struct adapter *adapter,
1560 const struct port_info *pi,
1561 struct queue_port_stats *stats)
1562{
1563 const struct sge_eth_txq *txq = &adapter->sge.ethtxq[pi->first_qset];
1564 const struct sge_eth_rxq *rxq = &adapter->sge.ethrxq[pi->first_qset];
1565 int qs;
1566
1567 memset(stats, 0, sizeof(*stats));
1568 for (qs = 0; qs < pi->nqsets; qs++, rxq++, txq++) {
1569 stats->tso += txq->tso;
1570 stats->tx_csum += txq->tx_cso;
1571 stats->rx_csum += rxq->stats.rx_cso;
1572 stats->vlan_ex += rxq->stats.vlan_ex;
1573 stats->vlan_ins += txq->vlan_ins;
1574 stats->lro_pkts += rxq->stats.lro_pkts;
1575 stats->lro_merged += rxq->stats.lro_merged;
1576 }
1577}
1578
1579
1580
1581
1582static void cxgb4vf_get_ethtool_stats(struct net_device *dev,
1583 struct ethtool_stats *stats,
1584 u64 *data)
1585{
1586 struct port_info *pi = netdev2pinfo(dev);
1587 struct adapter *adapter = pi->adapter;
1588 int err = t4vf_get_port_stats(adapter, pi->pidx,
1589 (struct t4vf_port_stats *)data);
1590 if (err)
1591 memset(data, 0, sizeof(struct t4vf_port_stats));
1592
1593 data += sizeof(struct t4vf_port_stats) / sizeof(u64);
1594 collect_sge_port_stats(adapter, pi, (struct queue_port_stats *)data);
1595}
1596
1597
1598
1599
1600static int cxgb4vf_get_regs_len(struct net_device *dev)
1601{
1602 return T4VF_REGMAP_SIZE;
1603}
1604
1605
1606
1607
1608static void reg_block_dump(struct adapter *adapter, void *regbuf,
1609 unsigned int start, unsigned int end)
1610{
1611 u32 *bp = regbuf + start - T4VF_REGMAP_START;
1612
1613 for ( ; start <= end; start += sizeof(u32)) {
1614
1615
1616
1617
1618
1619 if (start == T4VF_CIM_BASE_ADDR + CIM_VF_EXT_MAILBOX_CTRL)
1620 *bp++ = 0xffff;
1621 else
1622 *bp++ = t4_read_reg(adapter, start);
1623 }
1624}
1625
1626
1627
1628
1629static void cxgb4vf_get_regs(struct net_device *dev,
1630 struct ethtool_regs *regs,
1631 void *regbuf)
1632{
1633 struct adapter *adapter = netdev2adap(dev);
1634
1635 regs->version = mk_adap_vers(adapter);
1636
1637
1638
1639
1640 memset(regbuf, 0, T4VF_REGMAP_SIZE);
1641
1642 reg_block_dump(adapter, regbuf,
1643 T4VF_SGE_BASE_ADDR + T4VF_MOD_MAP_SGE_FIRST,
1644 T4VF_SGE_BASE_ADDR + T4VF_MOD_MAP_SGE_LAST);
1645 reg_block_dump(adapter, regbuf,
1646 T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_FIRST,
1647 T4VF_MPS_BASE_ADDR + T4VF_MOD_MAP_MPS_LAST);
1648
1649
1650
1651 reg_block_dump(adapter, regbuf,
1652 T4VF_PL_BASE_ADDR + T4VF_MOD_MAP_PL_FIRST,
1653 T4VF_PL_BASE_ADDR + (is_t4(adapter->params.chip)
1654 ? PL_VF_WHOAMI_A : PL_VF_REVISION_A));
1655 reg_block_dump(adapter, regbuf,
1656 T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_FIRST,
1657 T4VF_CIM_BASE_ADDR + T4VF_MOD_MAP_CIM_LAST);
1658
1659 reg_block_dump(adapter, regbuf,
1660 T4VF_MBDATA_BASE_ADDR + T4VF_MBDATA_FIRST,
1661 T4VF_MBDATA_BASE_ADDR + T4VF_MBDATA_LAST);
1662}
1663
1664
1665
1666
1667static void cxgb4vf_get_wol(struct net_device *dev,
1668 struct ethtool_wolinfo *wol)
1669{
1670 wol->supported = 0;
1671 wol->wolopts = 0;
1672 memset(&wol->sopass, 0, sizeof(wol->sopass));
1673}
1674
1675
1676
1677
1678#define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
1679
1680static const struct ethtool_ops cxgb4vf_ethtool_ops = {
1681 .get_settings = cxgb4vf_get_settings,
1682 .get_drvinfo = cxgb4vf_get_drvinfo,
1683 .get_msglevel = cxgb4vf_get_msglevel,
1684 .set_msglevel = cxgb4vf_set_msglevel,
1685 .get_ringparam = cxgb4vf_get_ringparam,
1686 .set_ringparam = cxgb4vf_set_ringparam,
1687 .get_coalesce = cxgb4vf_get_coalesce,
1688 .set_coalesce = cxgb4vf_set_coalesce,
1689 .get_pauseparam = cxgb4vf_get_pauseparam,
1690 .get_link = ethtool_op_get_link,
1691 .get_strings = cxgb4vf_get_strings,
1692 .set_phys_id = cxgb4vf_phys_id,
1693 .get_sset_count = cxgb4vf_get_sset_count,
1694 .get_ethtool_stats = cxgb4vf_get_ethtool_stats,
1695 .get_regs_len = cxgb4vf_get_regs_len,
1696 .get_regs = cxgb4vf_get_regs,
1697 .get_wol = cxgb4vf_get_wol,
1698};
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708#define QPL 4
1709
1710static int sge_qinfo_show(struct seq_file *seq, void *v)
1711{
1712 struct adapter *adapter = seq->private;
1713 int eth_entries = DIV_ROUND_UP(adapter->sge.ethqsets, QPL);
1714 int qs, r = (uintptr_t)v - 1;
1715
1716 if (r)
1717 seq_putc(seq, '\n');
1718
1719 #define S3(fmt_spec, s, v) \
1720 do {\
1721 seq_printf(seq, "%-12s", s); \
1722 for (qs = 0; qs < n; ++qs) \
1723 seq_printf(seq, " %16" fmt_spec, v); \
1724 seq_putc(seq, '\n'); \
1725 } while (0)
1726 #define S(s, v) S3("s", s, v)
1727 #define T(s, v) S3("u", s, txq[qs].v)
1728 #define R(s, v) S3("u", s, rxq[qs].v)
1729
1730 if (r < eth_entries) {
1731 const struct sge_eth_rxq *rxq = &adapter->sge.ethrxq[r * QPL];
1732 const struct sge_eth_txq *txq = &adapter->sge.ethtxq[r * QPL];
1733 int n = min(QPL, adapter->sge.ethqsets - QPL * r);
1734
1735 S("QType:", "Ethernet");
1736 S("Interface:",
1737 (rxq[qs].rspq.netdev
1738 ? rxq[qs].rspq.netdev->name
1739 : "N/A"));
1740 S3("d", "Port:",
1741 (rxq[qs].rspq.netdev
1742 ? ((struct port_info *)
1743 netdev_priv(rxq[qs].rspq.netdev))->port_id
1744 : -1));
1745 T("TxQ ID:", q.abs_id);
1746 T("TxQ size:", q.size);
1747 T("TxQ inuse:", q.in_use);
1748 T("TxQ PIdx:", q.pidx);
1749 T("TxQ CIdx:", q.cidx);
1750 R("RspQ ID:", rspq.abs_id);
1751 R("RspQ size:", rspq.size);
1752 R("RspQE size:", rspq.iqe_len);
1753 S3("u", "Intr delay:", qtimer_val(adapter, &rxq[qs].rspq));
1754 S3("u", "Intr pktcnt:",
1755 adapter->sge.counter_val[rxq[qs].rspq.pktcnt_idx]);
1756 R("RspQ CIdx:", rspq.cidx);
1757 R("RspQ Gen:", rspq.gen);
1758 R("FL ID:", fl.abs_id);
1759 R("FL size:", fl.size - MIN_FL_RESID);
1760 R("FL avail:", fl.avail);
1761 R("FL PIdx:", fl.pidx);
1762 R("FL CIdx:", fl.cidx);
1763 return 0;
1764 }
1765
1766 r -= eth_entries;
1767 if (r == 0) {
1768 const struct sge_rspq *evtq = &adapter->sge.fw_evtq;
1769
1770 seq_printf(seq, "%-12s %16s\n", "QType:", "FW event queue");
1771 seq_printf(seq, "%-12s %16u\n", "RspQ ID:", evtq->abs_id);
1772 seq_printf(seq, "%-12s %16u\n", "Intr delay:",
1773 qtimer_val(adapter, evtq));
1774 seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:",
1775 adapter->sge.counter_val[evtq->pktcnt_idx]);
1776 seq_printf(seq, "%-12s %16u\n", "RspQ Cidx:", evtq->cidx);
1777 seq_printf(seq, "%-12s %16u\n", "RspQ Gen:", evtq->gen);
1778 } else if (r == 1) {
1779 const struct sge_rspq *intrq = &adapter->sge.intrq;
1780
1781 seq_printf(seq, "%-12s %16s\n", "QType:", "Interrupt Queue");
1782 seq_printf(seq, "%-12s %16u\n", "RspQ ID:", intrq->abs_id);
1783 seq_printf(seq, "%-12s %16u\n", "Intr delay:",
1784 qtimer_val(adapter, intrq));
1785 seq_printf(seq, "%-12s %16u\n", "Intr pktcnt:",
1786 adapter->sge.counter_val[intrq->pktcnt_idx]);
1787 seq_printf(seq, "%-12s %16u\n", "RspQ Cidx:", intrq->cidx);
1788 seq_printf(seq, "%-12s %16u\n", "RspQ Gen:", intrq->gen);
1789 }
1790
1791 #undef R
1792 #undef T
1793 #undef S
1794 #undef S3
1795
1796 return 0;
1797}
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807static int sge_queue_entries(const struct adapter *adapter)
1808{
1809 return DIV_ROUND_UP(adapter->sge.ethqsets, QPL) + 1 +
1810 ((adapter->flags & USING_MSI) != 0);
1811}
1812
1813static void *sge_queue_start(struct seq_file *seq, loff_t *pos)
1814{
1815 int entries = sge_queue_entries(seq->private);
1816
1817 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
1818}
1819
1820static void sge_queue_stop(struct seq_file *seq, void *v)
1821{
1822}
1823
1824static void *sge_queue_next(struct seq_file *seq, void *v, loff_t *pos)
1825{
1826 int entries = sge_queue_entries(seq->private);
1827
1828 ++*pos;
1829 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
1830}
1831
1832static const struct seq_operations sge_qinfo_seq_ops = {
1833 .start = sge_queue_start,
1834 .next = sge_queue_next,
1835 .stop = sge_queue_stop,
1836 .show = sge_qinfo_show
1837};
1838
1839static int sge_qinfo_open(struct inode *inode, struct file *file)
1840{
1841 int res = seq_open(file, &sge_qinfo_seq_ops);
1842
1843 if (!res) {
1844 struct seq_file *seq = file->private_data;
1845 seq->private = inode->i_private;
1846 }
1847 return res;
1848}
1849
1850static const struct file_operations sge_qinfo_debugfs_fops = {
1851 .owner = THIS_MODULE,
1852 .open = sge_qinfo_open,
1853 .read = seq_read,
1854 .llseek = seq_lseek,
1855 .release = seq_release,
1856};
1857
1858
1859
1860
1861#define QPL 4
1862
1863static int sge_qstats_show(struct seq_file *seq, void *v)
1864{
1865 struct adapter *adapter = seq->private;
1866 int eth_entries = DIV_ROUND_UP(adapter->sge.ethqsets, QPL);
1867 int qs, r = (uintptr_t)v - 1;
1868
1869 if (r)
1870 seq_putc(seq, '\n');
1871
1872 #define S3(fmt, s, v) \
1873 do { \
1874 seq_printf(seq, "%-16s", s); \
1875 for (qs = 0; qs < n; ++qs) \
1876 seq_printf(seq, " %8" fmt, v); \
1877 seq_putc(seq, '\n'); \
1878 } while (0)
1879 #define S(s, v) S3("s", s, v)
1880
1881 #define T3(fmt, s, v) S3(fmt, s, txq[qs].v)
1882 #define T(s, v) T3("lu", s, v)
1883
1884 #define R3(fmt, s, v) S3(fmt, s, rxq[qs].v)
1885 #define R(s, v) R3("lu", s, v)
1886
1887 if (r < eth_entries) {
1888 const struct sge_eth_rxq *rxq = &adapter->sge.ethrxq[r * QPL];
1889 const struct sge_eth_txq *txq = &adapter->sge.ethtxq[r * QPL];
1890 int n = min(QPL, adapter->sge.ethqsets - QPL * r);
1891
1892 S("QType:", "Ethernet");
1893 S("Interface:",
1894 (rxq[qs].rspq.netdev
1895 ? rxq[qs].rspq.netdev->name
1896 : "N/A"));
1897 R3("u", "RspQNullInts:", rspq.unhandled_irqs);
1898 R("RxPackets:", stats.pkts);
1899 R("RxCSO:", stats.rx_cso);
1900 R("VLANxtract:", stats.vlan_ex);
1901 R("LROmerged:", stats.lro_merged);
1902 R("LROpackets:", stats.lro_pkts);
1903 R("RxDrops:", stats.rx_drops);
1904 T("TSO:", tso);
1905 T("TxCSO:", tx_cso);
1906 T("VLANins:", vlan_ins);
1907 T("TxQFull:", q.stops);
1908 T("TxQRestarts:", q.restarts);
1909 T("TxMapErr:", mapping_err);
1910 R("FLAllocErr:", fl.alloc_failed);
1911 R("FLLrgAlcErr:", fl.large_alloc_failed);
1912 R("FLStarving:", fl.starving);
1913 return 0;
1914 }
1915
1916 r -= eth_entries;
1917 if (r == 0) {
1918 const struct sge_rspq *evtq = &adapter->sge.fw_evtq;
1919
1920 seq_printf(seq, "%-8s %16s\n", "QType:", "FW event queue");
1921 seq_printf(seq, "%-16s %8u\n", "RspQNullInts:",
1922 evtq->unhandled_irqs);
1923 seq_printf(seq, "%-16s %8u\n", "RspQ CIdx:", evtq->cidx);
1924 seq_printf(seq, "%-16s %8u\n", "RspQ Gen:", evtq->gen);
1925 } else if (r == 1) {
1926 const struct sge_rspq *intrq = &adapter->sge.intrq;
1927
1928 seq_printf(seq, "%-8s %16s\n", "QType:", "Interrupt Queue");
1929 seq_printf(seq, "%-16s %8u\n", "RspQNullInts:",
1930 intrq->unhandled_irqs);
1931 seq_printf(seq, "%-16s %8u\n", "RspQ CIdx:", intrq->cidx);
1932 seq_printf(seq, "%-16s %8u\n", "RspQ Gen:", intrq->gen);
1933 }
1934
1935 #undef R
1936 #undef T
1937 #undef S
1938 #undef R3
1939 #undef T3
1940 #undef S3
1941
1942 return 0;
1943}
1944
1945
1946
1947
1948
1949
1950
1951
1952
1953static int sge_qstats_entries(const struct adapter *adapter)
1954{
1955 return DIV_ROUND_UP(adapter->sge.ethqsets, QPL) + 1 +
1956 ((adapter->flags & USING_MSI) != 0);
1957}
1958
1959static void *sge_qstats_start(struct seq_file *seq, loff_t *pos)
1960{
1961 int entries = sge_qstats_entries(seq->private);
1962
1963 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
1964}
1965
1966static void sge_qstats_stop(struct seq_file *seq, void *v)
1967{
1968}
1969
1970static void *sge_qstats_next(struct seq_file *seq, void *v, loff_t *pos)
1971{
1972 int entries = sge_qstats_entries(seq->private);
1973
1974 (*pos)++;
1975 return *pos < entries ? (void *)((uintptr_t)*pos + 1) : NULL;
1976}
1977
1978static const struct seq_operations sge_qstats_seq_ops = {
1979 .start = sge_qstats_start,
1980 .next = sge_qstats_next,
1981 .stop = sge_qstats_stop,
1982 .show = sge_qstats_show
1983};
1984
1985static int sge_qstats_open(struct inode *inode, struct file *file)
1986{
1987 int res = seq_open(file, &sge_qstats_seq_ops);
1988
1989 if (res == 0) {
1990 struct seq_file *seq = file->private_data;
1991 seq->private = inode->i_private;
1992 }
1993 return res;
1994}
1995
1996static const struct file_operations sge_qstats_proc_fops = {
1997 .owner = THIS_MODULE,
1998 .open = sge_qstats_open,
1999 .read = seq_read,
2000 .llseek = seq_lseek,
2001 .release = seq_release,
2002};
2003
2004
2005
2006
2007static int resources_show(struct seq_file *seq, void *v)
2008{
2009 struct adapter *adapter = seq->private;
2010 struct vf_resources *vfres = &adapter->params.vfres;
2011
2012 #define S(desc, fmt, var) \
2013 seq_printf(seq, "%-60s " fmt "\n", \
2014 desc " (" #var "):", vfres->var)
2015
2016 S("Virtual Interfaces", "%d", nvi);
2017 S("Egress Queues", "%d", neq);
2018 S("Ethernet Control", "%d", nethctrl);
2019 S("Ingress Queues/w Free Lists/Interrupts", "%d", niqflint);
2020 S("Ingress Queues", "%d", niq);
2021 S("Traffic Class", "%d", tc);
2022 S("Port Access Rights Mask", "%#x", pmask);
2023 S("MAC Address Filters", "%d", nexactf);
2024 S("Firmware Command Read Capabilities", "%#x", r_caps);
2025 S("Firmware Command Write/Execute Capabilities", "%#x", wx_caps);
2026
2027 #undef S
2028
2029 return 0;
2030}
2031
2032static int resources_open(struct inode *inode, struct file *file)
2033{
2034 return single_open(file, resources_show, inode->i_private);
2035}
2036
2037static const struct file_operations resources_proc_fops = {
2038 .owner = THIS_MODULE,
2039 .open = resources_open,
2040 .read = seq_read,
2041 .llseek = seq_lseek,
2042 .release = single_release,
2043};
2044
2045
2046
2047
2048static int interfaces_show(struct seq_file *seq, void *v)
2049{
2050 if (v == SEQ_START_TOKEN) {
2051 seq_puts(seq, "Interface Port VIID\n");
2052 } else {
2053 struct adapter *adapter = seq->private;
2054 int pidx = (uintptr_t)v - 2;
2055 struct net_device *dev = adapter->port[pidx];
2056 struct port_info *pi = netdev_priv(dev);
2057
2058 seq_printf(seq, "%9s %4d %#5x\n",
2059 dev->name, pi->port_id, pi->viid);
2060 }
2061 return 0;
2062}
2063
2064static inline void *interfaces_get_idx(struct adapter *adapter, loff_t pos)
2065{
2066 return pos <= adapter->params.nports
2067 ? (void *)(uintptr_t)(pos + 1)
2068 : NULL;
2069}
2070
2071static void *interfaces_start(struct seq_file *seq, loff_t *pos)
2072{
2073 return *pos
2074 ? interfaces_get_idx(seq->private, *pos)
2075 : SEQ_START_TOKEN;
2076}
2077
2078static void *interfaces_next(struct seq_file *seq, void *v, loff_t *pos)
2079{
2080 (*pos)++;
2081 return interfaces_get_idx(seq->private, *pos);
2082}
2083
2084static void interfaces_stop(struct seq_file *seq, void *v)
2085{
2086}
2087
2088static const struct seq_operations interfaces_seq_ops = {
2089 .start = interfaces_start,
2090 .next = interfaces_next,
2091 .stop = interfaces_stop,
2092 .show = interfaces_show
2093};
2094
2095static int interfaces_open(struct inode *inode, struct file *file)
2096{
2097 int res = seq_open(file, &interfaces_seq_ops);
2098
2099 if (res == 0) {
2100 struct seq_file *seq = file->private_data;
2101 seq->private = inode->i_private;
2102 }
2103 return res;
2104}
2105
2106static const struct file_operations interfaces_proc_fops = {
2107 .owner = THIS_MODULE,
2108 .open = interfaces_open,
2109 .read = seq_read,
2110 .llseek = seq_lseek,
2111 .release = seq_release,
2112};
2113
2114
2115
2116
2117struct cxgb4vf_debugfs_entry {
2118 const char *name;
2119 umode_t mode;
2120 const struct file_operations *fops;
2121};
2122
2123static struct cxgb4vf_debugfs_entry debugfs_files[] = {
2124 { "sge_qinfo", S_IRUGO, &sge_qinfo_debugfs_fops },
2125 { "sge_qstats", S_IRUGO, &sge_qstats_proc_fops },
2126 { "resources", S_IRUGO, &resources_proc_fops },
2127 { "interfaces", S_IRUGO, &interfaces_proc_fops },
2128};
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139static int setup_debugfs(struct adapter *adapter)
2140{
2141 int i;
2142
2143 BUG_ON(IS_ERR_OR_NULL(adapter->debugfs_root));
2144
2145
2146
2147
2148 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
2149 (void)debugfs_create_file(debugfs_files[i].name,
2150 debugfs_files[i].mode,
2151 adapter->debugfs_root,
2152 (void *)adapter,
2153 debugfs_files[i].fops);
2154
2155 return 0;
2156}
2157
2158
2159
2160
2161
2162static void cleanup_debugfs(struct adapter *adapter)
2163{
2164 BUG_ON(IS_ERR_OR_NULL(adapter->debugfs_root));
2165
2166
2167
2168
2169
2170
2171
2172
2173}
2174
2175
2176
2177
2178
2179static void size_nports_qsets(struct adapter *adapter)
2180{
2181 struct vf_resources *vfres = &adapter->params.vfres;
2182 unsigned int ethqsets, pmask_nports;
2183
2184
2185
2186
2187 adapter->params.nports = vfres->nvi;
2188 if (adapter->params.nports > MAX_NPORTS) {
2189 dev_warn(adapter->pdev_dev, "only using %d of %d maximum"
2190 " allowed virtual interfaces\n", MAX_NPORTS,
2191 adapter->params.nports);
2192 adapter->params.nports = MAX_NPORTS;
2193 }
2194
2195
2196
2197
2198
2199
2200 pmask_nports = hweight32(adapter->params.vfres.pmask);
2201 if (pmask_nports < adapter->params.nports) {
2202 dev_warn(adapter->pdev_dev, "only using %d of %d provissioned"
2203 " virtual interfaces; limited by Port Access Rights"
2204 " mask %#x\n", pmask_nports, adapter->params.nports,
2205 adapter->params.vfres.pmask);
2206 adapter->params.nports = pmask_nports;
2207 }
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225 ethqsets = vfres->niqflint - 1 - (msi == MSI_MSI);
2226 if (vfres->nethctrl != ethqsets)
2227 ethqsets = min(vfres->nethctrl, ethqsets);
2228 if (vfres->neq < ethqsets*2)
2229 ethqsets = vfres->neq/2;
2230 if (ethqsets > MAX_ETH_QSETS)
2231 ethqsets = MAX_ETH_QSETS;
2232 adapter->sge.max_ethqsets = ethqsets;
2233
2234 if (adapter->sge.max_ethqsets < adapter->params.nports) {
2235 dev_warn(adapter->pdev_dev, "only using %d of %d available"
2236 " virtual interfaces (too few Queue Sets)\n",
2237 adapter->sge.max_ethqsets, adapter->params.nports);
2238 adapter->params.nports = adapter->sge.max_ethqsets;
2239 }
2240}
2241
2242
2243
2244
2245
2246
2247static int adap_init0(struct adapter *adapter)
2248{
2249 struct sge_params *sge_params = &adapter->params.sge;
2250 struct sge *s = &adapter->sge;
2251 int err;
2252 u32 param, val = 0;
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264 err = t4vf_fw_reset(adapter);
2265 if (err < 0) {
2266 dev_err(adapter->pdev_dev, "FW reset failed: err=%d\n", err);
2267 return err;
2268 }
2269
2270
2271
2272
2273
2274
2275
2276
2277
2278 err = t4vf_get_dev_params(adapter);
2279 if (err) {
2280 dev_err(adapter->pdev_dev, "unable to retrieve adapter"
2281 " device parameters: err=%d\n", err);
2282 return err;
2283 }
2284 err = t4vf_get_vpd_params(adapter);
2285 if (err) {
2286 dev_err(adapter->pdev_dev, "unable to retrieve adapter"
2287 " VPD parameters: err=%d\n", err);
2288 return err;
2289 }
2290 err = t4vf_get_sge_params(adapter);
2291 if (err) {
2292 dev_err(adapter->pdev_dev, "unable to retrieve adapter"
2293 " SGE parameters: err=%d\n", err);
2294 return err;
2295 }
2296 err = t4vf_get_rss_glb_config(adapter);
2297 if (err) {
2298 dev_err(adapter->pdev_dev, "unable to retrieve adapter"
2299 " RSS parameters: err=%d\n", err);
2300 return err;
2301 }
2302 if (adapter->params.rss.mode !=
2303 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
2304 dev_err(adapter->pdev_dev, "unable to operate with global RSS"
2305 " mode %d\n", adapter->params.rss.mode);
2306 return -EINVAL;
2307 }
2308 err = t4vf_sge_init(adapter);
2309 if (err) {
2310 dev_err(adapter->pdev_dev, "unable to use adapter parameters:"
2311 " err=%d\n", err);
2312 return err;
2313 }
2314
2315
2316
2317
2318
2319
2320 param = FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
2321 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP);
2322 val = 1;
2323 (void) t4vf_set_params(adapter, 1, ¶m, &val);
2324
2325
2326
2327
2328
2329 s->timer_val[0] = core_ticks_to_us(adapter,
2330 TIMERVALUE0_G(sge_params->sge_timer_value_0_and_1));
2331 s->timer_val[1] = core_ticks_to_us(adapter,
2332 TIMERVALUE1_G(sge_params->sge_timer_value_0_and_1));
2333 s->timer_val[2] = core_ticks_to_us(adapter,
2334 TIMERVALUE0_G(sge_params->sge_timer_value_2_and_3));
2335 s->timer_val[3] = core_ticks_to_us(adapter,
2336 TIMERVALUE1_G(sge_params->sge_timer_value_2_and_3));
2337 s->timer_val[4] = core_ticks_to_us(adapter,
2338 TIMERVALUE0_G(sge_params->sge_timer_value_4_and_5));
2339 s->timer_val[5] = core_ticks_to_us(adapter,
2340 TIMERVALUE1_G(sge_params->sge_timer_value_4_and_5));
2341
2342 s->counter_val[0] = THRESHOLD_0_G(sge_params->sge_ingress_rx_threshold);
2343 s->counter_val[1] = THRESHOLD_1_G(sge_params->sge_ingress_rx_threshold);
2344 s->counter_val[2] = THRESHOLD_2_G(sge_params->sge_ingress_rx_threshold);
2345 s->counter_val[3] = THRESHOLD_3_G(sge_params->sge_ingress_rx_threshold);
2346
2347
2348
2349
2350
2351
2352 err = t4vf_get_vfres(adapter);
2353 if (err) {
2354 dev_err(adapter->pdev_dev, "unable to get virtual interface"
2355 " resources: err=%d\n", err);
2356 return err;
2357 }
2358
2359
2360 if (adapter->params.vfres.pmask == 0) {
2361 dev_err(adapter->pdev_dev, "no port access configured\n"
2362 "usable!\n");
2363 return -EINVAL;
2364 }
2365 if (adapter->params.vfres.nvi == 0) {
2366 dev_err(adapter->pdev_dev, "no virtual interfaces configured/"
2367 "usable!\n");
2368 return -EINVAL;
2369 }
2370
2371
2372
2373
2374 size_nports_qsets(adapter);
2375
2376 return 0;
2377}
2378
2379static inline void init_rspq(struct sge_rspq *rspq, u8 timer_idx,
2380 u8 pkt_cnt_idx, unsigned int size,
2381 unsigned int iqe_size)
2382{
2383 rspq->intr_params = (QINTR_TIMER_IDX_V(timer_idx) |
2384 (pkt_cnt_idx < SGE_NCOUNTERS ?
2385 QINTR_CNT_EN_F : 0));
2386 rspq->pktcnt_idx = (pkt_cnt_idx < SGE_NCOUNTERS
2387 ? pkt_cnt_idx
2388 : 0);
2389 rspq->iqe_len = iqe_size;
2390 rspq->size = size;
2391}
2392
2393
2394
2395
2396
2397
2398
2399static void cfg_queues(struct adapter *adapter)
2400{
2401 struct sge *s = &adapter->sge;
2402 int q10g, n10g, qidx, pidx, qs;
2403 size_t iqe_size;
2404
2405
2406
2407
2408
2409
2410 BUG_ON((adapter->flags & (USING_MSIX|USING_MSI)) == 0);
2411
2412
2413
2414
2415 n10g = 0;
2416 for_each_port(adapter, pidx)
2417 n10g += is_x_10g_port(&adap2pinfo(adapter, pidx)->link_cfg);
2418
2419
2420
2421
2422
2423 if (n10g == 0)
2424 q10g = 0;
2425 else {
2426 int n1g = (adapter->params.nports - n10g);
2427 q10g = (adapter->sge.max_ethqsets - n1g) / n10g;
2428 if (q10g > num_online_cpus())
2429 q10g = num_online_cpus();
2430 }
2431
2432
2433
2434
2435
2436
2437 qidx = 0;
2438 for_each_port(adapter, pidx) {
2439 struct port_info *pi = adap2pinfo(adapter, pidx);
2440
2441 pi->first_qset = qidx;
2442 pi->nqsets = is_x_10g_port(&pi->link_cfg) ? q10g : 1;
2443 qidx += pi->nqsets;
2444 }
2445 s->ethqsets = qidx;
2446
2447
2448
2449
2450
2451
2452 iqe_size = 64;
2453
2454
2455
2456
2457
2458 for (qs = 0; qs < s->max_ethqsets; qs++) {
2459 struct sge_eth_rxq *rxq = &s->ethrxq[qs];
2460 struct sge_eth_txq *txq = &s->ethtxq[qs];
2461
2462 init_rspq(&rxq->rspq, 0, 0, 1024, iqe_size);
2463 rxq->fl.size = 72;
2464 txq->q.size = 1024;
2465 }
2466
2467
2468
2469
2470
2471 init_rspq(&s->fw_evtq, SGE_TIMER_RSTRT_CNTR, 0, 512, iqe_size);
2472
2473
2474
2475
2476
2477
2478
2479
2480
2481
2482
2483
2484
2485
2486 init_rspq(&s->intrq, SGE_TIMER_RSTRT_CNTR, 0, MSIX_ENTRIES + 1,
2487 iqe_size);
2488}
2489
2490
2491
2492
2493
2494static void reduce_ethqs(struct adapter *adapter, int n)
2495{
2496 int i;
2497 struct port_info *pi;
2498
2499
2500
2501
2502
2503 BUG_ON(n < adapter->params.nports);
2504 while (n < adapter->sge.ethqsets)
2505 for_each_port(adapter, i) {
2506 pi = adap2pinfo(adapter, i);
2507 if (pi->nqsets > 1) {
2508 pi->nqsets--;
2509 adapter->sge.ethqsets--;
2510 if (adapter->sge.ethqsets <= n)
2511 break;
2512 }
2513 }
2514
2515
2516
2517
2518 n = 0;
2519 for_each_port(adapter, i) {
2520 pi = adap2pinfo(adapter, i);
2521 pi->first_qset = n;
2522 n += pi->nqsets;
2523 }
2524}
2525
2526
2527
2528
2529
2530
2531
2532
2533static int enable_msix(struct adapter *adapter)
2534{
2535 int i, want, need, nqsets;
2536 struct msix_entry entries[MSIX_ENTRIES];
2537 struct sge *s = &adapter->sge;
2538
2539 for (i = 0; i < MSIX_ENTRIES; ++i)
2540 entries[i].entry = i;
2541
2542
2543
2544
2545
2546
2547
2548
2549 want = s->max_ethqsets + MSIX_EXTRAS;
2550 need = adapter->params.nports + MSIX_EXTRAS;
2551
2552 want = pci_enable_msix_range(adapter->pdev, entries, need, want);
2553 if (want < 0)
2554 return want;
2555
2556 nqsets = want - MSIX_EXTRAS;
2557 if (nqsets < s->max_ethqsets) {
2558 dev_warn(adapter->pdev_dev, "only enough MSI-X vectors"
2559 " for %d Queue Sets\n", nqsets);
2560 s->max_ethqsets = nqsets;
2561 if (nqsets < s->ethqsets)
2562 reduce_ethqs(adapter, nqsets);
2563 }
2564 for (i = 0; i < want; ++i)
2565 adapter->msix_info[i].vec = entries[i].vector;
2566
2567 return 0;
2568}
2569
2570static const struct net_device_ops cxgb4vf_netdev_ops = {
2571 .ndo_open = cxgb4vf_open,
2572 .ndo_stop = cxgb4vf_stop,
2573 .ndo_start_xmit = t4vf_eth_xmit,
2574 .ndo_get_stats = cxgb4vf_get_stats,
2575 .ndo_set_rx_mode = cxgb4vf_set_rxmode,
2576 .ndo_set_mac_address = cxgb4vf_set_mac_addr,
2577 .ndo_validate_addr = eth_validate_addr,
2578 .ndo_do_ioctl = cxgb4vf_do_ioctl,
2579 .ndo_change_mtu = cxgb4vf_change_mtu,
2580 .ndo_fix_features = cxgb4vf_fix_features,
2581 .ndo_set_features = cxgb4vf_set_features,
2582#ifdef CONFIG_NET_POLL_CONTROLLER
2583 .ndo_poll_controller = cxgb4vf_poll_controller,
2584#endif
2585};
2586
2587
2588
2589
2590
2591
2592static int cxgb4vf_pci_probe(struct pci_dev *pdev,
2593 const struct pci_device_id *ent)
2594{
2595 int pci_using_dac;
2596 int err, pidx;
2597 unsigned int pmask;
2598 struct adapter *adapter;
2599 struct port_info *pi;
2600 struct net_device *netdev;
2601
2602
2603
2604
2605
2606 pr_info_once("%s - version %s\n", DRV_DESC, DRV_VERSION);
2607
2608
2609
2610
2611 err = pci_enable_device(pdev);
2612 if (err) {
2613 dev_err(&pdev->dev, "cannot enable PCI device\n");
2614 return err;
2615 }
2616
2617
2618
2619
2620
2621 err = pci_request_regions(pdev, KBUILD_MODNAME);
2622 if (err) {
2623 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
2624 goto err_disable_device;
2625 }
2626
2627
2628
2629
2630
2631 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
2632 if (err == 0) {
2633 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
2634 if (err) {
2635 dev_err(&pdev->dev, "unable to obtain 64-bit DMA for"
2636 " coherent allocations\n");
2637 goto err_release_regions;
2638 }
2639 pci_using_dac = 1;
2640 } else {
2641 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2642 if (err != 0) {
2643 dev_err(&pdev->dev, "no usable DMA configuration\n");
2644 goto err_release_regions;
2645 }
2646 pci_using_dac = 0;
2647 }
2648
2649
2650
2651
2652 pci_set_master(pdev);
2653
2654
2655
2656
2657 adapter = kzalloc(sizeof(*adapter), GFP_KERNEL);
2658 if (!adapter) {
2659 err = -ENOMEM;
2660 goto err_release_regions;
2661 }
2662 pci_set_drvdata(pdev, adapter);
2663 adapter->pdev = pdev;
2664 adapter->pdev_dev = &pdev->dev;
2665
2666
2667
2668
2669 spin_lock_init(&adapter->stats_lock);
2670
2671
2672
2673
2674 adapter->regs = pci_ioremap_bar(pdev, 0);
2675 if (!adapter->regs) {
2676 dev_err(&pdev->dev, "cannot map device registers\n");
2677 err = -ENOMEM;
2678 goto err_free_adapter;
2679 }
2680
2681
2682
2683 err = t4vf_prep_adapter(adapter);
2684 if (err) {
2685 dev_err(adapter->pdev_dev, "device didn't become ready:"
2686 " err=%d\n", err);
2687 goto err_unmap_bar0;
2688 }
2689
2690
2691
2692
2693 if (!is_t4(adapter->params.chip)) {
2694 adapter->bar2 = ioremap_wc(pci_resource_start(pdev, 2),
2695 pci_resource_len(pdev, 2));
2696 if (!adapter->bar2) {
2697 dev_err(adapter->pdev_dev, "cannot map BAR2 doorbells\n");
2698 err = -ENOMEM;
2699 goto err_unmap_bar0;
2700 }
2701 }
2702
2703
2704
2705 adapter->name = pci_name(pdev);
2706 adapter->msg_enable = dflt_msg_enable;
2707 err = adap_init0(adapter);
2708 if (err)
2709 goto err_unmap_bar;
2710
2711
2712
2713
2714 pmask = adapter->params.vfres.pmask;
2715 for_each_port(adapter, pidx) {
2716 int port_id, viid;
2717
2718
2719
2720
2721
2722
2723
2724 if (pmask == 0)
2725 break;
2726 port_id = ffs(pmask) - 1;
2727 pmask &= ~(1 << port_id);
2728 viid = t4vf_alloc_vi(adapter, port_id);
2729 if (viid < 0) {
2730 dev_err(&pdev->dev, "cannot allocate VI for port %d:"
2731 " err=%d\n", port_id, viid);
2732 err = viid;
2733 goto err_free_dev;
2734 }
2735
2736
2737
2738
2739 netdev = alloc_etherdev_mq(sizeof(struct port_info),
2740 MAX_PORT_QSETS);
2741 if (netdev == NULL) {
2742 t4vf_free_vi(adapter, viid);
2743 err = -ENOMEM;
2744 goto err_free_dev;
2745 }
2746 adapter->port[pidx] = netdev;
2747 SET_NETDEV_DEV(netdev, &pdev->dev);
2748 pi = netdev_priv(netdev);
2749 pi->adapter = adapter;
2750 pi->pidx = pidx;
2751 pi->port_id = port_id;
2752 pi->viid = viid;
2753
2754
2755
2756
2757
2758 pi->xact_addr_filt = -1;
2759 netif_carrier_off(netdev);
2760 netdev->irq = pdev->irq;
2761
2762 netdev->hw_features = NETIF_F_SG | TSO_FLAGS |
2763 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2764 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_RXCSUM;
2765 netdev->vlan_features = NETIF_F_SG | TSO_FLAGS |
2766 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
2767 NETIF_F_HIGHDMA;
2768 netdev->features = netdev->hw_features |
2769 NETIF_F_HW_VLAN_CTAG_TX;
2770 if (pci_using_dac)
2771 netdev->features |= NETIF_F_HIGHDMA;
2772
2773 netdev->priv_flags |= IFF_UNICAST_FLT;
2774
2775 netdev->netdev_ops = &cxgb4vf_netdev_ops;
2776 netdev->ethtool_ops = &cxgb4vf_ethtool_ops;
2777
2778
2779
2780
2781 err = t4vf_port_init(adapter, pidx);
2782 if (err) {
2783 dev_err(&pdev->dev, "cannot initialize port %d\n",
2784 pidx);
2785 goto err_free_dev;
2786 }
2787 }
2788
2789
2790
2791
2792
2793
2794 if (msi == MSI_MSIX && enable_msix(adapter) == 0)
2795 adapter->flags |= USING_MSIX;
2796 else {
2797 if (msi == MSI_MSIX) {
2798 dev_info(adapter->pdev_dev,
2799 "Unable to use MSI-X Interrupts; falling "
2800 "back to MSI Interrupts\n");
2801
2802
2803
2804
2805
2806 msi = MSI_MSI;
2807 size_nports_qsets(adapter);
2808 }
2809 err = pci_enable_msi(pdev);
2810 if (err) {
2811 dev_err(&pdev->dev, "Unable to allocate MSI Interrupts;"
2812 " err=%d\n", err);
2813 goto err_free_dev;
2814 }
2815 adapter->flags |= USING_MSI;
2816 }
2817
2818
2819
2820
2821 cfg_queues(adapter);
2822
2823
2824
2825
2826
2827
2828
2829 for_each_port(adapter, pidx) {
2830 struct port_info *pi = netdev_priv(adapter->port[pidx]);
2831 netdev = adapter->port[pidx];
2832 if (netdev == NULL)
2833 continue;
2834
2835 netif_set_real_num_tx_queues(netdev, pi->nqsets);
2836 netif_set_real_num_rx_queues(netdev, pi->nqsets);
2837
2838 err = register_netdev(netdev);
2839 if (err) {
2840 dev_warn(&pdev->dev, "cannot register net device %s,"
2841 " skipping\n", netdev->name);
2842 continue;
2843 }
2844
2845 set_bit(pidx, &adapter->registered_device_map);
2846 }
2847 if (adapter->registered_device_map == 0) {
2848 dev_err(&pdev->dev, "could not register any net devices\n");
2849 goto err_disable_interrupts;
2850 }
2851
2852
2853
2854
2855 if (!IS_ERR_OR_NULL(cxgb4vf_debugfs_root)) {
2856 adapter->debugfs_root =
2857 debugfs_create_dir(pci_name(pdev),
2858 cxgb4vf_debugfs_root);
2859 if (IS_ERR_OR_NULL(adapter->debugfs_root))
2860 dev_warn(&pdev->dev, "could not create debugfs"
2861 " directory");
2862 else
2863 setup_debugfs(adapter);
2864 }
2865
2866
2867
2868
2869
2870 for_each_port(adapter, pidx) {
2871 dev_info(adapter->pdev_dev, "%s: Chelsio VF NIC PCIe %s\n",
2872 adapter->port[pidx]->name,
2873 (adapter->flags & USING_MSIX) ? "MSI-X" :
2874 (adapter->flags & USING_MSI) ? "MSI" : "");
2875 }
2876
2877
2878
2879
2880 return 0;
2881
2882
2883
2884
2885
2886err_disable_interrupts:
2887 if (adapter->flags & USING_MSIX) {
2888 pci_disable_msix(adapter->pdev);
2889 adapter->flags &= ~USING_MSIX;
2890 } else if (adapter->flags & USING_MSI) {
2891 pci_disable_msi(adapter->pdev);
2892 adapter->flags &= ~USING_MSI;
2893 }
2894
2895err_free_dev:
2896 for_each_port(adapter, pidx) {
2897 netdev = adapter->port[pidx];
2898 if (netdev == NULL)
2899 continue;
2900 pi = netdev_priv(netdev);
2901 t4vf_free_vi(adapter, pi->viid);
2902 if (test_bit(pidx, &adapter->registered_device_map))
2903 unregister_netdev(netdev);
2904 free_netdev(netdev);
2905 }
2906
2907err_unmap_bar:
2908 if (!is_t4(adapter->params.chip))
2909 iounmap(adapter->bar2);
2910
2911err_unmap_bar0:
2912 iounmap(adapter->regs);
2913
2914err_free_adapter:
2915 kfree(adapter);
2916
2917err_release_regions:
2918 pci_release_regions(pdev);
2919 pci_clear_master(pdev);
2920
2921err_disable_device:
2922 pci_disable_device(pdev);
2923
2924 return err;
2925}
2926
2927
2928
2929
2930
2931
2932static void cxgb4vf_pci_remove(struct pci_dev *pdev)
2933{
2934 struct adapter *adapter = pci_get_drvdata(pdev);
2935
2936
2937
2938
2939 if (adapter) {
2940 int pidx;
2941
2942
2943
2944
2945
2946 for_each_port(adapter, pidx)
2947 if (test_bit(pidx, &adapter->registered_device_map))
2948 unregister_netdev(adapter->port[pidx]);
2949 t4vf_sge_stop(adapter);
2950 if (adapter->flags & USING_MSIX) {
2951 pci_disable_msix(adapter->pdev);
2952 adapter->flags &= ~USING_MSIX;
2953 } else if (adapter->flags & USING_MSI) {
2954 pci_disable_msi(adapter->pdev);
2955 adapter->flags &= ~USING_MSI;
2956 }
2957
2958
2959
2960
2961 if (!IS_ERR_OR_NULL(adapter->debugfs_root)) {
2962 cleanup_debugfs(adapter);
2963 debugfs_remove_recursive(adapter->debugfs_root);
2964 }
2965
2966
2967
2968
2969 t4vf_free_sge_resources(adapter);
2970 for_each_port(adapter, pidx) {
2971 struct net_device *netdev = adapter->port[pidx];
2972 struct port_info *pi;
2973
2974 if (netdev == NULL)
2975 continue;
2976
2977 pi = netdev_priv(netdev);
2978 t4vf_free_vi(adapter, pi->viid);
2979 free_netdev(netdev);
2980 }
2981 iounmap(adapter->regs);
2982 if (!is_t4(adapter->params.chip))
2983 iounmap(adapter->bar2);
2984 kfree(adapter);
2985 }
2986
2987
2988
2989
2990 pci_disable_device(pdev);
2991 pci_clear_master(pdev);
2992 pci_release_regions(pdev);
2993}
2994
2995
2996
2997
2998
2999static void cxgb4vf_pci_shutdown(struct pci_dev *pdev)
3000{
3001 struct adapter *adapter;
3002 int pidx;
3003
3004 adapter = pci_get_drvdata(pdev);
3005 if (!adapter)
3006 return;
3007
3008
3009
3010
3011
3012 for_each_port(adapter, pidx)
3013 if (test_bit(pidx, &adapter->registered_device_map))
3014 unregister_netdev(adapter->port[pidx]);
3015
3016
3017
3018
3019 t4vf_sge_stop(adapter);
3020 if (adapter->flags & USING_MSIX) {
3021 pci_disable_msix(adapter->pdev);
3022 adapter->flags &= ~USING_MSIX;
3023 } else if (adapter->flags & USING_MSI) {
3024 pci_disable_msi(adapter->pdev);
3025 adapter->flags &= ~USING_MSI;
3026 }
3027
3028
3029
3030
3031
3032 t4vf_free_sge_resources(adapter);
3033 pci_set_drvdata(pdev, NULL);
3034}
3035
3036
3037
3038#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
3039 static const struct pci_device_id cxgb4vf_pci_tbl[] = {
3040#define CH_PCI_DEVICE_ID_FUNCTION 0x8
3041
3042#define CH_PCI_ID_TABLE_ENTRY(devid) \
3043 { PCI_VDEVICE(CHELSIO, (devid)), 0 }
3044
3045#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END { 0, } }
3046
3047#include "../cxgb4/t4_pci_id_tbl.h"
3048
3049MODULE_DESCRIPTION(DRV_DESC);
3050MODULE_AUTHOR("Chelsio Communications");
3051MODULE_LICENSE("Dual BSD/GPL");
3052MODULE_VERSION(DRV_VERSION);
3053MODULE_DEVICE_TABLE(pci, cxgb4vf_pci_tbl);
3054
3055static struct pci_driver cxgb4vf_driver = {
3056 .name = KBUILD_MODNAME,
3057 .id_table = cxgb4vf_pci_tbl,
3058 .probe = cxgb4vf_pci_probe,
3059 .remove = cxgb4vf_pci_remove,
3060 .shutdown = cxgb4vf_pci_shutdown,
3061};
3062
3063
3064
3065
3066static int __init cxgb4vf_module_init(void)
3067{
3068 int ret;
3069
3070
3071
3072
3073 if (msi != MSI_MSIX && msi != MSI_MSI) {
3074 pr_warn("bad module parameter msi=%d; must be %d (MSI-X or MSI) or %d (MSI)\n",
3075 msi, MSI_MSIX, MSI_MSI);
3076 return -EINVAL;
3077 }
3078
3079
3080 cxgb4vf_debugfs_root = debugfs_create_dir(KBUILD_MODNAME, NULL);
3081 if (IS_ERR_OR_NULL(cxgb4vf_debugfs_root))
3082 pr_warn("could not create debugfs entry, continuing\n");
3083
3084 ret = pci_register_driver(&cxgb4vf_driver);
3085 if (ret < 0 && !IS_ERR_OR_NULL(cxgb4vf_debugfs_root))
3086 debugfs_remove(cxgb4vf_debugfs_root);
3087 return ret;
3088}
3089
3090
3091
3092
3093static void __exit cxgb4vf_module_exit(void)
3094{
3095 pci_unregister_driver(&cxgb4vf_driver);
3096 debugfs_remove(cxgb4vf_debugfs_root);
3097}
3098
3099module_init(cxgb4vf_module_init);
3100module_exit(cxgb4vf_module_exit);
3101