LXR linux/drivers/net/ethernet/cisco/enic/enic.h

   1/*
   2 * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.
   3 * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
   4 *
   5 * This program is free software; you may redistribute it and/or modify
   6 * it under the terms of the GNU General Public License as published by
   7 * the Free Software Foundation; version 2 of the License.
   8 *
   9 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  10 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  11 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  12 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  13 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  14 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  15 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  16 * SOFTWARE.
  17 *
  18 */
  19
  20#ifndef _ENIC_H_
  21#define _ENIC_H_
  22
  23#include "vnic_enet.h"
  24#include "vnic_dev.h"
  25#include "vnic_wq.h"
  26#include "vnic_rq.h"
  27#include "vnic_cq.h"
  28#include "vnic_intr.h"
  29#include "vnic_stats.h"
  30#include "vnic_nic.h"
  31#include "vnic_rss.h"
  32#include <linux/irq.h>
  33
  34#define DRV_NAME                "enic"
  35#define DRV_DESCRIPTION         "Cisco VIC Ethernet NIC Driver"
  36#define DRV_VERSION             "2.3.0.20"
  37#define DRV_COPYRIGHT           "Copyright 2008-2013 Cisco Systems, Inc"
  38
  39#define ENIC_BARS_MAX           6
  40
  41#define ENIC_WQ_MAX             8
  42#define ENIC_RQ_MAX             8
  43#define ENIC_CQ_MAX             (ENIC_WQ_MAX + ENIC_RQ_MAX)
  44#define ENIC_INTR_MAX           (ENIC_CQ_MAX + 2)
  45
  46#define ENIC_AIC_LARGE_PKT_DIFF 3
  47
  48struct enic_msix_entry {
  49        int requested;
  50        char devname[IFNAMSIZ];
  51        irqreturn_t (*isr)(int, void *);
  52        void *devid;
  53        cpumask_var_t affinity_mask;
  54};
  55
  56/* Store only the lower range.  Higher range is given by fw. */
  57struct enic_intr_mod_range {
  58        u32 small_pkt_range_start;
  59        u32 large_pkt_range_start;
  60};
  61
  62struct enic_intr_mod_table {
  63        u32 rx_rate;
  64        u32 range_percent;
  65};
  66
  67#define ENIC_MAX_LINK_SPEEDS            3
  68#define ENIC_LINK_SPEED_10G             10000
  69#define ENIC_LINK_SPEED_4G              4000
  70#define ENIC_LINK_40G_INDEX             2
  71#define ENIC_LINK_10G_INDEX             1
  72#define ENIC_LINK_4G_INDEX              0
  73#define ENIC_RX_COALESCE_RANGE_END      125
  74#define ENIC_AIC_TS_BREAK               100
  75
  76struct enic_rx_coal {
  77        u32 small_pkt_range_start;
  78        u32 large_pkt_range_start;
  79        u32 range_end;
  80        u32 use_adaptive_rx_coalesce;
  81};
  82
  83/* priv_flags */
  84#define ENIC_SRIOV_ENABLED              (1 << 0)
  85
  86/* enic port profile set flags */
  87#define ENIC_PORT_REQUEST_APPLIED       (1 << 0)
  88#define ENIC_SET_REQUEST                (1 << 1)
  89#define ENIC_SET_NAME                   (1 << 2)
  90#define ENIC_SET_INSTANCE               (1 << 3)
  91#define ENIC_SET_HOST                   (1 << 4)
  92
  93struct enic_port_profile {
  94        u32 set;
  95        u8 request;
  96        char name[PORT_PROFILE_MAX];
  97        u8 instance_uuid[PORT_UUID_MAX];
  98        u8 host_uuid[PORT_UUID_MAX];
  99        u8 vf_mac[ETH_ALEN];
 100        u8 mac_addr[ETH_ALEN];
 101};
 102
 103/* enic_rfs_fltr_node - rfs filter node in hash table
 104 *      @@keys: IPv4 5 tuple
 105 *      @flow_id: flow_id of clsf filter provided by kernel
 106 *      @fltr_id: filter id of clsf filter returned by adaptor
 107 *      @rq_id: desired rq index
 108 *      @node: hlist_node
 109 */
 110struct enic_rfs_fltr_node {
 111        struct flow_keys keys;
 112        u32 flow_id;
 113        u16 fltr_id;
 114        u16 rq_id;
 115        struct hlist_node node;
 116};
 117
 118/* enic_rfs_flw_tbl - rfs flow table
 119 *      @max: Maximum number of filters vNIC supports
 120 *      @free: Number of free filters available
 121 *      @toclean: hash table index to clean next
 122 *      @ht_head: hash table list head
 123 *      @lock: spin lock
 124 *      @rfs_may_expire: timer function for enic_rps_may_expire_flow
 125 */
 126struct enic_rfs_flw_tbl {
 127        u16 max;
 128        int free;
 129
 130#define ENIC_RFS_FLW_BITSHIFT   (10)
 131#define ENIC_RFS_FLW_MASK       ((1 << ENIC_RFS_FLW_BITSHIFT) - 1)
 132        u16 toclean:ENIC_RFS_FLW_BITSHIFT;
 133        struct hlist_head ht_head[1 << ENIC_RFS_FLW_BITSHIFT];
 134        spinlock_t lock;
 135        struct timer_list rfs_may_expire;
 136};
 137
 138/* Per-instance private data structure */
 139struct enic {
 140        struct net_device *netdev;
 141        struct pci_dev *pdev;
 142        struct vnic_enet_config config;
 143        struct vnic_dev_bar bar[ENIC_BARS_MAX];
 144        struct vnic_dev *vdev;
 145        struct timer_list notify_timer;
 146        struct work_struct reset;
 147        struct work_struct tx_hang_reset;
 148        struct work_struct change_mtu_work;
 149        struct msix_entry msix_entry[ENIC_INTR_MAX];
 150        struct enic_msix_entry msix[ENIC_INTR_MAX];
 151        u32 msg_enable;
 152        spinlock_t devcmd_lock;
 153        u8 mac_addr[ETH_ALEN];
 154        unsigned int flags;
 155        unsigned int priv_flags;
 156        unsigned int mc_count;
 157        unsigned int uc_count;
 158        u32 port_mtu;
 159        struct enic_rx_coal rx_coalesce_setting;
 160        u32 rx_coalesce_usecs;
 161        u32 tx_coalesce_usecs;
 162#ifdef CONFIG_PCI_IOV
 163        u16 num_vfs;
 164#endif
 165        spinlock_t enic_api_lock;
 166        struct enic_port_profile *pp;
 167
 168        /* work queue cache line section */
 169        ____cacheline_aligned struct vnic_wq wq[ENIC_WQ_MAX];
 170        spinlock_t wq_lock[ENIC_WQ_MAX];
 171        unsigned int wq_count;
 172        u16 loop_enable;
 173        u16 loop_tag;
 174
 175        /* receive queue cache line section */
 176        ____cacheline_aligned struct vnic_rq rq[ENIC_RQ_MAX];
 177        unsigned int rq_count;
 178        u64 rq_truncated_pkts;
 179        u64 rq_bad_fcs;
 180        struct napi_struct napi[ENIC_RQ_MAX + ENIC_WQ_MAX];
 181
 182        /* interrupt resource cache line section */
 183        ____cacheline_aligned struct vnic_intr intr[ENIC_INTR_MAX];
 184        unsigned int intr_count;
 185        u32 __iomem *legacy_pba;                /* memory-mapped */
 186
 187        /* completion queue cache line section */
 188        ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
 189        unsigned int cq_count;
 190        struct enic_rfs_flw_tbl rfs_h;
 191        u32 rx_copybreak;
 192        u8 rss_key[ENIC_RSS_LEN];
 193        struct vnic_gen_stats gen_stats;
 194};
 195
 196static inline struct net_device *vnic_get_netdev(struct vnic_dev *vdev)
 197{
 198        struct enic *enic = vdev->priv;
 199
 200        return enic->netdev;
 201}
 202
 203/* wrappers function for kernel log
 204 */
 205#define vdev_err(vdev, fmt, ...)                                        \
 206        dev_err(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
 207#define vdev_warn(vdev, fmt, ...)                                       \
 208        dev_warn(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
 209#define vdev_info(vdev, fmt, ...)                                       \
 210        dev_info(&(vdev)->pdev->dev, fmt, ##__VA_ARGS__)
 211
 212#define vdev_neterr(vdev, fmt, ...)                                     \
 213        netdev_err(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
 214#define vdev_netwarn(vdev, fmt, ...)                                    \
 215        netdev_warn(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
 216#define vdev_netinfo(vdev, fmt, ...)                                    \
 217        netdev_info(vnic_get_netdev(vdev), fmt, ##__VA_ARGS__)
 218
 219static inline struct device *enic_get_dev(struct enic *enic)
 220{
 221        return &(enic->pdev->dev);
 222}
 223
 224static inline unsigned int enic_cq_rq(struct enic *enic, unsigned int rq)
 225{
 226        return rq;
 227}
 228
 229static inline unsigned int enic_cq_wq(struct enic *enic, unsigned int wq)
 230{
 231        return enic->rq_count + wq;
 232}
 233
 234static inline unsigned int enic_legacy_io_intr(void)
 235{
 236        return 0;
 237}
 238
 239static inline unsigned int enic_legacy_err_intr(void)
 240{
 241        return 1;
 242}
 243
 244static inline unsigned int enic_legacy_notify_intr(void)
 245{
 246        return 2;
 247}
 248
 249static inline unsigned int enic_msix_rq_intr(struct enic *enic,
 250        unsigned int rq)
 251{
 252        return enic->cq[enic_cq_rq(enic, rq)].interrupt_offset;
 253}
 254
 255static inline unsigned int enic_msix_wq_intr(struct enic *enic,
 256        unsigned int wq)
 257{
 258        return enic->cq[enic_cq_wq(enic, wq)].interrupt_offset;
 259}
 260
 261static inline unsigned int enic_msix_err_intr(struct enic *enic)
 262{
 263        return enic->rq_count + enic->wq_count;
 264}
 265
 266static inline unsigned int enic_msix_notify_intr(struct enic *enic)
 267{
 268        return enic->rq_count + enic->wq_count + 1;
 269}
 270
 271static inline bool enic_is_err_intr(struct enic *enic, int intr)
 272{
 273        switch (vnic_dev_get_intr_mode(enic->vdev)) {
 274        case VNIC_DEV_INTR_MODE_INTX:
 275                return intr == enic_legacy_err_intr();
 276        case VNIC_DEV_INTR_MODE_MSIX:
 277                return intr == enic_msix_err_intr(enic);
 278        case VNIC_DEV_INTR_MODE_MSI:
 279        default:
 280                return false;
 281        }
 282}
 283
 284static inline bool enic_is_notify_intr(struct enic *enic, int intr)
 285{
 286        switch (vnic_dev_get_intr_mode(enic->vdev)) {
 287        case VNIC_DEV_INTR_MODE_INTX:
 288                return intr == enic_legacy_notify_intr();
 289        case VNIC_DEV_INTR_MODE_MSIX:
 290                return intr == enic_msix_notify_intr(enic);
 291        case VNIC_DEV_INTR_MODE_MSI:
 292        default:
 293                return false;
 294        }
 295}
 296
 297static inline int enic_dma_map_check(struct enic *enic, dma_addr_t dma_addr)
 298{
 299        if (unlikely(pci_dma_mapping_error(enic->pdev, dma_addr))) {
 300                net_warn_ratelimited("%s: PCI dma mapping failed!\n",
 301                                     enic->netdev->name);
 302                enic->gen_stats.dma_map_error++;
 303
 304                return -ENOMEM;
 305        }
 306
 307        return 0;
 308}
 309
 310void enic_reset_addr_lists(struct enic *enic);
 311int enic_sriov_enabled(struct enic *enic);
 312int enic_is_valid_vf(struct enic *enic, int vf);
 313int enic_is_dynamic(struct enic *enic);
 314void enic_set_ethtool_ops(struct net_device *netdev);
 315int __enic_set_rsskey(struct enic *enic);
 316
 317#endif /* _ENIC_H_ */
 318