1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#include <linux/kernel.h>
20#include <linux/string.h>
21#include <linux/errno.h>
22#include <linux/slab.h>
23#include <linux/delay.h>
24#include <linux/module.h>
25#include <linux/mii.h>
26#include <linux/of_address.h>
27#include <linux/of_mdio.h>
28#include <linux/of_device.h>
29
30#include <asm/io.h>
31#if IS_ENABLED(CONFIG_UCC_GETH)
32#include <soc/fsl/qe/ucc.h>
33#endif
34
35#include "gianfar.h"
36
37#define MIIMIND_BUSY 0x00000001
38#define MIIMIND_NOTVALID 0x00000004
39#define MIIMCFG_INIT_VALUE 0x00000007
40#define MIIMCFG_RESET 0x80000000
41
42#define MII_READ_COMMAND 0x00000001
43
44struct fsl_pq_mii {
45 u32 miimcfg;
46 u32 miimcom;
47 u32 miimadd;
48 u32 miimcon;
49 u32 miimstat;
50 u32 miimind;
51};
52
53struct fsl_pq_mdio {
54 u8 res1[16];
55 u32 ieventm;
56 u32 imaskm;
57 u8 res2[4];
58 u32 emapm;
59 u8 res3[1280];
60 struct fsl_pq_mii mii;
61 u8 res4[28];
62 u32 utbipar;
63 u8 res5[2728];
64} __packed;
65
66
67#define MII_TIMEOUT 1000
68
69struct fsl_pq_mdio_priv {
70 void __iomem *map;
71 struct fsl_pq_mii __iomem *regs;
72};
73
74
75
76
77
78
79
80
81
82
83
84
85
86struct fsl_pq_mdio_data {
87 unsigned int mii_offset;
88 uint32_t __iomem * (*get_tbipa)(void __iomem *p);
89 void (*ucc_configure)(phys_addr_t start, phys_addr_t end);
90};
91
92
93
94
95
96
97
98
99
100
101static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
102 u16 value)
103{
104 struct fsl_pq_mdio_priv *priv = bus->priv;
105 struct fsl_pq_mii __iomem *regs = priv->regs;
106 unsigned int timeout;
107
108
109 iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
110
111
112 iowrite32be(value, ®s->miimcon);
113
114
115 timeout = MII_TIMEOUT;
116 while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
117 cpu_relax();
118 timeout--;
119 }
120
121 return timeout ? 0 : -ETIMEDOUT;
122}
123
124
125
126
127
128
129
130
131
132
133
134static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
135{
136 struct fsl_pq_mdio_priv *priv = bus->priv;
137 struct fsl_pq_mii __iomem *regs = priv->regs;
138 unsigned int timeout;
139 u16 value;
140
141
142 iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
143
144
145 iowrite32be(0, ®s->miimcom);
146 iowrite32be(MII_READ_COMMAND, ®s->miimcom);
147
148
149 timeout = MII_TIMEOUT;
150 while ((ioread32be(®s->miimind) &
151 (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) {
152 cpu_relax();
153 timeout--;
154 }
155
156 if (!timeout)
157 return -ETIMEDOUT;
158
159
160 value = ioread32be(®s->miimstat);
161
162 dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum);
163 return value;
164}
165
166
167static int fsl_pq_mdio_reset(struct mii_bus *bus)
168{
169 struct fsl_pq_mdio_priv *priv = bus->priv;
170 struct fsl_pq_mii __iomem *regs = priv->regs;
171 unsigned int timeout;
172
173 mutex_lock(&bus->mdio_lock);
174
175
176 iowrite32be(MIIMCFG_RESET, ®s->miimcfg);
177
178
179 iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg);
180
181
182 timeout = MII_TIMEOUT;
183 while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
184 cpu_relax();
185 timeout--;
186 }
187
188 mutex_unlock(&bus->mdio_lock);
189
190 if (!timeout) {
191 dev_err(&bus->dev, "timeout waiting for MII bus\n");
192 return -EBUSY;
193 }
194
195 return 0;
196}
197
198#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
199
200
201
202
203
204
205
206static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p)
207{
208 struct gfar __iomem *enet_regs = p;
209
210 return &enet_regs->tbipa;
211}
212
213
214
215
216
217static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p)
218{
219 return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs));
220}
221
222
223
224
225static uint32_t __iomem *get_etsec_tbipa(void __iomem *p)
226{
227 return p;
228}
229#endif
230
231#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
232
233
234
235
236static uint32_t __iomem *get_ucc_tbipa(void __iomem *p)
237{
238 struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii);
239
240 return &mdio->utbipar;
241}
242
243
244
245
246
247
248
249
250
251
252
253
254static void ucc_configure(phys_addr_t start, phys_addr_t end)
255{
256 static bool found_mii_master;
257 struct device_node *np = NULL;
258
259 if (found_mii_master)
260 return;
261
262 for_each_compatible_node(np, NULL, "ucc_geth") {
263 struct resource res;
264 const uint32_t *iprop;
265 uint32_t id;
266 int ret;
267
268 ret = of_address_to_resource(np, 0, &res);
269 if (ret < 0) {
270 pr_debug("fsl-pq-mdio: no address range in node %s\n",
271 np->full_name);
272 continue;
273 }
274
275
276 if ((start < res.start) || (end > res.end))
277 continue;
278
279 iprop = of_get_property(np, "cell-index", NULL);
280 if (!iprop) {
281 iprop = of_get_property(np, "device-id", NULL);
282 if (!iprop) {
283 pr_debug("fsl-pq-mdio: no UCC ID in node %s\n",
284 np->full_name);
285 continue;
286 }
287 }
288
289 id = be32_to_cpup(iprop);
290
291
292
293
294
295 if (ucc_set_qe_mux_mii_mng(id - 1) < 0) {
296 pr_debug("fsl-pq-mdio: invalid UCC ID in node %s\n",
297 np->full_name);
298 continue;
299 }
300
301 pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id);
302 found_mii_master = true;
303 }
304}
305
306#endif
307
308static const struct of_device_id fsl_pq_mdio_match[] = {
309#if defined(CONFIG_GIANFAR) || defined(CONFIG_GIANFAR_MODULE)
310 {
311 .compatible = "fsl,gianfar-tbi",
312 .data = &(struct fsl_pq_mdio_data) {
313 .mii_offset = 0,
314 .get_tbipa = get_gfar_tbipa_from_mii,
315 },
316 },
317 {
318 .compatible = "fsl,gianfar-mdio",
319 .data = &(struct fsl_pq_mdio_data) {
320 .mii_offset = 0,
321 .get_tbipa = get_gfar_tbipa_from_mii,
322 },
323 },
324 {
325 .type = "mdio",
326 .compatible = "gianfar",
327 .data = &(struct fsl_pq_mdio_data) {
328 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
329 .get_tbipa = get_gfar_tbipa_from_mdio,
330 },
331 },
332 {
333 .compatible = "fsl,etsec2-tbi",
334 .data = &(struct fsl_pq_mdio_data) {
335 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
336 .get_tbipa = get_etsec_tbipa,
337 },
338 },
339 {
340 .compatible = "fsl,etsec2-mdio",
341 .data = &(struct fsl_pq_mdio_data) {
342 .mii_offset = offsetof(struct fsl_pq_mdio, mii),
343 .get_tbipa = get_etsec_tbipa,
344 },
345 },
346#endif
347#if defined(CONFIG_UCC_GETH) || defined(CONFIG_UCC_GETH_MODULE)
348 {
349 .compatible = "fsl,ucc-mdio",
350 .data = &(struct fsl_pq_mdio_data) {
351 .mii_offset = 0,
352 .get_tbipa = get_ucc_tbipa,
353 .ucc_configure = ucc_configure,
354 },
355 },
356 {
357
358 .type = "mdio",
359 .compatible = "ucc_geth_phy",
360 .data = &(struct fsl_pq_mdio_data) {
361 .mii_offset = 0,
362 .get_tbipa = get_ucc_tbipa,
363 .ucc_configure = ucc_configure,
364 },
365 },
366#endif
367
368 {
369 .compatible = "fsl,fman-mdio",
370 .data = &(struct fsl_pq_mdio_data) {
371 .mii_offset = 0,
372
373 },
374 },
375
376 {},
377};
378MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
379
380static int fsl_pq_mdio_probe(struct platform_device *pdev)
381{
382 const struct of_device_id *id =
383 of_match_device(fsl_pq_mdio_match, &pdev->dev);
384 const struct fsl_pq_mdio_data *data = id->data;
385 struct device_node *np = pdev->dev.of_node;
386 struct resource res;
387 struct device_node *tbi;
388 struct fsl_pq_mdio_priv *priv;
389 struct mii_bus *new_bus;
390 int err;
391
392 dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible);
393
394 new_bus = mdiobus_alloc_size(sizeof(*priv));
395 if (!new_bus)
396 return -ENOMEM;
397
398 priv = new_bus->priv;
399 new_bus->name = "Freescale PowerQUICC MII Bus",
400 new_bus->read = &fsl_pq_mdio_read;
401 new_bus->write = &fsl_pq_mdio_write;
402 new_bus->reset = &fsl_pq_mdio_reset;
403
404 err = of_address_to_resource(np, 0, &res);
405 if (err < 0) {
406 dev_err(&pdev->dev, "could not obtain address information\n");
407 goto error;
408 }
409
410 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s@%llx", np->name,
411 (unsigned long long)res.start);
412
413 priv->map = of_iomap(np, 0);
414 if (!priv->map) {
415 err = -ENOMEM;
416 goto error;
417 }
418
419
420
421
422
423
424
425 if (data->mii_offset > resource_size(&res)) {
426 dev_err(&pdev->dev, "invalid register map\n");
427 err = -EINVAL;
428 goto error;
429 }
430 priv->regs = priv->map + data->mii_offset;
431
432 new_bus->parent = &pdev->dev;
433 platform_set_drvdata(pdev, new_bus);
434
435 if (data->get_tbipa) {
436 for_each_child_of_node(np, tbi) {
437 if (strcmp(tbi->type, "tbi-phy") == 0) {
438 dev_dbg(&pdev->dev, "found TBI PHY node %s\n",
439 strrchr(tbi->full_name, '/') + 1);
440 break;
441 }
442 }
443
444 if (tbi) {
445 const u32 *prop = of_get_property(tbi, "reg", NULL);
446 uint32_t __iomem *tbipa;
447
448 if (!prop) {
449 dev_err(&pdev->dev,
450 "missing 'reg' property in node %s\n",
451 tbi->full_name);
452 err = -EBUSY;
453 goto error;
454 }
455
456 tbipa = data->get_tbipa(priv->map);
457
458
459
460
461
462
463
464 if ((void *)tbipa > priv->map + resource_size(&res) - 4)
465 dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n",
466 ((void *)tbipa - priv->map) + 4);
467
468 iowrite32be(be32_to_cpup(prop), tbipa);
469 }
470 }
471
472 if (data->ucc_configure)
473 data->ucc_configure(res.start, res.end);
474
475 err = of_mdiobus_register(new_bus, np);
476 if (err) {
477 dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
478 new_bus->name);
479 goto error;
480 }
481
482 return 0;
483
484error:
485 if (priv->map)
486 iounmap(priv->map);
487
488 kfree(new_bus);
489
490 return err;
491}
492
493
494static int fsl_pq_mdio_remove(struct platform_device *pdev)
495{
496 struct device *device = &pdev->dev;
497 struct mii_bus *bus = dev_get_drvdata(device);
498 struct fsl_pq_mdio_priv *priv = bus->priv;
499
500 mdiobus_unregister(bus);
501
502 iounmap(priv->map);
503 mdiobus_free(bus);
504
505 return 0;
506}
507
508static struct platform_driver fsl_pq_mdio_driver = {
509 .driver = {
510 .name = "fsl-pq_mdio",
511 .of_match_table = fsl_pq_mdio_match,
512 },
513 .probe = fsl_pq_mdio_probe,
514 .remove = fsl_pq_mdio_remove,
515};
516
517module_platform_driver(fsl_pq_mdio_driver);
518
519MODULE_LICENSE("GPL");
520