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21#include "fm10k_pf.h"
22#include "fm10k_vf.h"
23
24
25
26
27
28
29
30
31static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
32{
33 s32 err;
34 u32 reg;
35 u16 i;
36
37
38 fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
39
40
41 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
42 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
43
44
45
46
47 for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
48 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
49 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
50 }
51
52
53 err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
54 if (err)
55 return err;
56
57
58 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
59 if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
60 return FM10K_ERR_DMA_PENDING;
61
62
63 reg = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
64 if (!(reg & FM10K_DMA_CTRL2_SWITCH_READY))
65 goto out;
66
67
68 reg |= FM10K_DMA_CTRL_DATAPATH_RESET;
69 fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
70
71
72 fm10k_write_flush(hw);
73 udelay(FM10K_RESET_TIMEOUT);
74
75
76 reg = fm10k_read_reg(hw, FM10K_IP);
77 if (!(reg & FM10K_IP_NOTINRESET))
78 err = FM10K_ERR_RESET_FAILED;
79
80out:
81 return err;
82}
83
84
85
86
87
88
89
90static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
91{
92 u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL);
93
94 return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
95}
96
97
98
99
100
101
102static s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
103{
104 u32 dma_ctrl, txqctl;
105 u16 i;
106
107
108 fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
109 fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
110 FM10K_DGLORTMAP_ANY);
111
112
113 for (i = 1; i < FM10K_DGLORT_COUNT; i++)
114 fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
115
116
117 fm10k_write_reg(hw, FM10K_ITR2(0), 0);
118
119
120 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
121
122
123 for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
124 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
125
126
127 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
128
129
130 txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
131 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
132
133 for (i = 0; i < FM10K_MAX_QUEUES; i++) {
134
135 fm10k_write_reg(hw, FM10K_TQDLOC(i),
136 (i * FM10K_TQDLOC_BASE_32_DESC) |
137 FM10K_TQDLOC_SIZE_32_DESC);
138 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
139
140
141 fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
142 FM10K_TPH_TXCTRL_DESC_TPHEN |
143 FM10K_TPH_TXCTRL_DESC_RROEN |
144 FM10K_TPH_TXCTRL_DESC_WROEN |
145 FM10K_TPH_TXCTRL_DATA_RROEN);
146 fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
147 FM10K_TPH_RXCTRL_DESC_TPHEN |
148 FM10K_TPH_RXCTRL_DESC_RROEN |
149 FM10K_TPH_RXCTRL_DATA_WROEN |
150 FM10K_TPH_RXCTRL_HDR_WROEN);
151 }
152
153
154
155
156 switch (hw->bus.speed) {
157 case fm10k_bus_speed_2500:
158 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
159 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1;
160 break;
161 case fm10k_bus_speed_5000:
162 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
163 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2;
164 break;
165 case fm10k_bus_speed_8000:
166 dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
167 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
168 break;
169 default:
170 dma_ctrl = 0;
171
172 hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
173 break;
174 }
175
176
177 fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
178 fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
179
180
181
182
183
184
185 dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
186 FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
187 FM10K_DMA_CTRL_32_DESC;
188
189 fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
190
191
192 hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
193
194
195 hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
196
197 return 0;
198}
199
200
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209
210
211
212static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
213{
214 u32 vlan_table, reg, mask, bit, len;
215
216
217 if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
218 return FM10K_ERR_PARAM;
219
220
221
222
223
224
225
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228
229
230
231
232
233 len = vid >> 16;
234 vid = (vid << 17) >> 17;
235
236
237 if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)
238 return FM10K_ERR_PARAM;
239
240
241 for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
242 len < FM10K_VLAN_TABLE_VID_MAX;
243 len -= 32 - bit, reg++, bit = 0) {
244
245 vlan_table = fm10k_read_reg(hw, reg);
246
247
248 mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
249
250
251 mask &= set ? ~vlan_table : vlan_table;
252 if (mask)
253 fm10k_write_reg(hw, reg, vlan_table ^ mask);
254 }
255
256 return 0;
257}
258
259
260
261
262
263
264
265static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
266{
267 u8 perm_addr[ETH_ALEN];
268 u32 serial_num;
269
270 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
271
272
273 if ((~serial_num) << 24)
274 return FM10K_ERR_INVALID_MAC_ADDR;
275
276 perm_addr[0] = (u8)(serial_num >> 24);
277 perm_addr[1] = (u8)(serial_num >> 16);
278 perm_addr[2] = (u8)(serial_num >> 8);
279
280 serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
281
282
283 if ((~serial_num) >> 24)
284 return FM10K_ERR_INVALID_MAC_ADDR;
285
286 perm_addr[3] = (u8)(serial_num >> 16);
287 perm_addr[4] = (u8)(serial_num >> 8);
288 perm_addr[5] = (u8)(serial_num);
289
290 ether_addr_copy(hw->mac.perm_addr, perm_addr);
291 ether_addr_copy(hw->mac.addr, perm_addr);
292
293 return 0;
294}
295
296
297
298
299
300
301
302
303bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
304{
305 glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
306
307 return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
308}
309
310
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320
321
322static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
323 const u8 *mac, u16 vid, bool add, u8 flags)
324{
325 struct fm10k_mbx_info *mbx = &hw->mbx;
326 struct fm10k_mac_update mac_update;
327 u32 msg[5];
328
329
330 vid &= ~FM10K_VLAN_CLEAR;
331
332
333 if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
334 return FM10K_ERR_PARAM;
335
336
337 mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) |
338 ((u32)mac[3] << 16) |
339 ((u32)mac[4] << 8) |
340 ((u32)mac[5]));
341 mac_update.mac_upper = cpu_to_le16(((u16)mac[0] << 8) |
342 ((u16)mac[1]));
343 mac_update.vlan = cpu_to_le16(vid);
344 mac_update.glort = cpu_to_le16(glort);
345 mac_update.action = add ? 0 : 1;
346 mac_update.flags = flags;
347
348
349 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
350 fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
351 &mac_update, sizeof(mac_update));
352
353
354 return mbx->ops.enqueue_tx(hw, mbx, msg);
355}
356
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366
367
368
369static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
370 const u8 *mac, u16 vid, bool add, u8 flags)
371{
372
373 if (!is_valid_ether_addr(mac))
374 return FM10K_ERR_PARAM;
375
376 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
377}
378
379
380
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387
388
389
390static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
391 const u8 *mac, u16 vid, bool add)
392{
393
394 if (!is_multicast_ether_addr(mac))
395 return FM10K_ERR_PARAM;
396
397 return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
398}
399
400
401
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403
404
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408
409
410static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
411{
412 struct fm10k_mbx_info *mbx = &hw->mbx;
413 u32 msg[3], xcast_mode;
414
415 if (mode > FM10K_XCAST_MODE_NONE)
416 return FM10K_ERR_PARAM;
417
418
419 if (!fm10k_glort_valid_pf(hw, glort))
420 return FM10K_ERR_PARAM;
421
422
423
424
425
426 xcast_mode = ((u32)mode << 16) | glort;
427
428
429 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
430 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
431
432
433 return mbx->ops.enqueue_tx(hw, mbx, msg);
434}
435
436
437
438
439
440
441
442
443
444static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
445{
446 u32 i;
447
448
449 fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
450
451
452 for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
453 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
454 break;
455 }
456
457
458 fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
459
460
461 if (!hw->iov.num_vfs)
462 fm10k_write_reg(hw, FM10K_ITR2(0), i);
463
464
465 fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
466}
467
468
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470
471
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474
475
476
477static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
478 u16 count, bool enable)
479{
480 struct fm10k_mbx_info *mbx = &hw->mbx;
481 u32 msg[3], lport_msg;
482
483
484 if (!count)
485 return 0;
486
487
488 if (!fm10k_glort_valid_pf(hw, glort))
489 return FM10K_ERR_PARAM;
490
491
492 lport_msg = ((u32)count << 16) | glort;
493
494
495 fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
496 FM10K_PF_MSG_ID_LPORT_DELETE);
497 fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
498
499
500 return mbx->ops.enqueue_tx(hw, mbx, msg);
501}
502
503
504
505
506
507
508
509
510
511
512static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
513 struct fm10k_dglort_cfg *dglort)
514{
515 u16 glort, queue_count, vsi_count, pc_count;
516 u16 vsi, queue, pc, q_idx;
517 u32 txqctl, dglortdec, dglortmap;
518
519
520 if (!dglort)
521 return FM10K_ERR_PARAM;
522
523
524 if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
525 (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
526 (dglort->queue_l > 8) || (dglort->queue_b >= 256))
527 return FM10K_ERR_PARAM;
528
529
530 queue_count = 1 << (dglort->rss_l + dglort->pc_l);
531 vsi_count = 1 << (dglort->vsi_l + dglort->queue_l);
532 glort = dglort->glort;
533 q_idx = dglort->queue_b;
534
535
536 for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
537 for (queue = 0; queue < queue_count; queue++, q_idx++) {
538 if (q_idx >= FM10K_MAX_QUEUES)
539 break;
540
541 fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
542 fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
543 }
544 }
545
546
547 queue_count = 1 << (dglort->queue_l + dglort->rss_l + dglort->vsi_l);
548 pc_count = 1 << dglort->pc_l;
549
550
551 for (pc = 0; pc < pc_count; pc++) {
552 q_idx = pc + dglort->queue_b;
553 for (queue = 0; queue < queue_count; queue++) {
554 if (q_idx >= FM10K_MAX_QUEUES)
555 break;
556
557 txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
558 txqctl &= ~FM10K_TXQCTL_PC_MASK;
559 txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
560 fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
561
562 q_idx += pc_count;
563 }
564 }
565
566
567 dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
568 ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
569 ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
570 ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
571 ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
572 ((u32)(dglort->queue_l));
573 if (dglort->inner_rss)
574 dglortdec |= FM10K_DGLORTDEC_INNERRSS_ENABLE;
575
576
577 dglortmap = (dglort->idx == fm10k_dglort_default) ?
578 FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
579 dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
580 dglortmap |= dglort->glort;
581
582
583 fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
584 fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
585
586 return 0;
587}
588
589u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
590{
591 u16 num_pools = hw->iov.num_pools;
592
593 return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
594 8 : FM10K_MAX_QUEUES_POOL;
595}
596
597u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
598{
599 u16 num_vfs = hw->iov.num_vfs;
600 u16 vf_q_idx = FM10K_MAX_QUEUES;
601
602 vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
603
604 return vf_q_idx;
605}
606
607static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
608{
609 u16 num_pools = hw->iov.num_pools;
610
611 return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
612 FM10K_MAX_VECTORS_POOL;
613}
614
615static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
616{
617 u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
618
619 vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
620
621 return vf_v_idx;
622}
623
624
625
626
627
628
629
630
631
632
633static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
634 u16 num_pools)
635{
636 u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
637 u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
638 int i, j;
639
640
641 if (num_pools > 64)
642 return FM10K_ERR_PARAM;
643
644
645 if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
646 return FM10K_ERR_PARAM;
647
648
649 hw->iov.num_vfs = num_vfs;
650 hw->iov.num_pools = num_pools;
651
652
653 qmap_stride = (num_vfs > 8) ? 32 : 256;
654 qpp = fm10k_queues_per_pool(hw);
655 vpp = fm10k_vectors_per_pool(hw);
656
657
658 vf_q_idx = fm10k_vf_queue_index(hw, 0);
659 qmap_idx = 0;
660
661
662 for (i = 0; i < num_vfs; i++) {
663 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
664 fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
665 fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
666 FM10K_TC_CREDIT_CREDIT_MASK);
667 }
668
669
670 for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
671 fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
672
673
674 fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
675 fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
676
677
678 for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
679 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
680 fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF |
681 FM10K_TXQCTL_UNLIMITED_BW | vid);
682 fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
683 }
684
685
686
687
688 for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
689 if (!(i & (vpp - 1)))
690 fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
691 else
692 fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
693 }
694
695
696 fm10k_write_reg(hw, FM10K_ITR2(0),
697 fm10k_vf_vector_index(hw, num_vfs - 1));
698
699
700 for (i = 0; i < num_vfs; i++) {
701
702 vf_q_idx0 = vf_q_idx;
703
704 for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
705
706 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
707 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
708 (i << FM10K_TXQCTL_TC_SHIFT) | i |
709 FM10K_TXQCTL_VF | vid);
710 fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
711 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
712 FM10K_RXDCTL_DROP_ON_EMPTY);
713 fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
714 FM10K_RXQCTL_VF |
715 (i << FM10K_RXQCTL_VF_SHIFT));
716
717
718 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
719 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
720 }
721
722
723 for (; j < qmap_stride; j++, qmap_idx++) {
724 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
725 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
726 }
727 }
728
729
730 while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
731 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
732 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
733 qmap_idx++;
734 }
735
736 return 0;
737}
738
739
740
741
742
743
744
745
746
747
748static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
749{
750
751 u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
752 u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
753
754
755 if (vf_idx >= hw->iov.num_vfs)
756 return FM10K_ERR_PARAM;
757
758
759 switch (hw->bus.speed) {
760 case fm10k_bus_speed_2500:
761 interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
762 break;
763 case fm10k_bus_speed_5000:
764 interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
765 break;
766 default:
767 break;
768 }
769
770 if (rate) {
771 if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
772 return FM10K_ERR_PARAM;
773
774
775
776
777
778
779
780
781 tc_rate = (rate * 128) / 125;
782
783
784
785
786 if (rate < 4000)
787 interval <<= 1;
788 else
789 tc_rate >>= 1;
790 }
791
792
793 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
794 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
795 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
796
797 return 0;
798}
799
800
801
802
803
804
805
806
807
808static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
809{
810 u16 vf_v_idx, vf_v_limit, i;
811
812
813 if (vf_idx >= hw->iov.num_vfs)
814 return FM10K_ERR_PARAM;
815
816
817 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
818 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
819
820
821 for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
822 if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
823 break;
824 }
825
826
827 if (vf_idx == (hw->iov.num_vfs - 1))
828 fm10k_write_reg(hw, FM10K_ITR2(0), i);
829 else
830 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
831
832 return 0;
833}
834
835
836
837
838
839
840
841
842static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
843 struct fm10k_vf_info *vf_info)
844{
845 u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
846 u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
847 s32 err = 0;
848 u16 vf_idx, vf_vid;
849
850
851 if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
852 return FM10K_ERR_PARAM;
853
854
855 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
856 queues_per_pool = fm10k_queues_per_pool(hw);
857
858
859 vf_idx = vf_info->vf_idx;
860 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
861 qmap_idx = qmap_stride * vf_idx;
862
863
864 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
865 fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
866
867
868 if (vf_info->pf_vid)
869 vf_vid = vf_info->pf_vid | FM10K_VLAN_CLEAR;
870 else
871 vf_vid = vf_info->sw_vid;
872
873
874 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
875 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
876 vf_info->mac, vf_vid);
877
878
879 if (vf_info->mbx.ops.enqueue_tx)
880 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
881
882
883 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
884 for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
885
886 if (timeout == 10) {
887 err = FM10K_ERR_DMA_PENDING;
888 goto err_out;
889 }
890
891 usleep_range(100, 200);
892 txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
893 }
894
895
896 if (is_valid_ether_addr(vf_info->mac)) {
897 tdbal = (((u32)vf_info->mac[3]) << 24) |
898 (((u32)vf_info->mac[4]) << 16) |
899 (((u32)vf_info->mac[5]) << 8);
900
901 tdbah = (((u32)0xFF) << 24) |
902 (((u32)vf_info->mac[0]) << 16) |
903 (((u32)vf_info->mac[1]) << 8) |
904 ((u32)vf_info->mac[2]);
905 }
906
907
908 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
909 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
910
911
912
913
914
915 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale <<
916 FM10K_TDLEN_ITR_SCALE_SHIFT);
917
918err_out:
919
920 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
921 FM10K_TXQCTL_VID_MASK;
922 txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
923 FM10K_TXQCTL_VF | vf_idx;
924
925
926 for (i = 0; i < queues_per_pool; i++)
927 fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
928
929
930 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
931 return err;
932}
933
934
935
936
937
938
939
940
941static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
942 struct fm10k_vf_info *vf_info)
943{
944 u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
945 u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
946 u16 vf_v_idx, vf_v_limit, vf_vid;
947 u8 vf_idx = vf_info->vf_idx;
948 int i;
949
950
951 if (vf_idx >= hw->iov.num_vfs)
952 return FM10K_ERR_PARAM;
953
954
955 fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), 1 << (vf_idx % 32));
956
957
958 vf_info->mbx.timeout = 0;
959 if (vf_info->mbx.ops.disconnect)
960 vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
961
962
963 vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
964 vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
965
966
967 qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
968 queues_per_pool = fm10k_queues_per_pool(hw);
969 qmap_idx = qmap_stride * vf_idx;
970
971
972 for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
973 fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
974 fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
975 }
976
977
978 vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
979
980
981 if (vf_info->pf_vid)
982 vf_vid = vf_info->pf_vid;
983 else
984 vf_vid = vf_info->sw_vid;
985
986
987 txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
988 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
989 FM10K_TXQCTL_VF | vf_idx;
990 rxqctl = FM10K_RXQCTL_VF | (vf_idx << FM10K_RXQCTL_VF_SHIFT);
991
992
993 for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
994 fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
995 fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
996 fm10k_write_reg(hw, FM10K_RXDCTL(i),
997 FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
998 FM10K_RXDCTL_DROP_ON_EMPTY);
999 fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
1000 }
1001
1002
1003 fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
1004 fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
1005 fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
1006 FM10K_TC_CREDIT_CREDIT_MASK);
1007
1008
1009 if (!vf_idx)
1010 hw->mac.ops.update_int_moderator(hw);
1011 else
1012 hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1013
1014
1015 if (vf_idx == (hw->iov.num_vfs - 1))
1016 fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
1017 else
1018 fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1019
1020
1021 for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1022 fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1023
1024
1025 for (i = FM10K_VFMBMEM_LEN; i--;)
1026 fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1027 for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1028 fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1029 for (i = FM10K_RETA_SIZE; i--;)
1030 fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
1031 for (i = FM10K_RSSRK_SIZE; i--;)
1032 fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1033 fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
1034
1035
1036 if (is_valid_ether_addr(vf_info->mac)) {
1037 tdbal = (((u32)vf_info->mac[3]) << 24) |
1038 (((u32)vf_info->mac[4]) << 16) |
1039 (((u32)vf_info->mac[5]) << 8);
1040 tdbah = (((u32)0xFF) << 24) |
1041 (((u32)vf_info->mac[0]) << 16) |
1042 (((u32)vf_info->mac[1]) << 8) |
1043 ((u32)vf_info->mac[2]);
1044 }
1045
1046
1047 for (i = queues_per_pool; i--;) {
1048 fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1049 fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1050
1051
1052
1053 fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i),
1054 hw->mac.itr_scale <<
1055 FM10K_TDLEN_ITR_SCALE_SHIFT);
1056 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1057 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1058 }
1059
1060
1061 for (i = queues_per_pool; i < qmap_stride; i++) {
1062 fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx);
1063 fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx);
1064 }
1065
1066 return 0;
1067}
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1080 struct fm10k_vf_info *vf_info,
1081 u16 lport_idx, u8 flags)
1082{
1083 u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1084
1085
1086 if (!fm10k_glort_valid_pf(hw, glort))
1087 return FM10K_ERR_PARAM;
1088
1089 vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1090 vf_info->glort = glort;
1091
1092 return 0;
1093}
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1104 struct fm10k_vf_info *vf_info)
1105{
1106 u32 msg[1];
1107
1108
1109 if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1110
1111 fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1112
1113
1114 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1115 vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1116 }
1117
1118
1119 vf_info->vf_flags = 0;
1120 vf_info->glort = 0;
1121}
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1132 struct fm10k_hw_stats_q *q,
1133 u16 vf_idx)
1134{
1135 u32 idx, qpp;
1136
1137
1138 qpp = fm10k_queues_per_pool(hw);
1139 idx = fm10k_vf_queue_index(hw, vf_idx);
1140 fm10k_update_hw_stats_q(hw, q, idx, qpp);
1141}
1142
1143static s32 fm10k_iov_report_timestamp_pf(struct fm10k_hw *hw,
1144 struct fm10k_vf_info *vf_info,
1145 u64 timestamp)
1146{
1147 u32 msg[4];
1148
1149
1150 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_1588);
1151 fm10k_tlv_attr_put_u64(msg, FM10K_1588_MSG_TIMESTAMP, timestamp);
1152
1153 return vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1154}
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 **results,
1167 struct fm10k_mbx_info *mbx)
1168{
1169 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1170 u8 vf_idx = vf_info->vf_idx;
1171
1172 return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1173}
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183static s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid)
1184{
1185 if (!vid)
1186 return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid;
1187 else if (vf_info->pf_vid && vid != vf_info->pf_vid)
1188 return FM10K_ERR_PARAM;
1189 else
1190 return vid;
1191}
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1204 struct fm10k_mbx_info *mbx)
1205{
1206 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1207 u8 mac[ETH_ALEN];
1208 u32 *result;
1209 int err = 0;
1210 bool set;
1211 u16 vlan;
1212 u32 vid;
1213
1214
1215 if (!FM10K_VF_FLAG_ENABLED(vf_info))
1216 err = FM10K_ERR_PARAM;
1217
1218 if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1219 result = results[FM10K_MAC_VLAN_MSG_VLAN];
1220
1221
1222 err = fm10k_tlv_attr_get_u32(result, &vid);
1223 if (err)
1224 return err;
1225
1226 set = !(vid & FM10K_VLAN_CLEAR);
1227 vid &= ~FM10K_VLAN_CLEAR;
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239 if (vid >> 16) {
1240
1241
1242
1243 if (vf_info->pf_vid)
1244 return FM10K_ERR_PARAM;
1245 } else {
1246 err = fm10k_iov_select_vid(vf_info, (u16)vid);
1247 if (err < 0)
1248 return err;
1249
1250 vid = err;
1251 }
1252
1253
1254 err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set);
1255 }
1256
1257 if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1258 result = results[FM10K_MAC_VLAN_MSG_MAC];
1259
1260
1261 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1262 if (err)
1263 return err;
1264
1265
1266 if (is_valid_ether_addr(vf_info->mac) &&
1267 !ether_addr_equal(mac, vf_info->mac))
1268 return FM10K_ERR_PARAM;
1269
1270 set = !(vlan & FM10K_VLAN_CLEAR);
1271 vlan &= ~FM10K_VLAN_CLEAR;
1272
1273 err = fm10k_iov_select_vid(vf_info, vlan);
1274 if (err < 0)
1275 return err;
1276
1277 vlan = (u16)err;
1278
1279
1280 err = hw->mac.ops.update_uc_addr(hw, vf_info->glort,
1281 mac, vlan, set, 0);
1282 }
1283
1284 if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1285 result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1286
1287
1288 err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1289 if (err)
1290 return err;
1291
1292
1293 if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1294 return FM10K_ERR_PARAM;
1295
1296 set = !(vlan & FM10K_VLAN_CLEAR);
1297 vlan &= ~FM10K_VLAN_CLEAR;
1298
1299 err = fm10k_iov_select_vid(vf_info, vlan);
1300 if (err < 0)
1301 return err;
1302
1303 vlan = (u16)err;
1304
1305
1306 err = hw->mac.ops.update_mc_addr(hw, vf_info->glort,
1307 mac, vlan, set);
1308 }
1309
1310 return err;
1311}
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1322 u8 mode)
1323{
1324 u8 vf_flags = vf_info->vf_flags;
1325
1326
1327 switch (mode) {
1328 case FM10K_XCAST_MODE_PROMISC:
1329 if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1330 return FM10K_XCAST_MODE_PROMISC;
1331
1332 case FM10K_XCAST_MODE_ALLMULTI:
1333 if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1334 return FM10K_XCAST_MODE_ALLMULTI;
1335
1336 case FM10K_XCAST_MODE_MULTI:
1337 if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1338 return FM10K_XCAST_MODE_MULTI;
1339
1340 case FM10K_XCAST_MODE_NONE:
1341 if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1342 return FM10K_XCAST_MODE_NONE;
1343
1344 default:
1345 break;
1346 }
1347
1348
1349 return FM10K_XCAST_MODE_DISABLE;
1350}
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1363 struct fm10k_mbx_info *mbx)
1364{
1365 struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1366 u32 *result;
1367 s32 err = 0;
1368 u32 msg[2];
1369 u8 mode = 0;
1370
1371
1372 if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1373 return FM10K_ERR_PARAM;
1374
1375 if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1376 result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1377
1378
1379 err = fm10k_tlv_attr_get_u8(result, &mode);
1380 if (err)
1381 return FM10K_ERR_PARAM;
1382
1383
1384 mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1385
1386
1387 if (!(FM10K_VF_FLAG_ENABLED(vf_info) & (1 << mode)))
1388 fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1389
1390
1391 mode = FM10K_VF_FLAG_SET_MODE(mode);
1392 } else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1393
1394 if (FM10K_VF_FLAG_ENABLED(vf_info))
1395 err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1396 1, false);
1397
1398
1399
1400
1401
1402
1403 if (!err)
1404 vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info);
1405
1406
1407 hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1408
1409
1410 mode = FM10K_VF_FLAG_SET_MODE_NONE;
1411
1412
1413 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1414 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1415 mbx->ops.enqueue_tx(hw, mbx, msg);
1416 }
1417
1418
1419 if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1420 err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1421 !!mode);
1422
1423
1424 mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1425 if (!err)
1426 vf_info->vf_flags = mode;
1427
1428 return err;
1429}
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1440 struct fm10k_hw_stats *stats)
1441{
1442 u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1443 u32 id, id_prev;
1444
1445
1446 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1447
1448
1449 do {
1450 timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1451 &stats->timeout);
1452 ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1453 ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1454 um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1455 xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1456 vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1457 &stats->vlan_drop);
1458 loopback_drop =
1459 fm10k_read_hw_stats_32b(hw,
1460 FM10K_STATS_LOOPBACK_DROP,
1461 &stats->loopback_drop);
1462 nodesc_drop = fm10k_read_hw_stats_32b(hw,
1463 FM10K_STATS_NODESC_DROP,
1464 &stats->nodesc_drop);
1465
1466
1467 id_prev = id;
1468 id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1469 } while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1470
1471
1472 id &= FM10K_TXQCTL_ID_MASK;
1473 id |= FM10K_STAT_VALID;
1474
1475
1476 if (stats->stats_idx == id) {
1477 stats->timeout.count += timeout;
1478 stats->ur.count += ur;
1479 stats->ca.count += ca;
1480 stats->um.count += um;
1481 stats->xec.count += xec;
1482 stats->vlan_drop.count += vlan_drop;
1483 stats->loopback_drop.count += loopback_drop;
1484 stats->nodesc_drop.count += nodesc_drop;
1485 }
1486
1487
1488 fm10k_update_hw_base_32b(&stats->timeout, timeout);
1489 fm10k_update_hw_base_32b(&stats->ur, ur);
1490 fm10k_update_hw_base_32b(&stats->ca, ca);
1491 fm10k_update_hw_base_32b(&stats->um, um);
1492 fm10k_update_hw_base_32b(&stats->xec, xec);
1493 fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1494 fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1495 fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1496 stats->stats_idx = id;
1497
1498
1499 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1500}
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1511 struct fm10k_hw_stats *stats)
1512{
1513
1514 fm10k_unbind_hw_stats_32b(&stats->timeout);
1515 fm10k_unbind_hw_stats_32b(&stats->ur);
1516 fm10k_unbind_hw_stats_32b(&stats->ca);
1517 fm10k_unbind_hw_stats_32b(&stats->um);
1518 fm10k_unbind_hw_stats_32b(&stats->xec);
1519 fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1520 fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1521 fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1522
1523
1524 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1525
1526
1527 fm10k_update_hw_stats_pf(hw, stats);
1528}
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1539{
1540
1541 u32 phyaddr = (u32)(dma_mask >> 32);
1542
1543 fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
1544}
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1558 struct fm10k_fault *fault)
1559{
1560 u32 func;
1561
1562
1563 switch (type) {
1564 case FM10K_PCA_FAULT:
1565 case FM10K_THI_FAULT:
1566 case FM10K_FUM_FAULT:
1567 break;
1568 default:
1569 return FM10K_ERR_PARAM;
1570 }
1571
1572
1573 func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
1574 if (!(func & FM10K_FAULT_FUNC_VALID))
1575 return FM10K_ERR_PARAM;
1576
1577
1578 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
1579 fault->address <<= 32;
1580 fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
1581 fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
1582
1583
1584 fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1585
1586
1587 if (func & FM10K_FAULT_FUNC_PF)
1588 fault->func = 0;
1589 else
1590 fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1591 FM10K_FAULT_FUNC_VF_SHIFT);
1592
1593
1594 fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1595
1596 return 0;
1597}
1598
1599
1600
1601
1602
1603
1604static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1605{
1606 struct fm10k_mbx_info *mbx = &hw->mbx;
1607 u32 msg[1];
1608
1609
1610 fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1611
1612
1613 return mbx->ops.enqueue_tx(hw, mbx, msg);
1614}
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1626{
1627 s32 ret_val = 0;
1628 u32 dma_ctrl2;
1629
1630
1631 dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
1632 if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1633 goto out;
1634
1635
1636 ret_val = fm10k_get_host_state_generic(hw, switch_ready);
1637 if (ret_val)
1638 goto out;
1639
1640
1641 if (hw->mac.dglort_map == FM10K_DGLORTMAP_NONE)
1642 ret_val = fm10k_request_lport_map_pf(hw);
1643
1644out:
1645 return ret_val;
1646}
1647
1648
1649const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1650 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1651 FM10K_TLV_ATTR_LAST
1652};
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1664 struct fm10k_mbx_info *mbx)
1665{
1666 u16 glort, mask;
1667 u32 dglort_map;
1668 s32 err;
1669
1670 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1671 &dglort_map);
1672 if (err)
1673 return err;
1674
1675
1676 glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1677 mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1678
1679
1680 if (!mask || (glort & ~mask))
1681 return FM10K_ERR_PARAM;
1682
1683
1684 if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1685 return FM10K_ERR_PARAM;
1686
1687
1688 hw->mac.dglort_map = dglort_map;
1689
1690 return 0;
1691}
1692
1693const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1694 FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1695 FM10K_TLV_ATTR_LAST
1696};
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706static s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1707 struct fm10k_mbx_info *mbx)
1708{
1709 u16 glort, pvid;
1710 u32 pvid_update;
1711 s32 err;
1712
1713 err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1714 &pvid_update);
1715 if (err)
1716 return err;
1717
1718
1719 glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1720 pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1721
1722
1723 if (!fm10k_glort_valid_pf(hw, glort))
1724 return FM10K_ERR_PARAM;
1725
1726
1727 if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1728 return FM10K_ERR_PARAM;
1729
1730
1731 hw->mac.default_vid = pvid;
1732
1733 return 0;
1734}
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1745 struct fm10k_swapi_table_info *to)
1746{
1747
1748 to->used = le32_to_cpu(from->used);
1749 to->avail = le32_to_cpu(from->avail);
1750}
1751
1752const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1753 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1754 sizeof(struct fm10k_swapi_error)),
1755 FM10K_TLV_ATTR_LAST
1756};
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1768 struct fm10k_mbx_info *mbx)
1769{
1770 struct fm10k_swapi_error err_msg;
1771 s32 err;
1772
1773
1774 err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1775 &err_msg, sizeof(err_msg));
1776 if (err)
1777 return err;
1778
1779
1780 fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1781 fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1782 fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1783
1784
1785 hw->swapi.status = le32_to_cpu(err_msg.status);
1786
1787 return 0;
1788}
1789
1790const struct fm10k_tlv_attr fm10k_1588_timestamp_msg_attr[] = {
1791 FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_1588_TIMESTAMP,
1792 sizeof(struct fm10k_swapi_1588_timestamp)),
1793 FM10K_TLV_ATTR_LAST
1794};
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811static s32 fm10k_adjust_systime_pf(struct fm10k_hw *hw, s32 ppb)
1812{
1813 u64 systime_adjust;
1814
1815
1816 if (!hw->sw_addr)
1817 return ppb ? FM10K_ERR_PARAM : 0;
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832 systime_adjust = (ppb < 0) ? -ppb : ppb;
1833 systime_adjust <<= 31;
1834 do_div(systime_adjust, 1953125);
1835
1836
1837 if (systime_adjust > FM10K_SW_SYSTIME_ADJUST_MASK)
1838 return FM10K_ERR_PARAM;
1839
1840 if (ppb > 0)
1841 systime_adjust |= FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE;
1842
1843 fm10k_write_sw_reg(hw, FM10K_SW_SYSTIME_ADJUST, (u32)systime_adjust);
1844
1845 return 0;
1846}
1847
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858static u64 fm10k_read_systime_pf(struct fm10k_hw *hw)
1859{
1860 u32 systime_l, systime_h, systime_tmp;
1861
1862 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1863
1864 do {
1865 systime_tmp = systime_h;
1866 systime_l = fm10k_read_reg(hw, FM10K_SYSTIME);
1867 systime_h = fm10k_read_reg(hw, FM10K_SYSTIME + 1);
1868 } while (systime_tmp != systime_h);
1869
1870 return ((u64)systime_h << 32) | systime_l;
1871}
1872
1873static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1874 FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1875 FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1876 FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1877 FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1878 FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1879 FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1880 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1881};
1882
1883static const struct fm10k_mac_ops mac_ops_pf = {
1884 .get_bus_info = fm10k_get_bus_info_generic,
1885 .reset_hw = fm10k_reset_hw_pf,
1886 .init_hw = fm10k_init_hw_pf,
1887 .start_hw = fm10k_start_hw_generic,
1888 .stop_hw = fm10k_stop_hw_generic,
1889 .update_vlan = fm10k_update_vlan_pf,
1890 .read_mac_addr = fm10k_read_mac_addr_pf,
1891 .update_uc_addr = fm10k_update_uc_addr_pf,
1892 .update_mc_addr = fm10k_update_mc_addr_pf,
1893 .update_xcast_mode = fm10k_update_xcast_mode_pf,
1894 .update_int_moderator = fm10k_update_int_moderator_pf,
1895 .update_lport_state = fm10k_update_lport_state_pf,
1896 .update_hw_stats = fm10k_update_hw_stats_pf,
1897 .rebind_hw_stats = fm10k_rebind_hw_stats_pf,
1898 .configure_dglort_map = fm10k_configure_dglort_map_pf,
1899 .set_dma_mask = fm10k_set_dma_mask_pf,
1900 .get_fault = fm10k_get_fault_pf,
1901 .get_host_state = fm10k_get_host_state_pf,
1902 .adjust_systime = fm10k_adjust_systime_pf,
1903 .read_systime = fm10k_read_systime_pf,
1904};
1905
1906static const struct fm10k_iov_ops iov_ops_pf = {
1907 .assign_resources = fm10k_iov_assign_resources_pf,
1908 .configure_tc = fm10k_iov_configure_tc_pf,
1909 .assign_int_moderator = fm10k_iov_assign_int_moderator_pf,
1910 .assign_default_mac_vlan = fm10k_iov_assign_default_mac_vlan_pf,
1911 .reset_resources = fm10k_iov_reset_resources_pf,
1912 .set_lport = fm10k_iov_set_lport_pf,
1913 .reset_lport = fm10k_iov_reset_lport_pf,
1914 .update_stats = fm10k_iov_update_stats_pf,
1915 .report_timestamp = fm10k_iov_report_timestamp_pf,
1916};
1917
1918static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw)
1919{
1920 fm10k_get_invariants_generic(hw);
1921
1922 return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);
1923}
1924
1925const struct fm10k_info fm10k_pf_info = {
1926 .mac = fm10k_mac_pf,
1927 .get_invariants = fm10k_get_invariants_pf,
1928 .mac_ops = &mac_ops_pf,
1929 .iov_ops = &iov_ops_pf,
1930};
1931