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21#ifndef _FM10K_TYPE_H_
22#define _FM10K_TYPE_H_
23
24
25struct fm10k_hw;
26
27#include <linux/types.h>
28#include <asm/byteorder.h>
29#include <linux/etherdevice.h>
30
31#include "fm10k_mbx.h"
32
33#define FM10K_DEV_ID_PF 0x15A4
34#define FM10K_DEV_ID_VF 0x15A5
35
36#define FM10K_MAX_QUEUES 256
37#define FM10K_MAX_QUEUES_PF 128
38#define FM10K_MAX_QUEUES_POOL 16
39
40#define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
41#define FM10K_STAT_VALID 0x80000000
42
43
44#define FM10K_PCIE_LINK_CAP 0x7C
45#define FM10K_PCIE_LINK_STATUS 0x82
46#define FM10K_PCIE_LINK_WIDTH 0x3F0
47#define FM10K_PCIE_LINK_WIDTH_1 0x10
48#define FM10K_PCIE_LINK_WIDTH_2 0x20
49#define FM10K_PCIE_LINK_WIDTH_4 0x40
50#define FM10K_PCIE_LINK_WIDTH_8 0x80
51#define FM10K_PCIE_LINK_SPEED 0xF
52#define FM10K_PCIE_LINK_SPEED_2500 0x1
53#define FM10K_PCIE_LINK_SPEED_5000 0x2
54#define FM10K_PCIE_LINK_SPEED_8000 0x3
55
56
57#define FM10K_PCIE_DEV_CAP 0x74
58#define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
59#define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
60#define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
61#define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
62#define FM10K_PCIE_DEV_CTRL 0x78
63#define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
64#define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
65#define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
66#define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
67
68
69#define FM10K_PCI_MSIX_MSG_CTRL 0xB2
70#define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
71#define FM10K_MAX_MSIX_VECTORS 256
72#define FM10K_MAX_VECTORS_PF 256
73#define FM10K_MAX_VECTORS_POOL 32
74
75
76#define FM10K_PCIE_SRIOV_CTRL 0x190
77#define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
78
79#define FM10K_ERR_PARAM -2
80#define FM10K_ERR_NO_RESOURCES -3
81#define FM10K_ERR_REQUESTS_PENDING -4
82#define FM10K_ERR_RESET_REQUESTED -5
83#define FM10K_ERR_DMA_PENDING -6
84#define FM10K_ERR_RESET_FAILED -7
85#define FM10K_ERR_INVALID_MAC_ADDR -8
86#define FM10K_ERR_INVALID_VALUE -9
87#define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
88
89
90#define FM10K_CTRL 0x0000
91#define FM10K_CTRL_BAR4_ALLOWED 0x00000004
92
93#define FM10K_CTRL_EXT 0x0001
94#define FM10K_GCR 0x0003
95#define FM10K_GCR_EXT 0x0005
96
97
98#define FM10K_EICR 0x0006
99#define FM10K_EICR_FAULT_MASK 0x0000003F
100#define FM10K_EICR_MAILBOX 0x00000040
101#define FM10K_EICR_SWITCHREADY 0x00000080
102#define FM10K_EICR_SWITCHNOTREADY 0x00000100
103#define FM10K_EICR_SWITCHINTERRUPT 0x00000200
104#define FM10K_EICR_VFLR 0x00000800
105#define FM10K_EICR_MAXHOLDTIME 0x00001000
106#define FM10K_EIMR 0x0007
107#define FM10K_EIMR_PCA_FAULT 0x00000001
108#define FM10K_EIMR_THI_FAULT 0x00000010
109#define FM10K_EIMR_FUM_FAULT 0x00000400
110#define FM10K_EIMR_MAILBOX 0x00001000
111#define FM10K_EIMR_SWITCHREADY 0x00004000
112#define FM10K_EIMR_SWITCHNOTREADY 0x00010000
113#define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
114#define FM10K_EIMR_SRAMERROR 0x00100000
115#define FM10K_EIMR_VFLR 0x00400000
116#define FM10K_EIMR_MAXHOLDTIME 0x01000000
117#define FM10K_EIMR_ALL 0x55555555
118#define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
119#define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
120#define FM10K_FAULT_ADDR_LO 0x0
121#define FM10K_FAULT_ADDR_HI 0x1
122#define FM10K_FAULT_SPECINFO 0x2
123#define FM10K_FAULT_FUNC 0x3
124#define FM10K_FAULT_SIZE 0x4
125#define FM10K_FAULT_FUNC_VALID 0x00008000
126#define FM10K_FAULT_FUNC_PF 0x00004000
127#define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
128#define FM10K_FAULT_FUNC_VF_SHIFT 8
129#define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
130
131#define FM10K_PCA_FAULT 0x0008
132#define FM10K_THI_FAULT 0x0010
133#define FM10K_FUM_FAULT 0x001C
134
135
136#define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
137
138
139#define FM10K_SM_AREA(_n) ((_n) + 0x0028)
140
141
142#define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
143#define FM10K_DGLORT_COUNT 8
144#define FM10K_DGLORTMAP_MASK_SHIFT 16
145#define FM10K_DGLORTMAP_ANY 0x00000000
146#define FM10K_DGLORTMAP_NONE 0x0000FFFF
147#define FM10K_DGLORTMAP_ZERO 0xFFFF0000
148#define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
149#define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
150#define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
151#define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
152#define FM10K_DGLORTDEC_QBASE_SHIFT 16
153#define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
154#define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
155#define FM10K_TUNNEL_CFG 0x0040
156#define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
157#define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
158#define FM10K_SWPRI_MAX 16
159#define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
160#define FM10K_RSSRK_SIZE 10
161#define FM10K_RSSRK_ENTRIES_PER_REG 4
162#define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
163#define FM10K_RETA_SIZE 32
164#define FM10K_RETA_ENTRIES_PER_REG 4
165#define FM10K_MAX_RSS_INDICES 128
166
167
168#define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
169#define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
170#define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
171#define FM10K_TC_MAXCREDIT_64K 0x00010000
172#define FM10K_TC_RATE(_n) ((_n) + 0x2080)
173#define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
174#define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
175#define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
176#define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
177
178
179#define FM10K_DMA_CTRL 0x20C3
180#define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
181#define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
182#define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
183#define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
184#define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
185#define FM10K_DMA_CTRL_MINMSS_64 0x00008000
186#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
187#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
188#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
189#define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
190#define FM10K_DMA_CTRL_32_DESC 0x00000000
191
192#define FM10K_DMA_CTRL2 0x20C4
193#define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
194
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199
200#define FM10K_TSO_FLAGS_LOW 0x00300FF6
201#define FM10K_TSO_FLAGS_HI 0x00000039
202#define FM10K_DTXTCPFLGL 0x20C5
203#define FM10K_DTXTCPFLGH 0x20C6
204
205#define FM10K_TPH_CTRL 0x20C7
206#define FM10K_MRQC(_n) ((_n) + 0x2100)
207#define FM10K_MRQC_TCP_IPV4 0x00000001
208#define FM10K_MRQC_IPV4 0x00000002
209#define FM10K_MRQC_IPV6 0x00000010
210#define FM10K_MRQC_TCP_IPV6 0x00000020
211#define FM10K_MRQC_UDP_IPV4 0x00000040
212#define FM10K_MRQC_UDP_IPV6 0x00000080
213
214#define FM10K_TQMAP(_n) ((_n) + 0x2800)
215#define FM10K_TQMAP_TABLE_SIZE 2048
216#define FM10K_RQMAP(_n) ((_n) + 0x3000)
217
218
219#define FM10K_STATS_TIMEOUT 0x3800
220#define FM10K_STATS_UR 0x3801
221#define FM10K_STATS_CA 0x3802
222#define FM10K_STATS_UM 0x3803
223#define FM10K_STATS_XEC 0x3804
224#define FM10K_STATS_VLAN_DROP 0x3805
225#define FM10K_STATS_LOOPBACK_DROP 0x3806
226#define FM10K_STATS_NODESC_DROP 0x3807
227
228
229#define FM10K_SYSTIME 0x3814
230#define FM10K_SYSTIME_CFG 0x3818
231#define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F
232
233
234#define FM10K_PHYADDR 0x381C
235
236
237#define FM10K_RDBAL(_n) ((0x40 * (_n)) + 0x4000)
238#define FM10K_RDBAH(_n) ((0x40 * (_n)) + 0x4001)
239#define FM10K_RDLEN(_n) ((0x40 * (_n)) + 0x4002)
240#define FM10K_TPH_RXCTRL(_n) ((0x40 * (_n)) + 0x4003)
241#define FM10K_TPH_RXCTRL_DESC_TPHEN 0x00000020
242#define FM10K_TPH_RXCTRL_DESC_RROEN 0x00000200
243#define FM10K_TPH_RXCTRL_DATA_WROEN 0x00002000
244#define FM10K_TPH_RXCTRL_HDR_WROEN 0x00008000
245#define FM10K_RDH(_n) ((0x40 * (_n)) + 0x4004)
246#define FM10K_RDT(_n) ((0x40 * (_n)) + 0x4005)
247#define FM10K_RXQCTL(_n) ((0x40 * (_n)) + 0x4006)
248#define FM10K_RXQCTL_ENABLE 0x00000001
249#define FM10K_RXQCTL_PF 0x000000FC
250#define FM10K_RXQCTL_VF_SHIFT 2
251#define FM10K_RXQCTL_VF 0x00000100
252#define FM10K_RXQCTL_ID_MASK (FM10K_RXQCTL_PF | FM10K_RXQCTL_VF)
253#define FM10K_RXDCTL(_n) ((0x40 * (_n)) + 0x4007)
254#define FM10K_RXDCTL_WRITE_BACK_MIN_DELAY 0x00000001
255#define FM10K_RXDCTL_DROP_ON_EMPTY 0x00000200
256#define FM10K_RXINT(_n) ((0x40 * (_n)) + 0x4008)
257#define FM10K_SRRCTL(_n) ((0x40 * (_n)) + 0x4009)
258#define FM10K_SRRCTL_BSIZEPKT_SHIFT 8
259#define FM10K_SRRCTL_LOOPBACK_SUPPRESS 0x40000000
260#define FM10K_SRRCTL_BUFFER_CHAINING_EN 0x80000000
261
262
263#define FM10K_QPRC(_n) ((0x40 * (_n)) + 0x400A)
264#define FM10K_QPRDC(_n) ((0x40 * (_n)) + 0x400B)
265#define FM10K_QBRC_L(_n) ((0x40 * (_n)) + 0x400C)
266#define FM10K_QBRC_H(_n) ((0x40 * (_n)) + 0x400D)
267
268
269#define FM10K_RX_SGLORT(_n) ((0x40 * (_n)) + 0x400E)
270
271
272#define FM10K_TDBAL(_n) ((0x40 * (_n)) + 0x8000)
273#define FM10K_TDBAH(_n) ((0x40 * (_n)) + 0x8001)
274#define FM10K_TDLEN(_n) ((0x40 * (_n)) + 0x8002)
275
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282
283
284#define FM10K_TDLEN_ITR_SCALE_SHIFT 9
285#define FM10K_TDLEN_ITR_SCALE_MASK 0x00000E00
286#define FM10K_TDLEN_ITR_SCALE_GEN1 2
287#define FM10K_TDLEN_ITR_SCALE_GEN2 1
288#define FM10K_TDLEN_ITR_SCALE_GEN3 0
289#define FM10K_TPH_TXCTRL(_n) ((0x40 * (_n)) + 0x8003)
290#define FM10K_TPH_TXCTRL_DESC_TPHEN 0x00000020
291#define FM10K_TPH_TXCTRL_DESC_RROEN 0x00000200
292#define FM10K_TPH_TXCTRL_DESC_WROEN 0x00000800
293#define FM10K_TPH_TXCTRL_DATA_RROEN 0x00002000
294#define FM10K_TDH(_n) ((0x40 * (_n)) + 0x8004)
295#define FM10K_TDT(_n) ((0x40 * (_n)) + 0x8005)
296#define FM10K_TXDCTL(_n) ((0x40 * (_n)) + 0x8006)
297#define FM10K_TXDCTL_ENABLE 0x00004000
298#define FM10K_TXDCTL_MAX_TIME_SHIFT 16
299#define FM10K_TXQCTL(_n) ((0x40 * (_n)) + 0x8007)
300#define FM10K_TXQCTL_PF 0x0000003F
301#define FM10K_TXQCTL_VF 0x00000040
302#define FM10K_TXQCTL_ID_MASK (FM10K_TXQCTL_PF | FM10K_TXQCTL_VF)
303#define FM10K_TXQCTL_PC_SHIFT 7
304#define FM10K_TXQCTL_PC_MASK 0x00000380
305#define FM10K_TXQCTL_TC_SHIFT 10
306#define FM10K_TXQCTL_VID_SHIFT 16
307#define FM10K_TXQCTL_VID_MASK 0x0FFF0000
308#define FM10K_TXQCTL_UNLIMITED_BW 0x10000000
309#define FM10K_TXINT(_n) ((0x40 * (_n)) + 0x8008)
310
311
312#define FM10K_QPTC(_n) ((0x40 * (_n)) + 0x8009)
313#define FM10K_QBTC_L(_n) ((0x40 * (_n)) + 0x800A)
314#define FM10K_QBTC_H(_n) ((0x40 * (_n)) + 0x800B)
315
316
317#define FM10K_TQDLOC(_n) ((0x40 * (_n)) + 0x800C)
318#define FM10K_TQDLOC_BASE_32_DESC 0x08
319#define FM10K_TQDLOC_SIZE_32_DESC 0x00050000
320
321
322#define FM10K_TX_SGLORT(_n) ((0x40 * (_n)) + 0x800D)
323#define FM10K_PFVTCTL(_n) ((0x40 * (_n)) + 0x800E)
324#define FM10K_PFVTCTL_FTAG_DESC_ENABLE 0x00000001
325
326
327#define FM10K_INT_MAP(_n) ((_n) + 0x10080)
328#define FM10K_INT_MAP_TIMER0 0x00000000
329#define FM10K_INT_MAP_TIMER1 0x00000100
330#define FM10K_INT_MAP_IMMEDIATE 0x00000200
331#define FM10K_INT_MAP_DISABLE 0x00000300
332#define FM10K_MSIX_VECTOR_MASK(_n) ((0x4 * (_n)) + 0x11003)
333#define FM10K_INT_CTRL 0x12000
334#define FM10K_INT_CTRL_ENABLEMODERATOR 0x00000400
335#define FM10K_ITR(_n) ((_n) + 0x12400)
336#define FM10K_ITR_INTERVAL1_SHIFT 12
337#define FM10K_ITR_PENDING2 0x10000000
338#define FM10K_ITR_AUTOMASK 0x20000000
339#define FM10K_ITR_MASK_SET 0x40000000
340#define FM10K_ITR_MASK_CLEAR 0x80000000
341#define FM10K_ITR2(_n) ((0x2 * (_n)) + 0x12800)
342#define FM10K_ITR_REG_COUNT 768
343#define FM10K_ITR_REG_COUNT_PF 256
344
345
346#define FM10K_IP 0x13000
347#define FM10K_IP_NOTINRESET 0x00000100
348
349
350#define FM10K_VLAN_TABLE(_n, _m) ((0x80 * (_n)) + (_m) + 0x14000)
351#define FM10K_VLAN_TABLE_SIZE 128
352
353
354#define FM10K_VLAN_TABLE_VID_MAX 4096
355#define FM10K_VLAN_TABLE_VSI_MAX 64
356#define FM10K_VLAN_LENGTH_SHIFT 16
357#define FM10K_VLAN_CLEAR BIT(15)
358#define FM10K_VLAN_ALL \
359 ((FM10K_VLAN_TABLE_VID_MAX - 1) << FM10K_VLAN_LENGTH_SHIFT)
360
361
362#define FM10K_PFVFLRE(_n) ((0x1 * (_n)) + 0x18844)
363#define FM10K_PFVFLREC(_n) ((0x1 * (_n)) + 0x18846)
364
365
366#define FM10K_UC_ADDR_START 0x000000
367#define FM10K_UC_ADDR_END 0x100000
368#define FM10K_UC_ADDR_SIZE (FM10K_UC_ADDR_END - FM10K_UC_ADDR_START)
369
370
371#define FM10K_QUEUE_DISABLE_TIMEOUT 100
372#define FM10K_RESET_TIMEOUT 150
373
374
375#define FM10K_TUNNEL_HEADER_LENGTH 184
376
377
378#define FM10K_VFCTRL 0x00000
379#define FM10K_VFCTRL_RST 0x00000008
380#define FM10K_VFINT_MAP 0x00030
381#define FM10K_VFSYSTIME 0x00040
382#define FM10K_VFITR(_n) ((_n) + 0x00060)
383
384
385#define FM10K_SW_SYSTIME_ADJUST 0x0224D
386#define FM10K_SW_SYSTIME_ADJUST_MASK 0x3FFFFFFF
387#define FM10K_SW_SYSTIME_ADJUST_DIR_POSITIVE 0x80000000
388#define FM10K_SW_SYSTIME_PULSE(_n) ((_n) + 0x02252)
389
390enum fm10k_int_source {
391 fm10k_int_mailbox = 0,
392 fm10k_int_pcie_fault = 1,
393 fm10k_int_switch_up_down = 2,
394 fm10k_int_switch_event = 3,
395 fm10k_int_sram = 4,
396 fm10k_int_vflr = 5,
397 fm10k_int_max_hold_time = 6,
398 fm10k_int_sources_max_pf
399};
400
401
402enum fm10k_bus_speed {
403 fm10k_bus_speed_unknown = 0,
404 fm10k_bus_speed_2500 = 2500,
405 fm10k_bus_speed_5000 = 5000,
406 fm10k_bus_speed_8000 = 8000,
407 fm10k_bus_speed_reserved
408};
409
410
411enum fm10k_bus_width {
412 fm10k_bus_width_unknown = 0,
413 fm10k_bus_width_pcie_x1 = 1,
414 fm10k_bus_width_pcie_x2 = 2,
415 fm10k_bus_width_pcie_x4 = 4,
416 fm10k_bus_width_pcie_x8 = 8,
417 fm10k_bus_width_reserved
418};
419
420
421enum fm10k_bus_payload {
422 fm10k_bus_payload_unknown = 0,
423 fm10k_bus_payload_128 = 1,
424 fm10k_bus_payload_256 = 2,
425 fm10k_bus_payload_512 = 3,
426 fm10k_bus_payload_reserved
427};
428
429
430struct fm10k_bus_info {
431 enum fm10k_bus_speed speed;
432 enum fm10k_bus_width width;
433 enum fm10k_bus_payload payload;
434};
435
436
437struct fm10k_hw_stat {
438 u64 count;
439 u32 base_l;
440 u32 base_h;
441};
442
443struct fm10k_hw_stats_q {
444 struct fm10k_hw_stat tx_bytes;
445 struct fm10k_hw_stat tx_packets;
446#define tx_stats_idx tx_packets.base_h
447 struct fm10k_hw_stat rx_bytes;
448 struct fm10k_hw_stat rx_packets;
449#define rx_stats_idx rx_packets.base_h
450 struct fm10k_hw_stat rx_drops;
451};
452
453struct fm10k_hw_stats {
454 struct fm10k_hw_stat timeout;
455#define stats_idx timeout.base_h
456 struct fm10k_hw_stat ur;
457 struct fm10k_hw_stat ca;
458 struct fm10k_hw_stat um;
459 struct fm10k_hw_stat xec;
460 struct fm10k_hw_stat vlan_drop;
461 struct fm10k_hw_stat loopback_drop;
462 struct fm10k_hw_stat nodesc_drop;
463 struct fm10k_hw_stats_q q[FM10K_MAX_QUEUES_PF];
464};
465
466
467enum fm10k_dglortdec_idx {
468 fm10k_dglort_default = 0,
469 fm10k_dglort_vf_rsvd0 = 1,
470 fm10k_dglort_vf_rss = 2,
471 fm10k_dglort_pf_rsvd0 = 3,
472 fm10k_dglort_pf_queue = 4,
473 fm10k_dglort_pf_vsi = 5,
474 fm10k_dglort_pf_rsvd1 = 6,
475 fm10k_dglort_pf_rss = 7
476};
477
478struct fm10k_dglort_cfg {
479 u16 glort;
480 u16 queue_b;
481 u8 vsi_b;
482 u8 idx;
483 u8 rss_l;
484 u8 pc_l;
485 u8 vsi_l;
486 u8 queue_l;
487 u8 shared_l;
488 u8 inner_rss;
489};
490
491enum fm10k_pca_fault {
492 PCA_NO_FAULT,
493 PCA_UNMAPPED_ADDR,
494 PCA_BAD_QACCESS_PF,
495 PCA_BAD_QACCESS_VF,
496 PCA_MALICIOUS_REQ,
497 PCA_POISONED_TLP,
498 PCA_TLP_ABORT,
499 __PCA_MAX
500};
501
502enum fm10k_thi_fault {
503 THI_NO_FAULT,
504 THI_MAL_DIS_Q_FAULT,
505 __THI_MAX
506};
507
508enum fm10k_fum_fault {
509 FUM_NO_FAULT,
510 FUM_UNMAPPED_ADDR,
511 FUM_POISONED_TLP,
512 FUM_BAD_VF_QACCESS,
513 FUM_ADD_DECODE_ERR,
514 FUM_RO_ERROR,
515 FUM_QPRC_CRC_ERROR,
516 FUM_CSR_TIMEOUT,
517 FUM_INVALID_TYPE,
518 FUM_INVALID_LENGTH,
519 FUM_INVALID_BE,
520 FUM_INVALID_ALIGN,
521 __FUM_MAX
522};
523
524struct fm10k_fault {
525 u64 address;
526 u32 specinfo;
527 u8 type;
528 u8 func;
529};
530
531struct fm10k_mac_ops {
532
533 s32 (*reset_hw)(struct fm10k_hw *);
534 s32 (*init_hw)(struct fm10k_hw *);
535 s32 (*start_hw)(struct fm10k_hw *);
536 s32 (*stop_hw)(struct fm10k_hw *);
537 s32 (*get_bus_info)(struct fm10k_hw *);
538 s32 (*get_host_state)(struct fm10k_hw *, bool *);
539 s32 (*update_vlan)(struct fm10k_hw *, u32, u8, bool);
540 s32 (*read_mac_addr)(struct fm10k_hw *);
541 s32 (*update_uc_addr)(struct fm10k_hw *, u16, const u8 *,
542 u16, bool, u8);
543 s32 (*update_mc_addr)(struct fm10k_hw *, u16, const u8 *, u16, bool);
544 s32 (*update_xcast_mode)(struct fm10k_hw *, u16, u8);
545 void (*update_int_moderator)(struct fm10k_hw *);
546 s32 (*update_lport_state)(struct fm10k_hw *, u16, u16, bool);
547 void (*update_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
548 void (*rebind_hw_stats)(struct fm10k_hw *, struct fm10k_hw_stats *);
549 s32 (*configure_dglort_map)(struct fm10k_hw *,
550 struct fm10k_dglort_cfg *);
551 void (*set_dma_mask)(struct fm10k_hw *, u64);
552 s32 (*get_fault)(struct fm10k_hw *, int, struct fm10k_fault *);
553 s32 (*adjust_systime)(struct fm10k_hw *, s32 ppb);
554 u64 (*read_systime)(struct fm10k_hw *);
555};
556
557enum fm10k_mac_type {
558 fm10k_mac_unknown = 0,
559 fm10k_mac_pf,
560 fm10k_mac_vf,
561 fm10k_num_macs
562};
563
564struct fm10k_mac_info {
565 struct fm10k_mac_ops ops;
566 enum fm10k_mac_type type;
567 u8 addr[ETH_ALEN];
568 u8 perm_addr[ETH_ALEN];
569 u16 default_vid;
570 u16 max_msix_vectors;
571 u16 max_queues;
572 bool vlan_override;
573 bool get_host_state;
574 bool tx_ready;
575 u32 dglort_map;
576 u8 itr_scale;
577};
578
579struct fm10k_swapi_table_info {
580 u32 used;
581 u32 avail;
582};
583
584struct fm10k_swapi_info {
585 u32 status;
586 struct fm10k_swapi_table_info mac;
587 struct fm10k_swapi_table_info nexthop;
588 struct fm10k_swapi_table_info ffu;
589};
590
591enum fm10k_xcast_modes {
592 FM10K_XCAST_MODE_ALLMULTI = 0,
593 FM10K_XCAST_MODE_MULTI = 1,
594 FM10K_XCAST_MODE_PROMISC = 2,
595 FM10K_XCAST_MODE_NONE = 3,
596 FM10K_XCAST_MODE_DISABLE = 4
597};
598
599#define FM10K_VF_TC_MAX 100000
600#define FM10K_VF_TC_MIN 1
601
602struct fm10k_vf_info {
603
604
605
606
607 struct fm10k_mbx_info mbx;
608 int rate;
609 u16 glort;
610 u16 sw_vid;
611 u16 pf_vid;
612 u8 mac[ETH_ALEN];
613 u8 vsi;
614 u8 vf_idx;
615 u8 vf_flags;
616
617
618};
619
620#define FM10K_VF_FLAG_ALLMULTI_CAPABLE ((u8)1 << FM10K_XCAST_MODE_ALLMULTI)
621#define FM10K_VF_FLAG_MULTI_CAPABLE ((u8)1 << FM10K_XCAST_MODE_MULTI)
622#define FM10K_VF_FLAG_PROMISC_CAPABLE ((u8)1 << FM10K_XCAST_MODE_PROMISC)
623#define FM10K_VF_FLAG_NONE_CAPABLE ((u8)1 << FM10K_XCAST_MODE_NONE)
624#define FM10K_VF_FLAG_CAPABLE(vf_info) ((vf_info)->vf_flags & (u8)0xF)
625#define FM10K_VF_FLAG_ENABLED(vf_info) ((vf_info)->vf_flags >> 4)
626#define FM10K_VF_FLAG_SET_MODE(mode) ((u8)0x10 << (mode))
627#define FM10K_VF_FLAG_SET_MODE_NONE \
628 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_NONE)
629#define FM10K_VF_FLAG_MULTI_ENABLED \
630 (FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_ALLMULTI) | \
631 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_MULTI) | \
632 FM10K_VF_FLAG_SET_MODE(FM10K_XCAST_MODE_PROMISC))
633
634struct fm10k_iov_ops {
635
636 s32 (*assign_resources)(struct fm10k_hw *, u16, u16);
637 s32 (*configure_tc)(struct fm10k_hw *, u16, int);
638 s32 (*assign_int_moderator)(struct fm10k_hw *, u16);
639 s32 (*assign_default_mac_vlan)(struct fm10k_hw *,
640 struct fm10k_vf_info *);
641 s32 (*reset_resources)(struct fm10k_hw *,
642 struct fm10k_vf_info *);
643 s32 (*set_lport)(struct fm10k_hw *, struct fm10k_vf_info *, u16, u8);
644 void (*reset_lport)(struct fm10k_hw *, struct fm10k_vf_info *);
645 void (*update_stats)(struct fm10k_hw *, struct fm10k_hw_stats_q *, u16);
646 s32 (*report_timestamp)(struct fm10k_hw *, struct fm10k_vf_info *, u64);
647};
648
649struct fm10k_iov_info {
650 struct fm10k_iov_ops ops;
651 u16 total_vfs;
652 u16 num_vfs;
653 u16 num_pools;
654};
655
656enum fm10k_devices {
657 fm10k_device_pf,
658 fm10k_device_vf,
659};
660
661struct fm10k_info {
662 enum fm10k_mac_type mac;
663 s32 (*get_invariants)(struct fm10k_hw *);
664 const struct fm10k_mac_ops *mac_ops;
665 const struct fm10k_iov_ops *iov_ops;
666};
667
668struct fm10k_hw {
669 u32 __iomem *hw_addr;
670 u32 __iomem *sw_addr;
671 void *back;
672 struct fm10k_mac_info mac;
673 struct fm10k_bus_info bus;
674 struct fm10k_bus_info bus_caps;
675 struct fm10k_iov_info iov;
676 struct fm10k_mbx_info mbx;
677 struct fm10k_swapi_info swapi;
678 u16 device_id;
679 u16 vendor_id;
680 u16 subsystem_device_id;
681 u16 subsystem_vendor_id;
682 u8 revision_id;
683};
684
685
686#define FM10K_REQ_TX_DESCRIPTOR_MULTIPLE 8
687#define FM10K_REQ_RX_DESCRIPTOR_MULTIPLE 8
688
689
690struct fm10k_tx_desc {
691 __le64 buffer_addr;
692 __le16 buflen;
693 __le16 vlan;
694 __le16 mss;
695 u8 hdrlen;
696 u8 flags;
697};
698
699
700struct fm10k_tx_desc_cache {
701 struct fm10k_tx_desc tx_desc[256];
702};
703
704#define FM10K_TXD_FLAG_INT 0x01
705#define FM10K_TXD_FLAG_TIME 0x02
706#define FM10K_TXD_FLAG_CSUM 0x04
707#define FM10K_TXD_FLAG_FTAG 0x10
708#define FM10K_TXD_FLAG_RS 0x20
709#define FM10K_TXD_FLAG_LAST 0x40
710#define FM10K_TXD_FLAG_DONE 0x80
711
712
713
714
715
716
717
718#define FM10K_TXD_WB_FIFO_SIZE 4
719
720
721union fm10k_rx_desc {
722 struct {
723 __le64 pkt_addr;
724 __le64 hdr_addr;
725 __le64 reserved;
726 __le64 timestamp;
727 } q;
728 struct {
729 __le32 data;
730 __le32 rss;
731 __le32 staterr;
732 __le32 vlan_len;
733 __le32 glort;
734 } d;
735 struct {
736 __le16 pkt_info;
737 __le16 hdr_info;
738 __le16 rss_lower;
739 __le16 rss_upper;
740 __le16 status;
741 __le16 csum_err;
742 __le16 length;
743 __le16 vlan;
744 __le16 dglort;
745 __le16 sglort;
746 } w;
747};
748
749#define FM10K_RXD_RSSTYPE_MASK 0x000F
750enum fm10k_rdesc_rss_type {
751 FM10K_RSSTYPE_NONE = 0x0,
752 FM10K_RSSTYPE_IPV4_TCP = 0x1,
753 FM10K_RSSTYPE_IPV4 = 0x2,
754 FM10K_RSSTYPE_IPV6_TCP = 0x3,
755
756 FM10K_RSSTYPE_IPV6 = 0x5,
757
758 FM10K_RSSTYPE_IPV4_UDP = 0x7,
759 FM10K_RSSTYPE_IPV6_UDP = 0x8
760
761};
762
763#define FM10K_RXD_HDR_INFO_XC_MASK 0x0006
764enum fm10k_rxdesc_xc {
765 FM10K_XC_UNICAST = 0x0,
766 FM10K_XC_MULTICAST = 0x4,
767 FM10K_XC_BROADCAST = 0x6
768};
769
770#define FM10K_RXD_STATUS_DD 0x0001
771#define FM10K_RXD_STATUS_EOP 0x0002
772#define FM10K_RXD_STATUS_L4CS 0x0010
773#define FM10K_RXD_STATUS_L4CS2 0x0040
774#define FM10K_RXD_STATUS_L4E2 0x0800
775#define FM10K_RXD_STATUS_IPE2 0x1000
776#define FM10K_RXD_STATUS_RXE 0x2000
777#define FM10K_RXD_STATUS_L4E 0x4000
778#define FM10K_RXD_STATUS_IPE 0x8000
779
780#define FM10K_RXD_ERR_SWITCH_ERROR 0x0001
781#define FM10K_RXD_ERR_NO_DESCRIPTOR 0x0002
782#define FM10K_RXD_ERR_PP_ERROR 0x0004
783#define FM10K_RXD_ERR_SWITCH_READY 0x0008
784#define FM10K_RXD_ERR_TOO_BIG 0x0010
785
786struct fm10k_ftag {
787 __be16 swpri_type_user;
788 __be16 vlan;
789 __be16 sglort;
790 __be16 dglort;
791};
792
793#endif
794