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21#include "fm10k_vf.h"
22
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25
26
27
28static s32 fm10k_stop_hw_vf(struct fm10k_hw *hw)
29{
30 u8 *perm_addr = hw->mac.perm_addr;
31 u32 bal = 0, bah = 0, tdlen;
32 s32 err;
33 u16 i;
34
35
36 err = fm10k_stop_hw_generic(hw);
37 if (err)
38 return err;
39
40
41 if (is_valid_ether_addr(perm_addr)) {
42 bal = (((u32)perm_addr[3]) << 24) |
43 (((u32)perm_addr[4]) << 16) |
44 (((u32)perm_addr[5]) << 8);
45 bah = (((u32)0xFF) << 24) |
46 (((u32)perm_addr[0]) << 16) |
47 (((u32)perm_addr[1]) << 8) |
48 ((u32)perm_addr[2]);
49 }
50
51
52 tdlen = hw->mac.itr_scale << FM10K_TDLEN_ITR_SCALE_SHIFT;
53
54
55
56
57 for (i = 0; i < hw->mac.max_queues; i++) {
58 fm10k_write_reg(hw, FM10K_TDBAL(i), bal);
59 fm10k_write_reg(hw, FM10K_TDBAH(i), bah);
60 fm10k_write_reg(hw, FM10K_RDBAL(i), bal);
61 fm10k_write_reg(hw, FM10K_RDBAH(i), bah);
62
63
64
65
66
67 fm10k_write_reg(hw, FM10K_TDLEN(i), tdlen);
68 }
69
70 return 0;
71}
72
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74
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78
79
80static s32 fm10k_reset_hw_vf(struct fm10k_hw *hw)
81{
82 s32 err;
83
84
85 err = fm10k_stop_hw_vf(hw);
86 if (err)
87 return err;
88
89
90 fm10k_write_reg(hw, FM10K_VFCTRL, FM10K_VFCTRL_RST);
91
92
93 fm10k_write_flush(hw);
94 udelay(FM10K_RESET_TIMEOUT);
95
96
97 fm10k_write_reg(hw, FM10K_VFCTRL, 0);
98 if (fm10k_read_reg(hw, FM10K_VFCTRL) & FM10K_VFCTRL_RST)
99 err = FM10K_ERR_RESET_FAILED;
100
101 return err;
102}
103
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105
106
107
108
109static s32 fm10k_init_hw_vf(struct fm10k_hw *hw)
110{
111 u32 tqdloc, tqdloc0 = ~fm10k_read_reg(hw, FM10K_TQDLOC(0));
112 s32 err;
113 u16 i;
114
115
116 if (!~fm10k_read_reg(hw, FM10K_TXQCTL(0)) ||
117 !~fm10k_read_reg(hw, FM10K_RXQCTL(0))) {
118 err = FM10K_ERR_NO_RESOURCES;
119 goto reset_max_queues;
120 }
121
122
123 for (i = 1; tqdloc0 && (i < FM10K_MAX_QUEUES_POOL); i++) {
124
125 tqdloc = ~fm10k_read_reg(hw, FM10K_TQDLOC(i));
126 if (!tqdloc || (tqdloc == tqdloc0))
127 break;
128
129
130 if (!~fm10k_read_reg(hw, FM10K_TXQCTL(i)) ||
131 !~fm10k_read_reg(hw, FM10K_RXQCTL(i)))
132 break;
133 }
134
135
136 err = fm10k_disable_queues_generic(hw, i);
137 if (err)
138 goto reset_max_queues;
139
140
141 hw->mac.max_queues = i;
142
143
144 hw->mac.default_vid = (fm10k_read_reg(hw, FM10K_TXQCTL(0)) &
145 FM10K_TXQCTL_VID_MASK) >> FM10K_TXQCTL_VID_SHIFT;
146
147
148
149
150 hw->mac.itr_scale = (fm10k_read_reg(hw, FM10K_TDLEN(0)) &
151 FM10K_TDLEN_ITR_SCALE_MASK) >>
152 FM10K_TDLEN_ITR_SCALE_SHIFT;
153
154 return 0;
155
156reset_max_queues:
157 hw->mac.max_queues = 0;
158
159 return err;
160}
161
162
163const struct fm10k_tlv_attr fm10k_mac_vlan_msg_attr[] = {
164 FM10K_TLV_ATTR_U32(FM10K_MAC_VLAN_MSG_VLAN),
165 FM10K_TLV_ATTR_BOOL(FM10K_MAC_VLAN_MSG_SET),
166 FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MAC),
167 FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_DEFAULT_MAC),
168 FM10K_TLV_ATTR_MAC_ADDR(FM10K_MAC_VLAN_MSG_MULTICAST),
169 FM10K_TLV_ATTR_LAST
170};
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181
182static s32 fm10k_update_vlan_vf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
183{
184 struct fm10k_mbx_info *mbx = &hw->mbx;
185 u32 msg[4];
186
187
188 if (vsi)
189 return FM10K_ERR_PARAM;
190
191
192 if ((vid << 16 | vid) >> 28)
193 return FM10K_ERR_PARAM;
194
195
196 if (!set)
197 vid |= FM10K_VLAN_CLEAR;
198
199
200 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
201 fm10k_tlv_attr_put_u32(msg, FM10K_MAC_VLAN_MSG_VLAN, vid);
202
203
204 return mbx->ops.enqueue_tx(hw, mbx, msg);
205}
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214
215s32 fm10k_msg_mac_vlan_vf(struct fm10k_hw *hw, u32 **results,
216 struct fm10k_mbx_info *mbx)
217{
218 u8 perm_addr[ETH_ALEN];
219 u16 vid;
220 s32 err;
221
222
223 err = fm10k_tlv_attr_get_mac_vlan(
224 results[FM10K_MAC_VLAN_MSG_DEFAULT_MAC],
225 perm_addr, &vid);
226 if (err)
227 return err;
228
229 ether_addr_copy(hw->mac.perm_addr, perm_addr);
230 hw->mac.default_vid = vid & (FM10K_VLAN_TABLE_VID_MAX - 1);
231 hw->mac.vlan_override = !!(vid & FM10K_VLAN_CLEAR);
232
233 return 0;
234}
235
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240
241
242static s32 fm10k_read_mac_addr_vf(struct fm10k_hw *hw)
243{
244 u8 perm_addr[ETH_ALEN];
245 u32 base_addr;
246
247 base_addr = fm10k_read_reg(hw, FM10K_TDBAL(0));
248
249
250 if (base_addr << 24)
251 return FM10K_ERR_INVALID_MAC_ADDR;
252
253 perm_addr[3] = (u8)(base_addr >> 24);
254 perm_addr[4] = (u8)(base_addr >> 16);
255 perm_addr[5] = (u8)(base_addr >> 8);
256
257 base_addr = fm10k_read_reg(hw, FM10K_TDBAH(0));
258
259
260 if ((~base_addr) >> 24)
261 return FM10K_ERR_INVALID_MAC_ADDR;
262
263 perm_addr[0] = (u8)(base_addr >> 16);
264 perm_addr[1] = (u8)(base_addr >> 8);
265 perm_addr[2] = (u8)(base_addr);
266
267 ether_addr_copy(hw->mac.perm_addr, perm_addr);
268 ether_addr_copy(hw->mac.addr, perm_addr);
269
270 return 0;
271}
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284
285static s32 fm10k_update_uc_addr_vf(struct fm10k_hw *hw, u16 glort,
286 const u8 *mac, u16 vid, bool add, u8 flags)
287{
288 struct fm10k_mbx_info *mbx = &hw->mbx;
289 u32 msg[7];
290
291
292 if (vid >= FM10K_VLAN_TABLE_VID_MAX)
293 return FM10K_ERR_PARAM;
294
295
296 if (!is_valid_ether_addr(mac))
297 return FM10K_ERR_PARAM;
298
299
300 if (is_valid_ether_addr(hw->mac.perm_addr) &&
301 !ether_addr_equal(hw->mac.perm_addr, mac))
302 return FM10K_ERR_PARAM;
303
304
305 if (!add)
306 vid |= FM10K_VLAN_CLEAR;
307
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309 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
310 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_MAC, mac, vid);
311
312
313 return mbx->ops.enqueue_tx(hw, mbx, msg);
314}
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326
327static s32 fm10k_update_mc_addr_vf(struct fm10k_hw *hw, u16 glort,
328 const u8 *mac, u16 vid, bool add)
329{
330 struct fm10k_mbx_info *mbx = &hw->mbx;
331 u32 msg[7];
332
333
334 if (vid >= FM10K_VLAN_TABLE_VID_MAX)
335 return FM10K_ERR_PARAM;
336
337
338 if (!is_multicast_ether_addr(mac))
339 return FM10K_ERR_PARAM;
340
341
342 if (!add)
343 vid |= FM10K_VLAN_CLEAR;
344
345
346 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
347 fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_MULTICAST,
348 mac, vid);
349
350
351 return mbx->ops.enqueue_tx(hw, mbx, msg);
352}
353
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361static void fm10k_update_int_moderator_vf(struct fm10k_hw *hw)
362{
363 struct fm10k_mbx_info *mbx = &hw->mbx;
364 u32 msg[1];
365
366
367 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MSIX);
368
369
370 mbx->ops.enqueue_tx(hw, mbx, msg);
371}
372
373
374const struct fm10k_tlv_attr fm10k_lport_state_msg_attr[] = {
375 FM10K_TLV_ATTR_BOOL(FM10K_LPORT_STATE_MSG_DISABLE),
376 FM10K_TLV_ATTR_U8(FM10K_LPORT_STATE_MSG_XCAST_MODE),
377 FM10K_TLV_ATTR_BOOL(FM10K_LPORT_STATE_MSG_READY),
378 FM10K_TLV_ATTR_LAST
379};
380
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390s32 fm10k_msg_lport_state_vf(struct fm10k_hw *hw, u32 **results,
391 struct fm10k_mbx_info *mbx)
392{
393 hw->mac.dglort_map = !results[FM10K_LPORT_STATE_MSG_READY] ?
394 FM10K_DGLORTMAP_NONE : FM10K_DGLORTMAP_ZERO;
395
396 return 0;
397}
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409
410static s32 fm10k_update_lport_state_vf(struct fm10k_hw *hw, u16 glort,
411 u16 count, bool enable)
412{
413 struct fm10k_mbx_info *mbx = &hw->mbx;
414 u32 msg[2];
415
416
417 hw->mac.dglort_map = FM10K_DGLORTMAP_NONE;
418
419
420 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
421 if (!enable)
422 fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_DISABLE);
423
424
425 return mbx->ops.enqueue_tx(hw, mbx, msg);
426}
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437
438static s32 fm10k_update_xcast_mode_vf(struct fm10k_hw *hw, u16 glort, u8 mode)
439{
440 struct fm10k_mbx_info *mbx = &hw->mbx;
441 u32 msg[3];
442
443 if (mode > FM10K_XCAST_MODE_NONE)
444 return FM10K_ERR_PARAM;
445
446
447 fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
448 fm10k_tlv_attr_put_u8(msg, FM10K_LPORT_STATE_MSG_XCAST_MODE, mode);
449
450
451 return mbx->ops.enqueue_tx(hw, mbx, msg);
452}
453
454const struct fm10k_tlv_attr fm10k_1588_msg_attr[] = {
455 FM10K_TLV_ATTR_U64(FM10K_1588_MSG_TIMESTAMP),
456 FM10K_TLV_ATTR_LAST
457};
458
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467
468static void fm10k_update_hw_stats_vf(struct fm10k_hw *hw,
469 struct fm10k_hw_stats *stats)
470{
471 fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
472}
473
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480
481static void fm10k_rebind_hw_stats_vf(struct fm10k_hw *hw,
482 struct fm10k_hw_stats *stats)
483{
484
485 fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
486
487
488 fm10k_update_hw_stats_vf(hw, stats);
489}
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499
500static s32 fm10k_configure_dglort_map_vf(struct fm10k_hw *hw,
501 struct fm10k_dglort_cfg *dglort)
502{
503
504 if (!dglort)
505 return FM10K_ERR_PARAM;
506
507
508
509 return 0;
510}
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522
523static s32 fm10k_adjust_systime_vf(struct fm10k_hw *hw, s32 ppb)
524{
525
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527
528
529
530 return ppb ? FM10K_ERR_PARAM : 0;
531}
532
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541
542
543static u64 fm10k_read_systime_vf(struct fm10k_hw *hw)
544{
545 u32 systime_l, systime_h, systime_tmp;
546
547 systime_h = fm10k_read_reg(hw, FM10K_VFSYSTIME + 1);
548
549 do {
550 systime_tmp = systime_h;
551 systime_l = fm10k_read_reg(hw, FM10K_VFSYSTIME);
552 systime_h = fm10k_read_reg(hw, FM10K_VFSYSTIME + 1);
553 } while (systime_tmp != systime_h);
554
555 return ((u64)systime_h << 32) | systime_l;
556}
557
558static const struct fm10k_msg_data fm10k_msg_data_vf[] = {
559 FM10K_TLV_MSG_TEST_HANDLER(fm10k_tlv_msg_test),
560 FM10K_VF_MSG_MAC_VLAN_HANDLER(fm10k_msg_mac_vlan_vf),
561 FM10K_VF_MSG_LPORT_STATE_HANDLER(fm10k_msg_lport_state_vf),
562 FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
563};
564
565static const struct fm10k_mac_ops mac_ops_vf = {
566 .get_bus_info = fm10k_get_bus_info_generic,
567 .reset_hw = fm10k_reset_hw_vf,
568 .init_hw = fm10k_init_hw_vf,
569 .start_hw = fm10k_start_hw_generic,
570 .stop_hw = fm10k_stop_hw_vf,
571 .update_vlan = fm10k_update_vlan_vf,
572 .read_mac_addr = fm10k_read_mac_addr_vf,
573 .update_uc_addr = fm10k_update_uc_addr_vf,
574 .update_mc_addr = fm10k_update_mc_addr_vf,
575 .update_xcast_mode = fm10k_update_xcast_mode_vf,
576 .update_int_moderator = fm10k_update_int_moderator_vf,
577 .update_lport_state = fm10k_update_lport_state_vf,
578 .update_hw_stats = fm10k_update_hw_stats_vf,
579 .rebind_hw_stats = fm10k_rebind_hw_stats_vf,
580 .configure_dglort_map = fm10k_configure_dglort_map_vf,
581 .get_host_state = fm10k_get_host_state_generic,
582 .adjust_systime = fm10k_adjust_systime_vf,
583 .read_systime = fm10k_read_systime_vf,
584};
585
586static s32 fm10k_get_invariants_vf(struct fm10k_hw *hw)
587{
588 fm10k_get_invariants_generic(hw);
589
590 return fm10k_pfvf_mbx_init(hw, &hw->mbx, fm10k_msg_data_vf, 0);
591}
592
593const struct fm10k_info fm10k_vf_info = {
594 .mac = fm10k_mac_vf,
595 .get_invariants = fm10k_get_invariants_vf,
596 .mac_ops = &mac_ops_vf,
597};
598