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27#include "i40e_type.h"
28#include "i40e_adminq.h"
29#include "i40e_prototype.h"
30#include "i40e_virtchnl.h"
31
32
33
34
35
36
37
38
39static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
40{
41 i40e_status status = 0;
42
43 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
44 switch (hw->device_id) {
45 case I40E_DEV_ID_SFP_XL710:
46 case I40E_DEV_ID_QEMU:
47 case I40E_DEV_ID_KX_B:
48 case I40E_DEV_ID_KX_C:
49 case I40E_DEV_ID_QSFP_A:
50 case I40E_DEV_ID_QSFP_B:
51 case I40E_DEV_ID_QSFP_C:
52 case I40E_DEV_ID_10G_BASE_T:
53 case I40E_DEV_ID_10G_BASE_T4:
54 case I40E_DEV_ID_20G_KR2:
55 case I40E_DEV_ID_20G_KR2_A:
56 hw->mac.type = I40E_MAC_XL710;
57 break;
58 case I40E_DEV_ID_KX_X722:
59 case I40E_DEV_ID_QSFP_X722:
60 case I40E_DEV_ID_SFP_X722:
61 case I40E_DEV_ID_1G_BASE_T_X722:
62 case I40E_DEV_ID_10G_BASE_T_X722:
63 hw->mac.type = I40E_MAC_X722;
64 break;
65 default:
66 hw->mac.type = I40E_MAC_GENERIC;
67 break;
68 }
69 } else {
70 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
71 }
72
73 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
74 hw->mac.type, status);
75 return status;
76}
77
78
79
80
81
82
83const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
84{
85 switch (aq_err) {
86 case I40E_AQ_RC_OK:
87 return "OK";
88 case I40E_AQ_RC_EPERM:
89 return "I40E_AQ_RC_EPERM";
90 case I40E_AQ_RC_ENOENT:
91 return "I40E_AQ_RC_ENOENT";
92 case I40E_AQ_RC_ESRCH:
93 return "I40E_AQ_RC_ESRCH";
94 case I40E_AQ_RC_EINTR:
95 return "I40E_AQ_RC_EINTR";
96 case I40E_AQ_RC_EIO:
97 return "I40E_AQ_RC_EIO";
98 case I40E_AQ_RC_ENXIO:
99 return "I40E_AQ_RC_ENXIO";
100 case I40E_AQ_RC_E2BIG:
101 return "I40E_AQ_RC_E2BIG";
102 case I40E_AQ_RC_EAGAIN:
103 return "I40E_AQ_RC_EAGAIN";
104 case I40E_AQ_RC_ENOMEM:
105 return "I40E_AQ_RC_ENOMEM";
106 case I40E_AQ_RC_EACCES:
107 return "I40E_AQ_RC_EACCES";
108 case I40E_AQ_RC_EFAULT:
109 return "I40E_AQ_RC_EFAULT";
110 case I40E_AQ_RC_EBUSY:
111 return "I40E_AQ_RC_EBUSY";
112 case I40E_AQ_RC_EEXIST:
113 return "I40E_AQ_RC_EEXIST";
114 case I40E_AQ_RC_EINVAL:
115 return "I40E_AQ_RC_EINVAL";
116 case I40E_AQ_RC_ENOTTY:
117 return "I40E_AQ_RC_ENOTTY";
118 case I40E_AQ_RC_ENOSPC:
119 return "I40E_AQ_RC_ENOSPC";
120 case I40E_AQ_RC_ENOSYS:
121 return "I40E_AQ_RC_ENOSYS";
122 case I40E_AQ_RC_ERANGE:
123 return "I40E_AQ_RC_ERANGE";
124 case I40E_AQ_RC_EFLUSHED:
125 return "I40E_AQ_RC_EFLUSHED";
126 case I40E_AQ_RC_BAD_ADDR:
127 return "I40E_AQ_RC_BAD_ADDR";
128 case I40E_AQ_RC_EMODE:
129 return "I40E_AQ_RC_EMODE";
130 case I40E_AQ_RC_EFBIG:
131 return "I40E_AQ_RC_EFBIG";
132 }
133
134 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
135 return hw->err_str;
136}
137
138
139
140
141
142
143const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
144{
145 switch (stat_err) {
146 case 0:
147 return "OK";
148 case I40E_ERR_NVM:
149 return "I40E_ERR_NVM";
150 case I40E_ERR_NVM_CHECKSUM:
151 return "I40E_ERR_NVM_CHECKSUM";
152 case I40E_ERR_PHY:
153 return "I40E_ERR_PHY";
154 case I40E_ERR_CONFIG:
155 return "I40E_ERR_CONFIG";
156 case I40E_ERR_PARAM:
157 return "I40E_ERR_PARAM";
158 case I40E_ERR_MAC_TYPE:
159 return "I40E_ERR_MAC_TYPE";
160 case I40E_ERR_UNKNOWN_PHY:
161 return "I40E_ERR_UNKNOWN_PHY";
162 case I40E_ERR_LINK_SETUP:
163 return "I40E_ERR_LINK_SETUP";
164 case I40E_ERR_ADAPTER_STOPPED:
165 return "I40E_ERR_ADAPTER_STOPPED";
166 case I40E_ERR_INVALID_MAC_ADDR:
167 return "I40E_ERR_INVALID_MAC_ADDR";
168 case I40E_ERR_DEVICE_NOT_SUPPORTED:
169 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
170 case I40E_ERR_MASTER_REQUESTS_PENDING:
171 return "I40E_ERR_MASTER_REQUESTS_PENDING";
172 case I40E_ERR_INVALID_LINK_SETTINGS:
173 return "I40E_ERR_INVALID_LINK_SETTINGS";
174 case I40E_ERR_AUTONEG_NOT_COMPLETE:
175 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
176 case I40E_ERR_RESET_FAILED:
177 return "I40E_ERR_RESET_FAILED";
178 case I40E_ERR_SWFW_SYNC:
179 return "I40E_ERR_SWFW_SYNC";
180 case I40E_ERR_NO_AVAILABLE_VSI:
181 return "I40E_ERR_NO_AVAILABLE_VSI";
182 case I40E_ERR_NO_MEMORY:
183 return "I40E_ERR_NO_MEMORY";
184 case I40E_ERR_BAD_PTR:
185 return "I40E_ERR_BAD_PTR";
186 case I40E_ERR_RING_FULL:
187 return "I40E_ERR_RING_FULL";
188 case I40E_ERR_INVALID_PD_ID:
189 return "I40E_ERR_INVALID_PD_ID";
190 case I40E_ERR_INVALID_QP_ID:
191 return "I40E_ERR_INVALID_QP_ID";
192 case I40E_ERR_INVALID_CQ_ID:
193 return "I40E_ERR_INVALID_CQ_ID";
194 case I40E_ERR_INVALID_CEQ_ID:
195 return "I40E_ERR_INVALID_CEQ_ID";
196 case I40E_ERR_INVALID_AEQ_ID:
197 return "I40E_ERR_INVALID_AEQ_ID";
198 case I40E_ERR_INVALID_SIZE:
199 return "I40E_ERR_INVALID_SIZE";
200 case I40E_ERR_INVALID_ARP_INDEX:
201 return "I40E_ERR_INVALID_ARP_INDEX";
202 case I40E_ERR_INVALID_FPM_FUNC_ID:
203 return "I40E_ERR_INVALID_FPM_FUNC_ID";
204 case I40E_ERR_QP_INVALID_MSG_SIZE:
205 return "I40E_ERR_QP_INVALID_MSG_SIZE";
206 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
207 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
208 case I40E_ERR_INVALID_FRAG_COUNT:
209 return "I40E_ERR_INVALID_FRAG_COUNT";
210 case I40E_ERR_QUEUE_EMPTY:
211 return "I40E_ERR_QUEUE_EMPTY";
212 case I40E_ERR_INVALID_ALIGNMENT:
213 return "I40E_ERR_INVALID_ALIGNMENT";
214 case I40E_ERR_FLUSHED_QUEUE:
215 return "I40E_ERR_FLUSHED_QUEUE";
216 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
217 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
218 case I40E_ERR_INVALID_IMM_DATA_SIZE:
219 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
220 case I40E_ERR_TIMEOUT:
221 return "I40E_ERR_TIMEOUT";
222 case I40E_ERR_OPCODE_MISMATCH:
223 return "I40E_ERR_OPCODE_MISMATCH";
224 case I40E_ERR_CQP_COMPL_ERROR:
225 return "I40E_ERR_CQP_COMPL_ERROR";
226 case I40E_ERR_INVALID_VF_ID:
227 return "I40E_ERR_INVALID_VF_ID";
228 case I40E_ERR_INVALID_HMCFN_ID:
229 return "I40E_ERR_INVALID_HMCFN_ID";
230 case I40E_ERR_BACKING_PAGE_ERROR:
231 return "I40E_ERR_BACKING_PAGE_ERROR";
232 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
233 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
234 case I40E_ERR_INVALID_PBLE_INDEX:
235 return "I40E_ERR_INVALID_PBLE_INDEX";
236 case I40E_ERR_INVALID_SD_INDEX:
237 return "I40E_ERR_INVALID_SD_INDEX";
238 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
239 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
240 case I40E_ERR_INVALID_SD_TYPE:
241 return "I40E_ERR_INVALID_SD_TYPE";
242 case I40E_ERR_MEMCPY_FAILED:
243 return "I40E_ERR_MEMCPY_FAILED";
244 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
245 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
246 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
247 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
248 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
249 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
250 case I40E_ERR_SRQ_ENABLED:
251 return "I40E_ERR_SRQ_ENABLED";
252 case I40E_ERR_ADMIN_QUEUE_ERROR:
253 return "I40E_ERR_ADMIN_QUEUE_ERROR";
254 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
255 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
256 case I40E_ERR_BUF_TOO_SHORT:
257 return "I40E_ERR_BUF_TOO_SHORT";
258 case I40E_ERR_ADMIN_QUEUE_FULL:
259 return "I40E_ERR_ADMIN_QUEUE_FULL";
260 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
261 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
262 case I40E_ERR_BAD_IWARP_CQE:
263 return "I40E_ERR_BAD_IWARP_CQE";
264 case I40E_ERR_NVM_BLANK_MODE:
265 return "I40E_ERR_NVM_BLANK_MODE";
266 case I40E_ERR_NOT_IMPLEMENTED:
267 return "I40E_ERR_NOT_IMPLEMENTED";
268 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
269 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
270 case I40E_ERR_DIAG_TEST_FAILED:
271 return "I40E_ERR_DIAG_TEST_FAILED";
272 case I40E_ERR_NOT_READY:
273 return "I40E_ERR_NOT_READY";
274 case I40E_NOT_SUPPORTED:
275 return "I40E_NOT_SUPPORTED";
276 case I40E_ERR_FIRMWARE_API_VERSION:
277 return "I40E_ERR_FIRMWARE_API_VERSION";
278 }
279
280 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
281 return hw->err_str;
282}
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293
294void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
295 void *buffer, u16 buf_len)
296{
297 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
298 u16 len = le16_to_cpu(aq_desc->datalen);
299 u8 *buf = (u8 *)buffer;
300 u16 i = 0;
301
302 if ((!(mask & hw->debug_mask)) || (desc == NULL))
303 return;
304
305 i40e_debug(hw, mask,
306 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
307 le16_to_cpu(aq_desc->opcode),
308 le16_to_cpu(aq_desc->flags),
309 le16_to_cpu(aq_desc->datalen),
310 le16_to_cpu(aq_desc->retval));
311 i40e_debug(hw, mask, "\tcookie (h,l) 0x%08X 0x%08X\n",
312 le32_to_cpu(aq_desc->cookie_high),
313 le32_to_cpu(aq_desc->cookie_low));
314 i40e_debug(hw, mask, "\tparam (0,1) 0x%08X 0x%08X\n",
315 le32_to_cpu(aq_desc->params.internal.param0),
316 le32_to_cpu(aq_desc->params.internal.param1));
317 i40e_debug(hw, mask, "\taddr (h,l) 0x%08X 0x%08X\n",
318 le32_to_cpu(aq_desc->params.external.addr_high),
319 le32_to_cpu(aq_desc->params.external.addr_low));
320
321 if ((buffer != NULL) && (aq_desc->datalen != 0)) {
322 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
323 if (buf_len < len)
324 len = buf_len;
325
326 for (i = 0; i < (len - 16); i += 16)
327 i40e_debug(hw, mask, "\t0x%04X %16ph\n", i, buf + i);
328
329 if (i < len)
330 i40e_debug(hw, mask, "\t0x%04X %*ph\n",
331 i, len - i, buf + i);
332 }
333}
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340
341bool i40e_check_asq_alive(struct i40e_hw *hw)
342{
343 if (hw->aq.asq.len)
344 return !!(rd32(hw, hw->aq.asq.len) &
345 I40E_PF_ATQLEN_ATQENABLE_MASK);
346 else
347 return false;
348}
349
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357
358i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
359 bool unloading)
360{
361 struct i40e_aq_desc desc;
362 struct i40e_aqc_queue_shutdown *cmd =
363 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
364 i40e_status status;
365
366 i40e_fill_default_direct_cmd_desc(&desc,
367 i40e_aqc_opc_queue_shutdown);
368
369 if (unloading)
370 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
371 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
372
373 return status;
374}
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387static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
388 u16 vsi_id, bool pf_lut,
389 u8 *lut, u16 lut_size,
390 bool set)
391{
392 i40e_status status;
393 struct i40e_aq_desc desc;
394 struct i40e_aqc_get_set_rss_lut *cmd_resp =
395 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
396
397 if (set)
398 i40e_fill_default_direct_cmd_desc(&desc,
399 i40e_aqc_opc_set_rss_lut);
400 else
401 i40e_fill_default_direct_cmd_desc(&desc,
402 i40e_aqc_opc_get_rss_lut);
403
404
405 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
406 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
407
408 cmd_resp->vsi_id =
409 cpu_to_le16((u16)((vsi_id <<
410 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
411 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
412 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
413
414 if (pf_lut)
415 cmd_resp->flags |= cpu_to_le16((u16)
416 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
417 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
418 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
419 else
420 cmd_resp->flags |= cpu_to_le16((u16)
421 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
422 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
423 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
424
425 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
426
427 return status;
428}
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440i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
441 bool pf_lut, u8 *lut, u16 lut_size)
442{
443 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
444 false);
445}
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457i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
458 bool pf_lut, u8 *lut, u16 lut_size)
459{
460 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
461}
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471
472static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
473 u16 vsi_id,
474 struct i40e_aqc_get_set_rss_key_data *key,
475 bool set)
476{
477 i40e_status status;
478 struct i40e_aq_desc desc;
479 struct i40e_aqc_get_set_rss_key *cmd_resp =
480 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
481 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
482
483 if (set)
484 i40e_fill_default_direct_cmd_desc(&desc,
485 i40e_aqc_opc_set_rss_key);
486 else
487 i40e_fill_default_direct_cmd_desc(&desc,
488 i40e_aqc_opc_get_rss_key);
489
490
491 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
492 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
493
494 cmd_resp->vsi_id =
495 cpu_to_le16((u16)((vsi_id <<
496 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
497 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
498 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
499
500 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
501
502 return status;
503}
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511
512i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
513 u16 vsi_id,
514 struct i40e_aqc_get_set_rss_key_data *key)
515{
516 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
517}
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526
527i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
528 u16 vsi_id,
529 struct i40e_aqc_get_set_rss_key_data *key)
530{
531 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
532}
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558#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
559 { PTYPE, \
560 1, \
561 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
562 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
563 I40E_RX_PTYPE_##OUTER_FRAG, \
564 I40E_RX_PTYPE_TUNNEL_##T, \
565 I40E_RX_PTYPE_TUNNEL_END_##TE, \
566 I40E_RX_PTYPE_##TEF, \
567 I40E_RX_PTYPE_INNER_PROT_##I, \
568 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
569
570#define I40E_PTT_UNUSED_ENTRY(PTYPE) \
571 { PTYPE, 0, 0, 0, 0, 0, 0, 0, 0, 0 }
572
573
574#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
575#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
576#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
577
578
579struct i40e_rx_ptype_decoded i40e_ptype_lookup[] = {
580
581 I40E_PTT_UNUSED_ENTRY(0),
582 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
583 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
584 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT_UNUSED_ENTRY(4),
586 I40E_PTT_UNUSED_ENTRY(5),
587 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
588 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT_UNUSED_ENTRY(8),
590 I40E_PTT_UNUSED_ENTRY(9),
591 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
592 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
593 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
601 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
602 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
603
604
605 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
606 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
607 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
608 I40E_PTT_UNUSED_ENTRY(25),
609 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
610 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
611 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
612
613
614 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
615 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
616 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
617 I40E_PTT_UNUSED_ENTRY(32),
618 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
619 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
620 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
621
622
623 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
624 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
625 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
626 I40E_PTT_UNUSED_ENTRY(39),
627 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
628 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
629 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
630
631
632 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
633
634
635 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
636 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
637 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
638 I40E_PTT_UNUSED_ENTRY(47),
639 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
640 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
641 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
642
643
644 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
645 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
646 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
647 I40E_PTT_UNUSED_ENTRY(54),
648 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
649 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
650 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
651
652
653 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
654
655
656 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
657 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
658 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
659 I40E_PTT_UNUSED_ENTRY(62),
660 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
661 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
662 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
663
664
665 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
666 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
667 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
668 I40E_PTT_UNUSED_ENTRY(69),
669 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
670 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
671 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
672
673
674 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
675
676
677 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
678 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
679 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
680 I40E_PTT_UNUSED_ENTRY(77),
681 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
682 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
683 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
684
685
686 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
687 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
688 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
689 I40E_PTT_UNUSED_ENTRY(84),
690 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
691 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
692 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
693
694
695 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
696 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
697 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY3),
698 I40E_PTT_UNUSED_ENTRY(91),
699 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
700 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
701 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
702
703
704 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
705 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
706 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
707 I40E_PTT_UNUSED_ENTRY(98),
708 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
709 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
710 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
711
712
713 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
714 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
715 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
716 I40E_PTT_UNUSED_ENTRY(105),
717 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
718 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
719 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
720
721
722 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
723
724
725 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
726 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
727 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
728 I40E_PTT_UNUSED_ENTRY(113),
729 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
730 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
731 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
732
733
734 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
735 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
736 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
737 I40E_PTT_UNUSED_ENTRY(120),
738 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
739 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
740 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
741
742
743 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
744
745
746 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
747 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
748 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
749 I40E_PTT_UNUSED_ENTRY(128),
750 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
751 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
752 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
753
754
755 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
756 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
757 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
758 I40E_PTT_UNUSED_ENTRY(135),
759 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
760 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
761 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
762
763
764 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
765
766
767 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
768 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
769 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
770 I40E_PTT_UNUSED_ENTRY(143),
771 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
772 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
773 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
774
775
776 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
777 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
778 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
779 I40E_PTT_UNUSED_ENTRY(150),
780 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
781 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
782 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
783
784
785 I40E_PTT_UNUSED_ENTRY(154),
786 I40E_PTT_UNUSED_ENTRY(155),
787 I40E_PTT_UNUSED_ENTRY(156),
788 I40E_PTT_UNUSED_ENTRY(157),
789 I40E_PTT_UNUSED_ENTRY(158),
790 I40E_PTT_UNUSED_ENTRY(159),
791
792 I40E_PTT_UNUSED_ENTRY(160),
793 I40E_PTT_UNUSED_ENTRY(161),
794 I40E_PTT_UNUSED_ENTRY(162),
795 I40E_PTT_UNUSED_ENTRY(163),
796 I40E_PTT_UNUSED_ENTRY(164),
797 I40E_PTT_UNUSED_ENTRY(165),
798 I40E_PTT_UNUSED_ENTRY(166),
799 I40E_PTT_UNUSED_ENTRY(167),
800 I40E_PTT_UNUSED_ENTRY(168),
801 I40E_PTT_UNUSED_ENTRY(169),
802
803 I40E_PTT_UNUSED_ENTRY(170),
804 I40E_PTT_UNUSED_ENTRY(171),
805 I40E_PTT_UNUSED_ENTRY(172),
806 I40E_PTT_UNUSED_ENTRY(173),
807 I40E_PTT_UNUSED_ENTRY(174),
808 I40E_PTT_UNUSED_ENTRY(175),
809 I40E_PTT_UNUSED_ENTRY(176),
810 I40E_PTT_UNUSED_ENTRY(177),
811 I40E_PTT_UNUSED_ENTRY(178),
812 I40E_PTT_UNUSED_ENTRY(179),
813
814 I40E_PTT_UNUSED_ENTRY(180),
815 I40E_PTT_UNUSED_ENTRY(181),
816 I40E_PTT_UNUSED_ENTRY(182),
817 I40E_PTT_UNUSED_ENTRY(183),
818 I40E_PTT_UNUSED_ENTRY(184),
819 I40E_PTT_UNUSED_ENTRY(185),
820 I40E_PTT_UNUSED_ENTRY(186),
821 I40E_PTT_UNUSED_ENTRY(187),
822 I40E_PTT_UNUSED_ENTRY(188),
823 I40E_PTT_UNUSED_ENTRY(189),
824
825 I40E_PTT_UNUSED_ENTRY(190),
826 I40E_PTT_UNUSED_ENTRY(191),
827 I40E_PTT_UNUSED_ENTRY(192),
828 I40E_PTT_UNUSED_ENTRY(193),
829 I40E_PTT_UNUSED_ENTRY(194),
830 I40E_PTT_UNUSED_ENTRY(195),
831 I40E_PTT_UNUSED_ENTRY(196),
832 I40E_PTT_UNUSED_ENTRY(197),
833 I40E_PTT_UNUSED_ENTRY(198),
834 I40E_PTT_UNUSED_ENTRY(199),
835
836 I40E_PTT_UNUSED_ENTRY(200),
837 I40E_PTT_UNUSED_ENTRY(201),
838 I40E_PTT_UNUSED_ENTRY(202),
839 I40E_PTT_UNUSED_ENTRY(203),
840 I40E_PTT_UNUSED_ENTRY(204),
841 I40E_PTT_UNUSED_ENTRY(205),
842 I40E_PTT_UNUSED_ENTRY(206),
843 I40E_PTT_UNUSED_ENTRY(207),
844 I40E_PTT_UNUSED_ENTRY(208),
845 I40E_PTT_UNUSED_ENTRY(209),
846
847 I40E_PTT_UNUSED_ENTRY(210),
848 I40E_PTT_UNUSED_ENTRY(211),
849 I40E_PTT_UNUSED_ENTRY(212),
850 I40E_PTT_UNUSED_ENTRY(213),
851 I40E_PTT_UNUSED_ENTRY(214),
852 I40E_PTT_UNUSED_ENTRY(215),
853 I40E_PTT_UNUSED_ENTRY(216),
854 I40E_PTT_UNUSED_ENTRY(217),
855 I40E_PTT_UNUSED_ENTRY(218),
856 I40E_PTT_UNUSED_ENTRY(219),
857
858 I40E_PTT_UNUSED_ENTRY(220),
859 I40E_PTT_UNUSED_ENTRY(221),
860 I40E_PTT_UNUSED_ENTRY(222),
861 I40E_PTT_UNUSED_ENTRY(223),
862 I40E_PTT_UNUSED_ENTRY(224),
863 I40E_PTT_UNUSED_ENTRY(225),
864 I40E_PTT_UNUSED_ENTRY(226),
865 I40E_PTT_UNUSED_ENTRY(227),
866 I40E_PTT_UNUSED_ENTRY(228),
867 I40E_PTT_UNUSED_ENTRY(229),
868
869 I40E_PTT_UNUSED_ENTRY(230),
870 I40E_PTT_UNUSED_ENTRY(231),
871 I40E_PTT_UNUSED_ENTRY(232),
872 I40E_PTT_UNUSED_ENTRY(233),
873 I40E_PTT_UNUSED_ENTRY(234),
874 I40E_PTT_UNUSED_ENTRY(235),
875 I40E_PTT_UNUSED_ENTRY(236),
876 I40E_PTT_UNUSED_ENTRY(237),
877 I40E_PTT_UNUSED_ENTRY(238),
878 I40E_PTT_UNUSED_ENTRY(239),
879
880 I40E_PTT_UNUSED_ENTRY(240),
881 I40E_PTT_UNUSED_ENTRY(241),
882 I40E_PTT_UNUSED_ENTRY(242),
883 I40E_PTT_UNUSED_ENTRY(243),
884 I40E_PTT_UNUSED_ENTRY(244),
885 I40E_PTT_UNUSED_ENTRY(245),
886 I40E_PTT_UNUSED_ENTRY(246),
887 I40E_PTT_UNUSED_ENTRY(247),
888 I40E_PTT_UNUSED_ENTRY(248),
889 I40E_PTT_UNUSED_ENTRY(249),
890
891 I40E_PTT_UNUSED_ENTRY(250),
892 I40E_PTT_UNUSED_ENTRY(251),
893 I40E_PTT_UNUSED_ENTRY(252),
894 I40E_PTT_UNUSED_ENTRY(253),
895 I40E_PTT_UNUSED_ENTRY(254),
896 I40E_PTT_UNUSED_ENTRY(255)
897};
898
899
900
901
902
903
904
905
906
907
908
909
910
911i40e_status i40e_init_shared_code(struct i40e_hw *hw)
912{
913 i40e_status status = 0;
914 u32 port, ari, func_rid;
915
916 i40e_set_mac_type(hw);
917
918 switch (hw->mac.type) {
919 case I40E_MAC_XL710:
920 case I40E_MAC_X722:
921 break;
922 default:
923 return I40E_ERR_DEVICE_NOT_SUPPORTED;
924 }
925
926 hw->phy.get_link_info = true;
927
928
929 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
930 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
931 hw->port = (u8)port;
932 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
933 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
934 func_rid = rd32(hw, I40E_PF_FUNC_RID);
935 if (ari)
936 hw->pf_id = (u8)(func_rid & 0xff);
937 else
938 hw->pf_id = (u8)(func_rid & 0x7);
939
940 if (hw->mac.type == I40E_MAC_X722)
941 hw->flags |= I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE;
942
943 status = i40e_init_nvm(hw);
944 return status;
945}
946
947
948
949
950
951
952
953
954static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
955 u16 *flags,
956 struct i40e_aqc_mac_address_read_data *addrs,
957 struct i40e_asq_cmd_details *cmd_details)
958{
959 struct i40e_aq_desc desc;
960 struct i40e_aqc_mac_address_read *cmd_data =
961 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
962 i40e_status status;
963
964 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
965 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
966
967 status = i40e_asq_send_command(hw, &desc, addrs,
968 sizeof(*addrs), cmd_details);
969 *flags = le16_to_cpu(cmd_data->command_flags);
970
971 return status;
972}
973
974
975
976
977
978
979
980
981i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
982 u16 flags, u8 *mac_addr,
983 struct i40e_asq_cmd_details *cmd_details)
984{
985 struct i40e_aq_desc desc;
986 struct i40e_aqc_mac_address_write *cmd_data =
987 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
988 i40e_status status;
989
990 i40e_fill_default_direct_cmd_desc(&desc,
991 i40e_aqc_opc_mac_address_write);
992 cmd_data->command_flags = cpu_to_le16(flags);
993 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
994 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
995 ((u32)mac_addr[3] << 16) |
996 ((u32)mac_addr[4] << 8) |
997 mac_addr[5]);
998
999 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1000
1001 return status;
1002}
1003
1004
1005
1006
1007
1008
1009
1010
1011i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1012{
1013 struct i40e_aqc_mac_address_read_data addrs;
1014 i40e_status status;
1015 u16 flags = 0;
1016
1017 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1018
1019 if (flags & I40E_AQC_LAN_ADDR_VALID)
1020 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
1021
1022 return status;
1023}
1024
1025
1026
1027
1028
1029
1030
1031
1032i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1033{
1034 struct i40e_aqc_mac_address_read_data addrs;
1035 i40e_status status;
1036 u16 flags = 0;
1037
1038 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1039 if (status)
1040 return status;
1041
1042 if (flags & I40E_AQC_PORT_ADDR_VALID)
1043 ether_addr_copy(mac_addr, addrs.port_mac);
1044 else
1045 status = I40E_ERR_INVALID_MAC_ADDR;
1046
1047 return status;
1048}
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
1060{
1061 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
1062 u32 reg_block = 0;
1063 u32 reg_val;
1064
1065 if (abs_queue_idx >= 128) {
1066 reg_block = abs_queue_idx / 128;
1067 abs_queue_idx %= 128;
1068 }
1069
1070 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1071 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1072 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1073
1074 if (enable)
1075 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
1076 else
1077 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1078
1079 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
1080}
1081#ifdef I40E_FCOE
1082
1083
1084
1085
1086
1087
1088
1089
1090i40e_status i40e_get_san_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
1091{
1092 struct i40e_aqc_mac_address_read_data addrs;
1093 i40e_status status;
1094 u16 flags = 0;
1095
1096 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
1097 if (status)
1098 return status;
1099
1100 if (flags & I40E_AQC_SAN_ADDR_VALID)
1101 ether_addr_copy(mac_addr, addrs.pf_san_mac);
1102 else
1103 status = I40E_ERR_INVALID_MAC_ADDR;
1104
1105 return status;
1106}
1107#endif
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
1118 u32 pba_num_size)
1119{
1120 i40e_status status = 0;
1121 u16 pba_word = 0;
1122 u16 pba_size = 0;
1123 u16 pba_ptr = 0;
1124 u16 i = 0;
1125
1126 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
1127 if (status || (pba_word != 0xFAFA)) {
1128 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
1129 return status;
1130 }
1131
1132 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
1133 if (status) {
1134 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
1135 return status;
1136 }
1137
1138 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
1139 if (status) {
1140 hw_dbg(hw, "Failed to read PBA Block size.\n");
1141 return status;
1142 }
1143
1144
1145
1146
1147 pba_size--;
1148 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1149 hw_dbg(hw, "Buffer to small for PBA data.\n");
1150 return I40E_ERR_PARAM;
1151 }
1152
1153 for (i = 0; i < pba_size; i++) {
1154 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1155 if (status) {
1156 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1157 return status;
1158 }
1159
1160 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1161 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1162 }
1163 pba_num[(pba_size * 2)] = '\0';
1164
1165 return status;
1166}
1167
1168
1169
1170
1171
1172static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1173{
1174 enum i40e_media_type media;
1175
1176 switch (hw->phy.link_info.phy_type) {
1177 case I40E_PHY_TYPE_10GBASE_SR:
1178 case I40E_PHY_TYPE_10GBASE_LR:
1179 case I40E_PHY_TYPE_1000BASE_SX:
1180 case I40E_PHY_TYPE_1000BASE_LX:
1181 case I40E_PHY_TYPE_40GBASE_SR4:
1182 case I40E_PHY_TYPE_40GBASE_LR4:
1183 media = I40E_MEDIA_TYPE_FIBER;
1184 break;
1185 case I40E_PHY_TYPE_100BASE_TX:
1186 case I40E_PHY_TYPE_1000BASE_T:
1187 case I40E_PHY_TYPE_10GBASE_T:
1188 media = I40E_MEDIA_TYPE_BASET;
1189 break;
1190 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1191 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1192 case I40E_PHY_TYPE_10GBASE_CR1:
1193 case I40E_PHY_TYPE_40GBASE_CR4:
1194 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1195 case I40E_PHY_TYPE_40GBASE_AOC:
1196 case I40E_PHY_TYPE_10GBASE_AOC:
1197 media = I40E_MEDIA_TYPE_DA;
1198 break;
1199 case I40E_PHY_TYPE_1000BASE_KX:
1200 case I40E_PHY_TYPE_10GBASE_KX4:
1201 case I40E_PHY_TYPE_10GBASE_KR:
1202 case I40E_PHY_TYPE_40GBASE_KR4:
1203 case I40E_PHY_TYPE_20GBASE_KR2:
1204 media = I40E_MEDIA_TYPE_BACKPLANE;
1205 break;
1206 case I40E_PHY_TYPE_SGMII:
1207 case I40E_PHY_TYPE_XAUI:
1208 case I40E_PHY_TYPE_XFI:
1209 case I40E_PHY_TYPE_XLAUI:
1210 case I40E_PHY_TYPE_XLPPI:
1211 default:
1212 media = I40E_MEDIA_TYPE_UNKNOWN;
1213 break;
1214 }
1215
1216 return media;
1217}
1218
1219#define I40E_PF_RESET_WAIT_COUNT_A0 200
1220#define I40E_PF_RESET_WAIT_COUNT 200
1221
1222
1223
1224
1225
1226
1227
1228i40e_status i40e_pf_reset(struct i40e_hw *hw)
1229{
1230 u32 cnt = 0;
1231 u32 cnt1 = 0;
1232 u32 reg = 0;
1233 u32 grst_del;
1234
1235
1236
1237
1238
1239 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1240 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1241 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1242
1243
1244
1245
1246 grst_del = grst_del * 20;
1247
1248 for (cnt = 0; cnt < grst_del; cnt++) {
1249 reg = rd32(hw, I40E_GLGEN_RSTAT);
1250 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1251 break;
1252 msleep(100);
1253 }
1254 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1255 hw_dbg(hw, "Global reset polling failed to complete.\n");
1256 return I40E_ERR_RESET_FAILED;
1257 }
1258
1259
1260 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1261 reg = rd32(hw, I40E_GLNVM_ULD);
1262 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1263 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1264 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1265 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1266 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1267 break;
1268 }
1269 usleep_range(10000, 20000);
1270 }
1271 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1272 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1273 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1274 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1275 return I40E_ERR_RESET_FAILED;
1276 }
1277
1278
1279
1280
1281 if (!cnt) {
1282 if (hw->revision_id == 0)
1283 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1284 else
1285 cnt = I40E_PF_RESET_WAIT_COUNT;
1286 reg = rd32(hw, I40E_PFGEN_CTRL);
1287 wr32(hw, I40E_PFGEN_CTRL,
1288 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1289 for (; cnt; cnt--) {
1290 reg = rd32(hw, I40E_PFGEN_CTRL);
1291 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1292 break;
1293 usleep_range(1000, 2000);
1294 }
1295 if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1296 hw_dbg(hw, "PF reset polling failed to complete.\n");
1297 return I40E_ERR_RESET_FAILED;
1298 }
1299 }
1300
1301 i40e_clear_pxe_mode(hw);
1302
1303 return 0;
1304}
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314void i40e_clear_hw(struct i40e_hw *hw)
1315{
1316 u32 num_queues, base_queue;
1317 u32 num_pf_int;
1318 u32 num_vf_int;
1319 u32 num_vfs;
1320 u32 i, j;
1321 u32 val;
1322 u32 eol = 0x7ff;
1323
1324
1325 val = rd32(hw, I40E_GLPCI_CNF2);
1326 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1327 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1328 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1329 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1330
1331 val = rd32(hw, I40E_PFLAN_QALLOC);
1332 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1333 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1334 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1335 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1336 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1337 num_queues = (j - base_queue) + 1;
1338 else
1339 num_queues = 0;
1340
1341 val = rd32(hw, I40E_PF_VT_PFALLOC);
1342 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1343 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1344 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1345 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1346 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1347 num_vfs = (j - i) + 1;
1348 else
1349 num_vfs = 0;
1350
1351
1352 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1353 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1354 for (i = 0; i < num_pf_int - 2; i++)
1355 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1356
1357
1358 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1359 wr32(hw, I40E_PFINT_LNKLST0, val);
1360 for (i = 0; i < num_pf_int - 2; i++)
1361 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1362 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1363 for (i = 0; i < num_vfs; i++)
1364 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1365 for (i = 0; i < num_vf_int - 2; i++)
1366 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1367
1368
1369 for (i = 0; i < num_queues; i++) {
1370 u32 abs_queue_idx = base_queue + i;
1371 u32 reg_block = 0;
1372
1373 if (abs_queue_idx >= 128) {
1374 reg_block = abs_queue_idx / 128;
1375 abs_queue_idx %= 128;
1376 }
1377
1378 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1379 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1380 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1381 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1382
1383 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1384 }
1385 udelay(400);
1386
1387
1388 for (i = 0; i < num_queues; i++) {
1389 wr32(hw, I40E_QINT_TQCTL(i), 0);
1390 wr32(hw, I40E_QTX_ENA(i), 0);
1391 wr32(hw, I40E_QINT_RQCTL(i), 0);
1392 wr32(hw, I40E_QRX_ENA(i), 0);
1393 }
1394
1395
1396 udelay(50);
1397}
1398
1399
1400
1401
1402
1403
1404
1405
1406void i40e_clear_pxe_mode(struct i40e_hw *hw)
1407{
1408 u32 reg;
1409
1410 if (i40e_check_asq_alive(hw))
1411 i40e_aq_clear_pxe_mode(hw, NULL);
1412
1413
1414 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1415
1416 if (hw->revision_id == 0) {
1417
1418 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1419 } else {
1420 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1421 }
1422}
1423
1424
1425
1426
1427
1428
1429
1430
1431static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1432{
1433 u32 gpio_val = 0;
1434 u32 port;
1435
1436 if (!hw->func_caps.led[idx])
1437 return 0;
1438
1439 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1440 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1441 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1442
1443
1444
1445
1446 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1447 (port != hw->port))
1448 return 0;
1449
1450 return gpio_val;
1451}
1452
1453#define I40E_COMBINED_ACTIVITY 0xA
1454#define I40E_FILTER_ACTIVITY 0xE
1455#define I40E_LINK_ACTIVITY 0xC
1456#define I40E_MAC_ACTIVITY 0xD
1457#define I40E_LED0 22
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468u32 i40e_led_get(struct i40e_hw *hw)
1469{
1470 u32 current_mode = 0;
1471 u32 mode = 0;
1472 int i;
1473
1474
1475
1476
1477 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1478 u32 gpio_val = i40e_led_is_mine(hw, i);
1479
1480 if (!gpio_val)
1481 continue;
1482
1483
1484
1485
1486 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1487 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1488 switch (current_mode) {
1489 case I40E_COMBINED_ACTIVITY:
1490 case I40E_FILTER_ACTIVITY:
1491 case I40E_MAC_ACTIVITY:
1492 continue;
1493 default:
1494 break;
1495 }
1496
1497 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1498 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1499 break;
1500 }
1501
1502 return mode;
1503}
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1515{
1516 u32 current_mode = 0;
1517 int i;
1518
1519 if (mode & 0xfffffff0)
1520 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1521
1522
1523
1524
1525 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1526 u32 gpio_val = i40e_led_is_mine(hw, i);
1527
1528 if (!gpio_val)
1529 continue;
1530
1531
1532
1533
1534 current_mode = ((gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK)
1535 >> I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT);
1536 switch (current_mode) {
1537 case I40E_COMBINED_ACTIVITY:
1538 case I40E_FILTER_ACTIVITY:
1539 case I40E_MAC_ACTIVITY:
1540 continue;
1541 default:
1542 break;
1543 }
1544
1545 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1546
1547 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1548 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1549
1550 if (mode == I40E_LINK_ACTIVITY)
1551 blink = false;
1552
1553 if (blink)
1554 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1555 else
1556 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1557
1558 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1559 break;
1560 }
1561}
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1576 bool qualified_modules, bool report_init,
1577 struct i40e_aq_get_phy_abilities_resp *abilities,
1578 struct i40e_asq_cmd_details *cmd_details)
1579{
1580 struct i40e_aq_desc desc;
1581 i40e_status status;
1582 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1583
1584 if (!abilities)
1585 return I40E_ERR_PARAM;
1586
1587 i40e_fill_default_direct_cmd_desc(&desc,
1588 i40e_aqc_opc_get_phy_abilities);
1589
1590 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1591 if (abilities_size > I40E_AQ_LARGE_BUF)
1592 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1593
1594 if (qualified_modules)
1595 desc.params.external.param0 |=
1596 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1597
1598 if (report_init)
1599 desc.params.external.param0 |=
1600 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1601
1602 status = i40e_asq_send_command(hw, &desc, abilities, abilities_size,
1603 cmd_details);
1604
1605 if (hw->aq.asq_last_status == I40E_AQ_RC_EIO)
1606 status = I40E_ERR_UNKNOWN_PHY;
1607
1608 if (report_init)
1609 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1610
1611 return status;
1612}
1613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1627 struct i40e_aq_set_phy_config *config,
1628 struct i40e_asq_cmd_details *cmd_details)
1629{
1630 struct i40e_aq_desc desc;
1631 struct i40e_aq_set_phy_config *cmd =
1632 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1633 enum i40e_status_code status;
1634
1635 if (!config)
1636 return I40E_ERR_PARAM;
1637
1638 i40e_fill_default_direct_cmd_desc(&desc,
1639 i40e_aqc_opc_set_phy_config);
1640
1641 *cmd = *config;
1642
1643 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1644
1645 return status;
1646}
1647
1648
1649
1650
1651
1652
1653
1654enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1655 bool atomic_restart)
1656{
1657 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1658 struct i40e_aq_get_phy_abilities_resp abilities;
1659 struct i40e_aq_set_phy_config config;
1660 enum i40e_status_code status;
1661 u8 pause_mask = 0x0;
1662
1663 *aq_failures = 0x0;
1664
1665 switch (fc_mode) {
1666 case I40E_FC_FULL:
1667 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1668 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1669 break;
1670 case I40E_FC_RX_PAUSE:
1671 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1672 break;
1673 case I40E_FC_TX_PAUSE:
1674 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1675 break;
1676 default:
1677 break;
1678 }
1679
1680
1681 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1682 NULL);
1683 if (status) {
1684 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1685 return status;
1686 }
1687
1688 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1689
1690 config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1691 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1692
1693 config.abilities |= pause_mask;
1694
1695 if (config.abilities != abilities.abilities) {
1696
1697 if (atomic_restart)
1698 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1699
1700 config.phy_type = abilities.phy_type;
1701 config.link_speed = abilities.link_speed;
1702 config.eee_capability = abilities.eee_capability;
1703 config.eeer = abilities.eeer_val;
1704 config.low_power_ctrl = abilities.d3_lpan;
1705 status = i40e_aq_set_phy_config(hw, &config, NULL);
1706
1707 if (status)
1708 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1709 }
1710
1711 status = i40e_update_link_info(hw);
1712 if (status) {
1713
1714
1715
1716
1717 msleep(1000);
1718 status = i40e_update_link_info(hw);
1719 }
1720 if (status)
1721 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1722
1723 return status;
1724}
1725
1726
1727
1728
1729
1730
1731
1732
1733i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1734 struct i40e_asq_cmd_details *cmd_details)
1735{
1736 i40e_status status;
1737 struct i40e_aq_desc desc;
1738 struct i40e_aqc_clear_pxe *cmd =
1739 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1740
1741 i40e_fill_default_direct_cmd_desc(&desc,
1742 i40e_aqc_opc_clear_pxe_mode);
1743
1744 cmd->rx_cnt = 0x2;
1745
1746 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1747
1748 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1749
1750 return status;
1751}
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1762 bool enable_link,
1763 struct i40e_asq_cmd_details *cmd_details)
1764{
1765 struct i40e_aq_desc desc;
1766 struct i40e_aqc_set_link_restart_an *cmd =
1767 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1768 i40e_status status;
1769
1770 i40e_fill_default_direct_cmd_desc(&desc,
1771 i40e_aqc_opc_set_link_restart_an);
1772
1773 cmd->command = I40E_AQ_PHY_RESTART_AN;
1774 if (enable_link)
1775 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1776 else
1777 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1778
1779 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1780
1781 return status;
1782}
1783
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1794 bool enable_lse, struct i40e_link_status *link,
1795 struct i40e_asq_cmd_details *cmd_details)
1796{
1797 struct i40e_aq_desc desc;
1798 struct i40e_aqc_get_link_status *resp =
1799 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1800 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1801 i40e_status status;
1802 bool tx_pause, rx_pause;
1803 u16 command_flags;
1804
1805 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1806
1807 if (enable_lse)
1808 command_flags = I40E_AQ_LSE_ENABLE;
1809 else
1810 command_flags = I40E_AQ_LSE_DISABLE;
1811 resp->command_flags = cpu_to_le16(command_flags);
1812
1813 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1814
1815 if (status)
1816 goto aq_get_link_info_exit;
1817
1818
1819 hw->phy.link_info_old = *hw_link_info;
1820
1821
1822 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1823 hw->phy.media_type = i40e_get_media_type(hw);
1824 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1825 hw_link_info->link_info = resp->link_info;
1826 hw_link_info->an_info = resp->an_info;
1827 hw_link_info->ext_info = resp->ext_info;
1828 hw_link_info->loopback = resp->loopback;
1829 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1830 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1831
1832
1833 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1834 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1835 if (tx_pause & rx_pause)
1836 hw->fc.current_mode = I40E_FC_FULL;
1837 else if (tx_pause)
1838 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1839 else if (rx_pause)
1840 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1841 else
1842 hw->fc.current_mode = I40E_FC_NONE;
1843
1844 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1845 hw_link_info->crc_enable = true;
1846 else
1847 hw_link_info->crc_enable = false;
1848
1849 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_ENABLE))
1850 hw_link_info->lse_enable = true;
1851 else
1852 hw_link_info->lse_enable = false;
1853
1854 if ((hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1855 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1856 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1857
1858
1859 if (link)
1860 *link = *hw_link_info;
1861
1862
1863 hw->phy.get_link_info = false;
1864
1865aq_get_link_info_exit:
1866 return status;
1867}
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1878 u16 mask,
1879 struct i40e_asq_cmd_details *cmd_details)
1880{
1881 struct i40e_aq_desc desc;
1882 struct i40e_aqc_set_phy_int_mask *cmd =
1883 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1884 i40e_status status;
1885
1886 i40e_fill_default_direct_cmd_desc(&desc,
1887 i40e_aqc_opc_set_phy_int_mask);
1888
1889 cmd->event_mask = cpu_to_le16(mask);
1890
1891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1892
1893 return status;
1894}
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904enum i40e_status_code i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1905 struct i40e_asq_cmd_details *cmd_details)
1906{
1907 struct i40e_aq_desc desc;
1908 struct i40e_aqc_set_phy_debug *cmd =
1909 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1910 enum i40e_status_code status;
1911
1912 i40e_fill_default_direct_cmd_desc(&desc,
1913 i40e_aqc_opc_set_phy_debug);
1914
1915 cmd->command_flags = cmd_flags;
1916
1917 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1918
1919 return status;
1920}
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1931 struct i40e_vsi_context *vsi_ctx,
1932 struct i40e_asq_cmd_details *cmd_details)
1933{
1934 struct i40e_aq_desc desc;
1935 struct i40e_aqc_add_get_update_vsi *cmd =
1936 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1937 struct i40e_aqc_add_get_update_vsi_completion *resp =
1938 (struct i40e_aqc_add_get_update_vsi_completion *)
1939 &desc.params.raw;
1940 i40e_status status;
1941
1942 i40e_fill_default_direct_cmd_desc(&desc,
1943 i40e_aqc_opc_add_vsi);
1944
1945 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1946 cmd->connection_type = vsi_ctx->connection_type;
1947 cmd->vf_id = vsi_ctx->vf_num;
1948 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1949
1950 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1951
1952 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1953 sizeof(vsi_ctx->info), cmd_details);
1954
1955 if (status)
1956 goto aq_add_vsi_exit;
1957
1958 vsi_ctx->seid = le16_to_cpu(resp->seid);
1959 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1960 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1961 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1962
1963aq_add_vsi_exit:
1964 return status;
1965}
1966
1967
1968
1969
1970
1971
1972
1973
1974i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1975 u16 seid, bool set,
1976 struct i40e_asq_cmd_details *cmd_details)
1977{
1978 struct i40e_aq_desc desc;
1979 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1980 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1981 i40e_status status;
1982 u16 flags = 0;
1983
1984 i40e_fill_default_direct_cmd_desc(&desc,
1985 i40e_aqc_opc_set_vsi_promiscuous_modes);
1986
1987 if (set) {
1988 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1989 if (((hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver >= 5)) ||
1990 (hw->aq.api_maj_ver > 1))
1991 flags |= I40E_AQC_SET_VSI_PROMISC_TX;
1992 }
1993
1994 cmd->promiscuous_flags = cpu_to_le16(flags);
1995
1996 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
1997 if (((hw->aq.api_maj_ver >= 1) && (hw->aq.api_min_ver >= 5)) ||
1998 (hw->aq.api_maj_ver > 1))
1999 cmd->valid_flags |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_TX);
2000
2001 cmd->seid = cpu_to_le16(seid);
2002 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2003
2004 return status;
2005}
2006
2007
2008
2009
2010
2011
2012
2013
2014i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2015 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2016{
2017 struct i40e_aq_desc desc;
2018 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2019 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2020 i40e_status status;
2021 u16 flags = 0;
2022
2023 i40e_fill_default_direct_cmd_desc(&desc,
2024 i40e_aqc_opc_set_vsi_promiscuous_modes);
2025
2026 if (set)
2027 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2028
2029 cmd->promiscuous_flags = cpu_to_le16(flags);
2030
2031 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2032
2033 cmd->seid = cpu_to_le16(seid);
2034 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2035
2036 return status;
2037}
2038
2039
2040
2041
2042
2043
2044
2045
2046
2047
2048i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2049 u16 seid, bool set_filter,
2050 struct i40e_asq_cmd_details *cmd_details)
2051{
2052 struct i40e_aq_desc desc;
2053 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2054 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2055 i40e_status status;
2056
2057 i40e_fill_default_direct_cmd_desc(&desc,
2058 i40e_aqc_opc_set_vsi_promiscuous_modes);
2059
2060 if (set_filter)
2061 cmd->promiscuous_flags
2062 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2063 else
2064 cmd->promiscuous_flags
2065 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2066
2067 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2068 cmd->seid = cpu_to_le16(seid);
2069 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2070
2071 return status;
2072}
2073
2074
2075
2076
2077
2078
2079
2080
2081i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2082 u16 seid, bool enable,
2083 struct i40e_asq_cmd_details *cmd_details)
2084{
2085 struct i40e_aq_desc desc;
2086 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2087 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2088 i40e_status status;
2089 u16 flags = 0;
2090
2091 i40e_fill_default_direct_cmd_desc(&desc,
2092 i40e_aqc_opc_set_vsi_promiscuous_modes);
2093 if (enable)
2094 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2095
2096 cmd->promiscuous_flags = cpu_to_le16(flags);
2097 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2098 cmd->seid = cpu_to_le16(seid);
2099
2100 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2101
2102 return status;
2103}
2104
2105
2106
2107
2108
2109
2110
2111i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2112 struct i40e_vsi_context *vsi_ctx,
2113 struct i40e_asq_cmd_details *cmd_details)
2114{
2115 struct i40e_aq_desc desc;
2116 struct i40e_aqc_add_get_update_vsi *cmd =
2117 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2118 struct i40e_aqc_add_get_update_vsi_completion *resp =
2119 (struct i40e_aqc_add_get_update_vsi_completion *)
2120 &desc.params.raw;
2121 i40e_status status;
2122
2123 i40e_fill_default_direct_cmd_desc(&desc,
2124 i40e_aqc_opc_get_vsi_parameters);
2125
2126 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2127
2128 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2129
2130 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2131 sizeof(vsi_ctx->info), NULL);
2132
2133 if (status)
2134 goto aq_get_vsi_params_exit;
2135
2136 vsi_ctx->seid = le16_to_cpu(resp->seid);
2137 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2138 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2139 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2140
2141aq_get_vsi_params_exit:
2142 return status;
2143}
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2154 struct i40e_vsi_context *vsi_ctx,
2155 struct i40e_asq_cmd_details *cmd_details)
2156{
2157 struct i40e_aq_desc desc;
2158 struct i40e_aqc_add_get_update_vsi *cmd =
2159 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2160 i40e_status status;
2161
2162 i40e_fill_default_direct_cmd_desc(&desc,
2163 i40e_aqc_opc_update_vsi_parameters);
2164 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2165
2166 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2167
2168 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2169 sizeof(vsi_ctx->info), cmd_details);
2170
2171 return status;
2172}
2173
2174
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2185 struct i40e_aqc_get_switch_config_resp *buf,
2186 u16 buf_size, u16 *start_seid,
2187 struct i40e_asq_cmd_details *cmd_details)
2188{
2189 struct i40e_aq_desc desc;
2190 struct i40e_aqc_switch_seid *scfg =
2191 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2192 i40e_status status;
2193
2194 i40e_fill_default_direct_cmd_desc(&desc,
2195 i40e_aqc_opc_get_switch_config);
2196 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2197 if (buf_size > I40E_AQ_LARGE_BUF)
2198 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2199 scfg->seid = cpu_to_le16(*start_seid);
2200
2201 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2202 *start_seid = le16_to_cpu(scfg->seid);
2203
2204 return status;
2205}
2206
2207
2208
2209
2210
2211
2212
2213
2214
2215
2216
2217
2218
2219i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2220 u16 *fw_major_version, u16 *fw_minor_version,
2221 u32 *fw_build,
2222 u16 *api_major_version, u16 *api_minor_version,
2223 struct i40e_asq_cmd_details *cmd_details)
2224{
2225 struct i40e_aq_desc desc;
2226 struct i40e_aqc_get_version *resp =
2227 (struct i40e_aqc_get_version *)&desc.params.raw;
2228 i40e_status status;
2229
2230 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2231
2232 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2233
2234 if (!status) {
2235 if (fw_major_version)
2236 *fw_major_version = le16_to_cpu(resp->fw_major);
2237 if (fw_minor_version)
2238 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2239 if (fw_build)
2240 *fw_build = le32_to_cpu(resp->fw_build);
2241 if (api_major_version)
2242 *api_major_version = le16_to_cpu(resp->api_major);
2243 if (api_minor_version)
2244 *api_minor_version = le16_to_cpu(resp->api_minor);
2245 }
2246
2247 return status;
2248}
2249
2250
2251
2252
2253
2254
2255
2256
2257
2258i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2259 struct i40e_driver_version *dv,
2260 struct i40e_asq_cmd_details *cmd_details)
2261{
2262 struct i40e_aq_desc desc;
2263 struct i40e_aqc_driver_version *cmd =
2264 (struct i40e_aqc_driver_version *)&desc.params.raw;
2265 i40e_status status;
2266 u16 len;
2267
2268 if (dv == NULL)
2269 return I40E_ERR_PARAM;
2270
2271 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2272
2273 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2274 cmd->driver_major_ver = dv->major_version;
2275 cmd->driver_minor_ver = dv->minor_version;
2276 cmd->driver_build_ver = dv->build_version;
2277 cmd->driver_subbuild_ver = dv->subbuild_version;
2278
2279 len = 0;
2280 while (len < sizeof(dv->driver_string) &&
2281 (dv->driver_string[len] < 0x80) &&
2282 dv->driver_string[len])
2283 len++;
2284 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2285 len, cmd_details);
2286
2287 return status;
2288}
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2301{
2302 i40e_status status = 0;
2303
2304 if (hw->phy.get_link_info) {
2305 status = i40e_update_link_info(hw);
2306
2307 if (status)
2308 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2309 status);
2310 }
2311
2312 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2313
2314 return status;
2315}
2316
2317
2318
2319
2320
2321i40e_status i40e_update_link_info(struct i40e_hw *hw)
2322{
2323 struct i40e_aq_get_phy_abilities_resp abilities;
2324 i40e_status status = 0;
2325
2326 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2327 if (status)
2328 return status;
2329
2330 if (hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) {
2331 status = i40e_aq_get_phy_capabilities(hw, false, false,
2332 &abilities, NULL);
2333 if (status)
2334 return status;
2335
2336 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2337 sizeof(hw->phy.link_info.module_type));
2338 }
2339
2340 return status;
2341}
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2358 u16 downlink_seid, u8 enabled_tc,
2359 bool default_port, u16 *veb_seid,
2360 bool enable_stats,
2361 struct i40e_asq_cmd_details *cmd_details)
2362{
2363 struct i40e_aq_desc desc;
2364 struct i40e_aqc_add_veb *cmd =
2365 (struct i40e_aqc_add_veb *)&desc.params.raw;
2366 struct i40e_aqc_add_veb_completion *resp =
2367 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2368 i40e_status status;
2369 u16 veb_flags = 0;
2370
2371
2372 if (!!uplink_seid != !!downlink_seid)
2373 return I40E_ERR_PARAM;
2374
2375 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2376
2377 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2378 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2379 cmd->enable_tcs = enabled_tc;
2380 if (!uplink_seid)
2381 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2382 if (default_port)
2383 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2384 else
2385 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2386
2387
2388 if (!enable_stats)
2389 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2390
2391 cmd->veb_flags = cpu_to_le16(veb_flags);
2392
2393 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2394
2395 if (!status && veb_seid)
2396 *veb_seid = le16_to_cpu(resp->veb_seid);
2397
2398 return status;
2399}
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
2413
2414
2415i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2416 u16 veb_seid, u16 *switch_id,
2417 bool *floating, u16 *statistic_index,
2418 u16 *vebs_used, u16 *vebs_free,
2419 struct i40e_asq_cmd_details *cmd_details)
2420{
2421 struct i40e_aq_desc desc;
2422 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2423 (struct i40e_aqc_get_veb_parameters_completion *)
2424 &desc.params.raw;
2425 i40e_status status;
2426
2427 if (veb_seid == 0)
2428 return I40E_ERR_PARAM;
2429
2430 i40e_fill_default_direct_cmd_desc(&desc,
2431 i40e_aqc_opc_get_veb_parameters);
2432 cmd_resp->seid = cpu_to_le16(veb_seid);
2433
2434 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2435 if (status)
2436 goto get_veb_exit;
2437
2438 if (switch_id)
2439 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2440 if (statistic_index)
2441 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2442 if (vebs_used)
2443 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2444 if (vebs_free)
2445 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2446 if (floating) {
2447 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2448
2449 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2450 *floating = true;
2451 else
2452 *floating = false;
2453 }
2454
2455get_veb_exit:
2456 return status;
2457}
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467
2468
2469i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2470 struct i40e_aqc_add_macvlan_element_data *mv_list,
2471 u16 count, struct i40e_asq_cmd_details *cmd_details)
2472{
2473 struct i40e_aq_desc desc;
2474 struct i40e_aqc_macvlan *cmd =
2475 (struct i40e_aqc_macvlan *)&desc.params.raw;
2476 i40e_status status;
2477 u16 buf_size;
2478 int i;
2479
2480 if (count == 0 || !mv_list || !hw)
2481 return I40E_ERR_PARAM;
2482
2483 buf_size = count * sizeof(*mv_list);
2484
2485
2486 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2487 cmd->num_addresses = cpu_to_le16(count);
2488 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2489 cmd->seid[1] = 0;
2490 cmd->seid[2] = 0;
2491
2492 for (i = 0; i < count; i++)
2493 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2494 mv_list[i].flags |=
2495 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2496
2497 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2498 if (buf_size > I40E_AQ_LARGE_BUF)
2499 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2500
2501 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2502 cmd_details);
2503
2504 return status;
2505}
2506
2507
2508
2509
2510
2511
2512
2513
2514
2515
2516
2517i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2518 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2519 u16 count, struct i40e_asq_cmd_details *cmd_details)
2520{
2521 struct i40e_aq_desc desc;
2522 struct i40e_aqc_macvlan *cmd =
2523 (struct i40e_aqc_macvlan *)&desc.params.raw;
2524 i40e_status status;
2525 u16 buf_size;
2526
2527 if (count == 0 || !mv_list || !hw)
2528 return I40E_ERR_PARAM;
2529
2530 buf_size = count * sizeof(*mv_list);
2531
2532
2533 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2534 cmd->num_addresses = cpu_to_le16(count);
2535 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2536 cmd->seid[1] = 0;
2537 cmd->seid[2] = 0;
2538
2539 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2540 if (buf_size > I40E_AQ_LARGE_BUF)
2541 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2542
2543 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2544 cmd_details);
2545
2546 return status;
2547}
2548
2549
2550
2551
2552
2553
2554
2555
2556
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2567 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2568 u16 count, __le16 *mr_list,
2569 struct i40e_asq_cmd_details *cmd_details,
2570 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2571{
2572 struct i40e_aq_desc desc;
2573 struct i40e_aqc_add_delete_mirror_rule *cmd =
2574 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2575 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2576 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2577 i40e_status status;
2578 u16 buf_size;
2579
2580 buf_size = count * sizeof(*mr_list);
2581
2582
2583 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2584 cmd->seid = cpu_to_le16(sw_seid);
2585 cmd->rule_type = cpu_to_le16(rule_type &
2586 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2587 cmd->num_entries = cpu_to_le16(count);
2588
2589 cmd->destination = cpu_to_le16(id);
2590 if (mr_list) {
2591 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2592 I40E_AQ_FLAG_RD));
2593 if (buf_size > I40E_AQ_LARGE_BUF)
2594 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2595 }
2596
2597 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2598 cmd_details);
2599 if (!status ||
2600 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2601 if (rule_id)
2602 *rule_id = le16_to_cpu(resp->rule_id);
2603 if (rules_used)
2604 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2605 if (rules_free)
2606 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2607 }
2608 return status;
2609}
2610
2611
2612
2613
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623
2624
2625
2626i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2627 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2628 struct i40e_asq_cmd_details *cmd_details,
2629 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2630{
2631 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2632 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2633 if (count == 0 || !mr_list)
2634 return I40E_ERR_PARAM;
2635 }
2636
2637 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2638 rule_type, dest_vsi, count, mr_list,
2639 cmd_details, rule_id, rules_used, rules_free);
2640}
2641
2642
2643
2644
2645
2646
2647
2648
2649
2650
2651
2652
2653
2654
2655
2656
2657i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2658 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2659 struct i40e_asq_cmd_details *cmd_details,
2660 u16 *rules_used, u16 *rules_free)
2661{
2662
2663 if (rule_type != I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2664 if (!rule_id)
2665 return I40E_ERR_PARAM;
2666 } else {
2667
2668
2669
2670
2671 if (count == 0 || !mr_list)
2672 return I40E_ERR_PARAM;
2673 }
2674
2675 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2676 rule_type, rule_id, count, mr_list,
2677 cmd_details, NULL, rules_used, rules_free);
2678}
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690
2691
2692i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2693 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2694 struct i40e_asq_cmd_details *cmd_details)
2695{
2696 struct i40e_aq_desc desc;
2697 struct i40e_aqc_pf_vf_message *cmd =
2698 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2699 i40e_status status;
2700
2701 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2702 cmd->id = cpu_to_le32(vfid);
2703 desc.cookie_high = cpu_to_le32(v_opcode);
2704 desc.cookie_low = cpu_to_le32(v_retval);
2705 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2706 if (msglen) {
2707 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2708 I40E_AQ_FLAG_RD));
2709 if (msglen > I40E_AQ_LARGE_BUF)
2710 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2711 desc.datalen = cpu_to_le16(msglen);
2712 }
2713 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2714
2715 return status;
2716}
2717
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2728 u32 reg_addr, u64 *reg_val,
2729 struct i40e_asq_cmd_details *cmd_details)
2730{
2731 struct i40e_aq_desc desc;
2732 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2733 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2734 i40e_status status;
2735
2736 if (reg_val == NULL)
2737 return I40E_ERR_PARAM;
2738
2739 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2740
2741 cmd_resp->address = cpu_to_le32(reg_addr);
2742
2743 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2744
2745 if (!status) {
2746 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2747 (u64)le32_to_cpu(cmd_resp->value_low);
2748 }
2749
2750 return status;
2751}
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2763 u32 reg_addr, u64 reg_val,
2764 struct i40e_asq_cmd_details *cmd_details)
2765{
2766 struct i40e_aq_desc desc;
2767 struct i40e_aqc_debug_reg_read_write *cmd =
2768 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2769 i40e_status status;
2770
2771 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2772
2773 cmd->address = cpu_to_le32(reg_addr);
2774 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2775 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2776
2777 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2778
2779 return status;
2780}
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791i40e_status i40e_aq_set_hmc_resource_profile(struct i40e_hw *hw,
2792 enum i40e_aq_hmc_profile profile,
2793 u8 pe_vf_enabled_count,
2794 struct i40e_asq_cmd_details *cmd_details)
2795{
2796 struct i40e_aq_desc desc;
2797 struct i40e_aq_get_set_hmc_resource_profile *cmd =
2798 (struct i40e_aq_get_set_hmc_resource_profile *)&desc.params.raw;
2799 i40e_status status;
2800
2801 i40e_fill_default_direct_cmd_desc(&desc,
2802 i40e_aqc_opc_set_hmc_resource_profile);
2803
2804 cmd->pm_profile = (u8)profile;
2805 cmd->pe_vf_enabled = pe_vf_enabled_count;
2806
2807 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2808
2809 return status;
2810}
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2824 enum i40e_aq_resources_ids resource,
2825 enum i40e_aq_resource_access_type access,
2826 u8 sdp_number, u64 *timeout,
2827 struct i40e_asq_cmd_details *cmd_details)
2828{
2829 struct i40e_aq_desc desc;
2830 struct i40e_aqc_request_resource *cmd_resp =
2831 (struct i40e_aqc_request_resource *)&desc.params.raw;
2832 i40e_status status;
2833
2834 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2835
2836 cmd_resp->resource_id = cpu_to_le16(resource);
2837 cmd_resp->access_type = cpu_to_le16(access);
2838 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2839
2840 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2841
2842
2843
2844
2845
2846
2847 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2848 *timeout = le32_to_cpu(cmd_resp->timeout);
2849
2850 return status;
2851}
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
2863 enum i40e_aq_resources_ids resource,
2864 u8 sdp_number,
2865 struct i40e_asq_cmd_details *cmd_details)
2866{
2867 struct i40e_aq_desc desc;
2868 struct i40e_aqc_request_resource *cmd =
2869 (struct i40e_aqc_request_resource *)&desc.params.raw;
2870 i40e_status status;
2871
2872 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
2873
2874 cmd->resource_id = cpu_to_le16(resource);
2875 cmd->resource_number = cpu_to_le32(sdp_number);
2876
2877 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2878
2879 return status;
2880}
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
2895 u32 offset, u16 length, void *data,
2896 bool last_command,
2897 struct i40e_asq_cmd_details *cmd_details)
2898{
2899 struct i40e_aq_desc desc;
2900 struct i40e_aqc_nvm_update *cmd =
2901 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2902 i40e_status status;
2903
2904
2905 if (offset & 0xFF000000) {
2906 status = I40E_ERR_PARAM;
2907 goto i40e_aq_read_nvm_exit;
2908 }
2909
2910 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
2911
2912
2913 if (last_command)
2914 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2915 cmd->module_pointer = module_pointer;
2916 cmd->offset = cpu_to_le32(offset);
2917 cmd->length = cpu_to_le16(length);
2918
2919 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2920 if (length > I40E_AQ_LARGE_BUF)
2921 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2922
2923 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
2924
2925i40e_aq_read_nvm_exit:
2926 return status;
2927}
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
2941 u32 offset, u16 length, bool last_command,
2942 struct i40e_asq_cmd_details *cmd_details)
2943{
2944 struct i40e_aq_desc desc;
2945 struct i40e_aqc_nvm_update *cmd =
2946 (struct i40e_aqc_nvm_update *)&desc.params.raw;
2947 i40e_status status;
2948
2949
2950 if (offset & 0xFF000000) {
2951 status = I40E_ERR_PARAM;
2952 goto i40e_aq_erase_nvm_exit;
2953 }
2954
2955 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
2956
2957
2958 if (last_command)
2959 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
2960 cmd->module_pointer = module_pointer;
2961 cmd->offset = cpu_to_le32(offset);
2962 cmd->length = cpu_to_le16(length);
2963
2964 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2965
2966i40e_aq_erase_nvm_exit:
2967 return status;
2968}
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
2980 u32 cap_count,
2981 enum i40e_admin_queue_opc list_type_opc)
2982{
2983 struct i40e_aqc_list_capabilities_element_resp *cap;
2984 u32 valid_functions, num_functions;
2985 u32 number, logical_id, phys_id;
2986 struct i40e_hw_capabilities *p;
2987 u8 major_rev;
2988 u32 i = 0;
2989 u16 id;
2990
2991 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
2992
2993 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
2994 p = &hw->dev_caps;
2995 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
2996 p = &hw->func_caps;
2997 else
2998 return;
2999
3000 for (i = 0; i < cap_count; i++, cap++) {
3001 id = le16_to_cpu(cap->id);
3002 number = le32_to_cpu(cap->number);
3003 logical_id = le32_to_cpu(cap->logical_id);
3004 phys_id = le32_to_cpu(cap->phys_id);
3005 major_rev = cap->major_rev;
3006
3007 switch (id) {
3008 case I40E_AQ_CAP_ID_SWITCH_MODE:
3009 p->switch_mode = number;
3010 break;
3011 case I40E_AQ_CAP_ID_MNG_MODE:
3012 p->management_mode = number;
3013 break;
3014 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3015 p->npar_enable = number;
3016 break;
3017 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3018 p->os2bmc = number;
3019 break;
3020 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3021 p->valid_functions = number;
3022 break;
3023 case I40E_AQ_CAP_ID_SRIOV:
3024 if (number == 1)
3025 p->sr_iov_1_1 = true;
3026 break;
3027 case I40E_AQ_CAP_ID_VF:
3028 p->num_vfs = number;
3029 p->vf_base_id = logical_id;
3030 break;
3031 case I40E_AQ_CAP_ID_VMDQ:
3032 if (number == 1)
3033 p->vmdq = true;
3034 break;
3035 case I40E_AQ_CAP_ID_8021QBG:
3036 if (number == 1)
3037 p->evb_802_1_qbg = true;
3038 break;
3039 case I40E_AQ_CAP_ID_8021QBR:
3040 if (number == 1)
3041 p->evb_802_1_qbh = true;
3042 break;
3043 case I40E_AQ_CAP_ID_VSI:
3044 p->num_vsis = number;
3045 break;
3046 case I40E_AQ_CAP_ID_DCB:
3047 if (number == 1) {
3048 p->dcb = true;
3049 p->enabled_tcmap = logical_id;
3050 p->maxtc = phys_id;
3051 }
3052 break;
3053 case I40E_AQ_CAP_ID_FCOE:
3054 if (number == 1)
3055 p->fcoe = true;
3056 break;
3057 case I40E_AQ_CAP_ID_ISCSI:
3058 if (number == 1)
3059 p->iscsi = true;
3060 break;
3061 case I40E_AQ_CAP_ID_RSS:
3062 p->rss = true;
3063 p->rss_table_size = number;
3064 p->rss_table_entry_width = logical_id;
3065 break;
3066 case I40E_AQ_CAP_ID_RXQ:
3067 p->num_rx_qp = number;
3068 p->base_queue = phys_id;
3069 break;
3070 case I40E_AQ_CAP_ID_TXQ:
3071 p->num_tx_qp = number;
3072 p->base_queue = phys_id;
3073 break;
3074 case I40E_AQ_CAP_ID_MSIX:
3075 p->num_msix_vectors = number;
3076 break;
3077 case I40E_AQ_CAP_ID_VF_MSIX:
3078 p->num_msix_vectors_vf = number;
3079 break;
3080 case I40E_AQ_CAP_ID_FLEX10:
3081 if (major_rev == 1) {
3082 if (number == 1) {
3083 p->flex10_enable = true;
3084 p->flex10_capable = true;
3085 }
3086 } else {
3087
3088 if (number & 1)
3089 p->flex10_enable = true;
3090 if (number & 2)
3091 p->flex10_capable = true;
3092 }
3093 p->flex10_mode = logical_id;
3094 p->flex10_status = phys_id;
3095 break;
3096 case I40E_AQ_CAP_ID_CEM:
3097 if (number == 1)
3098 p->mgmt_cem = true;
3099 break;
3100 case I40E_AQ_CAP_ID_IWARP:
3101 if (number == 1)
3102 p->iwarp = true;
3103 break;
3104 case I40E_AQ_CAP_ID_LED:
3105 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3106 p->led[phys_id] = true;
3107 break;
3108 case I40E_AQ_CAP_ID_SDP:
3109 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3110 p->sdp[phys_id] = true;
3111 break;
3112 case I40E_AQ_CAP_ID_MDIO:
3113 if (number == 1) {
3114 p->mdio_port_num = phys_id;
3115 p->mdio_port_mode = logical_id;
3116 }
3117 break;
3118 case I40E_AQ_CAP_ID_1588:
3119 if (number == 1)
3120 p->ieee_1588 = true;
3121 break;
3122 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3123 p->fd = true;
3124 p->fd_filters_guaranteed = number;
3125 p->fd_filters_best_effort = logical_id;
3126 break;
3127 case I40E_AQ_CAP_ID_WSR_PROT:
3128 p->wr_csr_prot = (u64)number;
3129 p->wr_csr_prot |= (u64)logical_id << 32;
3130 break;
3131 default:
3132 break;
3133 }
3134 }
3135
3136 if (p->fcoe)
3137 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3138
3139
3140
3141
3142 if (p->npar_enable || p->flex10_enable)
3143 p->fcoe = false;
3144
3145
3146 hw->num_ports = 0;
3147 for (i = 0; i < 4; i++) {
3148 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3149 u64 port_cfg = 0;
3150
3151
3152
3153
3154 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3155 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3156 hw->num_ports++;
3157 }
3158
3159 valid_functions = p->valid_functions;
3160 num_functions = 0;
3161 while (valid_functions) {
3162 if (valid_functions & 1)
3163 num_functions++;
3164 valid_functions >>= 1;
3165 }
3166
3167
3168
3169
3170 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3171 hw->num_partitions = num_functions / hw->num_ports;
3172
3173
3174
3175
3176 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3177}
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3191 void *buff, u16 buff_size, u16 *data_size,
3192 enum i40e_admin_queue_opc list_type_opc,
3193 struct i40e_asq_cmd_details *cmd_details)
3194{
3195 struct i40e_aqc_list_capabilites *cmd;
3196 struct i40e_aq_desc desc;
3197 i40e_status status = 0;
3198
3199 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3200
3201 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3202 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3203 status = I40E_ERR_PARAM;
3204 goto exit;
3205 }
3206
3207 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3208
3209 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3210 if (buff_size > I40E_AQ_LARGE_BUF)
3211 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3212
3213 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3214 *data_size = le16_to_cpu(desc.datalen);
3215
3216 if (status)
3217 goto exit;
3218
3219 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3220 list_type_opc);
3221
3222exit:
3223 return status;
3224}
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3239 u32 offset, u16 length, void *data,
3240 bool last_command,
3241 struct i40e_asq_cmd_details *cmd_details)
3242{
3243 struct i40e_aq_desc desc;
3244 struct i40e_aqc_nvm_update *cmd =
3245 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3246 i40e_status status;
3247
3248
3249 if (offset & 0xFF000000) {
3250 status = I40E_ERR_PARAM;
3251 goto i40e_aq_update_nvm_exit;
3252 }
3253
3254 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3255
3256
3257 if (last_command)
3258 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3259 cmd->module_pointer = module_pointer;
3260 cmd->offset = cpu_to_le32(offset);
3261 cmd->length = cpu_to_le16(length);
3262
3263 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3264 if (length > I40E_AQ_LARGE_BUF)
3265 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3266
3267 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3268
3269i40e_aq_update_nvm_exit:
3270 return status;
3271}
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3287 u8 mib_type, void *buff, u16 buff_size,
3288 u16 *local_len, u16 *remote_len,
3289 struct i40e_asq_cmd_details *cmd_details)
3290{
3291 struct i40e_aq_desc desc;
3292 struct i40e_aqc_lldp_get_mib *cmd =
3293 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3294 struct i40e_aqc_lldp_get_mib *resp =
3295 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3296 i40e_status status;
3297
3298 if (buff_size == 0 || !buff)
3299 return I40E_ERR_PARAM;
3300
3301 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3302
3303 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3304
3305 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3306 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3307 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3308
3309 desc.datalen = cpu_to_le16(buff_size);
3310
3311 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3312 if (buff_size > I40E_AQ_LARGE_BUF)
3313 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3314
3315 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3316 if (!status) {
3317 if (local_len != NULL)
3318 *local_len = le16_to_cpu(resp->local_len);
3319 if (remote_len != NULL)
3320 *remote_len = le16_to_cpu(resp->remote_len);
3321 }
3322
3323 return status;
3324}
3325
3326
3327
3328
3329
3330
3331
3332
3333
3334
3335i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3336 bool enable_update,
3337 struct i40e_asq_cmd_details *cmd_details)
3338{
3339 struct i40e_aq_desc desc;
3340 struct i40e_aqc_lldp_update_mib *cmd =
3341 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3342 i40e_status status;
3343
3344 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3345
3346 if (!enable_update)
3347 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3348
3349 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3350
3351 return status;
3352}
3353
3354
3355
3356
3357
3358
3359
3360
3361
3362i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3363 struct i40e_asq_cmd_details *cmd_details)
3364{
3365 struct i40e_aq_desc desc;
3366 struct i40e_aqc_lldp_stop *cmd =
3367 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3368 i40e_status status;
3369
3370 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3371
3372 if (shutdown_agent)
3373 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3374
3375 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3376
3377 return status;
3378}
3379
3380
3381
3382
3383
3384
3385
3386
3387i40e_status i40e_aq_start_lldp(struct i40e_hw *hw,
3388 struct i40e_asq_cmd_details *cmd_details)
3389{
3390 struct i40e_aq_desc desc;
3391 struct i40e_aqc_lldp_start *cmd =
3392 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3393 i40e_status status;
3394
3395 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3396
3397 cmd->command = I40E_AQ_LLDP_AGENT_START;
3398
3399 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3400
3401 return status;
3402}
3403
3404
3405
3406
3407
3408
3409
3410
3411
3412
3413i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3414 void *buff, u16 buff_size,
3415 struct i40e_asq_cmd_details *cmd_details)
3416{
3417 struct i40e_aq_desc desc;
3418 i40e_status status;
3419
3420 if (buff_size == 0 || !buff)
3421 return I40E_ERR_PARAM;
3422
3423 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3424
3425 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3426 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3427 cmd_details);
3428
3429 return status;
3430}
3431
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3442 u16 udp_port, u8 protocol_index,
3443 u8 *filter_index,
3444 struct i40e_asq_cmd_details *cmd_details)
3445{
3446 struct i40e_aq_desc desc;
3447 struct i40e_aqc_add_udp_tunnel *cmd =
3448 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3449 struct i40e_aqc_del_udp_tunnel_completion *resp =
3450 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3451 i40e_status status;
3452
3453 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3454
3455 cmd->udp_port = cpu_to_le16(udp_port);
3456 cmd->protocol_type = protocol_index;
3457
3458 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3459
3460 if (!status && filter_index)
3461 *filter_index = resp->index;
3462
3463 return status;
3464}
3465
3466
3467
3468
3469
3470
3471
3472i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3473 struct i40e_asq_cmd_details *cmd_details)
3474{
3475 struct i40e_aq_desc desc;
3476 struct i40e_aqc_remove_udp_tunnel *cmd =
3477 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3478 i40e_status status;
3479
3480 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3481
3482 cmd->index = index;
3483
3484 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3485
3486 return status;
3487}
3488
3489
3490
3491
3492
3493
3494
3495
3496
3497i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3498 struct i40e_asq_cmd_details *cmd_details)
3499{
3500 struct i40e_aq_desc desc;
3501 struct i40e_aqc_switch_seid *cmd =
3502 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3503 i40e_status status;
3504
3505 if (seid == 0)
3506 return I40E_ERR_PARAM;
3507
3508 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3509
3510 cmd->seid = cpu_to_le16(seid);
3511
3512 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3513
3514 return status;
3515}
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3527 struct i40e_asq_cmd_details *cmd_details)
3528{
3529 struct i40e_aq_desc desc;
3530 i40e_status status;
3531
3532 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3533
3534 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3535
3536 return status;
3537}
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3551 void *buff, u16 buff_size,
3552 enum i40e_admin_queue_opc opcode,
3553 struct i40e_asq_cmd_details *cmd_details)
3554{
3555 struct i40e_aq_desc desc;
3556 struct i40e_aqc_tx_sched_ind *cmd =
3557 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3558 i40e_status status;
3559 bool cmd_param_flag = false;
3560
3561 switch (opcode) {
3562 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3563 case i40e_aqc_opc_configure_vsi_tc_bw:
3564 case i40e_aqc_opc_enable_switching_comp_ets:
3565 case i40e_aqc_opc_modify_switching_comp_ets:
3566 case i40e_aqc_opc_disable_switching_comp_ets:
3567 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3568 case i40e_aqc_opc_configure_switching_comp_bw_config:
3569 cmd_param_flag = true;
3570 break;
3571 case i40e_aqc_opc_query_vsi_bw_config:
3572 case i40e_aqc_opc_query_vsi_ets_sla_config:
3573 case i40e_aqc_opc_query_switching_comp_ets_config:
3574 case i40e_aqc_opc_query_port_ets_config:
3575 case i40e_aqc_opc_query_switching_comp_bw_config:
3576 cmd_param_flag = false;
3577 break;
3578 default:
3579 return I40E_ERR_PARAM;
3580 }
3581
3582 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3583
3584
3585 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3586 if (cmd_param_flag)
3587 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3588 if (buff_size > I40E_AQ_LARGE_BUF)
3589 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3590
3591 desc.datalen = cpu_to_le16(buff_size);
3592
3593 cmd->vsi_seid = cpu_to_le16(seid);
3594
3595 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3596
3597 return status;
3598}
3599
3600
3601
3602
3603
3604
3605
3606
3607
3608i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3609 u16 seid, u16 credit, u8 max_credit,
3610 struct i40e_asq_cmd_details *cmd_details)
3611{
3612 struct i40e_aq_desc desc;
3613 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3614 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3615 i40e_status status;
3616
3617 i40e_fill_default_direct_cmd_desc(&desc,
3618 i40e_aqc_opc_configure_vsi_bw_limit);
3619
3620 cmd->vsi_seid = cpu_to_le16(seid);
3621 cmd->credit = cpu_to_le16(credit);
3622 cmd->max_credit = max_credit;
3623
3624 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3625
3626 return status;
3627}
3628
3629
3630
3631
3632
3633
3634
3635
3636i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3637 u16 seid,
3638 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3639 struct i40e_asq_cmd_details *cmd_details)
3640{
3641 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3642 i40e_aqc_opc_configure_vsi_tc_bw,
3643 cmd_details);
3644}
3645
3646
3647
3648
3649
3650
3651
3652
3653i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
3654 u16 seid,
3655 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
3656 enum i40e_admin_queue_opc opcode,
3657 struct i40e_asq_cmd_details *cmd_details)
3658{
3659 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
3660 sizeof(*ets_data), opcode, cmd_details);
3661}
3662
3663
3664
3665
3666
3667
3668
3669
3670i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
3671 u16 seid,
3672 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
3673 struct i40e_asq_cmd_details *cmd_details)
3674{
3675 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3676 i40e_aqc_opc_configure_switching_comp_bw_config,
3677 cmd_details);
3678}
3679
3680
3681
3682
3683
3684
3685
3686
3687i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
3688 u16 seid,
3689 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
3690 struct i40e_asq_cmd_details *cmd_details)
3691{
3692 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3693 i40e_aqc_opc_query_vsi_bw_config,
3694 cmd_details);
3695}
3696
3697
3698
3699
3700
3701
3702
3703
3704i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
3705 u16 seid,
3706 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
3707 struct i40e_asq_cmd_details *cmd_details)
3708{
3709 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3710 i40e_aqc_opc_query_vsi_ets_sla_config,
3711 cmd_details);
3712}
3713
3714
3715
3716
3717
3718
3719
3720
3721i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
3722 u16 seid,
3723 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
3724 struct i40e_asq_cmd_details *cmd_details)
3725{
3726 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3727 i40e_aqc_opc_query_switching_comp_ets_config,
3728 cmd_details);
3729}
3730
3731
3732
3733
3734
3735
3736
3737
3738i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
3739 u16 seid,
3740 struct i40e_aqc_query_port_ets_config_resp *bw_data,
3741 struct i40e_asq_cmd_details *cmd_details)
3742{
3743 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3744 i40e_aqc_opc_query_port_ets_config,
3745 cmd_details);
3746}
3747
3748
3749
3750
3751
3752
3753
3754
3755i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
3756 u16 seid,
3757 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
3758 struct i40e_asq_cmd_details *cmd_details)
3759{
3760 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3761 i40e_aqc_opc_query_switching_comp_bw_config,
3762 cmd_details);
3763}
3764
3765
3766
3767
3768
3769
3770
3771
3772
3773
3774
3775
3776
3777static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
3778 struct i40e_filter_control_settings *settings)
3779{
3780 u32 fcoe_cntx_size, fcoe_filt_size;
3781 u32 pe_cntx_size, pe_filt_size;
3782 u32 fcoe_fmax;
3783 u32 val;
3784
3785
3786 switch (settings->fcoe_filt_num) {
3787 case I40E_HASH_FILTER_SIZE_1K:
3788 case I40E_HASH_FILTER_SIZE_2K:
3789 case I40E_HASH_FILTER_SIZE_4K:
3790 case I40E_HASH_FILTER_SIZE_8K:
3791 case I40E_HASH_FILTER_SIZE_16K:
3792 case I40E_HASH_FILTER_SIZE_32K:
3793 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3794 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
3795 break;
3796 default:
3797 return I40E_ERR_PARAM;
3798 }
3799
3800 switch (settings->fcoe_cntx_num) {
3801 case I40E_DMA_CNTX_SIZE_512:
3802 case I40E_DMA_CNTX_SIZE_1K:
3803 case I40E_DMA_CNTX_SIZE_2K:
3804 case I40E_DMA_CNTX_SIZE_4K:
3805 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3806 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
3807 break;
3808 default:
3809 return I40E_ERR_PARAM;
3810 }
3811
3812
3813 switch (settings->pe_filt_num) {
3814 case I40E_HASH_FILTER_SIZE_1K:
3815 case I40E_HASH_FILTER_SIZE_2K:
3816 case I40E_HASH_FILTER_SIZE_4K:
3817 case I40E_HASH_FILTER_SIZE_8K:
3818 case I40E_HASH_FILTER_SIZE_16K:
3819 case I40E_HASH_FILTER_SIZE_32K:
3820 case I40E_HASH_FILTER_SIZE_64K:
3821 case I40E_HASH_FILTER_SIZE_128K:
3822 case I40E_HASH_FILTER_SIZE_256K:
3823 case I40E_HASH_FILTER_SIZE_512K:
3824 case I40E_HASH_FILTER_SIZE_1M:
3825 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
3826 pe_filt_size <<= (u32)settings->pe_filt_num;
3827 break;
3828 default:
3829 return I40E_ERR_PARAM;
3830 }
3831
3832 switch (settings->pe_cntx_num) {
3833 case I40E_DMA_CNTX_SIZE_512:
3834 case I40E_DMA_CNTX_SIZE_1K:
3835 case I40E_DMA_CNTX_SIZE_2K:
3836 case I40E_DMA_CNTX_SIZE_4K:
3837 case I40E_DMA_CNTX_SIZE_8K:
3838 case I40E_DMA_CNTX_SIZE_16K:
3839 case I40E_DMA_CNTX_SIZE_32K:
3840 case I40E_DMA_CNTX_SIZE_64K:
3841 case I40E_DMA_CNTX_SIZE_128K:
3842 case I40E_DMA_CNTX_SIZE_256K:
3843 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
3844 pe_cntx_size <<= (u32)settings->pe_cntx_num;
3845 break;
3846 default:
3847 return I40E_ERR_PARAM;
3848 }
3849
3850
3851 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
3852 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
3853 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
3854 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
3855 return I40E_ERR_INVALID_SIZE;
3856
3857 return 0;
3858}
3859
3860
3861
3862
3863
3864
3865
3866
3867
3868
3869i40e_status i40e_set_filter_control(struct i40e_hw *hw,
3870 struct i40e_filter_control_settings *settings)
3871{
3872 i40e_status ret = 0;
3873 u32 hash_lut_size = 0;
3874 u32 val;
3875
3876 if (!settings)
3877 return I40E_ERR_PARAM;
3878
3879
3880 ret = i40e_validate_filter_settings(hw, settings);
3881 if (ret)
3882 return ret;
3883
3884
3885 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
3886
3887
3888 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
3889 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
3890 I40E_PFQF_CTL_0_PEHSIZE_MASK;
3891
3892 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
3893 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
3894 I40E_PFQF_CTL_0_PEDSIZE_MASK;
3895
3896
3897 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3898 val |= ((u32)settings->fcoe_filt_num <<
3899 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
3900 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
3901
3902 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3903 val |= ((u32)settings->fcoe_cntx_num <<
3904 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
3905 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
3906
3907
3908 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3909 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
3910 hash_lut_size = 1;
3911 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
3912 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
3913
3914
3915 if (settings->enable_fdir)
3916 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
3917 if (settings->enable_ethtype)
3918 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
3919 if (settings->enable_macvlan)
3920 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
3921
3922 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
3923
3924 return 0;
3925}
3926
3927
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938
3939
3940
3941
3942
3943i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
3944 u8 *mac_addr, u16 ethtype, u16 flags,
3945 u16 vsi_seid, u16 queue, bool is_add,
3946 struct i40e_control_filter_stats *stats,
3947 struct i40e_asq_cmd_details *cmd_details)
3948{
3949 struct i40e_aq_desc desc;
3950 struct i40e_aqc_add_remove_control_packet_filter *cmd =
3951 (struct i40e_aqc_add_remove_control_packet_filter *)
3952 &desc.params.raw;
3953 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
3954 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
3955 &desc.params.raw;
3956 i40e_status status;
3957
3958 if (vsi_seid == 0)
3959 return I40E_ERR_PARAM;
3960
3961 if (is_add) {
3962 i40e_fill_default_direct_cmd_desc(&desc,
3963 i40e_aqc_opc_add_control_packet_filter);
3964 cmd->queue = cpu_to_le16(queue);
3965 } else {
3966 i40e_fill_default_direct_cmd_desc(&desc,
3967 i40e_aqc_opc_remove_control_packet_filter);
3968 }
3969
3970 if (mac_addr)
3971 ether_addr_copy(cmd->mac, mac_addr);
3972
3973 cmd->etype = cpu_to_le16(ethtype);
3974 cmd->flags = cpu_to_le16(flags);
3975 cmd->seid = cpu_to_le16(vsi_seid);
3976
3977 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3978
3979 if (!status && stats) {
3980 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
3981 stats->etype_used = le16_to_cpu(resp->etype_used);
3982 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
3983 stats->etype_free = le16_to_cpu(resp->etype_free);
3984 }
3985
3986 return status;
3987}
3988
3989
3990
3991
3992
3993
3994#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
3995void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
3996 u16 seid)
3997{
3998 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
3999 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4000 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4001 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4002 i40e_status status;
4003
4004 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4005 seid, 0, true, NULL,
4006 NULL);
4007 if (status)
4008 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4009}
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4020
4021
4022
4023
4024static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4025 u32 reg_addr0, u32 *reg_val0,
4026 u32 reg_addr1, u32 *reg_val1)
4027{
4028 struct i40e_aq_desc desc;
4029 struct i40e_aqc_alternate_write *cmd_resp =
4030 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4031 i40e_status status;
4032
4033 if (!reg_val0)
4034 return I40E_ERR_PARAM;
4035
4036 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4037 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4038 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4039
4040 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4041
4042 if (!status) {
4043 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4044
4045 if (reg_val1)
4046 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4047 }
4048
4049 return status;
4050}
4051
4052
4053
4054
4055
4056
4057
4058
4059i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4060 struct i40e_asq_cmd_details *cmd_details)
4061{
4062 struct i40e_aq_desc desc;
4063 i40e_status status;
4064
4065 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4066
4067 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4068
4069 return status;
4070}
4071
4072
4073
4074
4075
4076
4077
4078
4079void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4080{
4081 hw->bus.type = i40e_bus_type_pci_express;
4082
4083 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4084 case PCI_EXP_LNKSTA_NLW_X1:
4085 hw->bus.width = i40e_bus_width_pcie_x1;
4086 break;
4087 case PCI_EXP_LNKSTA_NLW_X2:
4088 hw->bus.width = i40e_bus_width_pcie_x2;
4089 break;
4090 case PCI_EXP_LNKSTA_NLW_X4:
4091 hw->bus.width = i40e_bus_width_pcie_x4;
4092 break;
4093 case PCI_EXP_LNKSTA_NLW_X8:
4094 hw->bus.width = i40e_bus_width_pcie_x8;
4095 break;
4096 default:
4097 hw->bus.width = i40e_bus_width_unknown;
4098 break;
4099 }
4100
4101 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4102 case PCI_EXP_LNKSTA_CLS_2_5GB:
4103 hw->bus.speed = i40e_bus_speed_2500;
4104 break;
4105 case PCI_EXP_LNKSTA_CLS_5_0GB:
4106 hw->bus.speed = i40e_bus_speed_5000;
4107 break;
4108 case PCI_EXP_LNKSTA_CLS_8_0GB:
4109 hw->bus.speed = i40e_bus_speed_8000;
4110 break;
4111 default:
4112 hw->bus.speed = i40e_bus_speed_unknown;
4113 break;
4114 }
4115}
4116
4117
4118
4119
4120
4121
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4133 u8 table_id, u32 start_index, u16 buff_size,
4134 void *buff, u16 *ret_buff_size,
4135 u8 *ret_next_table, u32 *ret_next_index,
4136 struct i40e_asq_cmd_details *cmd_details)
4137{
4138 struct i40e_aq_desc desc;
4139 struct i40e_aqc_debug_dump_internals *cmd =
4140 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4141 struct i40e_aqc_debug_dump_internals *resp =
4142 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4143 i40e_status status;
4144
4145 if (buff_size == 0 || !buff)
4146 return I40E_ERR_PARAM;
4147
4148 i40e_fill_default_direct_cmd_desc(&desc,
4149 i40e_aqc_opc_debug_dump_internals);
4150
4151 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4152 if (buff_size > I40E_AQ_LARGE_BUF)
4153 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4154
4155 cmd->cluster_id = cluster_id;
4156 cmd->table_id = table_id;
4157 cmd->idx = cpu_to_le32(start_index);
4158
4159 desc.datalen = cpu_to_le16(buff_size);
4160
4161 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4162 if (!status) {
4163 if (ret_buff_size)
4164 *ret_buff_size = le16_to_cpu(desc.datalen);
4165 if (ret_next_table)
4166 *ret_next_table = resp->table_id;
4167 if (ret_next_index)
4168 *ret_next_index = le32_to_cpu(resp->idx);
4169 }
4170
4171 return status;
4172}
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183
4184i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4185 u32 *max_bw, u32 *min_bw,
4186 bool *min_valid, bool *max_valid)
4187{
4188 i40e_status status;
4189 u32 max_bw_addr, min_bw_addr;
4190
4191
4192 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4193 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4194 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4195 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4196 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4197 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4198
4199
4200 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4201 min_bw_addr, min_bw);
4202
4203 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4204 *min_valid = true;
4205 else
4206 *min_valid = false;
4207
4208 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4209 *max_valid = true;
4210 else
4211 *max_valid = false;
4212
4213 return status;
4214}
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4225 struct i40e_aqc_configure_partition_bw_data *bw_data,
4226 struct i40e_asq_cmd_details *cmd_details)
4227{
4228 i40e_status status;
4229 struct i40e_aq_desc desc;
4230 u16 bwd_size = sizeof(*bw_data);
4231
4232 i40e_fill_default_direct_cmd_desc(&desc,
4233 i40e_aqc_opc_configure_partition_bw);
4234
4235
4236 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4237 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4238
4239 if (bwd_size > I40E_AQ_LARGE_BUF)
4240 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4241
4242 desc.datalen = cpu_to_le16(bwd_size);
4243
4244 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4245 cmd_details);
4246
4247 return status;
4248}
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258
4259
4260i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4261 u8 page, u16 reg, u8 phy_addr,
4262 u16 *value)
4263{
4264 i40e_status status = I40E_ERR_TIMEOUT;
4265 u32 command = 0;
4266 u16 retry = 1000;
4267 u8 port_num = hw->func_caps.mdio_port_num;
4268
4269 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4270 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4271 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4272 (I40E_MDIO_OPCODE_ADDRESS) |
4273 (I40E_MDIO_STCODE) |
4274 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4275 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4276 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4277 do {
4278 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4279 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4280 status = 0;
4281 break;
4282 }
4283 usleep_range(10, 20);
4284 retry--;
4285 } while (retry);
4286
4287 if (status) {
4288 i40e_debug(hw, I40E_DEBUG_PHY,
4289 "PHY: Can't write command to external PHY.\n");
4290 goto phy_read_end;
4291 }
4292
4293 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4294 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4295 (I40E_MDIO_OPCODE_READ) |
4296 (I40E_MDIO_STCODE) |
4297 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4298 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4299 status = I40E_ERR_TIMEOUT;
4300 retry = 1000;
4301 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4302 do {
4303 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4304 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4305 status = 0;
4306 break;
4307 }
4308 usleep_range(10, 20);
4309 retry--;
4310 } while (retry);
4311
4312 if (!status) {
4313 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4314 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4315 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4316 } else {
4317 i40e_debug(hw, I40E_DEBUG_PHY,
4318 "PHY: Can't read register value from external PHY.\n");
4319 }
4320
4321phy_read_end:
4322 return status;
4323}
4324
4325
4326
4327
4328
4329
4330
4331
4332
4333
4334
4335i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4336 u8 page, u16 reg, u8 phy_addr,
4337 u16 value)
4338{
4339 i40e_status status = I40E_ERR_TIMEOUT;
4340 u32 command = 0;
4341 u16 retry = 1000;
4342 u8 port_num = hw->func_caps.mdio_port_num;
4343
4344 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4345 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4346 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4347 (I40E_MDIO_OPCODE_ADDRESS) |
4348 (I40E_MDIO_STCODE) |
4349 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4350 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4351 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4352 do {
4353 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4354 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4355 status = 0;
4356 break;
4357 }
4358 usleep_range(10, 20);
4359 retry--;
4360 } while (retry);
4361 if (status) {
4362 i40e_debug(hw, I40E_DEBUG_PHY,
4363 "PHY: Can't write command to external PHY.\n");
4364 goto phy_write_end;
4365 }
4366
4367 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4368 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4369
4370 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4371 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4372 (I40E_MDIO_OPCODE_WRITE) |
4373 (I40E_MDIO_STCODE) |
4374 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4375 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4376 status = I40E_ERR_TIMEOUT;
4377 retry = 1000;
4378 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4379 do {
4380 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4381 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4382 status = 0;
4383 break;
4384 }
4385 usleep_range(10, 20);
4386 retry--;
4387 } while (retry);
4388
4389phy_write_end:
4390 return status;
4391}
4392
4393
4394
4395
4396
4397
4398
4399
4400
4401u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4402{
4403 u8 port_num = hw->func_caps.mdio_port_num;
4404 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4405
4406 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4407}
4408
4409
4410
4411
4412
4413
4414
4415
4416
4417i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4418 u32 time, u32 interval)
4419{
4420 i40e_status status = 0;
4421 u32 i;
4422 u16 led_ctl;
4423 u16 gpio_led_port;
4424 u16 led_reg;
4425 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4426 u8 phy_addr = 0;
4427 u8 port_num;
4428
4429 i = rd32(hw, I40E_PFGEN_PORTNUM);
4430 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4431 phy_addr = i40e_get_phy_address(hw, port_num);
4432
4433 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4434 led_addr++) {
4435 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4436 led_addr, phy_addr, &led_reg);
4437 if (status)
4438 goto phy_blinking_end;
4439 led_ctl = led_reg;
4440 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4441 led_reg = 0;
4442 status = i40e_write_phy_register(hw,
4443 I40E_PHY_COM_REG_PAGE,
4444 led_addr, phy_addr,
4445 led_reg);
4446 if (status)
4447 goto phy_blinking_end;
4448 break;
4449 }
4450 }
4451
4452 if (time > 0 && interval > 0) {
4453 for (i = 0; i < time * 1000; i += interval) {
4454 status = i40e_read_phy_register(hw,
4455 I40E_PHY_COM_REG_PAGE,
4456 led_addr, phy_addr,
4457 &led_reg);
4458 if (status)
4459 goto restore_config;
4460 if (led_reg & I40E_PHY_LED_MANUAL_ON)
4461 led_reg = 0;
4462 else
4463 led_reg = I40E_PHY_LED_MANUAL_ON;
4464 status = i40e_write_phy_register(hw,
4465 I40E_PHY_COM_REG_PAGE,
4466 led_addr, phy_addr,
4467 led_reg);
4468 if (status)
4469 goto restore_config;
4470 msleep(interval);
4471 }
4472 }
4473
4474restore_config:
4475 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4476 phy_addr, led_ctl);
4477
4478phy_blinking_end:
4479 return status;
4480}
4481
4482
4483
4484
4485
4486
4487
4488
4489i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
4490 u16 *val)
4491{
4492 i40e_status status = 0;
4493 u16 gpio_led_port;
4494 u8 phy_addr = 0;
4495 u16 reg_val;
4496 u16 temp_addr;
4497 u8 port_num;
4498 u32 i;
4499
4500 temp_addr = I40E_PHY_LED_PROV_REG_1;
4501 i = rd32(hw, I40E_PFGEN_PORTNUM);
4502 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4503 phy_addr = i40e_get_phy_address(hw, port_num);
4504
4505 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4506 temp_addr++) {
4507 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4508 temp_addr, phy_addr, ®_val);
4509 if (status)
4510 return status;
4511 *val = reg_val;
4512 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
4513 *led_addr = temp_addr;
4514 break;
4515 }
4516 }
4517 return status;
4518}
4519
4520
4521
4522
4523
4524
4525
4526
4527
4528i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
4529 u16 led_addr, u32 mode)
4530{
4531 i40e_status status = 0;
4532 u16 led_ctl = 0;
4533 u16 led_reg = 0;
4534 u8 phy_addr = 0;
4535 u8 port_num;
4536 u32 i;
4537
4538 i = rd32(hw, I40E_PFGEN_PORTNUM);
4539 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4540 phy_addr = i40e_get_phy_address(hw, port_num);
4541
4542 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4543 phy_addr, &led_reg);
4544 if (status)
4545 return status;
4546 led_ctl = led_reg;
4547 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4548 led_reg = 0;
4549 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4550 led_addr, phy_addr, led_reg);
4551 if (status)
4552 return status;
4553 }
4554 status = i40e_read_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4555 led_addr, phy_addr, &led_reg);
4556 if (status)
4557 goto restore_config;
4558 if (on)
4559 led_reg = I40E_PHY_LED_MANUAL_ON;
4560 else
4561 led_reg = 0;
4562 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE,
4563 led_addr, phy_addr, led_reg);
4564 if (status)
4565 goto restore_config;
4566 if (mode & I40E_PHY_LED_MODE_ORIG) {
4567 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
4568 status = i40e_write_phy_register(hw,
4569 I40E_PHY_COM_REG_PAGE,
4570 led_addr, phy_addr, led_ctl);
4571 }
4572 return status;
4573restore_config:
4574 status = i40e_write_phy_register(hw, I40E_PHY_COM_REG_PAGE, led_addr,
4575 phy_addr, led_ctl);
4576 return status;
4577}
4578
4579
4580
4581
4582
4583
4584
4585
4586
4587
4588
4589i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
4590 u32 reg_addr, u32 *reg_val,
4591 struct i40e_asq_cmd_details *cmd_details)
4592{
4593 struct i40e_aq_desc desc;
4594 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
4595 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4596 i40e_status status;
4597
4598 if (!reg_val)
4599 return I40E_ERR_PARAM;
4600
4601 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
4602
4603 cmd_resp->address = cpu_to_le32(reg_addr);
4604
4605 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4606
4607 if (status == 0)
4608 *reg_val = le32_to_cpu(cmd_resp->value);
4609
4610 return status;
4611}
4612
4613
4614
4615
4616
4617
4618u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
4619{
4620 i40e_status status = 0;
4621 bool use_register;
4622 int retry = 5;
4623 u32 val = 0;
4624
4625 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4626 if (!use_register) {
4627do_retry:
4628 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
4629 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4630 usleep_range(1000, 2000);
4631 retry--;
4632 goto do_retry;
4633 }
4634 }
4635
4636
4637 if (status || use_register)
4638 val = rd32(hw, reg_addr);
4639
4640 return val;
4641}
4642
4643
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
4654 u32 reg_addr, u32 reg_val,
4655 struct i40e_asq_cmd_details *cmd_details)
4656{
4657 struct i40e_aq_desc desc;
4658 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
4659 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
4660 i40e_status status;
4661
4662 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
4663
4664 cmd->address = cpu_to_le32(reg_addr);
4665 cmd->value = cpu_to_le32(reg_val);
4666
4667 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4668
4669 return status;
4670}
4671
4672
4673
4674
4675
4676
4677
4678void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
4679{
4680 i40e_status status = 0;
4681 bool use_register;
4682 int retry = 5;
4683
4684 use_register = (hw->aq.api_maj_ver == 1) && (hw->aq.api_min_ver < 5);
4685 if (!use_register) {
4686do_retry:
4687 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
4688 reg_val, NULL);
4689 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
4690 usleep_range(1000, 2000);
4691 retry--;
4692 goto do_retry;
4693 }
4694 }
4695
4696
4697 if (status || use_register)
4698 wr32(hw, reg_addr, reg_val);
4699}
4700
