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27#ifndef _I40E_TYPE_H_
28#define _I40E_TYPE_H_
29
30#include "i40e_status.h"
31#include "i40e_osdep.h"
32#include "i40e_register.h"
33#include "i40e_adminq.h"
34#include "i40e_hmc.h"
35#include "i40e_lan_hmc.h"
36#include "i40e_devids.h"
37
38
39#define I40E_MASK(mask, shift) (mask << shift)
40
41#define I40E_MAX_VSI_QP 16
42#define I40E_MAX_VF_VSI 3
43#define I40E_MAX_CHAINED_RX_BUFFERS 5
44#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
45
46
47#define I40E_MAX_NVM_TIMEOUT 18000
48
49
50#define I40E_MS_TO_GTIME(time) ((time) * 1000)
51
52
53struct i40e_hw;
54typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
55
56
57
58#define I40E_DESC_UNUSED(R) \
59 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
60 (R)->next_to_clean - (R)->next_to_use - 1)
61
62
63#define I40E_QTX_CTL_VF_QUEUE 0x0
64#define I40E_QTX_CTL_VM_QUEUE 0x1
65#define I40E_QTX_CTL_PF_QUEUE 0x2
66
67
68enum i40e_debug_mask {
69 I40E_DEBUG_INIT = 0x00000001,
70 I40E_DEBUG_RELEASE = 0x00000002,
71
72 I40E_DEBUG_LINK = 0x00000010,
73 I40E_DEBUG_PHY = 0x00000020,
74 I40E_DEBUG_HMC = 0x00000040,
75 I40E_DEBUG_NVM = 0x00000080,
76 I40E_DEBUG_LAN = 0x00000100,
77 I40E_DEBUG_FLOW = 0x00000200,
78 I40E_DEBUG_DCB = 0x00000400,
79 I40E_DEBUG_DIAG = 0x00000800,
80 I40E_DEBUG_FD = 0x00001000,
81 I40E_DEBUG_IWARP = 0x00F00000,
82 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
83 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
84 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
85 I40E_DEBUG_AQ_COMMAND = 0x06000000,
86 I40E_DEBUG_AQ = 0x0F000000,
87
88 I40E_DEBUG_USER = 0xF0000000,
89
90 I40E_DEBUG_ALL = 0xFFFFFFFF
91};
92
93#define I40E_MDIO_STCODE 0
94#define I40E_MDIO_OPCODE_ADDRESS 0
95#define I40E_MDIO_OPCODE_WRITE I40E_MASK(1, \
96 I40E_GLGEN_MSCA_OPCODE_SHIFT)
97#define I40E_MDIO_OPCODE_READ_INC_ADDR I40E_MASK(2, \
98 I40E_GLGEN_MSCA_OPCODE_SHIFT)
99#define I40E_MDIO_OPCODE_READ I40E_MASK(3, \
100 I40E_GLGEN_MSCA_OPCODE_SHIFT)
101
102#define I40E_PHY_COM_REG_PAGE 0x1E
103#define I40E_PHY_LED_LINK_MODE_MASK 0xF0
104#define I40E_PHY_LED_MANUAL_ON 0x100
105#define I40E_PHY_LED_PROV_REG_1 0xC430
106#define I40E_PHY_LED_MODE_MASK 0xFFFF
107#define I40E_PHY_LED_MODE_ORIG 0x80000000
108
109
110
111
112
113
114
115
116
117enum i40e_mac_type {
118 I40E_MAC_UNKNOWN = 0,
119 I40E_MAC_X710,
120 I40E_MAC_XL710,
121 I40E_MAC_VF,
122 I40E_MAC_X722,
123 I40E_MAC_X722_VF,
124 I40E_MAC_GENERIC,
125};
126
127enum i40e_media_type {
128 I40E_MEDIA_TYPE_UNKNOWN = 0,
129 I40E_MEDIA_TYPE_FIBER,
130 I40E_MEDIA_TYPE_BASET,
131 I40E_MEDIA_TYPE_BACKPLANE,
132 I40E_MEDIA_TYPE_CX4,
133 I40E_MEDIA_TYPE_DA,
134 I40E_MEDIA_TYPE_VIRTUAL
135};
136
137enum i40e_fc_mode {
138 I40E_FC_NONE = 0,
139 I40E_FC_RX_PAUSE,
140 I40E_FC_TX_PAUSE,
141 I40E_FC_FULL,
142 I40E_FC_PFC,
143 I40E_FC_DEFAULT
144};
145
146enum i40e_set_fc_aq_failures {
147 I40E_SET_FC_AQ_FAIL_NONE = 0,
148 I40E_SET_FC_AQ_FAIL_GET = 1,
149 I40E_SET_FC_AQ_FAIL_SET = 2,
150 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
151 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
152};
153
154enum i40e_vsi_type {
155 I40E_VSI_MAIN = 0,
156 I40E_VSI_VMDQ1 = 1,
157 I40E_VSI_VMDQ2 = 2,
158 I40E_VSI_CTRL = 3,
159 I40E_VSI_FCOE = 4,
160 I40E_VSI_MIRROR = 5,
161 I40E_VSI_SRIOV = 6,
162 I40E_VSI_FDIR = 7,
163 I40E_VSI_IWARP = 8,
164 I40E_VSI_TYPE_UNKNOWN
165};
166
167enum i40e_queue_type {
168 I40E_QUEUE_TYPE_RX = 0,
169 I40E_QUEUE_TYPE_TX,
170 I40E_QUEUE_TYPE_PE_CEQ,
171 I40E_QUEUE_TYPE_UNKNOWN
172};
173
174struct i40e_link_status {
175 enum i40e_aq_phy_type phy_type;
176 enum i40e_aq_link_speed link_speed;
177 u8 link_info;
178 u8 an_info;
179 u8 ext_info;
180 u8 loopback;
181
182 bool lse_enable;
183 u16 max_frame_size;
184 bool crc_enable;
185 u8 pacing;
186 u8 requested_speeds;
187 u8 module_type[3];
188
189#define I40E_MODULE_TYPE_SFP 0x03
190#define I40E_MODULE_TYPE_QSFP 0x0D
191
192#define I40E_MODULE_TYPE_40G_ACTIVE 0x01
193#define I40E_MODULE_TYPE_40G_LR4 0x02
194#define I40E_MODULE_TYPE_40G_SR4 0x04
195#define I40E_MODULE_TYPE_40G_CR4 0x08
196#define I40E_MODULE_TYPE_10G_BASE_SR 0x10
197#define I40E_MODULE_TYPE_10G_BASE_LR 0x20
198#define I40E_MODULE_TYPE_10G_BASE_LRM 0x40
199#define I40E_MODULE_TYPE_10G_BASE_ER 0x80
200
201#define I40E_MODULE_TYPE_1000BASE_SX 0x01
202#define I40E_MODULE_TYPE_1000BASE_LX 0x02
203#define I40E_MODULE_TYPE_1000BASE_CX 0x04
204#define I40E_MODULE_TYPE_1000BASE_T 0x08
205};
206
207enum i40e_aq_capabilities_phy_type {
208 I40E_CAP_PHY_TYPE_SGMII = BIT(I40E_PHY_TYPE_SGMII),
209 I40E_CAP_PHY_TYPE_1000BASE_KX = BIT(I40E_PHY_TYPE_1000BASE_KX),
210 I40E_CAP_PHY_TYPE_10GBASE_KX4 = BIT(I40E_PHY_TYPE_10GBASE_KX4),
211 I40E_CAP_PHY_TYPE_10GBASE_KR = BIT(I40E_PHY_TYPE_10GBASE_KR),
212 I40E_CAP_PHY_TYPE_40GBASE_KR4 = BIT(I40E_PHY_TYPE_40GBASE_KR4),
213 I40E_CAP_PHY_TYPE_XAUI = BIT(I40E_PHY_TYPE_XAUI),
214 I40E_CAP_PHY_TYPE_XFI = BIT(I40E_PHY_TYPE_XFI),
215 I40E_CAP_PHY_TYPE_SFI = BIT(I40E_PHY_TYPE_SFI),
216 I40E_CAP_PHY_TYPE_XLAUI = BIT(I40E_PHY_TYPE_XLAUI),
217 I40E_CAP_PHY_TYPE_XLPPI = BIT(I40E_PHY_TYPE_XLPPI),
218 I40E_CAP_PHY_TYPE_40GBASE_CR4_CU = BIT(I40E_PHY_TYPE_40GBASE_CR4_CU),
219 I40E_CAP_PHY_TYPE_10GBASE_CR1_CU = BIT(I40E_PHY_TYPE_10GBASE_CR1_CU),
220 I40E_CAP_PHY_TYPE_10GBASE_AOC = BIT(I40E_PHY_TYPE_10GBASE_AOC),
221 I40E_CAP_PHY_TYPE_40GBASE_AOC = BIT(I40E_PHY_TYPE_40GBASE_AOC),
222 I40E_CAP_PHY_TYPE_100BASE_TX = BIT(I40E_PHY_TYPE_100BASE_TX),
223 I40E_CAP_PHY_TYPE_1000BASE_T = BIT(I40E_PHY_TYPE_1000BASE_T),
224 I40E_CAP_PHY_TYPE_10GBASE_T = BIT(I40E_PHY_TYPE_10GBASE_T),
225 I40E_CAP_PHY_TYPE_10GBASE_SR = BIT(I40E_PHY_TYPE_10GBASE_SR),
226 I40E_CAP_PHY_TYPE_10GBASE_LR = BIT(I40E_PHY_TYPE_10GBASE_LR),
227 I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU = BIT(I40E_PHY_TYPE_10GBASE_SFPP_CU),
228 I40E_CAP_PHY_TYPE_10GBASE_CR1 = BIT(I40E_PHY_TYPE_10GBASE_CR1),
229 I40E_CAP_PHY_TYPE_40GBASE_CR4 = BIT(I40E_PHY_TYPE_40GBASE_CR4),
230 I40E_CAP_PHY_TYPE_40GBASE_SR4 = BIT(I40E_PHY_TYPE_40GBASE_SR4),
231 I40E_CAP_PHY_TYPE_40GBASE_LR4 = BIT(I40E_PHY_TYPE_40GBASE_LR4),
232 I40E_CAP_PHY_TYPE_1000BASE_SX = BIT(I40E_PHY_TYPE_1000BASE_SX),
233 I40E_CAP_PHY_TYPE_1000BASE_LX = BIT(I40E_PHY_TYPE_1000BASE_LX),
234 I40E_CAP_PHY_TYPE_1000BASE_T_OPTICAL =
235 BIT(I40E_PHY_TYPE_1000BASE_T_OPTICAL),
236 I40E_CAP_PHY_TYPE_20GBASE_KR2 = BIT(I40E_PHY_TYPE_20GBASE_KR2)
237};
238
239struct i40e_phy_info {
240 struct i40e_link_status link_info;
241 struct i40e_link_status link_info_old;
242 bool get_link_info;
243 enum i40e_media_type media_type;
244
245 enum i40e_aq_capabilities_phy_type phy_types;
246};
247
248#define I40E_HW_CAP_MAX_GPIO 30
249
250struct i40e_hw_capabilities {
251 u32 switch_mode;
252#define I40E_NVM_IMAGE_TYPE_EVB 0x0
253#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
254#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
255
256 u32 management_mode;
257 u32 npar_enable;
258 u32 os2bmc;
259 u32 valid_functions;
260 bool sr_iov_1_1;
261 bool vmdq;
262 bool evb_802_1_qbg;
263 bool evb_802_1_qbh;
264 bool dcb;
265 bool fcoe;
266 bool iscsi;
267 bool flex10_enable;
268 bool flex10_capable;
269 u32 flex10_mode;
270#define I40E_FLEX10_MODE_UNKNOWN 0x0
271#define I40E_FLEX10_MODE_DCC 0x1
272#define I40E_FLEX10_MODE_DCI 0x2
273
274 u32 flex10_status;
275#define I40E_FLEX10_STATUS_DCC_ERROR 0x1
276#define I40E_FLEX10_STATUS_VC_MODE 0x2
277
278 bool mgmt_cem;
279 bool ieee_1588;
280 bool iwarp;
281 bool fd;
282 u32 fd_filters_guaranteed;
283 u32 fd_filters_best_effort;
284 bool rss;
285 u32 rss_table_size;
286 u32 rss_table_entry_width;
287 bool led[I40E_HW_CAP_MAX_GPIO];
288 bool sdp[I40E_HW_CAP_MAX_GPIO];
289 u32 nvm_image_type;
290 u32 num_flow_director_filters;
291 u32 num_vfs;
292 u32 vf_base_id;
293 u32 num_vsis;
294 u32 num_rx_qp;
295 u32 num_tx_qp;
296 u32 base_queue;
297 u32 num_msix_vectors;
298 u32 num_msix_vectors_vf;
299 u32 led_pin_num;
300 u32 sdp_pin_num;
301 u32 mdio_port_num;
302 u32 mdio_port_mode;
303 u8 rx_buf_chain_len;
304 u32 enabled_tcmap;
305 u32 maxtc;
306 u64 wr_csr_prot;
307};
308
309struct i40e_mac_info {
310 enum i40e_mac_type type;
311 u8 addr[ETH_ALEN];
312 u8 perm_addr[ETH_ALEN];
313 u8 san_addr[ETH_ALEN];
314 u8 port_addr[ETH_ALEN];
315 u16 max_fcoeq;
316};
317
318enum i40e_aq_resources_ids {
319 I40E_NVM_RESOURCE_ID = 1
320};
321
322enum i40e_aq_resource_access_type {
323 I40E_RESOURCE_READ = 1,
324 I40E_RESOURCE_WRITE
325};
326
327struct i40e_nvm_info {
328 u64 hw_semaphore_timeout;
329 u32 timeout;
330 u16 sr_size;
331 bool blank_nvm_mode;
332 u16 version;
333 u32 eetrack;
334 u32 oem_ver;
335};
336
337
338
339enum i40e_nvmupd_cmd {
340 I40E_NVMUPD_INVALID,
341 I40E_NVMUPD_READ_CON,
342 I40E_NVMUPD_READ_SNT,
343 I40E_NVMUPD_READ_LCB,
344 I40E_NVMUPD_READ_SA,
345 I40E_NVMUPD_WRITE_ERA,
346 I40E_NVMUPD_WRITE_CON,
347 I40E_NVMUPD_WRITE_SNT,
348 I40E_NVMUPD_WRITE_LCB,
349 I40E_NVMUPD_WRITE_SA,
350 I40E_NVMUPD_CSUM_CON,
351 I40E_NVMUPD_CSUM_SA,
352 I40E_NVMUPD_CSUM_LCB,
353 I40E_NVMUPD_STATUS,
354 I40E_NVMUPD_EXEC_AQ,
355 I40E_NVMUPD_GET_AQ_RESULT,
356};
357
358enum i40e_nvmupd_state {
359 I40E_NVMUPD_STATE_INIT,
360 I40E_NVMUPD_STATE_READING,
361 I40E_NVMUPD_STATE_WRITING,
362 I40E_NVMUPD_STATE_INIT_WAIT,
363 I40E_NVMUPD_STATE_WRITE_WAIT,
364};
365
366
367
368
369#define I40E_NVM_READ 0xB
370#define I40E_NVM_WRITE 0xC
371
372#define I40E_NVM_MOD_PNT_MASK 0xFF
373
374#define I40E_NVM_TRANS_SHIFT 8
375#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
376#define I40E_NVM_CON 0x0
377#define I40E_NVM_SNT 0x1
378#define I40E_NVM_LCB 0x2
379#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
380#define I40E_NVM_ERA 0x4
381#define I40E_NVM_CSUM 0x8
382#define I40E_NVM_EXEC 0xf
383
384#define I40E_NVM_ADAPT_SHIFT 16
385#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
386
387#define I40E_NVMUPD_MAX_DATA 4096
388#define I40E_NVMUPD_IFACE_TIMEOUT 2
389
390struct i40e_nvm_access {
391 u32 command;
392 u32 config;
393 u32 offset;
394 u32 data_size;
395 u8 data[1];
396};
397
398
399enum i40e_bus_type {
400 i40e_bus_type_unknown = 0,
401 i40e_bus_type_pci,
402 i40e_bus_type_pcix,
403 i40e_bus_type_pci_express,
404 i40e_bus_type_reserved
405};
406
407
408enum i40e_bus_speed {
409 i40e_bus_speed_unknown = 0,
410 i40e_bus_speed_33 = 33,
411 i40e_bus_speed_66 = 66,
412 i40e_bus_speed_100 = 100,
413 i40e_bus_speed_120 = 120,
414 i40e_bus_speed_133 = 133,
415 i40e_bus_speed_2500 = 2500,
416 i40e_bus_speed_5000 = 5000,
417 i40e_bus_speed_8000 = 8000,
418 i40e_bus_speed_reserved
419};
420
421
422enum i40e_bus_width {
423 i40e_bus_width_unknown = 0,
424 i40e_bus_width_pcie_x1 = 1,
425 i40e_bus_width_pcie_x2 = 2,
426 i40e_bus_width_pcie_x4 = 4,
427 i40e_bus_width_pcie_x8 = 8,
428 i40e_bus_width_32 = 32,
429 i40e_bus_width_64 = 64,
430 i40e_bus_width_reserved
431};
432
433
434struct i40e_bus_info {
435 enum i40e_bus_speed speed;
436 enum i40e_bus_width width;
437 enum i40e_bus_type type;
438
439 u16 func;
440 u16 device;
441 u16 lan_id;
442};
443
444
445struct i40e_fc_info {
446 enum i40e_fc_mode current_mode;
447 enum i40e_fc_mode requested_mode;
448};
449
450#define I40E_MAX_TRAFFIC_CLASS 8
451#define I40E_MAX_USER_PRIORITY 8
452#define I40E_DCBX_MAX_APPS 32
453#define I40E_LLDPDU_SIZE 1500
454#define I40E_TLV_STATUS_OPER 0x1
455#define I40E_TLV_STATUS_SYNC 0x2
456#define I40E_TLV_STATUS_ERR 0x4
457#define I40E_CEE_OPER_MAX_APPS 3
458#define I40E_APP_PROTOID_FCOE 0x8906
459#define I40E_APP_PROTOID_ISCSI 0x0cbc
460#define I40E_APP_PROTOID_FIP 0x8914
461#define I40E_APP_SEL_ETHTYPE 0x1
462#define I40E_APP_SEL_TCPIP 0x2
463#define I40E_CEE_APP_SEL_ETHTYPE 0x0
464#define I40E_CEE_APP_SEL_TCPIP 0x1
465
466
467struct i40e_dcb_ets_config {
468 u8 willing;
469 u8 cbs;
470 u8 maxtcs;
471 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
472 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
473 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
474};
475
476
477struct i40e_dcb_pfc_config {
478 u8 willing;
479 u8 mbc;
480 u8 pfccap;
481 u8 pfcenable;
482};
483
484
485struct i40e_dcb_app_priority_table {
486 u8 priority;
487 u8 selector;
488 u16 protocolid;
489};
490
491struct i40e_dcbx_config {
492 u8 dcbx_mode;
493#define I40E_DCBX_MODE_CEE 0x1
494#define I40E_DCBX_MODE_IEEE 0x2
495 u8 app_mode;
496#define I40E_DCBX_APPS_NON_WILLING 0x1
497 u32 numapps;
498 u32 tlv_status;
499 struct i40e_dcb_ets_config etscfg;
500 struct i40e_dcb_ets_config etsrec;
501 struct i40e_dcb_pfc_config pfc;
502 struct i40e_dcb_app_priority_table app[I40E_DCBX_MAX_APPS];
503};
504
505
506struct i40e_hw {
507 u8 __iomem *hw_addr;
508 void *back;
509
510
511 struct i40e_phy_info phy;
512 struct i40e_mac_info mac;
513 struct i40e_bus_info bus;
514 struct i40e_nvm_info nvm;
515 struct i40e_fc_info fc;
516
517
518 u16 device_id;
519 u16 vendor_id;
520 u16 subsystem_device_id;
521 u16 subsystem_vendor_id;
522 u8 revision_id;
523 u8 port;
524 bool adapter_stopped;
525
526
527 struct i40e_hw_capabilities dev_caps;
528 struct i40e_hw_capabilities func_caps;
529
530
531 u16 fdir_shared_filter_count;
532
533
534 u8 pf_id;
535 u16 main_vsi_seid;
536
537
538 u16 partition_id;
539 u16 num_partitions;
540 u16 num_ports;
541
542
543 u16 numa_node;
544
545
546 struct i40e_adminq_info aq;
547
548
549 enum i40e_nvmupd_state nvmupd_state;
550 struct i40e_aq_desc nvm_wb_desc;
551 struct i40e_virt_mem nvm_buff;
552
553
554 struct i40e_hmc_info hmc;
555
556
557 u16 dcbx_status;
558
559
560 struct i40e_dcbx_config local_dcbx_config;
561 struct i40e_dcbx_config remote_dcbx_config;
562 struct i40e_dcbx_config desired_dcbx_config;
563
564#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
565 u64 flags;
566
567
568 u32 debug_mask;
569 char err_str[16];
570};
571
572static inline bool i40e_is_vf(struct i40e_hw *hw)
573{
574 return (hw->mac.type == I40E_MAC_VF ||
575 hw->mac.type == I40E_MAC_X722_VF);
576}
577
578struct i40e_driver_version {
579 u8 major_version;
580 u8 minor_version;
581 u8 build_version;
582 u8 subbuild_version;
583 u8 driver_string[32];
584};
585
586
587union i40e_16byte_rx_desc {
588 struct {
589 __le64 pkt_addr;
590 __le64 hdr_addr;
591 } read;
592 struct {
593 struct {
594 struct {
595 union {
596 __le16 mirroring_status;
597 __le16 fcoe_ctx_id;
598 } mirr_fcoe;
599 __le16 l2tag1;
600 } lo_dword;
601 union {
602 __le32 rss;
603 __le32 fd_id;
604 __le32 fcoe_param;
605 } hi_dword;
606 } qword0;
607 struct {
608
609 __le64 status_error_len;
610 } qword1;
611 } wb;
612};
613
614union i40e_32byte_rx_desc {
615 struct {
616 __le64 pkt_addr;
617 __le64 hdr_addr;
618
619 __le64 rsvd1;
620 __le64 rsvd2;
621 } read;
622 struct {
623 struct {
624 struct {
625 union {
626 __le16 mirroring_status;
627 __le16 fcoe_ctx_id;
628 } mirr_fcoe;
629 __le16 l2tag1;
630 } lo_dword;
631 union {
632 __le32 rss;
633 __le32 fcoe_param;
634
635
636
637 __le32 fd_id;
638 } hi_dword;
639 } qword0;
640 struct {
641
642 __le64 status_error_len;
643 } qword1;
644 struct {
645 __le16 ext_status;
646 __le16 rsvd;
647 __le16 l2tag2_1;
648 __le16 l2tag2_2;
649 } qword2;
650 struct {
651 union {
652 __le32 flex_bytes_lo;
653 __le32 pe_status;
654 } lo_dword;
655 union {
656 __le32 flex_bytes_hi;
657 __le32 fd_id;
658 } hi_dword;
659 } qword3;
660 } wb;
661};
662
663enum i40e_rx_desc_status_bits {
664
665 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
666 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
667 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
668 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
669 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
670 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5,
671 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
672
673 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
674 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9,
675 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
676 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12,
677 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
678 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
679 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16,
680
681
682
683 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
684 I40E_RX_DESC_STATUS_LAST
685};
686
687#define I40E_RXD_QW1_STATUS_SHIFT 0
688#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
689 << I40E_RXD_QW1_STATUS_SHIFT)
690
691#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
692#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
693 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
694
695#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
696#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
697 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
698
699enum i40e_rx_desc_fltstat_values {
700 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
701 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1,
702 I40E_RX_DESC_FLTSTAT_RSV = 2,
703 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
704};
705
706#define I40E_RXD_QW1_ERROR_SHIFT 19
707#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
708
709enum i40e_rx_desc_error_bits {
710
711 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
712 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
713 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
714 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3,
715 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
716 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
717 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
718 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
719 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
720};
721
722enum i40e_rx_desc_error_l3l4e_fcoe_masks {
723 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
724 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
725 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
726 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
727 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
728};
729
730#define I40E_RXD_QW1_PTYPE_SHIFT 30
731#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
732
733
734enum i40e_rx_l2_ptype {
735 I40E_RX_PTYPE_L2_RESERVED = 0,
736 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
737 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
738 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
739 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
740 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
741 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
742 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
743 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
744 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
745 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
746 I40E_RX_PTYPE_L2_ARP = 11,
747 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
748 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
749 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
750 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
751 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
752 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
753 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
754 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
755 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
756 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
757 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
758 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
759 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
760 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
761};
762
763struct i40e_rx_ptype_decoded {
764 u32 ptype:8;
765 u32 known:1;
766 u32 outer_ip:1;
767 u32 outer_ip_ver:1;
768 u32 outer_frag:1;
769 u32 tunnel_type:3;
770 u32 tunnel_end_prot:2;
771 u32 tunnel_end_frag:1;
772 u32 inner_prot:4;
773 u32 payload_layer:3;
774};
775
776enum i40e_rx_ptype_outer_ip {
777 I40E_RX_PTYPE_OUTER_L2 = 0,
778 I40E_RX_PTYPE_OUTER_IP = 1
779};
780
781enum i40e_rx_ptype_outer_ip_ver {
782 I40E_RX_PTYPE_OUTER_NONE = 0,
783 I40E_RX_PTYPE_OUTER_IPV4 = 0,
784 I40E_RX_PTYPE_OUTER_IPV6 = 1
785};
786
787enum i40e_rx_ptype_outer_fragmented {
788 I40E_RX_PTYPE_NOT_FRAG = 0,
789 I40E_RX_PTYPE_FRAG = 1
790};
791
792enum i40e_rx_ptype_tunnel_type {
793 I40E_RX_PTYPE_TUNNEL_NONE = 0,
794 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
795 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
796 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
797 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
798};
799
800enum i40e_rx_ptype_tunnel_end_prot {
801 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
802 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
803 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
804};
805
806enum i40e_rx_ptype_inner_prot {
807 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
808 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
809 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
810 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
811 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
812 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
813};
814
815enum i40e_rx_ptype_payload_layer {
816 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
817 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
818 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
819 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
820};
821
822#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
823#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
824 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
825
826#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
827#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
828 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
829
830#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
831#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
832
833enum i40e_rx_desc_ext_status_bits {
834
835 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
836 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
837 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2,
838 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4,
839 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
840 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
841 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
842};
843
844enum i40e_rx_desc_pe_status_bits {
845
846 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0,
847 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0,
848 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16,
849 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
850 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
851 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
852 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
853 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
854 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
855};
856
857#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
858#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
859
860#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
861#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
862 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
863
864#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
865#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
866 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
867
868enum i40e_rx_prog_status_desc_status_bits {
869
870 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
871 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2
872};
873
874enum i40e_rx_prog_status_desc_prog_id_masks {
875 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
876 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
877 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
878};
879
880enum i40e_rx_prog_status_desc_error_bits {
881
882 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
883 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
884 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
885 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
886};
887
888
889struct i40e_tx_desc {
890 __le64 buffer_addr;
891 __le64 cmd_type_offset_bsz;
892};
893
894#define I40E_TXD_QW1_DTYPE_SHIFT 0
895#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
896
897enum i40e_tx_desc_dtype_value {
898 I40E_TX_DESC_DTYPE_DATA = 0x0,
899 I40E_TX_DESC_DTYPE_NOP = 0x1,
900 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
901 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
902 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
903 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
904 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
905 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
906 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
907 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
908};
909
910#define I40E_TXD_QW1_CMD_SHIFT 4
911#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
912
913enum i40e_tx_desc_cmd_bits {
914 I40E_TX_DESC_CMD_EOP = 0x0001,
915 I40E_TX_DESC_CMD_RS = 0x0002,
916 I40E_TX_DESC_CMD_ICRC = 0x0004,
917 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
918 I40E_TX_DESC_CMD_DUMMY = 0x0010,
919 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000,
920 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020,
921 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040,
922 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060,
923 I40E_TX_DESC_CMD_FCOET = 0x0080,
924 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000,
925 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100,
926 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200,
927 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300,
928 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000,
929 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100,
930 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200,
931 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300,
932};
933
934#define I40E_TXD_QW1_OFFSET_SHIFT 16
935#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
936 I40E_TXD_QW1_OFFSET_SHIFT)
937
938enum i40e_tx_desc_length_fields {
939
940 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0,
941 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7,
942 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14
943};
944
945#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
946#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
947 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
948
949#define I40E_TXD_QW1_L2TAG1_SHIFT 48
950#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
951
952
953struct i40e_tx_context_desc {
954 __le32 tunneling_params;
955 __le16 l2tag2;
956 __le16 rsvd;
957 __le64 type_cmd_tso_mss;
958};
959
960#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
961#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
962
963#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
964#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
965
966enum i40e_tx_ctx_desc_cmd_bits {
967 I40E_TX_CTX_DESC_TSO = 0x01,
968 I40E_TX_CTX_DESC_TSYN = 0x02,
969 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
970 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
971 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
972 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
973 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
974 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
975 I40E_TX_CTX_DESC_SWPE = 0x40
976};
977
978#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
979#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
980 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
981
982#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
983#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
984 I40E_TXD_CTX_QW1_MSS_SHIFT)
985
986#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
987#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
988
989#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
990#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
991 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
992
993enum i40e_tx_ctx_desc_eipt_offload {
994 I40E_TX_CTX_EXT_IP_NONE = 0x0,
995 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
996 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
997 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
998};
999
1000#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
1001#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1002 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1003
1004#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
1005#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1006
1007#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
1008#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
1009
1010#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
1011#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
1012 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1013
1014#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
1015
1016#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
1017#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
1018 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
1019
1020#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
1021#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
1022 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
1023
1024#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
1025#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
1026struct i40e_filter_program_desc {
1027 __le32 qindex_flex_ptype_vsi;
1028 __le32 rsvd;
1029 __le32 dtype_cmd_cntindex;
1030 __le32 fd_id;
1031};
1032#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
1033#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
1034 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
1035#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1036#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
1037 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1038#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
1039#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
1040 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
1041
1042
1043enum i40e_filter_pctype {
1044
1045
1046
1047 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
1048 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
1049 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
1050 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
1051 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
1052 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
1053 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
1054 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
1055
1056
1057
1058 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1059 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
1060 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
1061 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
1062 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1063 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1064 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1065 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1066
1067 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1068 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1069 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1070
1071 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1072};
1073
1074enum i40e_filter_program_desc_dest {
1075 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1076 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1077 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1078};
1079
1080enum i40e_filter_program_desc_fd_status {
1081 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1082 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1083 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1084 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1085};
1086
1087#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
1088#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1089 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1090
1091#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1092#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1093 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1094
1095#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1096#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1097
1098enum i40e_filter_program_desc_pcmd {
1099 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1100 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1101};
1102
1103#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1104#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1105
1106#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1107#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1108
1109#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1110 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1111#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1112 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1113
1114#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1115 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1116#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1117
1118#define I40E_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
1119 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1120#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
1121
1122#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1123#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1124 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1125
1126enum i40e_filter_type {
1127 I40E_FLOW_DIRECTOR_FLTR = 0,
1128 I40E_PE_QUAD_HASH_FLTR = 1,
1129 I40E_ETHERTYPE_FLTR,
1130 I40E_FCOE_CTX_FLTR,
1131 I40E_MAC_VLAN_FLTR,
1132 I40E_HASH_FLTR
1133};
1134
1135struct i40e_vsi_context {
1136 u16 seid;
1137 u16 uplink_seid;
1138 u16 vsi_number;
1139 u16 vsis_allocated;
1140 u16 vsis_unallocated;
1141 u16 flags;
1142 u8 pf_num;
1143 u8 vf_num;
1144 u8 connection_type;
1145 struct i40e_aqc_vsi_properties_data info;
1146};
1147
1148struct i40e_veb_context {
1149 u16 seid;
1150 u16 uplink_seid;
1151 u16 veb_number;
1152 u16 vebs_allocated;
1153 u16 vebs_unallocated;
1154 u16 flags;
1155 struct i40e_aqc_get_veb_parameters_completion info;
1156};
1157
1158
1159struct i40e_eth_stats {
1160 u64 rx_bytes;
1161 u64 rx_unicast;
1162 u64 rx_multicast;
1163 u64 rx_broadcast;
1164 u64 rx_discards;
1165 u64 rx_unknown_protocol;
1166 u64 tx_bytes;
1167 u64 tx_unicast;
1168 u64 tx_multicast;
1169 u64 tx_broadcast;
1170 u64 tx_discards;
1171 u64 tx_errors;
1172};
1173
1174
1175struct i40e_veb_tc_stats {
1176 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1177 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1178 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1179 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1180};
1181
1182#ifdef I40E_FCOE
1183
1184struct i40e_fcoe_stats {
1185 u64 rx_fcoe_packets;
1186 u64 rx_fcoe_dwords;
1187 u64 rx_fcoe_dropped;
1188 u64 tx_fcoe_packets;
1189 u64 tx_fcoe_dwords;
1190 u64 fcoe_bad_fccrc;
1191 u64 fcoe_last_error;
1192 u64 fcoe_ddp_count;
1193};
1194
1195
1196#define I40E_FCOE_VF_STAT_OFFSET 0
1197#define I40E_FCOE_PF_STAT_OFFSET 128
1198#define I40E_FCOE_STAT_MAX (I40E_FCOE_PF_STAT_OFFSET + I40E_MAX_PF)
1199
1200#endif
1201
1202struct i40e_hw_port_stats {
1203
1204 struct i40e_eth_stats eth;
1205
1206
1207 u64 tx_dropped_link_down;
1208 u64 crc_errors;
1209 u64 illegal_bytes;
1210 u64 error_bytes;
1211 u64 mac_local_faults;
1212 u64 mac_remote_faults;
1213 u64 rx_length_errors;
1214 u64 link_xon_rx;
1215 u64 link_xoff_rx;
1216 u64 priority_xon_rx[8];
1217 u64 priority_xoff_rx[8];
1218 u64 link_xon_tx;
1219 u64 link_xoff_tx;
1220 u64 priority_xon_tx[8];
1221 u64 priority_xoff_tx[8];
1222 u64 priority_xon_2_xoff[8];
1223 u64 rx_size_64;
1224 u64 rx_size_127;
1225 u64 rx_size_255;
1226 u64 rx_size_511;
1227 u64 rx_size_1023;
1228 u64 rx_size_1522;
1229 u64 rx_size_big;
1230 u64 rx_undersize;
1231 u64 rx_fragments;
1232 u64 rx_oversize;
1233 u64 rx_jabber;
1234 u64 tx_size_64;
1235 u64 tx_size_127;
1236 u64 tx_size_255;
1237 u64 tx_size_511;
1238 u64 tx_size_1023;
1239 u64 tx_size_1522;
1240 u64 tx_size_big;
1241 u64 mac_short_packet_dropped;
1242 u64 checksum_error;
1243
1244 u64 fd_atr_match;
1245 u64 fd_sb_match;
1246 u64 fd_atr_tunnel_match;
1247 u32 fd_atr_status;
1248 u32 fd_sb_status;
1249
1250 u32 tx_lpi_status;
1251 u32 rx_lpi_status;
1252 u64 tx_lpi_count;
1253 u64 rx_lpi_count;
1254};
1255
1256
1257#define I40E_SR_NVM_CONTROL_WORD 0x00
1258#define I40E_SR_EMP_MODULE_PTR 0x0F
1259#define I40E_SR_PBA_FLAGS 0x15
1260#define I40E_SR_PBA_BLOCK_PTR 0x16
1261#define I40E_SR_BOOT_CONFIG_PTR 0x17
1262#define I40E_NVM_OEM_VER_OFF 0x83
1263#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
1264#define I40E_SR_NVM_WAKE_ON_LAN 0x19
1265#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1266#define I40E_SR_NVM_EETRACK_LO 0x2D
1267#define I40E_SR_NVM_EETRACK_HI 0x2E
1268#define I40E_SR_VPD_PTR 0x2F
1269#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1270#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1271
1272
1273#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1274#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1275#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1276#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1277
1278
1279#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1280#define I40E_SR_WORDS_IN_1KB 512
1281
1282
1283
1284#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1285
1286#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1287
1288#ifdef I40E_FCOE
1289
1290
1291enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1292 I40E_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00,
1293 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01,
1294 I40E_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05,
1295 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02,
1296 I40E_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06,
1297 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03,
1298 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07,
1299 I40E_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08,
1300 I40E_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09,
1301 I40E_FCOE_TX_CTX_DESC_RELOFF = 0x10,
1302 I40E_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
1303 I40E_FCOE_TX_CTX_DESC_DIFENA = 0x40,
1304 I40E_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
1305};
1306
1307
1308struct i40e_fcoe_ddp_context_desc {
1309 __le64 rsvd;
1310 __le64 type_cmd_foff_lsize;
1311};
1312
1313#define I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
1314#define I40E_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
1315 I40E_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1316
1317#define I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1318#define I40E_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
1319 I40E_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1320
1321enum i40e_fcoe_ddp_ctx_desc_cmd_bits {
1322 I40E_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00,
1323 I40E_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01,
1324 I40E_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02,
1325 I40E_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03,
1326 I40E_FCOE_DDP_CTX_DESC_DIFENA = 0x04,
1327 I40E_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08,
1328};
1329
1330#define I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
1331#define I40E_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1332 I40E_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1333
1334#define I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
1335#define I40E_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
1336 I40E_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1337
1338
1339struct i40e_fcoe_queue_context_desc {
1340 __le64 dmaindx_fbase;
1341 __le64 flen_tph;
1342};
1343
1344#define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
1345#define I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
1346 I40E_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1347
1348#define I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
1349#define I40E_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
1350 I40E_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1351
1352#define I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
1353#define I40E_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
1354 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1355
1356#define I40E_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
1357#define I40E_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
1358 I40E_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1359
1360enum i40e_fcoe_queue_ctx_desc_tph_bits {
1361 I40E_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
1362 I40E_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
1363};
1364
1365#define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
1366#define I40E_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
1367 I40E_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1368
1369
1370struct i40e_fcoe_filter_context_desc {
1371 __le32 param;
1372 __le16 seqn;
1373
1374
1375 __le16 rsvd_dmaindx;
1376
1377
1378 __le64 flags_rsvd_lanq;
1379};
1380
1381#define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
1382#define I40E_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
1383 I40E_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1384
1385enum i40e_fcoe_filter_ctx_desc_flags_bits {
1386 I40E_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
1387 I40E_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
1388 I40E_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
1389 I40E_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
1390 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
1391 I40E_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
1392};
1393
1394#define I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
1395#define I40E_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
1396 I40E_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1397
1398#define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
1399#define I40E_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
1400 I40E_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1401
1402#define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
1403#define I40E_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
1404 I40E_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1405
1406#endif
1407enum i40e_switch_element_types {
1408 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1409 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1410 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1411 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1412 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1413 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1414 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1415 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1416 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1417};
1418
1419
1420enum i40e_ether_type_index {
1421 I40E_ETHER_TYPE_1588 = 0,
1422 I40E_ETHER_TYPE_FIP = 1,
1423 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1424 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1425 I40E_ETHER_TYPE_LLDP = 4,
1426 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1427 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1428 I40E_ETHER_TYPE_QCN_CNM = 7,
1429 I40E_ETHER_TYPE_8021X = 8,
1430 I40E_ETHER_TYPE_ARP = 9,
1431 I40E_ETHER_TYPE_RSV1 = 10,
1432 I40E_ETHER_TYPE_RSV2 = 11,
1433};
1434
1435
1436#define I40E_HASH_FILTER_BASE_SIZE 1024
1437
1438enum i40e_hash_filter_size {
1439 I40E_HASH_FILTER_SIZE_1K = 0,
1440 I40E_HASH_FILTER_SIZE_2K = 1,
1441 I40E_HASH_FILTER_SIZE_4K = 2,
1442 I40E_HASH_FILTER_SIZE_8K = 3,
1443 I40E_HASH_FILTER_SIZE_16K = 4,
1444 I40E_HASH_FILTER_SIZE_32K = 5,
1445 I40E_HASH_FILTER_SIZE_64K = 6,
1446 I40E_HASH_FILTER_SIZE_128K = 7,
1447 I40E_HASH_FILTER_SIZE_256K = 8,
1448 I40E_HASH_FILTER_SIZE_512K = 9,
1449 I40E_HASH_FILTER_SIZE_1M = 10,
1450};
1451
1452
1453#define I40E_DMA_CNTX_BASE_SIZE 512
1454
1455enum i40e_dma_cntx_size {
1456 I40E_DMA_CNTX_SIZE_512 = 0,
1457 I40E_DMA_CNTX_SIZE_1K = 1,
1458 I40E_DMA_CNTX_SIZE_2K = 2,
1459 I40E_DMA_CNTX_SIZE_4K = 3,
1460 I40E_DMA_CNTX_SIZE_8K = 4,
1461 I40E_DMA_CNTX_SIZE_16K = 5,
1462 I40E_DMA_CNTX_SIZE_32K = 6,
1463 I40E_DMA_CNTX_SIZE_64K = 7,
1464 I40E_DMA_CNTX_SIZE_128K = 8,
1465 I40E_DMA_CNTX_SIZE_256K = 9,
1466};
1467
1468
1469enum i40e_hash_lut_size {
1470 I40E_HASH_LUT_SIZE_128 = 0,
1471 I40E_HASH_LUT_SIZE_512 = 1,
1472};
1473
1474
1475struct i40e_filter_control_settings {
1476
1477 enum i40e_hash_filter_size pe_filt_num;
1478
1479 enum i40e_dma_cntx_size pe_cntx_num;
1480
1481 enum i40e_hash_filter_size fcoe_filt_num;
1482
1483 enum i40e_dma_cntx_size fcoe_cntx_num;
1484
1485 enum i40e_hash_lut_size hash_lut_size;
1486
1487 bool enable_fdir;
1488
1489 bool enable_ethtype;
1490
1491 bool enable_macvlan;
1492};
1493
1494
1495struct i40e_control_filter_stats {
1496 u16 mac_etype_used;
1497 u16 etype_used;
1498 u16 mac_etype_free;
1499 u16 etype_free;
1500};
1501
1502enum i40e_reset_type {
1503 I40E_RESET_POR = 0,
1504 I40E_RESET_CORER = 1,
1505 I40E_RESET_GLOBR = 2,
1506 I40E_RESET_EMPR = 3,
1507};
1508
1509
1510#define I40E_NVM_LLDP_CFG_PTR 0xD
1511struct i40e_lldp_variables {
1512 u16 length;
1513 u16 adminstatus;
1514 u16 msgfasttx;
1515 u16 msgtxinterval;
1516 u16 txparams;
1517 u16 timers;
1518 u16 crc8;
1519};
1520
1521
1522#define I40E_ALT_STRUCT_FIRST_PF_OFFSET 0
1523#define I40E_ALT_STRUCT_DWORDS_PER_PF 64
1524#define I40E_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET 0xD
1525#define I40E_ALT_STRUCT_USER_PRIORITY_OFFSET 0xC
1526#define I40E_ALT_STRUCT_MIN_BW_OFFSET 0xE
1527#define I40E_ALT_STRUCT_MAX_BW_OFFSET 0xF
1528
1529
1530#define I40E_ALT_BW_VALUE_MASK 0xFF
1531#define I40E_ALT_BW_RELATIVE_MASK 0x40000000
1532#define I40E_ALT_BW_VALID_MASK 0x80000000
1533
1534
1535#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1536#endif
1537
