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18#include <linux/module.h>
19#include <linux/device.h>
20#include <linux/pci.h>
21#include <linux/ptp_classify.h>
22
23#include "igb.h"
24
25#define INCVALUE_MASK 0x7fffffff
26#define ISGN 0x80000000
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70#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
71#define IGB_PTP_TX_TIMEOUT (HZ * 15)
72#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT)
73#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1)
74#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
75#define IGB_NBITS_82580 40
76
77static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
78
79
80static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc)
81{
82 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
83 struct e1000_hw *hw = &igb->hw;
84 u64 val;
85 u32 lo, hi;
86
87 lo = rd32(E1000_SYSTIML);
88 hi = rd32(E1000_SYSTIMH);
89
90 val = ((u64) hi) << 32;
91 val |= lo;
92
93 return val;
94}
95
96
97static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc)
98{
99 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
100 struct e1000_hw *hw = &igb->hw;
101 u32 lo, hi;
102 u64 val;
103
104
105
106
107
108 rd32(E1000_SYSTIMR);
109 lo = rd32(E1000_SYSTIML);
110 hi = rd32(E1000_SYSTIMH);
111
112 val = ((u64) hi) << 32;
113 val |= lo;
114
115 return val;
116}
117
118
119static void igb_ptp_read_i210(struct igb_adapter *adapter,
120 struct timespec64 *ts)
121{
122 struct e1000_hw *hw = &adapter->hw;
123 u32 sec, nsec;
124
125
126
127
128
129 rd32(E1000_SYSTIMR);
130 nsec = rd32(E1000_SYSTIML);
131 sec = rd32(E1000_SYSTIMH);
132
133 ts->tv_sec = sec;
134 ts->tv_nsec = nsec;
135}
136
137static void igb_ptp_write_i210(struct igb_adapter *adapter,
138 const struct timespec64 *ts)
139{
140 struct e1000_hw *hw = &adapter->hw;
141
142
143
144
145 wr32(E1000_SYSTIML, ts->tv_nsec);
146 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
147}
148
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164
165
166static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
167 struct skb_shared_hwtstamps *hwtstamps,
168 u64 systim)
169{
170 unsigned long flags;
171 u64 ns;
172
173 switch (adapter->hw.mac.type) {
174 case e1000_82576:
175 case e1000_82580:
176 case e1000_i354:
177 case e1000_i350:
178 spin_lock_irqsave(&adapter->tmreg_lock, flags);
179
180 ns = timecounter_cyc2time(&adapter->tc, systim);
181
182 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
183
184 memset(hwtstamps, 0, sizeof(*hwtstamps));
185 hwtstamps->hwtstamp = ns_to_ktime(ns);
186 break;
187 case e1000_i210:
188 case e1000_i211:
189 memset(hwtstamps, 0, sizeof(*hwtstamps));
190
191 hwtstamps->hwtstamp = ktime_set(systim >> 32,
192 systim & 0xFFFFFFFF);
193 break;
194 default:
195 break;
196 }
197}
198
199
200static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
201{
202 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
203 ptp_caps);
204 struct e1000_hw *hw = &igb->hw;
205 int neg_adj = 0;
206 u64 rate;
207 u32 incvalue;
208
209 if (ppb < 0) {
210 neg_adj = 1;
211 ppb = -ppb;
212 }
213 rate = ppb;
214 rate <<= 14;
215 rate = div_u64(rate, 1953125);
216
217 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
218
219 if (neg_adj)
220 incvalue -= rate;
221 else
222 incvalue += rate;
223
224 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
225
226 return 0;
227}
228
229static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb)
230{
231 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
232 ptp_caps);
233 struct e1000_hw *hw = &igb->hw;
234 int neg_adj = 0;
235 u64 rate;
236 u32 inca;
237
238 if (ppb < 0) {
239 neg_adj = 1;
240 ppb = -ppb;
241 }
242 rate = ppb;
243 rate <<= 26;
244 rate = div_u64(rate, 1953125);
245
246 inca = rate & INCVALUE_MASK;
247 if (neg_adj)
248 inca |= ISGN;
249
250 wr32(E1000_TIMINCA, inca);
251
252 return 0;
253}
254
255static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
256{
257 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
258 ptp_caps);
259 unsigned long flags;
260
261 spin_lock_irqsave(&igb->tmreg_lock, flags);
262 timecounter_adjtime(&igb->tc, delta);
263 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
264
265 return 0;
266}
267
268static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
269{
270 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
271 ptp_caps);
272 unsigned long flags;
273 struct timespec64 now, then = ns_to_timespec64(delta);
274
275 spin_lock_irqsave(&igb->tmreg_lock, flags);
276
277 igb_ptp_read_i210(igb, &now);
278 now = timespec64_add(now, then);
279 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
280
281 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
282
283 return 0;
284}
285
286static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
287 struct timespec64 *ts)
288{
289 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
290 ptp_caps);
291 unsigned long flags;
292 u64 ns;
293
294 spin_lock_irqsave(&igb->tmreg_lock, flags);
295
296 ns = timecounter_read(&igb->tc);
297
298 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
299
300 *ts = ns_to_timespec64(ns);
301
302 return 0;
303}
304
305static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
306 struct timespec64 *ts)
307{
308 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
309 ptp_caps);
310 unsigned long flags;
311
312 spin_lock_irqsave(&igb->tmreg_lock, flags);
313
314 igb_ptp_read_i210(igb, ts);
315
316 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
317
318 return 0;
319}
320
321static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
322 const struct timespec64 *ts)
323{
324 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
325 ptp_caps);
326 unsigned long flags;
327 u64 ns;
328
329 ns = timespec64_to_ns(ts);
330
331 spin_lock_irqsave(&igb->tmreg_lock, flags);
332
333 timecounter_init(&igb->tc, &igb->cc, ns);
334
335 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
336
337 return 0;
338}
339
340static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
341 const struct timespec64 *ts)
342{
343 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
344 ptp_caps);
345 unsigned long flags;
346
347 spin_lock_irqsave(&igb->tmreg_lock, flags);
348
349 igb_ptp_write_i210(igb, ts);
350
351 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
352
353 return 0;
354}
355
356static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
357{
358 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
359 static const u32 mask[IGB_N_SDP] = {
360 E1000_CTRL_SDP0_DIR,
361 E1000_CTRL_SDP1_DIR,
362 E1000_CTRL_EXT_SDP2_DIR,
363 E1000_CTRL_EXT_SDP3_DIR,
364 };
365
366 if (input)
367 *ptr &= ~mask[pin];
368 else
369 *ptr |= mask[pin];
370}
371
372static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
373{
374 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
375 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
376 };
377 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
378 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
379 };
380 static const u32 ts_sdp_en[IGB_N_SDP] = {
381 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
382 };
383 struct e1000_hw *hw = &igb->hw;
384 u32 ctrl, ctrl_ext, tssdp = 0;
385
386 ctrl = rd32(E1000_CTRL);
387 ctrl_ext = rd32(E1000_CTRL_EXT);
388 tssdp = rd32(E1000_TSSDP);
389
390 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
391
392
393 tssdp &= ~ts_sdp_en[pin];
394
395 if (chan == 1) {
396 tssdp &= ~AUX1_SEL_SDP3;
397 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
398 } else {
399 tssdp &= ~AUX0_SEL_SDP3;
400 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
401 }
402
403 wr32(E1000_TSSDP, tssdp);
404 wr32(E1000_CTRL, ctrl);
405 wr32(E1000_CTRL_EXT, ctrl_ext);
406}
407
408static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
409{
410 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
411 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
412 };
413 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
414 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
415 };
416 static const u32 ts_sdp_en[IGB_N_SDP] = {
417 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
418 };
419 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
420 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
421 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
422 };
423 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
424 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
425 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
426 };
427 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
428 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
429 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
430 };
431 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
432 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
433 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
434 };
435 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
436 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
437 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
438 };
439 struct e1000_hw *hw = &igb->hw;
440 u32 ctrl, ctrl_ext, tssdp = 0;
441
442 ctrl = rd32(E1000_CTRL);
443 ctrl_ext = rd32(E1000_CTRL_EXT);
444 tssdp = rd32(E1000_TSSDP);
445
446 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
447
448
449 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
450 tssdp &= ~AUX0_TS_SDP_EN;
451
452 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
453 tssdp &= ~AUX1_TS_SDP_EN;
454
455 tssdp &= ~ts_sdp_sel_clr[pin];
456 if (freq) {
457 if (chan == 1)
458 tssdp |= ts_sdp_sel_fc1[pin];
459 else
460 tssdp |= ts_sdp_sel_fc0[pin];
461 } else {
462 if (chan == 1)
463 tssdp |= ts_sdp_sel_tt1[pin];
464 else
465 tssdp |= ts_sdp_sel_tt0[pin];
466 }
467 tssdp |= ts_sdp_en[pin];
468
469 wr32(E1000_TSSDP, tssdp);
470 wr32(E1000_CTRL, ctrl);
471 wr32(E1000_CTRL_EXT, ctrl_ext);
472}
473
474static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
475 struct ptp_clock_request *rq, int on)
476{
477 struct igb_adapter *igb =
478 container_of(ptp, struct igb_adapter, ptp_caps);
479 struct e1000_hw *hw = &igb->hw;
480 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
481 unsigned long flags;
482 struct timespec64 ts;
483 int use_freq = 0, pin = -1;
484 s64 ns;
485
486 switch (rq->type) {
487 case PTP_CLK_REQ_EXTTS:
488 if (on) {
489 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
490 rq->extts.index);
491 if (pin < 0)
492 return -EBUSY;
493 }
494 if (rq->extts.index == 1) {
495 tsauxc_mask = TSAUXC_EN_TS1;
496 tsim_mask = TSINTR_AUTT1;
497 } else {
498 tsauxc_mask = TSAUXC_EN_TS0;
499 tsim_mask = TSINTR_AUTT0;
500 }
501 spin_lock_irqsave(&igb->tmreg_lock, flags);
502 tsauxc = rd32(E1000_TSAUXC);
503 tsim = rd32(E1000_TSIM);
504 if (on) {
505 igb_pin_extts(igb, rq->extts.index, pin);
506 tsauxc |= tsauxc_mask;
507 tsim |= tsim_mask;
508 } else {
509 tsauxc &= ~tsauxc_mask;
510 tsim &= ~tsim_mask;
511 }
512 wr32(E1000_TSAUXC, tsauxc);
513 wr32(E1000_TSIM, tsim);
514 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
515 return 0;
516
517 case PTP_CLK_REQ_PEROUT:
518 if (on) {
519 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
520 rq->perout.index);
521 if (pin < 0)
522 return -EBUSY;
523 }
524 ts.tv_sec = rq->perout.period.sec;
525 ts.tv_nsec = rq->perout.period.nsec;
526 ns = timespec64_to_ns(&ts);
527 ns = ns >> 1;
528 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
529 (ns == 250000000LL) || (ns == 500000000LL))) {
530 if (ns < 8LL)
531 return -EINVAL;
532 use_freq = 1;
533 }
534 ts = ns_to_timespec64(ns);
535 if (rq->perout.index == 1) {
536 if (use_freq) {
537 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
538 tsim_mask = 0;
539 } else {
540 tsauxc_mask = TSAUXC_EN_TT1;
541 tsim_mask = TSINTR_TT1;
542 }
543 trgttiml = E1000_TRGTTIML1;
544 trgttimh = E1000_TRGTTIMH1;
545 freqout = E1000_FREQOUT1;
546 } else {
547 if (use_freq) {
548 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
549 tsim_mask = 0;
550 } else {
551 tsauxc_mask = TSAUXC_EN_TT0;
552 tsim_mask = TSINTR_TT0;
553 }
554 trgttiml = E1000_TRGTTIML0;
555 trgttimh = E1000_TRGTTIMH0;
556 freqout = E1000_FREQOUT0;
557 }
558 spin_lock_irqsave(&igb->tmreg_lock, flags);
559 tsauxc = rd32(E1000_TSAUXC);
560 tsim = rd32(E1000_TSIM);
561 if (rq->perout.index == 1) {
562 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
563 tsim &= ~TSINTR_TT1;
564 } else {
565 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
566 tsim &= ~TSINTR_TT0;
567 }
568 if (on) {
569 int i = rq->perout.index;
570 igb_pin_perout(igb, i, pin, use_freq);
571 igb->perout[i].start.tv_sec = rq->perout.start.sec;
572 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
573 igb->perout[i].period.tv_sec = ts.tv_sec;
574 igb->perout[i].period.tv_nsec = ts.tv_nsec;
575 wr32(trgttimh, rq->perout.start.sec);
576 wr32(trgttiml, rq->perout.start.nsec);
577 if (use_freq)
578 wr32(freqout, ns);
579 tsauxc |= tsauxc_mask;
580 tsim |= tsim_mask;
581 }
582 wr32(E1000_TSAUXC, tsauxc);
583 wr32(E1000_TSIM, tsim);
584 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
585 return 0;
586
587 case PTP_CLK_REQ_PPS:
588 spin_lock_irqsave(&igb->tmreg_lock, flags);
589 tsim = rd32(E1000_TSIM);
590 if (on)
591 tsim |= TSINTR_SYS_WRAP;
592 else
593 tsim &= ~TSINTR_SYS_WRAP;
594 wr32(E1000_TSIM, tsim);
595 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
596 return 0;
597 }
598
599 return -EOPNOTSUPP;
600}
601
602static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
603 struct ptp_clock_request *rq, int on)
604{
605 return -EOPNOTSUPP;
606}
607
608static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
609 enum ptp_pin_function func, unsigned int chan)
610{
611 switch (func) {
612 case PTP_PF_NONE:
613 case PTP_PF_EXTTS:
614 case PTP_PF_PEROUT:
615 break;
616 case PTP_PF_PHYSYNC:
617 return -1;
618 }
619 return 0;
620}
621
622
623
624
625
626
627
628
629static void igb_ptp_tx_work(struct work_struct *work)
630{
631 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
632 ptp_tx_work);
633 struct e1000_hw *hw = &adapter->hw;
634 u32 tsynctxctl;
635
636 if (!adapter->ptp_tx_skb)
637 return;
638
639 if (time_is_before_jiffies(adapter->ptp_tx_start +
640 IGB_PTP_TX_TIMEOUT)) {
641 dev_kfree_skb_any(adapter->ptp_tx_skb);
642 adapter->ptp_tx_skb = NULL;
643 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
644 adapter->tx_hwtstamp_timeouts++;
645 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
646 return;
647 }
648
649 tsynctxctl = rd32(E1000_TSYNCTXCTL);
650 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
651 igb_ptp_tx_hwtstamp(adapter);
652 else
653
654 schedule_work(&adapter->ptp_tx_work);
655}
656
657static void igb_ptp_overflow_check(struct work_struct *work)
658{
659 struct igb_adapter *igb =
660 container_of(work, struct igb_adapter, ptp_overflow_work.work);
661 struct timespec64 ts;
662
663 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
664
665 pr_debug("igb overflow check at %lld.%09lu\n",
666 (long long) ts.tv_sec, ts.tv_nsec);
667
668 schedule_delayed_work(&igb->ptp_overflow_work,
669 IGB_SYSTIM_OVERFLOW_PERIOD);
670}
671
672
673
674
675
676
677
678
679
680
681void igb_ptp_rx_hang(struct igb_adapter *adapter)
682{
683 struct e1000_hw *hw = &adapter->hw;
684 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
685 unsigned long rx_event;
686
687 if (hw->mac.type != e1000_82576)
688 return;
689
690
691
692
693 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
694 adapter->last_rx_ptp_check = jiffies;
695 return;
696 }
697
698
699 rx_event = adapter->last_rx_ptp_check;
700 if (time_after(adapter->last_rx_timestamp, rx_event))
701 rx_event = adapter->last_rx_timestamp;
702
703
704 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
705 rd32(E1000_RXSTMPH);
706 adapter->last_rx_ptp_check = jiffies;
707 adapter->rx_hwtstamp_cleared++;
708 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
709 }
710}
711
712
713
714
715
716
717
718
719
720static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
721{
722 struct e1000_hw *hw = &adapter->hw;
723 struct skb_shared_hwtstamps shhwtstamps;
724 u64 regval;
725
726 regval = rd32(E1000_TXSTMPL);
727 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
728
729 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
730 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps);
731 dev_kfree_skb_any(adapter->ptp_tx_skb);
732 adapter->ptp_tx_skb = NULL;
733 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
734}
735
736
737
738
739
740
741
742
743
744
745
746void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector,
747 unsigned char *va,
748 struct sk_buff *skb)
749{
750 __le64 *regval = (__le64 *)va;
751
752
753
754
755
756 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
757 le64_to_cpu(regval[1]));
758}
759
760
761
762
763
764
765
766
767
768void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
769 struct sk_buff *skb)
770{
771 struct igb_adapter *adapter = q_vector->adapter;
772 struct e1000_hw *hw = &adapter->hw;
773 u64 regval;
774
775
776
777
778
779
780
781
782
783
784
785 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
786 return;
787
788 regval = rd32(E1000_RXSTMPL);
789 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
790
791 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
792
793
794
795
796 adapter->last_rx_timestamp = jiffies;
797}
798
799
800
801
802
803
804
805
806
807
808int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
809{
810 struct igb_adapter *adapter = netdev_priv(netdev);
811 struct hwtstamp_config *config = &adapter->tstamp_config;
812
813 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
814 -EFAULT : 0;
815}
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
835 struct hwtstamp_config *config)
836{
837 struct e1000_hw *hw = &adapter->hw;
838 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
839 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
840 u32 tsync_rx_cfg = 0;
841 bool is_l4 = false;
842 bool is_l2 = false;
843 u32 regval;
844
845
846 if (config->flags)
847 return -EINVAL;
848
849 switch (config->tx_type) {
850 case HWTSTAMP_TX_OFF:
851 tsync_tx_ctl = 0;
852 case HWTSTAMP_TX_ON:
853 break;
854 default:
855 return -ERANGE;
856 }
857
858 switch (config->rx_filter) {
859 case HWTSTAMP_FILTER_NONE:
860 tsync_rx_ctl = 0;
861 break;
862 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
863 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
864 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
865 is_l4 = true;
866 break;
867 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
868 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
869 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
870 is_l4 = true;
871 break;
872 case HWTSTAMP_FILTER_PTP_V2_EVENT:
873 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
874 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
875 case HWTSTAMP_FILTER_PTP_V2_SYNC:
876 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
877 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
878 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
879 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
880 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
881 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
882 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
883 is_l2 = true;
884 is_l4 = true;
885 break;
886 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
887 case HWTSTAMP_FILTER_ALL:
888
889
890
891 if (hw->mac.type != e1000_82576) {
892 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
893 config->rx_filter = HWTSTAMP_FILTER_ALL;
894 break;
895 }
896
897 default:
898 config->rx_filter = HWTSTAMP_FILTER_NONE;
899 return -ERANGE;
900 }
901
902 if (hw->mac.type == e1000_82575) {
903 if (tsync_rx_ctl | tsync_tx_ctl)
904 return -EINVAL;
905 return 0;
906 }
907
908
909
910
911
912 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
913 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
914 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
915 config->rx_filter = HWTSTAMP_FILTER_ALL;
916 is_l2 = true;
917 is_l4 = true;
918
919 if ((hw->mac.type == e1000_i210) ||
920 (hw->mac.type == e1000_i211)) {
921 regval = rd32(E1000_RXPBS);
922 regval |= E1000_RXPBS_CFG_TS_EN;
923 wr32(E1000_RXPBS, regval);
924 }
925 }
926
927
928 regval = rd32(E1000_TSYNCTXCTL);
929 regval &= ~E1000_TSYNCTXCTL_ENABLED;
930 regval |= tsync_tx_ctl;
931 wr32(E1000_TSYNCTXCTL, regval);
932
933
934 regval = rd32(E1000_TSYNCRXCTL);
935 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
936 regval |= tsync_rx_ctl;
937 wr32(E1000_TSYNCRXCTL, regval);
938
939
940 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
941
942
943 if (is_l2)
944 wr32(E1000_ETQF(3),
945 (E1000_ETQF_FILTER_ENABLE |
946 E1000_ETQF_1588 |
947 ETH_P_1588));
948 else
949 wr32(E1000_ETQF(3), 0);
950
951
952 if (is_l4) {
953 u32 ftqf = (IPPROTO_UDP
954 | E1000_FTQF_VF_BP
955 | E1000_FTQF_1588_TIME_STAMP
956 | E1000_FTQF_MASK);
957 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
958
959 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
960 wr32(E1000_IMIREXT(3),
961 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
962 if (hw->mac.type == e1000_82576) {
963
964 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
965 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
966 }
967 wr32(E1000_FTQF(3), ftqf);
968 } else {
969 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
970 }
971 wrfl();
972
973
974 regval = rd32(E1000_TXSTMPL);
975 regval = rd32(E1000_TXSTMPH);
976 regval = rd32(E1000_RXSTMPL);
977 regval = rd32(E1000_RXSTMPH);
978
979 return 0;
980}
981
982
983
984
985
986
987
988int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
989{
990 struct igb_adapter *adapter = netdev_priv(netdev);
991 struct hwtstamp_config config;
992 int err;
993
994 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
995 return -EFAULT;
996
997 err = igb_ptp_set_timestamp_mode(adapter, &config);
998 if (err)
999 return err;
1000
1001
1002 memcpy(&adapter->tstamp_config, &config,
1003 sizeof(adapter->tstamp_config));
1004
1005 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1006 -EFAULT : 0;
1007}
1008
1009void igb_ptp_init(struct igb_adapter *adapter)
1010{
1011 struct e1000_hw *hw = &adapter->hw;
1012 struct net_device *netdev = adapter->netdev;
1013 int i;
1014
1015 switch (hw->mac.type) {
1016 case e1000_82576:
1017 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1018 adapter->ptp_caps.owner = THIS_MODULE;
1019 adapter->ptp_caps.max_adj = 999999881;
1020 adapter->ptp_caps.n_ext_ts = 0;
1021 adapter->ptp_caps.pps = 0;
1022 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1023 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1024 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1025 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1026 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1027 adapter->cc.read = igb_ptp_read_82576;
1028 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1029 adapter->cc.mult = 1;
1030 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1031
1032 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1033 break;
1034 case e1000_82580:
1035 case e1000_i354:
1036 case e1000_i350:
1037 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1038 adapter->ptp_caps.owner = THIS_MODULE;
1039 adapter->ptp_caps.max_adj = 62499999;
1040 adapter->ptp_caps.n_ext_ts = 0;
1041 adapter->ptp_caps.pps = 0;
1042 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1043 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1044 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1045 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1046 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1047 adapter->cc.read = igb_ptp_read_82580;
1048 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1049 adapter->cc.mult = 1;
1050 adapter->cc.shift = 0;
1051
1052 wr32(E1000_TSAUXC, 0x0);
1053 break;
1054 case e1000_i210:
1055 case e1000_i211:
1056 for (i = 0; i < IGB_N_SDP; i++) {
1057 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1058
1059 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1060 ppd->index = i;
1061 ppd->func = PTP_PF_NONE;
1062 }
1063 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1064 adapter->ptp_caps.owner = THIS_MODULE;
1065 adapter->ptp_caps.max_adj = 62499999;
1066 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1067 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1068 adapter->ptp_caps.n_pins = IGB_N_SDP;
1069 adapter->ptp_caps.pps = 1;
1070 adapter->ptp_caps.pin_config = adapter->sdp_config;
1071 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580;
1072 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1073 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1074 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1075 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1076 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1077
1078 wr32(E1000_TSAUXC, 0x0);
1079 break;
1080 default:
1081 adapter->ptp_clock = NULL;
1082 return;
1083 }
1084
1085 wrfl();
1086
1087 spin_lock_init(&adapter->tmreg_lock);
1088 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1089
1090
1091 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1092 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1093
1094 igb_ptp_settime_i210(&adapter->ptp_caps, &ts);
1095 } else {
1096 timecounter_init(&adapter->tc, &adapter->cc,
1097 ktime_to_ns(ktime_get_real()));
1098
1099 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1100 igb_ptp_overflow_check);
1101
1102 schedule_delayed_work(&adapter->ptp_overflow_work,
1103 IGB_SYSTIM_OVERFLOW_PERIOD);
1104 }
1105
1106
1107 if (hw->mac.type >= e1000_82580) {
1108 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1109 wr32(E1000_IMS, E1000_IMS_TS);
1110 }
1111
1112 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1113 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1114
1115 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1116 &adapter->pdev->dev);
1117 if (IS_ERR(adapter->ptp_clock)) {
1118 adapter->ptp_clock = NULL;
1119 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1120 } else {
1121 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1122 adapter->netdev->name);
1123 adapter->flags |= IGB_FLAG_PTP;
1124 }
1125}
1126
1127
1128
1129
1130
1131
1132
1133void igb_ptp_stop(struct igb_adapter *adapter)
1134{
1135 switch (adapter->hw.mac.type) {
1136 case e1000_82576:
1137 case e1000_82580:
1138 case e1000_i354:
1139 case e1000_i350:
1140 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1141 break;
1142 case e1000_i210:
1143 case e1000_i211:
1144
1145 break;
1146 default:
1147 return;
1148 }
1149
1150 cancel_work_sync(&adapter->ptp_tx_work);
1151 if (adapter->ptp_tx_skb) {
1152 dev_kfree_skb_any(adapter->ptp_tx_skb);
1153 adapter->ptp_tx_skb = NULL;
1154 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1155 }
1156
1157 if (adapter->ptp_clock) {
1158 ptp_clock_unregister(adapter->ptp_clock);
1159 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1160 adapter->netdev->name);
1161 adapter->flags &= ~IGB_FLAG_PTP;
1162 }
1163}
1164
1165
1166
1167
1168
1169
1170
1171void igb_ptp_reset(struct igb_adapter *adapter)
1172{
1173 struct e1000_hw *hw = &adapter->hw;
1174 unsigned long flags;
1175
1176 if (!(adapter->flags & IGB_FLAG_PTP))
1177 return;
1178
1179
1180 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1181
1182 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1183
1184 switch (adapter->hw.mac.type) {
1185 case e1000_82576:
1186
1187 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1188 break;
1189 case e1000_82580:
1190 case e1000_i354:
1191 case e1000_i350:
1192 case e1000_i210:
1193 case e1000_i211:
1194 wr32(E1000_TSAUXC, 0x0);
1195 wr32(E1000_TSSDP, 0x0);
1196 wr32(E1000_TSIM, TSYNC_INTERRUPTS);
1197 wr32(E1000_IMS, E1000_IMS_TS);
1198 break;
1199 default:
1200
1201 goto out;
1202 }
1203
1204
1205 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1206 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1207
1208 igb_ptp_write_i210(adapter, &ts);
1209 } else {
1210 timecounter_init(&adapter->tc, &adapter->cc,
1211 ktime_to_ns(ktime_get_real()));
1212 }
1213out:
1214 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1215}
1216