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29#include <linux/pci.h>
30#include <linux/delay.h>
31#include <linux/sched.h>
32
33#include "ixgbe.h"
34#include "ixgbe_phy.h"
35
36static void ixgbe_i2c_start(struct ixgbe_hw *hw);
37static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
38static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
39static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
40static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
41static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
42static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
43static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
45static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
46static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
47static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
48static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
49static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
50static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
51
52
53
54
55
56
57
58
59static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
60{
61 s32 status;
62
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
64 if (status)
65 return status;
66 return ixgbe_get_i2c_ack(hw);
67}
68
69
70
71
72
73
74
75
76static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
77{
78 s32 status;
79
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
81 if (status)
82 return status;
83
84 return ixgbe_clock_out_i2c_bit(hw, false);
85}
86
87
88
89
90
91
92
93
94static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
95{
96 u16 sum = add1 + add2;
97
98 sum = (sum & 0xFF) + (sum >> 8);
99 return sum & 0xFF;
100}
101
102
103
104
105
106
107
108
109
110
111
112static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
113 u16 reg, u16 *val, bool lock)
114{
115 u32 swfw_mask = hw->phy.phy_semaphore_mask;
116 int max_retry = 10;
117 int retry = 0;
118 u8 csum_byte;
119 u8 high_bits;
120 u8 low_bits;
121 u8 reg_high;
122 u8 csum;
123
124 reg_high = ((reg >> 7) & 0xFE) | 1;
125 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
126 csum = ~csum;
127 do {
128 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
129 return IXGBE_ERR_SWFW_SYNC;
130 ixgbe_i2c_start(hw);
131
132 if (ixgbe_out_i2c_byte_ack(hw, addr))
133 goto fail;
134
135 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
136 goto fail;
137
138 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
139 goto fail;
140
141 if (ixgbe_out_i2c_byte_ack(hw, csum))
142 goto fail;
143
144 ixgbe_i2c_start(hw);
145
146 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
147 goto fail;
148
149 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
150 goto fail;
151
152 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
153 goto fail;
154
155 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
156 goto fail;
157
158 if (ixgbe_clock_out_i2c_bit(hw, false))
159 goto fail;
160 ixgbe_i2c_stop(hw);
161 if (lock)
162 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
163 *val = (high_bits << 8) | low_bits;
164 return 0;
165
166fail:
167 ixgbe_i2c_bus_clear(hw);
168 if (lock)
169 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
170 retry++;
171 if (retry < max_retry)
172 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
173 else
174 hw_dbg(hw, "I2C byte read combined error.\n");
175 } while (retry < max_retry);
176
177 return IXGBE_ERR_I2C;
178}
179
180
181
182
183
184
185
186
187
188
189s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
190 u16 reg, u16 *val)
191{
192 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
193}
194
195
196
197
198
199
200
201
202
203
204s32 ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
205 u16 reg, u16 *val)
206{
207 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
208}
209
210
211
212
213
214
215
216
217
218
219
220static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
221 u16 reg, u16 val, bool lock)
222{
223 u32 swfw_mask = hw->phy.phy_semaphore_mask;
224 int max_retry = 1;
225 int retry = 0;
226 u8 reg_high;
227 u8 csum;
228
229 reg_high = (reg >> 7) & 0xFE;
230 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
231 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
232 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
233 csum = ~csum;
234 do {
235 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
236 return IXGBE_ERR_SWFW_SYNC;
237 ixgbe_i2c_start(hw);
238
239 if (ixgbe_out_i2c_byte_ack(hw, addr))
240 goto fail;
241
242 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
243 goto fail;
244
245 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
246 goto fail;
247
248 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
249 goto fail;
250
251 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
252 goto fail;
253
254 if (ixgbe_out_i2c_byte_ack(hw, csum))
255 goto fail;
256 ixgbe_i2c_stop(hw);
257 if (lock)
258 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
259 return 0;
260
261fail:
262 ixgbe_i2c_bus_clear(hw);
263 if (lock)
264 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
265 retry++;
266 if (retry < max_retry)
267 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
268 else
269 hw_dbg(hw, "I2C byte write combined error.\n");
270 } while (retry < max_retry);
271
272 return IXGBE_ERR_I2C;
273}
274
275
276
277
278
279
280
281
282
283
284s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
285 u8 addr, u16 reg, u16 val)
286{
287 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
288}
289
290
291
292
293
294
295
296
297
298
299s32 ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
300 u8 addr, u16 reg, u16 val)
301{
302 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
303}
304
305
306
307
308
309
310
311s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
312{
313 u32 phy_addr;
314 u16 ext_ability = 0;
315
316 if (!hw->phy.phy_semaphore_mask) {
317 if (hw->bus.lan_id)
318 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
319 else
320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
321 }
322
323 if (hw->phy.type == ixgbe_phy_unknown) {
324 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
325 hw->phy.mdio.prtad = phy_addr;
326 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
327 ixgbe_get_phy_id(hw);
328 hw->phy.type =
329 ixgbe_get_phy_type_from_id(hw->phy.id);
330
331 if (hw->phy.type == ixgbe_phy_unknown) {
332 hw->phy.ops.read_reg(hw,
333 MDIO_PMA_EXTABLE,
334 MDIO_MMD_PMAPMD,
335 &ext_ability);
336 if (ext_ability &
337 (MDIO_PMA_EXTABLE_10GBT |
338 MDIO_PMA_EXTABLE_1000BT))
339 hw->phy.type =
340 ixgbe_phy_cu_unknown;
341 else
342 hw->phy.type =
343 ixgbe_phy_generic;
344 }
345
346 return 0;
347 }
348 }
349
350 hw->phy.mdio.prtad = 0;
351 return IXGBE_ERR_PHY_ADDR_INVALID;
352 }
353 return 0;
354}
355
356
357
358
359
360
361
362
363
364
365bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
366{
367 u32 mmngc;
368
369
370 if (hw->mac.type == ixgbe_mac_82598EB)
371 return false;
372
373 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
374 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
375 hw_dbg(hw, "MNG_VETO bit detected.\n");
376 return true;
377 }
378
379 return false;
380}
381
382
383
384
385
386
387static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
388{
389 s32 status;
390 u16 phy_id_high = 0;
391 u16 phy_id_low = 0;
392
393 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
394 &phy_id_high);
395
396 if (!status) {
397 hw->phy.id = (u32)(phy_id_high << 16);
398 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
399 &phy_id_low);
400 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
401 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
402 }
403 return status;
404}
405
406
407
408
409
410
411static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
412{
413 enum ixgbe_phy_type phy_type;
414
415 switch (phy_id) {
416 case TN1010_PHY_ID:
417 phy_type = ixgbe_phy_tn;
418 break;
419 case X550_PHY_ID:
420 case X540_PHY_ID:
421 phy_type = ixgbe_phy_aq;
422 break;
423 case QT2022_PHY_ID:
424 phy_type = ixgbe_phy_qt;
425 break;
426 case ATH_PHY_ID:
427 phy_type = ixgbe_phy_nl;
428 break;
429 case X557_PHY_ID:
430 phy_type = ixgbe_phy_x550em_ext_t;
431 break;
432 default:
433 phy_type = ixgbe_phy_unknown;
434 break;
435 }
436
437 return phy_type;
438}
439
440
441
442
443
444s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
445{
446 u32 i;
447 u16 ctrl = 0;
448 s32 status = 0;
449
450 if (hw->phy.type == ixgbe_phy_unknown)
451 status = ixgbe_identify_phy_generic(hw);
452
453 if (status != 0 || hw->phy.type == ixgbe_phy_none)
454 return status;
455
456
457 if (!hw->phy.reset_if_overtemp &&
458 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
459 return 0;
460
461
462 if (ixgbe_check_reset_blocked(hw))
463 return 0;
464
465
466
467
468
469 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
470 MDIO_MMD_PHYXS,
471 MDIO_CTRL1_RESET);
472
473
474
475
476
477
478 for (i = 0; i < 30; i++) {
479 msleep(100);
480 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
481 MDIO_MMD_PHYXS, &ctrl);
482 if (!(ctrl & MDIO_CTRL1_RESET)) {
483 udelay(2);
484 break;
485 }
486 }
487
488 if (ctrl & MDIO_CTRL1_RESET) {
489 hw_dbg(hw, "PHY reset polling failed to complete.\n");
490 return IXGBE_ERR_RESET_FAILED;
491 }
492
493 return 0;
494}
495
496
497
498
499
500
501
502
503s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
504 u16 *phy_data)
505{
506 u32 i, data, command;
507
508
509 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
510 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
511 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
512 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
513
514 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
515
516
517
518
519
520 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
521 udelay(10);
522
523 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
524 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
525 break;
526 }
527
528
529 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
530 hw_dbg(hw, "PHY address command did not complete.\n");
531 return IXGBE_ERR_PHY;
532 }
533
534
535
536
537 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
538 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
539 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
540 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
541
542 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
543
544
545
546
547
548 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
549 udelay(10);
550
551 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
552 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
553 break;
554 }
555
556 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
557 hw_dbg(hw, "PHY read command didn't complete\n");
558 return IXGBE_ERR_PHY;
559 }
560
561
562
563
564 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
565 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
566 *phy_data = (u16)(data);
567
568 return 0;
569}
570
571
572
573
574
575
576
577
578s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
579 u32 device_type, u16 *phy_data)
580{
581 s32 status;
582 u32 gssr = hw->phy.phy_semaphore_mask;
583
584 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
585 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
586 phy_data);
587 hw->mac.ops.release_swfw_sync(hw, gssr);
588 } else {
589 return IXGBE_ERR_SWFW_SYNC;
590 }
591
592 return status;
593}
594
595
596
597
598
599
600
601
602
603s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
604 u32 device_type, u16 phy_data)
605{
606 u32 i, command;
607
608
609 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
610
611
612 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
613 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
615 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
616
617 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
618
619
620
621
622
623
624 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
625 udelay(10);
626
627 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
628 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
629 break;
630 }
631
632 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
633 hw_dbg(hw, "PHY address cmd didn't complete\n");
634 return IXGBE_ERR_PHY;
635 }
636
637
638
639
640
641 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
642 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
643 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
644 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
645
646 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
647
648
649
650
651
652 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
653 udelay(10);
654
655 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
656 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
657 break;
658 }
659
660 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
661 hw_dbg(hw, "PHY write cmd didn't complete\n");
662 return IXGBE_ERR_PHY;
663 }
664
665 return 0;
666}
667
668
669
670
671
672
673
674
675
676s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
677 u32 device_type, u16 phy_data)
678{
679 s32 status;
680 u32 gssr = hw->phy.phy_semaphore_mask;
681
682 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
683 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
684 phy_data);
685 hw->mac.ops.release_swfw_sync(hw, gssr);
686 } else {
687 return IXGBE_ERR_SWFW_SYNC;
688 }
689
690 return status;
691}
692
693
694
695
696
697
698
699s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
700{
701 s32 status = 0;
702 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
703 bool autoneg = false;
704 ixgbe_link_speed speed;
705
706 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
707
708 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
709
710 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
711 MDIO_MMD_AN,
712 &autoneg_reg);
713
714 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
715 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
716 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
717
718 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
719 MDIO_MMD_AN,
720 autoneg_reg);
721 }
722
723 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
724
725 hw->phy.ops.read_reg(hw,
726 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
727 MDIO_MMD_AN,
728 &autoneg_reg);
729
730 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
731 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
732 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
733
734 hw->phy.ops.write_reg(hw,
735 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
736 MDIO_MMD_AN,
737 autoneg_reg);
738 }
739
740 if (speed & IXGBE_LINK_SPEED_100_FULL) {
741
742 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
743 MDIO_MMD_AN,
744 &autoneg_reg);
745
746 autoneg_reg &= ~(ADVERTISE_100FULL |
747 ADVERTISE_100HALF);
748 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
749 autoneg_reg |= ADVERTISE_100FULL;
750
751 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
752 MDIO_MMD_AN,
753 autoneg_reg);
754 }
755
756
757 if (ixgbe_check_reset_blocked(hw))
758 return 0;
759
760
761 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
762 MDIO_MMD_AN, &autoneg_reg);
763
764 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
765
766 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
767 MDIO_MMD_AN, autoneg_reg);
768
769 return status;
770}
771
772
773
774
775
776
777s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
778 ixgbe_link_speed speed,
779 bool autoneg_wait_to_complete)
780{
781
782
783
784
785
786 hw->phy.autoneg_advertised = 0;
787
788 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
789 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
790
791 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
792 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
793
794 if (speed & IXGBE_LINK_SPEED_100_FULL)
795 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
796
797
798 hw->phy.ops.setup_link(hw);
799
800 return 0;
801}
802
803
804
805
806
807
808
809
810static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
811{
812 u16 speed_ability;
813 s32 status;
814
815 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
816 &speed_ability);
817 if (status)
818 return status;
819
820 if (speed_ability & MDIO_SPEED_10G)
821 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
822 if (speed_ability & MDIO_PMA_SPEED_1000)
823 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
824 if (speed_ability & MDIO_PMA_SPEED_100)
825 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
826
827 switch (hw->mac.type) {
828 case ixgbe_mac_X550:
829 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
830 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
831 break;
832 case ixgbe_mac_X550EM_x:
833 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
834 break;
835 default:
836 break;
837 }
838
839 return 0;
840}
841
842
843
844
845
846
847
848s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
849 ixgbe_link_speed *speed,
850 bool *autoneg)
851{
852 s32 status = 0;
853
854 *autoneg = true;
855 if (!hw->phy.speeds_supported)
856 status = ixgbe_get_copper_speeds_supported(hw);
857
858 *speed = hw->phy.speeds_supported;
859 return status;
860}
861
862
863
864
865
866
867
868
869s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
870 bool *link_up)
871{
872 s32 status;
873 u32 time_out;
874 u32 max_time_out = 10;
875 u16 phy_link = 0;
876 u16 phy_speed = 0;
877 u16 phy_data = 0;
878
879
880 *link_up = false;
881 *speed = IXGBE_LINK_SPEED_10GB_FULL;
882
883
884
885
886
887
888 for (time_out = 0; time_out < max_time_out; time_out++) {
889 udelay(10);
890 status = hw->phy.ops.read_reg(hw,
891 MDIO_STAT1,
892 MDIO_MMD_VEND1,
893 &phy_data);
894 phy_link = phy_data &
895 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
896 phy_speed = phy_data &
897 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
898 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
899 *link_up = true;
900 if (phy_speed ==
901 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
902 *speed = IXGBE_LINK_SPEED_1GB_FULL;
903 break;
904 }
905 }
906
907 return status;
908}
909
910
911
912
913
914
915
916
917
918
919s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
920{
921 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
922 bool autoneg = false;
923 ixgbe_link_speed speed;
924
925 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
926
927 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
928
929 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
930 MDIO_MMD_AN,
931 &autoneg_reg);
932
933 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
934 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
935 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
936
937 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
938 MDIO_MMD_AN,
939 autoneg_reg);
940 }
941
942 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
943
944 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
945 MDIO_MMD_AN,
946 &autoneg_reg);
947
948 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
949 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
950 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
951
952 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
953 MDIO_MMD_AN,
954 autoneg_reg);
955 }
956
957 if (speed & IXGBE_LINK_SPEED_100_FULL) {
958
959 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
960 MDIO_MMD_AN,
961 &autoneg_reg);
962
963 autoneg_reg &= ~(ADVERTISE_100FULL |
964 ADVERTISE_100HALF);
965 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
966 autoneg_reg |= ADVERTISE_100FULL;
967
968 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
969 MDIO_MMD_AN,
970 autoneg_reg);
971 }
972
973
974 if (ixgbe_check_reset_blocked(hw))
975 return 0;
976
977
978 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
979 MDIO_MMD_AN, &autoneg_reg);
980
981 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
982
983 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
984 MDIO_MMD_AN, autoneg_reg);
985 return 0;
986}
987
988
989
990
991
992
993s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
994 u16 *firmware_version)
995{
996 s32 status;
997
998 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
999 MDIO_MMD_VEND1,
1000 firmware_version);
1001
1002 return status;
1003}
1004
1005
1006
1007
1008
1009
1010s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1011 u16 *firmware_version)
1012{
1013 s32 status;
1014
1015 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1016 MDIO_MMD_VEND1,
1017 firmware_version);
1018
1019 return status;
1020}
1021
1022
1023
1024
1025
1026s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1027{
1028 u16 phy_offset, control, eword, edata, block_crc;
1029 bool end_data = false;
1030 u16 list_offset, data_offset;
1031 u16 phy_data = 0;
1032 s32 ret_val;
1033 u32 i;
1034
1035
1036 if (ixgbe_check_reset_blocked(hw))
1037 return 0;
1038
1039 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1040
1041
1042 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1043 (phy_data | MDIO_CTRL1_RESET));
1044
1045 for (i = 0; i < 100; i++) {
1046 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1047 &phy_data);
1048 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1049 break;
1050 usleep_range(10000, 20000);
1051 }
1052
1053 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1054 hw_dbg(hw, "PHY reset did not complete.\n");
1055 return IXGBE_ERR_PHY;
1056 }
1057
1058
1059 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1060 &data_offset);
1061 if (ret_val)
1062 return ret_val;
1063
1064 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1065 data_offset++;
1066 while (!end_data) {
1067
1068
1069
1070 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1071 if (ret_val)
1072 goto err_eeprom;
1073 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1074 IXGBE_CONTROL_SHIFT_NL;
1075 edata = eword & IXGBE_DATA_MASK_NL;
1076 switch (control) {
1077 case IXGBE_DELAY_NL:
1078 data_offset++;
1079 hw_dbg(hw, "DELAY: %d MS\n", edata);
1080 usleep_range(edata * 1000, edata * 2000);
1081 break;
1082 case IXGBE_DATA_NL:
1083 hw_dbg(hw, "DATA:\n");
1084 data_offset++;
1085 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1086 &phy_offset);
1087 if (ret_val)
1088 goto err_eeprom;
1089 for (i = 0; i < edata; i++) {
1090 ret_val = hw->eeprom.ops.read(hw, data_offset,
1091 &eword);
1092 if (ret_val)
1093 goto err_eeprom;
1094 hw->phy.ops.write_reg(hw, phy_offset,
1095 MDIO_MMD_PMAPMD, eword);
1096 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1097 phy_offset);
1098 data_offset++;
1099 phy_offset++;
1100 }
1101 break;
1102 case IXGBE_CONTROL_NL:
1103 data_offset++;
1104 hw_dbg(hw, "CONTROL:\n");
1105 if (edata == IXGBE_CONTROL_EOL_NL) {
1106 hw_dbg(hw, "EOL\n");
1107 end_data = true;
1108 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1109 hw_dbg(hw, "SOL\n");
1110 } else {
1111 hw_dbg(hw, "Bad control value\n");
1112 return IXGBE_ERR_PHY;
1113 }
1114 break;
1115 default:
1116 hw_dbg(hw, "Bad control type\n");
1117 return IXGBE_ERR_PHY;
1118 }
1119 }
1120
1121 return ret_val;
1122
1123err_eeprom:
1124 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1125 return IXGBE_ERR_PHY;
1126}
1127
1128
1129
1130
1131
1132
1133
1134s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1135{
1136 switch (hw->mac.ops.get_media_type(hw)) {
1137 case ixgbe_media_type_fiber:
1138 return ixgbe_identify_sfp_module_generic(hw);
1139 case ixgbe_media_type_fiber_qsfp:
1140 return ixgbe_identify_qsfp_module_generic(hw);
1141 default:
1142 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1143 return IXGBE_ERR_SFP_NOT_PRESENT;
1144 }
1145
1146 return IXGBE_ERR_SFP_NOT_PRESENT;
1147}
1148
1149
1150
1151
1152
1153
1154
1155s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1156{
1157 struct ixgbe_adapter *adapter = hw->back;
1158 s32 status;
1159 u32 vendor_oui = 0;
1160 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1161 u8 identifier = 0;
1162 u8 comp_codes_1g = 0;
1163 u8 comp_codes_10g = 0;
1164 u8 oui_bytes[3] = {0, 0, 0};
1165 u8 cable_tech = 0;
1166 u8 cable_spec = 0;
1167 u16 enforce_sfp = 0;
1168
1169 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1170 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1171 return IXGBE_ERR_SFP_NOT_PRESENT;
1172 }
1173
1174
1175 hw->mac.ops.set_lan_id(hw);
1176
1177 status = hw->phy.ops.read_i2c_eeprom(hw,
1178 IXGBE_SFF_IDENTIFIER,
1179 &identifier);
1180
1181 if (status)
1182 goto err_read_i2c_eeprom;
1183
1184 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1185 hw->phy.type = ixgbe_phy_sfp_unsupported;
1186 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1187 }
1188 status = hw->phy.ops.read_i2c_eeprom(hw,
1189 IXGBE_SFF_1GBE_COMP_CODES,
1190 &comp_codes_1g);
1191
1192 if (status)
1193 goto err_read_i2c_eeprom;
1194
1195 status = hw->phy.ops.read_i2c_eeprom(hw,
1196 IXGBE_SFF_10GBE_COMP_CODES,
1197 &comp_codes_10g);
1198
1199 if (status)
1200 goto err_read_i2c_eeprom;
1201 status = hw->phy.ops.read_i2c_eeprom(hw,
1202 IXGBE_SFF_CABLE_TECHNOLOGY,
1203 &cable_tech);
1204
1205 if (status)
1206 goto err_read_i2c_eeprom;
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224 if (hw->mac.type == ixgbe_mac_82598EB) {
1225 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1226 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1227 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1228 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1229 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1230 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1231 else
1232 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1233 } else {
1234 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1235 if (hw->bus.lan_id == 0)
1236 hw->phy.sfp_type =
1237 ixgbe_sfp_type_da_cu_core0;
1238 else
1239 hw->phy.sfp_type =
1240 ixgbe_sfp_type_da_cu_core1;
1241 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1242 hw->phy.ops.read_i2c_eeprom(
1243 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1244 &cable_spec);
1245 if (cable_spec &
1246 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1247 if (hw->bus.lan_id == 0)
1248 hw->phy.sfp_type =
1249 ixgbe_sfp_type_da_act_lmt_core0;
1250 else
1251 hw->phy.sfp_type =
1252 ixgbe_sfp_type_da_act_lmt_core1;
1253 } else {
1254 hw->phy.sfp_type =
1255 ixgbe_sfp_type_unknown;
1256 }
1257 } else if (comp_codes_10g &
1258 (IXGBE_SFF_10GBASESR_CAPABLE |
1259 IXGBE_SFF_10GBASELR_CAPABLE)) {
1260 if (hw->bus.lan_id == 0)
1261 hw->phy.sfp_type =
1262 ixgbe_sfp_type_srlr_core0;
1263 else
1264 hw->phy.sfp_type =
1265 ixgbe_sfp_type_srlr_core1;
1266 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1267 if (hw->bus.lan_id == 0)
1268 hw->phy.sfp_type =
1269 ixgbe_sfp_type_1g_cu_core0;
1270 else
1271 hw->phy.sfp_type =
1272 ixgbe_sfp_type_1g_cu_core1;
1273 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1274 if (hw->bus.lan_id == 0)
1275 hw->phy.sfp_type =
1276 ixgbe_sfp_type_1g_sx_core0;
1277 else
1278 hw->phy.sfp_type =
1279 ixgbe_sfp_type_1g_sx_core1;
1280 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1281 if (hw->bus.lan_id == 0)
1282 hw->phy.sfp_type =
1283 ixgbe_sfp_type_1g_lx_core0;
1284 else
1285 hw->phy.sfp_type =
1286 ixgbe_sfp_type_1g_lx_core1;
1287 } else {
1288 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1289 }
1290 }
1291
1292 if (hw->phy.sfp_type != stored_sfp_type)
1293 hw->phy.sfp_setup_needed = true;
1294
1295
1296 hw->phy.multispeed_fiber = false;
1297 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1298 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1299 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1300 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1301 hw->phy.multispeed_fiber = true;
1302
1303
1304 if (hw->phy.type != ixgbe_phy_nl) {
1305 hw->phy.id = identifier;
1306 status = hw->phy.ops.read_i2c_eeprom(hw,
1307 IXGBE_SFF_VENDOR_OUI_BYTE0,
1308 &oui_bytes[0]);
1309
1310 if (status != 0)
1311 goto err_read_i2c_eeprom;
1312
1313 status = hw->phy.ops.read_i2c_eeprom(hw,
1314 IXGBE_SFF_VENDOR_OUI_BYTE1,
1315 &oui_bytes[1]);
1316
1317 if (status != 0)
1318 goto err_read_i2c_eeprom;
1319
1320 status = hw->phy.ops.read_i2c_eeprom(hw,
1321 IXGBE_SFF_VENDOR_OUI_BYTE2,
1322 &oui_bytes[2]);
1323
1324 if (status != 0)
1325 goto err_read_i2c_eeprom;
1326
1327 vendor_oui =
1328 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1329 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1330 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1331
1332 switch (vendor_oui) {
1333 case IXGBE_SFF_VENDOR_OUI_TYCO:
1334 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1335 hw->phy.type =
1336 ixgbe_phy_sfp_passive_tyco;
1337 break;
1338 case IXGBE_SFF_VENDOR_OUI_FTL:
1339 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1340 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1341 else
1342 hw->phy.type = ixgbe_phy_sfp_ftl;
1343 break;
1344 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1345 hw->phy.type = ixgbe_phy_sfp_avago;
1346 break;
1347 case IXGBE_SFF_VENDOR_OUI_INTEL:
1348 hw->phy.type = ixgbe_phy_sfp_intel;
1349 break;
1350 default:
1351 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1352 hw->phy.type =
1353 ixgbe_phy_sfp_passive_unknown;
1354 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1355 hw->phy.type =
1356 ixgbe_phy_sfp_active_unknown;
1357 else
1358 hw->phy.type = ixgbe_phy_sfp_unknown;
1359 break;
1360 }
1361 }
1362
1363
1364 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1365 IXGBE_SFF_DA_ACTIVE_CABLE))
1366 return 0;
1367
1368
1369 if (comp_codes_10g == 0 &&
1370 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1371 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1372 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1373 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1374 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1375 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1376 hw->phy.type = ixgbe_phy_sfp_unsupported;
1377 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1378 }
1379
1380
1381 if (hw->mac.type == ixgbe_mac_82598EB)
1382 return 0;
1383
1384 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1385 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1386 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1387 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1388 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1389 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1390 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1391 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1392
1393 if (hw->phy.type == ixgbe_phy_sfp_intel)
1394 return 0;
1395 if (hw->allow_unsupported_sfp) {
1396 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1397 return 0;
1398 }
1399 hw_dbg(hw, "SFP+ module not supported\n");
1400 hw->phy.type = ixgbe_phy_sfp_unsupported;
1401 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1402 }
1403 return 0;
1404
1405err_read_i2c_eeprom:
1406 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1407 if (hw->phy.type != ixgbe_phy_nl) {
1408 hw->phy.id = 0;
1409 hw->phy.type = ixgbe_phy_unknown;
1410 }
1411 return IXGBE_ERR_SFP_NOT_PRESENT;
1412}
1413
1414
1415
1416
1417
1418
1419
1420static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1421{
1422 struct ixgbe_adapter *adapter = hw->back;
1423 s32 status;
1424 u32 vendor_oui = 0;
1425 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1426 u8 identifier = 0;
1427 u8 comp_codes_1g = 0;
1428 u8 comp_codes_10g = 0;
1429 u8 oui_bytes[3] = {0, 0, 0};
1430 u16 enforce_sfp = 0;
1431 u8 connector = 0;
1432 u8 cable_length = 0;
1433 u8 device_tech = 0;
1434 bool active_cable = false;
1435
1436 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1437 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1438 return IXGBE_ERR_SFP_NOT_PRESENT;
1439 }
1440
1441
1442 hw->mac.ops.set_lan_id(hw);
1443
1444 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1445 &identifier);
1446
1447 if (status != 0)
1448 goto err_read_i2c_eeprom;
1449
1450 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1451 hw->phy.type = ixgbe_phy_sfp_unsupported;
1452 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1453 }
1454
1455 hw->phy.id = identifier;
1456
1457 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1458 &comp_codes_10g);
1459
1460 if (status != 0)
1461 goto err_read_i2c_eeprom;
1462
1463 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1464 &comp_codes_1g);
1465
1466 if (status != 0)
1467 goto err_read_i2c_eeprom;
1468
1469 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1470 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1471 if (hw->bus.lan_id == 0)
1472 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1473 else
1474 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1475 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1476 IXGBE_SFF_10GBASELR_CAPABLE)) {
1477 if (hw->bus.lan_id == 0)
1478 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1479 else
1480 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1481 } else {
1482 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1483 active_cable = true;
1484
1485 if (!active_cable) {
1486
1487
1488
1489 hw->phy.ops.read_i2c_eeprom(hw,
1490 IXGBE_SFF_QSFP_CONNECTOR,
1491 &connector);
1492
1493 hw->phy.ops.read_i2c_eeprom(hw,
1494 IXGBE_SFF_QSFP_CABLE_LENGTH,
1495 &cable_length);
1496
1497 hw->phy.ops.read_i2c_eeprom(hw,
1498 IXGBE_SFF_QSFP_DEVICE_TECH,
1499 &device_tech);
1500
1501 if ((connector ==
1502 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1503 (cable_length > 0) &&
1504 ((device_tech >> 4) ==
1505 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1506 active_cable = true;
1507 }
1508
1509 if (active_cable) {
1510 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1511 if (hw->bus.lan_id == 0)
1512 hw->phy.sfp_type =
1513 ixgbe_sfp_type_da_act_lmt_core0;
1514 else
1515 hw->phy.sfp_type =
1516 ixgbe_sfp_type_da_act_lmt_core1;
1517 } else {
1518
1519 hw->phy.type = ixgbe_phy_sfp_unsupported;
1520 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1521 }
1522 }
1523
1524 if (hw->phy.sfp_type != stored_sfp_type)
1525 hw->phy.sfp_setup_needed = true;
1526
1527
1528 hw->phy.multispeed_fiber = false;
1529 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1530 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1531 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1532 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1533 hw->phy.multispeed_fiber = true;
1534
1535
1536 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1537 IXGBE_SFF_10GBASELR_CAPABLE)) {
1538 status = hw->phy.ops.read_i2c_eeprom(hw,
1539 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1540 &oui_bytes[0]);
1541
1542 if (status != 0)
1543 goto err_read_i2c_eeprom;
1544
1545 status = hw->phy.ops.read_i2c_eeprom(hw,
1546 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1547 &oui_bytes[1]);
1548
1549 if (status != 0)
1550 goto err_read_i2c_eeprom;
1551
1552 status = hw->phy.ops.read_i2c_eeprom(hw,
1553 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1554 &oui_bytes[2]);
1555
1556 if (status != 0)
1557 goto err_read_i2c_eeprom;
1558
1559 vendor_oui =
1560 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1561 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1562 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1563
1564 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1565 hw->phy.type = ixgbe_phy_qsfp_intel;
1566 else
1567 hw->phy.type = ixgbe_phy_qsfp_unknown;
1568
1569 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1570 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1571
1572 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1573 return 0;
1574 if (hw->allow_unsupported_sfp) {
1575 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1576 return 0;
1577 }
1578 hw_dbg(hw, "QSFP module not supported\n");
1579 hw->phy.type = ixgbe_phy_sfp_unsupported;
1580 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1581 }
1582 return 0;
1583 }
1584 return 0;
1585
1586err_read_i2c_eeprom:
1587 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1588 hw->phy.id = 0;
1589 hw->phy.type = ixgbe_phy_unknown;
1590
1591 return IXGBE_ERR_SFP_NOT_PRESENT;
1592}
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1604 u16 *list_offset,
1605 u16 *data_offset)
1606{
1607 u16 sfp_id;
1608 u16 sfp_type = hw->phy.sfp_type;
1609
1610 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1611 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1612
1613 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1614 return IXGBE_ERR_SFP_NOT_PRESENT;
1615
1616 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1617 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1618 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1619
1620
1621
1622
1623
1624 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1625 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1626 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1627 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1628 sfp_type = ixgbe_sfp_type_srlr_core0;
1629 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1630 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1631 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1632 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1633 sfp_type = ixgbe_sfp_type_srlr_core1;
1634
1635
1636 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1637 hw_err(hw, "eeprom read at %d failed\n",
1638 IXGBE_PHY_INIT_OFFSET_NL);
1639 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1640 }
1641
1642 if ((!*list_offset) || (*list_offset == 0xFFFF))
1643 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1644
1645
1646 (*list_offset)++;
1647
1648
1649
1650
1651
1652 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1653 goto err_phy;
1654
1655 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1656 if (sfp_id == sfp_type) {
1657 (*list_offset)++;
1658 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1659 goto err_phy;
1660 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1661 hw_dbg(hw, "SFP+ module not supported\n");
1662 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1663 } else {
1664 break;
1665 }
1666 } else {
1667 (*list_offset) += 2;
1668 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1669 goto err_phy;
1670 }
1671 }
1672
1673 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1674 hw_dbg(hw, "No matching SFP+ module found\n");
1675 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1676 }
1677
1678 return 0;
1679
1680err_phy:
1681 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
1682 return IXGBE_ERR_PHY;
1683}
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1694 u8 *eeprom_data)
1695{
1696 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1697 IXGBE_I2C_EEPROM_DEV_ADDR,
1698 eeprom_data);
1699}
1700
1701
1702
1703
1704
1705
1706
1707
1708
1709s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1710 u8 *sff8472_data)
1711{
1712 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1713 IXGBE_I2C_EEPROM_DEV_ADDR2,
1714 sff8472_data);
1715}
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1726 u8 eeprom_data)
1727{
1728 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1729 IXGBE_I2C_EEPROM_DEV_ADDR,
1730 eeprom_data);
1731}
1732
1733
1734
1735
1736
1737
1738
1739static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1740{
1741 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1742 offset == IXGBE_SFF_IDENTIFIER &&
1743 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1744 return true;
1745 return false;
1746}
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1759 u8 dev_addr, u8 *data, bool lock)
1760{
1761 s32 status;
1762 u32 max_retry = 10;
1763 u32 retry = 0;
1764 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1765 bool nack = true;
1766
1767 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1768 max_retry = IXGBE_SFP_DETECT_RETRIES;
1769
1770 *data = 0;
1771
1772 do {
1773 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1774 return IXGBE_ERR_SWFW_SYNC;
1775
1776 ixgbe_i2c_start(hw);
1777
1778
1779 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1780 if (status != 0)
1781 goto fail;
1782
1783 status = ixgbe_get_i2c_ack(hw);
1784 if (status != 0)
1785 goto fail;
1786
1787 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1788 if (status != 0)
1789 goto fail;
1790
1791 status = ixgbe_get_i2c_ack(hw);
1792 if (status != 0)
1793 goto fail;
1794
1795 ixgbe_i2c_start(hw);
1796
1797
1798 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1799 if (status != 0)
1800 goto fail;
1801
1802 status = ixgbe_get_i2c_ack(hw);
1803 if (status != 0)
1804 goto fail;
1805
1806 status = ixgbe_clock_in_i2c_byte(hw, data);
1807 if (status != 0)
1808 goto fail;
1809
1810 status = ixgbe_clock_out_i2c_bit(hw, nack);
1811 if (status != 0)
1812 goto fail;
1813
1814 ixgbe_i2c_stop(hw);
1815 if (lock)
1816 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1817 return 0;
1818
1819fail:
1820 ixgbe_i2c_bus_clear(hw);
1821 if (lock) {
1822 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1823 msleep(100);
1824 }
1825 retry++;
1826 if (retry < max_retry)
1827 hw_dbg(hw, "I2C byte read error - Retrying.\n");
1828 else
1829 hw_dbg(hw, "I2C byte read error.\n");
1830
1831 } while (retry < max_retry);
1832
1833 return status;
1834}
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1846 u8 dev_addr, u8 *data)
1847{
1848 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1849 data, true);
1850}
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1862 u8 dev_addr, u8 *data)
1863{
1864 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1865 data, false);
1866}
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
1879 u8 dev_addr, u8 data, bool lock)
1880{
1881 s32 status;
1882 u32 max_retry = 1;
1883 u32 retry = 0;
1884 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1885
1886 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1887 return IXGBE_ERR_SWFW_SYNC;
1888
1889 do {
1890 ixgbe_i2c_start(hw);
1891
1892 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1893 if (status != 0)
1894 goto fail;
1895
1896 status = ixgbe_get_i2c_ack(hw);
1897 if (status != 0)
1898 goto fail;
1899
1900 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1901 if (status != 0)
1902 goto fail;
1903
1904 status = ixgbe_get_i2c_ack(hw);
1905 if (status != 0)
1906 goto fail;
1907
1908 status = ixgbe_clock_out_i2c_byte(hw, data);
1909 if (status != 0)
1910 goto fail;
1911
1912 status = ixgbe_get_i2c_ack(hw);
1913 if (status != 0)
1914 goto fail;
1915
1916 ixgbe_i2c_stop(hw);
1917 if (lock)
1918 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1919 return 0;
1920
1921fail:
1922 ixgbe_i2c_bus_clear(hw);
1923 retry++;
1924 if (retry < max_retry)
1925 hw_dbg(hw, "I2C byte write error - Retrying.\n");
1926 else
1927 hw_dbg(hw, "I2C byte write error.\n");
1928 } while (retry < max_retry);
1929
1930 if (lock)
1931 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1932
1933 return status;
1934}
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944
1945s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1946 u8 dev_addr, u8 data)
1947{
1948 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1949 data, true);
1950}
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
1962 u8 dev_addr, u8 data)
1963{
1964 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
1965 data, false);
1966}
1967
1968
1969
1970
1971
1972
1973
1974
1975static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1976{
1977 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
1978
1979 i2cctl |= IXGBE_I2C_BB_EN(hw);
1980
1981
1982 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1983 ixgbe_raise_i2c_clk(hw, &i2cctl);
1984
1985
1986 udelay(IXGBE_I2C_T_SU_STA);
1987
1988 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1989
1990
1991 udelay(IXGBE_I2C_T_HD_STA);
1992
1993 ixgbe_lower_i2c_clk(hw, &i2cctl);
1994
1995
1996 udelay(IXGBE_I2C_T_LOW);
1997
1998}
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2009{
2010 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2011 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2012 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2013 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2014
2015
2016 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2017 ixgbe_raise_i2c_clk(hw, &i2cctl);
2018
2019
2020 udelay(IXGBE_I2C_T_SU_STO);
2021
2022 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2023
2024
2025 udelay(IXGBE_I2C_T_BUF);
2026
2027 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2028 i2cctl &= ~bb_en_bit;
2029 i2cctl |= data_oe_bit | clk_oe_bit;
2030 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2031 IXGBE_WRITE_FLUSH(hw);
2032 }
2033}
2034
2035
2036
2037
2038
2039
2040
2041
2042static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2043{
2044 s32 i;
2045 bool bit = false;
2046
2047 *data = 0;
2048 for (i = 7; i >= 0; i--) {
2049 ixgbe_clock_in_i2c_bit(hw, &bit);
2050 *data |= bit << i;
2051 }
2052
2053 return 0;
2054}
2055
2056
2057
2058
2059
2060
2061
2062
2063static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2064{
2065 s32 status;
2066 s32 i;
2067 u32 i2cctl;
2068 bool bit = false;
2069
2070 for (i = 7; i >= 0; i--) {
2071 bit = (data >> i) & 0x1;
2072 status = ixgbe_clock_out_i2c_bit(hw, bit);
2073
2074 if (status != 0)
2075 break;
2076 }
2077
2078
2079 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2080 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2081 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2082 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2083 IXGBE_WRITE_FLUSH(hw);
2084
2085 return status;
2086}
2087
2088
2089
2090
2091
2092
2093
2094static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2095{
2096 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2097 s32 status = 0;
2098 u32 i = 0;
2099 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2100 u32 timeout = 10;
2101 bool ack = true;
2102
2103 if (data_oe_bit) {
2104 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2105 i2cctl |= data_oe_bit;
2106 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2107 IXGBE_WRITE_FLUSH(hw);
2108 }
2109 ixgbe_raise_i2c_clk(hw, &i2cctl);
2110
2111
2112 udelay(IXGBE_I2C_T_HIGH);
2113
2114
2115
2116 for (i = 0; i < timeout; i++) {
2117 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2118 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2119
2120 udelay(1);
2121 if (ack == 0)
2122 break;
2123 }
2124
2125 if (ack == 1) {
2126 hw_dbg(hw, "I2C ack was not received.\n");
2127 status = IXGBE_ERR_I2C;
2128 }
2129
2130 ixgbe_lower_i2c_clk(hw, &i2cctl);
2131
2132
2133 udelay(IXGBE_I2C_T_LOW);
2134
2135 return status;
2136}
2137
2138
2139
2140
2141
2142
2143
2144
2145static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2146{
2147 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2148 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2149
2150 if (data_oe_bit) {
2151 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2152 i2cctl |= data_oe_bit;
2153 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2154 IXGBE_WRITE_FLUSH(hw);
2155 }
2156 ixgbe_raise_i2c_clk(hw, &i2cctl);
2157
2158
2159 udelay(IXGBE_I2C_T_HIGH);
2160
2161 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2162 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2163
2164 ixgbe_lower_i2c_clk(hw, &i2cctl);
2165
2166
2167 udelay(IXGBE_I2C_T_LOW);
2168
2169 return 0;
2170}
2171
2172
2173
2174
2175
2176
2177
2178
2179static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2180{
2181 s32 status;
2182 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2183
2184 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2185 if (status == 0) {
2186 ixgbe_raise_i2c_clk(hw, &i2cctl);
2187
2188
2189 udelay(IXGBE_I2C_T_HIGH);
2190
2191 ixgbe_lower_i2c_clk(hw, &i2cctl);
2192
2193
2194
2195
2196 udelay(IXGBE_I2C_T_LOW);
2197 } else {
2198 hw_dbg(hw, "I2C data was not set to %X\n", data);
2199 return IXGBE_ERR_I2C;
2200 }
2201
2202 return 0;
2203}
2204
2205
2206
2207
2208
2209
2210
2211
2212static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2213{
2214 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2215 u32 i = 0;
2216 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2217 u32 i2cctl_r = 0;
2218
2219 if (clk_oe_bit) {
2220 *i2cctl |= clk_oe_bit;
2221 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2222 }
2223
2224 for (i = 0; i < timeout; i++) {
2225 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2226 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2227 IXGBE_WRITE_FLUSH(hw);
2228
2229 udelay(IXGBE_I2C_T_RISE);
2230
2231 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2232 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2233 break;
2234 }
2235}
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2246{
2247
2248 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2249 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2250
2251 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2252 IXGBE_WRITE_FLUSH(hw);
2253
2254
2255 udelay(IXGBE_I2C_T_FALL);
2256}
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2268{
2269 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2270
2271 if (data)
2272 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2273 else
2274 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2275 *i2cctl &= ~data_oe_bit;
2276
2277 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2278 IXGBE_WRITE_FLUSH(hw);
2279
2280
2281 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2282
2283 if (!data)
2284 return 0;
2285 if (data_oe_bit) {
2286 *i2cctl |= data_oe_bit;
2287 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2288 IXGBE_WRITE_FLUSH(hw);
2289 }
2290
2291
2292 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2293 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2294 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2295 return IXGBE_ERR_I2C;
2296 }
2297
2298 return 0;
2299}
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2310{
2311 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2312
2313 if (data_oe_bit) {
2314 *i2cctl |= data_oe_bit;
2315 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2316 IXGBE_WRITE_FLUSH(hw);
2317 udelay(IXGBE_I2C_T_FALL);
2318 }
2319
2320 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2321 return true;
2322 return false;
2323}
2324
2325
2326
2327
2328
2329
2330
2331
2332static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2333{
2334 u32 i2cctl;
2335 u32 i;
2336
2337 ixgbe_i2c_start(hw);
2338 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2339
2340 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2341
2342 for (i = 0; i < 9; i++) {
2343 ixgbe_raise_i2c_clk(hw, &i2cctl);
2344
2345
2346 udelay(IXGBE_I2C_T_HIGH);
2347
2348 ixgbe_lower_i2c_clk(hw, &i2cctl);
2349
2350
2351 udelay(IXGBE_I2C_T_LOW);
2352 }
2353
2354 ixgbe_i2c_start(hw);
2355
2356
2357 ixgbe_i2c_stop(hw);
2358}
2359
2360
2361
2362
2363
2364
2365
2366s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2367{
2368 u16 phy_data = 0;
2369
2370 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2371 return 0;
2372
2373
2374 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2375 MDIO_MMD_PMAPMD, &phy_data);
2376
2377 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2378 return 0;
2379
2380 return IXGBE_ERR_OVERTEMP;
2381}
2382
2383
2384
2385
2386
2387s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2388{
2389 u32 status;
2390 u16 reg;
2391
2392
2393 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2394 return 0;
2395
2396 if (!on && ixgbe_mng_present(hw))
2397 return 0;
2398
2399 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2400 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2401 ®);
2402 if (status)
2403 return status;
2404
2405 if (on) {
2406 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2407 } else {
2408 if (ixgbe_check_reset_blocked(hw))
2409 return 0;
2410 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2411 }
2412
2413 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2414 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2415 reg);
2416 return status;
2417}
2418