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29#ifndef _IXGBE_TYPE_H_
30#define _IXGBE_TYPE_H_
31
32#include <linux/types.h>
33#include <linux/mdio.h>
34#include <linux/netdevice.h>
35
36
37#define IXGBE_DEV_ID_82598 0x10B6
38#define IXGBE_DEV_ID_82598_BX 0x1508
39#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
40#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
41#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB
42#define IXGBE_DEV_ID_82598AT 0x10C8
43#define IXGBE_DEV_ID_82598AT2 0x150B
44#define IXGBE_DEV_ID_82598EB_CX4 0x10DD
45#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
46#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1
47#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1
48#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
49#define IXGBE_DEV_ID_82599_KX4 0x10F7
50#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514
51#define IXGBE_DEV_ID_82599_KR 0x1517
52#define IXGBE_DEV_ID_82599_T3_LOM 0x151C
53#define IXGBE_DEV_ID_82599_CX4 0x10F9
54#define IXGBE_DEV_ID_82599_SFP 0x10FB
55#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152a
56#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529
57#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9
58#define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071
59#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72
60#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0
61#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B
62#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470
63#define IXGBE_SUBDEV_ID_82599_LOM_SFP 0x8976
64#define IXGBE_DEV_ID_82599_SFP_EM 0x1507
65#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D
66#define IXGBE_DEV_ID_82599EN_SFP 0x1557
67#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
68#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC
69#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
70#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C
71#define IXGBE_DEV_ID_82599_LS 0x154F
72#define IXGBE_DEV_ID_X540T 0x1528
73#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A
74#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558
75#define IXGBE_DEV_ID_X540T1 0x1560
76
77#define IXGBE_DEV_ID_X550T 0x1563
78#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA
79#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB
80#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC
81#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD
82#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE
83#define IXGBE_DEV_ID_X550_VF_HV 0x1564
84#define IXGBE_DEV_ID_X550_VF 0x1565
85#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
86#define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
87
88
89#define IXGBE_DEV_ID_82599_VF 0x10ED
90#define IXGBE_DEV_ID_X540_VF 0x1515
91#define IXGBE_DEV_ID_X550_VF 0x1565
92#define IXGBE_DEV_ID_X550EM_X_VF 0x15A8
93
94#define IXGBE_CAT(r, m) IXGBE_##r##_##m
95
96#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, IDX)])
97
98
99#define IXGBE_CTRL 0x00000
100#define IXGBE_STATUS 0x00008
101#define IXGBE_CTRL_EXT 0x00018
102#define IXGBE_ESDP 0x00020
103#define IXGBE_EODSDP 0x00028
104
105#define IXGBE_I2CCTL_8259X 0x00028
106#define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_8259X
107#define IXGBE_I2CCTL_X550 0x15F5C
108#define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550
109#define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550
110#define IXGBE_I2CCTL(_hw) IXGBE_BY_MAC((_hw), I2CCTL)
111
112#define IXGBE_LEDCTL 0x00200
113#define IXGBE_FRTIMER 0x00048
114#define IXGBE_TCPTIMER 0x0004C
115#define IXGBE_CORESPARE 0x00600
116#define IXGBE_EXVET 0x05078
117
118
119#define IXGBE_EEC_8259X 0x10010
120#define IXGBE_EEC_X540 IXGBE_EEC_8259X
121#define IXGBE_EEC_X550 IXGBE_EEC_8259X
122#define IXGBE_EEC_X550EM_x IXGBE_EEC_8259X
123#define IXGBE_EEC_X550EM_a 0x15FF8
124#define IXGBE_EEC(_hw) IXGBE_BY_MAC((_hw), EEC)
125#define IXGBE_EERD 0x10014
126#define IXGBE_EEWR 0x10018
127#define IXGBE_FLA_8259X 0x1001C
128#define IXGBE_FLA_X540 IXGBE_FLA_8259X
129#define IXGBE_FLA_X550 IXGBE_FLA_8259X
130#define IXGBE_FLA_X550EM_x IXGBE_FLA_8259X
131#define IXGBE_FLA_X550EM_a 0x15F6C
132#define IXGBE_FLA(_hw) IXGBE_BY_MAC((_hw), FLA)
133#define IXGBE_EEMNGCTL 0x10110
134#define IXGBE_EEMNGDATA 0x10114
135#define IXGBE_FLMNGCTL 0x10118
136#define IXGBE_FLMNGDATA 0x1011C
137#define IXGBE_FLMNGCNT 0x10120
138#define IXGBE_FLOP 0x1013C
139#define IXGBE_GRC_8259X 0x10200
140#define IXGBE_GRC_X540 IXGBE_GRC_8259X
141#define IXGBE_GRC_X550 IXGBE_GRC_8259X
142#define IXGBE_GRC_X550EM_x IXGBE_GRC_8259X
143#define IXGBE_GRC_X550EM_a 0x15F64
144#define IXGBE_GRC(_hw) IXGBE_BY_MAC((_hw), GRC)
145
146#define IXGBE_SRAMREL_8259X 0x10210
147#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL_8259X
148#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL_8259X
149#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL_8259X
150#define IXGBE_SRAMREL_X550EM_a 0x15F6C
151#define IXGBE_SRAMREL(_hw) IXGBE_BY_MAC((_hw), SRAMREL)
152
153
154#define IXGBE_GRC_MNG 0x00000001
155#define IXGBE_GRC_APME 0x00000002
156
157#define IXGBE_VPDDIAG0 0x10204
158#define IXGBE_VPDDIAG1 0x10208
159
160
161#define IXGBE_I2C_CLK_IN_8259X 0x00000001
162#define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN_8259X
163#define IXGBE_I2C_CLK_IN_X550 0x00004000
164#define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550
165#define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550
166#define IXGBE_I2C_CLK_IN(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN)
167
168#define IXGBE_I2C_CLK_OUT_8259X 0x00000002
169#define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT_8259X
170#define IXGBE_I2C_CLK_OUT_X550 0x00000200
171#define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550
172#define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550
173#define IXGBE_I2C_CLK_OUT(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT)
174
175#define IXGBE_I2C_DATA_IN_8259X 0x00000004
176#define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN_8259X
177#define IXGBE_I2C_DATA_IN_X550 0x00001000
178#define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550
179#define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550
180#define IXGBE_I2C_DATA_IN(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN)
181
182#define IXGBE_I2C_DATA_OUT_8259X 0x00000008
183#define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT_8259X
184#define IXGBE_I2C_DATA_OUT_X550 0x00000400
185#define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550
186#define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550
187#define IXGBE_I2C_DATA_OUT(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT)
188
189#define IXGBE_I2C_DATA_OE_N_EN_8259X 0
190#define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN_8259X
191#define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800
192#define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550
193#define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550
194#define IXGBE_I2C_DATA_OE_N_EN(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN)
195
196#define IXGBE_I2C_BB_EN_8259X 0
197#define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN_8259X
198#define IXGBE_I2C_BB_EN_X550 0x00000100
199#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550
200#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550
201#define IXGBE_I2C_BB_EN(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN)
202
203#define IXGBE_I2C_CLK_OE_N_EN_8259X 0
204#define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN_8259X
205#define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000
206#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550
207#define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550
208#define IXGBE_I2C_CLK_OE_N_EN(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN)
209
210#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500
211
212#define IXGBE_I2C_THERMAL_SENSOR_ADDR 0xF8
213#define IXGBE_EMC_INTERNAL_DATA 0x00
214#define IXGBE_EMC_INTERNAL_THERM_LIMIT 0x20
215#define IXGBE_EMC_DIODE1_DATA 0x01
216#define IXGBE_EMC_DIODE1_THERM_LIMIT 0x19
217#define IXGBE_EMC_DIODE2_DATA 0x23
218#define IXGBE_EMC_DIODE2_THERM_LIMIT 0x1A
219
220#define IXGBE_MAX_SENSORS 3
221
222struct ixgbe_thermal_diode_data {
223 u8 location;
224 u8 temp;
225 u8 caution_thresh;
226 u8 max_op_thresh;
227};
228
229struct ixgbe_thermal_sensor_data {
230 struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
231};
232
233
234#define IXGBE_EICR 0x00800
235#define IXGBE_EICS 0x00808
236#define IXGBE_EIMS 0x00880
237#define IXGBE_EIMC 0x00888
238#define IXGBE_EIAC 0x00810
239#define IXGBE_EIAM 0x00890
240#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4)
241#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4)
242#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4)
243#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4)
244
245
246
247
248
249#define IXGBE_MAX_INT_RATE 488281
250#define IXGBE_MIN_INT_RATE 956
251#define IXGBE_MAX_EITR 0x00000FF8
252#define IXGBE_MIN_EITR 8
253#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
254 (0x012300 + (((_i) - 24) * 4)))
255#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
256#define IXGBE_EITR_LLI_MOD 0x00008000
257#define IXGBE_EITR_CNT_WDIS 0x80000000
258#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4))
259#define IXGBE_IVAR_MISC 0x00A00
260#define IXGBE_EITRSEL 0x00894
261#define IXGBE_MSIXT 0x00000
262#define IXGBE_MSIXPBA 0x02000
263#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
264#define IXGBE_GPIE 0x00898
265
266
267#define IXGBE_FCADBUL 0x03210
268#define IXGBE_FCADBUH 0x03214
269#define IXGBE_FCAMACL 0x04328
270#define IXGBE_FCAMACH 0x0432C
271#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4))
272#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4))
273#define IXGBE_PFCTOP 0x03008
274#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4))
275#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8))
276#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8))
277#define IXGBE_FCRTV 0x032A0
278#define IXGBE_FCCFG 0x03D00
279#define IXGBE_TFCS 0x0CE00
280
281
282#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
283 (0x0D000 + (((_i) - 64) * 0x40)))
284#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
285 (0x0D004 + (((_i) - 64) * 0x40)))
286#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
287 (0x0D008 + (((_i) - 64) * 0x40)))
288#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
289 (0x0D010 + (((_i) - 64) * 0x40)))
290#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
291 (0x0D018 + (((_i) - 64) * 0x40)))
292#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
293 (0x0D028 + (((_i) - 64) * 0x40)))
294#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
295 (0x0D02C + (((_i) - 64) * 0x40)))
296#define IXGBE_RSCDBU 0x03028
297#define IXGBE_RDDCC 0x02F20
298#define IXGBE_RXMEMWRAP 0x03190
299#define IXGBE_STARCTRL 0x03024
300
301
302
303
304
305
306#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
307 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
308 (0x0D014 + (((_i) - 64) * 0x40))))
309
310
311
312
313
314
315#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
316 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
317 (0x0D00C + (((_i) - 64) * 0x40))))
318#define IXGBE_RDRXCTL 0x02F00
319#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
320
321#define IXGBE_RXCTRL 0x03000
322#define IXGBE_DROPEN 0x03D04
323#define IXGBE_RXPBSIZE_SHIFT 10
324
325
326#define IXGBE_RXCSUM 0x05000
327#define IXGBE_RFCTL 0x05008
328#define IXGBE_DRECCCTL 0x02F08
329#define IXGBE_DRECCCTL_DISABLE 0
330
331#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
332#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
333 (0x0A200 + ((_i) * 8)))
334#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
335 (0x0A204 + ((_i) * 8)))
336#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
337#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
338
339#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
340 (0x0EA00 + ((_i) * 4)))
341
342#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
343
344#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
345#define IXGBE_FCTRL 0x05080
346#define IXGBE_VLNCTRL 0x05088
347#define IXGBE_MCSTCTRL 0x05090
348#define IXGBE_MRQC 0x05818
349#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4))
350#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4))
351#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4))
352#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4))
353#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4))
354#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4))
355#define IXGBE_SYNQF 0x0EC30
356#define IXGBE_RQTC 0x0EC70
357#define IXGBE_MTQC 0x08120
358#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4))
359#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))
360#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))
361#define IXGBE_PFFLPL 0x050B0
362#define IXGBE_PFFLPH 0x050B4
363#define IXGBE_VT_CTL 0x051B0
364#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i)))
365#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i)))
366#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i)))
367#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i)))
368#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4))
369#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4))
370#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4))
371#define IXGBE_QDE 0x2F04
372#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4))
373#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4))
374#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4))
375#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4))
376#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4))
377#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4))
378#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4))
379#define IXGBE_RXFECCERR0 0x051B8
380#define IXGBE_LLITHRESH 0x0EC90
381#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4))
382#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4))
383#define IXGBE_IMIRVP 0x05AC0
384#define IXGBE_VMD_CTL 0x0581C
385#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4))
386#define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4))
387#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))
388
389
390
391
392
393#define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4))
394#define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40))
395#define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40))
396
397
398#define IXGBE_FDIRCTRL 0x0EE00
399#define IXGBE_FDIRHKEY 0x0EE68
400#define IXGBE_FDIRSKEY 0x0EE6C
401#define IXGBE_FDIRDIP4M 0x0EE3C
402#define IXGBE_FDIRSIP4M 0x0EE40
403#define IXGBE_FDIRTCPM 0x0EE44
404#define IXGBE_FDIRUDPM 0x0EE48
405#define IXGBE_FDIRSCTPM 0x0EE78
406#define IXGBE_FDIRIP6M 0x0EE74
407#define IXGBE_FDIRM 0x0EE70
408
409
410#define IXGBE_FDIRFREE 0x0EE38
411#define IXGBE_FDIRLEN 0x0EE4C
412#define IXGBE_FDIRUSTAT 0x0EE50
413#define IXGBE_FDIRFSTAT 0x0EE54
414#define IXGBE_FDIRMATCH 0x0EE58
415#define IXGBE_FDIRMISS 0x0EE5C
416
417
418#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4))
419#define IXGBE_FDIRIPSA 0x0EE18
420#define IXGBE_FDIRIPDA 0x0EE1C
421#define IXGBE_FDIRPORT 0x0EE20
422#define IXGBE_FDIRVLAN 0x0EE24
423#define IXGBE_FDIRHASH 0x0EE28
424#define IXGBE_FDIRCMD 0x0EE2C
425
426
427#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40))
428#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
429#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
430#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
431#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
432#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
433#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
434#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
435#define IXGBE_DTXCTL 0x07E00
436
437#define IXGBE_DMATXCTL 0x04A80
438#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4))
439#define IXGBE_PFDTXGSWC 0x08220
440#define IXGBE_DTXMXSZRQ 0x08100
441#define IXGBE_DTXTCPFLGL 0x04A88
442#define IXGBE_DTXTCPFLGH 0x04A8C
443#define IXGBE_LBDRPEN 0x0CA00
444#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4))
445
446#define IXGBE_DMATXCTL_TE 0x1
447#define IXGBE_DMATXCTL_NS 0x2
448#define IXGBE_DMATXCTL_GDV 0x8
449#define IXGBE_DMATXCTL_VT_SHIFT 16
450
451#define IXGBE_PFDTXGSWC_VT_LBEN 0x1
452
453
454#define IXGBE_SPOOF_MACAS_MASK 0xFF
455#define IXGBE_SPOOF_VLANAS_MASK 0xFF00
456#define IXGBE_SPOOF_VLANAS_SHIFT 8
457#define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000
458#define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16
459#define IXGBE_PFVFSPOOF_REG_COUNT 8
460
461#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4))
462
463#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40))
464#define IXGBE_TIPG 0x0CB00
465#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4))
466#define IXGBE_MNGTXMAP 0x0CD10
467#define IXGBE_TIPG_FIBER_DEFAULT 3
468#define IXGBE_TXPBSIZE_SHIFT 10
469
470
471#define IXGBE_WUC 0x05800
472#define IXGBE_WUFC 0x05808
473#define IXGBE_WUS 0x05810
474#define IXGBE_IPAV 0x05838
475#define IXGBE_IP4AT 0x05840
476#define IXGBE_IP6AT 0x05880
477
478#define IXGBE_WUPL 0x05900
479#define IXGBE_WUPM 0x05A00
480#define IXGBE_VXLANCTRL 0x0000507C
481#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100))
482#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100))
483
484
485#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4
486#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2
487
488
489#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128
490#define IXGBE_FHFT_LENGTH_OFFSET 0xFC
491#define IXGBE_FHFT_LENGTH_MASK 0x0FF
492
493
494
495#define IXGBE_WUC_PME_EN 0x00000002
496#define IXGBE_WUC_PME_STATUS 0x00000004
497#define IXGBE_WUC_WKEN 0x00000010
498
499
500#define IXGBE_WUFC_LNKC 0x00000001
501#define IXGBE_WUFC_MAG 0x00000002
502#define IXGBE_WUFC_EX 0x00000004
503#define IXGBE_WUFC_MC 0x00000008
504#define IXGBE_WUFC_BC 0x00000010
505#define IXGBE_WUFC_ARP 0x00000020
506#define IXGBE_WUFC_IPV4 0x00000040
507#define IXGBE_WUFC_IPV6 0x00000080
508#define IXGBE_WUFC_MNG 0x00000100
509
510#define IXGBE_WUFC_IGNORE_TCO 0x00008000
511#define IXGBE_WUFC_FLX0 0x00010000
512#define IXGBE_WUFC_FLX1 0x00020000
513#define IXGBE_WUFC_FLX2 0x00040000
514#define IXGBE_WUFC_FLX3 0x00080000
515#define IXGBE_WUFC_FLX4 0x00100000
516#define IXGBE_WUFC_FLX5 0x00200000
517#define IXGBE_WUFC_FLX_FILTERS 0x000F0000
518#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000
519#define IXGBE_WUFC_ALL_FILTERS 0x003F00FF
520#define IXGBE_WUFC_FLX_OFFSET 16
521
522
523#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC
524#define IXGBE_WUS_MAG IXGBE_WUFC_MAG
525#define IXGBE_WUS_EX IXGBE_WUFC_EX
526#define IXGBE_WUS_MC IXGBE_WUFC_MC
527#define IXGBE_WUS_BC IXGBE_WUFC_BC
528#define IXGBE_WUS_ARP IXGBE_WUFC_ARP
529#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4
530#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6
531#define IXGBE_WUS_MNG IXGBE_WUFC_MNG
532#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0
533#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1
534#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2
535#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3
536#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4
537#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
538#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
539
540
541#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
542
543
544#define MAX_TRAFFIC_CLASS 8
545#define X540_TRAFFIC_CLASS 4
546#define IXGBE_RMCS 0x03D00
547#define IXGBE_DPMCS 0x07F40
548#define IXGBE_PDPMCS 0x0CD00
549#define IXGBE_RUPPBMR 0x050A0
550#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4))
551#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4))
552#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40))
553#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40))
554#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4))
555#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4))
556
557
558
559#define IXGBE_SECTXCTRL 0x08800
560#define IXGBE_SECTXSTAT 0x08804
561#define IXGBE_SECTXBUFFAF 0x08808
562#define IXGBE_SECTXMINIFG 0x08810
563#define IXGBE_SECRXCTRL 0x08D00
564#define IXGBE_SECRXSTAT 0x08D04
565
566
567#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001
568#define IXGBE_SECTXCTRL_TX_DIS 0x00000002
569#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004
570
571#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001
572#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002
573
574#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001
575#define IXGBE_SECRXCTRL_RX_DIS 0x00000002
576
577#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001
578#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002
579
580
581#define IXGBE_LSECTXCAP 0x08A00
582#define IXGBE_LSECRXCAP 0x08F00
583#define IXGBE_LSECTXCTRL 0x08A04
584#define IXGBE_LSECTXSCL 0x08A08
585#define IXGBE_LSECTXSCH 0x08A0C
586#define IXGBE_LSECTXSA 0x08A10
587#define IXGBE_LSECTXPN0 0x08A14
588#define IXGBE_LSECTXPN1 0x08A18
589#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n)))
590#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n)))
591#define IXGBE_LSECRXCTRL 0x08F04
592#define IXGBE_LSECRXSCL 0x08F08
593#define IXGBE_LSECRXSCH 0x08F0C
594#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i)))
595#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i)))
596#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
597#define IXGBE_LSECTXUT 0x08A3C
598#define IXGBE_LSECTXPKTE 0x08A40
599#define IXGBE_LSECTXPKTP 0x08A44
600#define IXGBE_LSECTXOCTE 0x08A48
601#define IXGBE_LSECTXOCTP 0x08A4C
602#define IXGBE_LSECRXUT 0x08F40
603#define IXGBE_LSECRXOCTD 0x08F44
604#define IXGBE_LSECRXOCTV 0x08F48
605#define IXGBE_LSECRXBAD 0x08F4C
606#define IXGBE_LSECRXNOSCI 0x08F50
607#define IXGBE_LSECRXUNSCI 0x08F54
608#define IXGBE_LSECRXUNCH 0x08F58
609#define IXGBE_LSECRXDELAY 0x08F5C
610#define IXGBE_LSECRXLATE 0x08F60
611#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n)))
612#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n)))
613#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n)))
614#define IXGBE_LSECRXUNSA 0x08F7C
615#define IXGBE_LSECRXNUSA 0x08F80
616
617
618#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000
619#define IXGBE_LSECTXCAP_SUM_SHIFT 16
620#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000
621#define IXGBE_LSECRXCAP_SUM_SHIFT 16
622
623#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003
624#define IXGBE_LSECTXCTRL_DISABLE 0x0
625#define IXGBE_LSECTXCTRL_AUTH 0x1
626#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2
627#define IXGBE_LSECTXCTRL_AISCI 0x00000020
628#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00
629#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8
630
631#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C
632#define IXGBE_LSECRXCTRL_EN_SHIFT 2
633#define IXGBE_LSECRXCTRL_DISABLE 0x0
634#define IXGBE_LSECRXCTRL_CHECK 0x1
635#define IXGBE_LSECRXCTRL_STRICT 0x2
636#define IXGBE_LSECRXCTRL_DROP 0x3
637#define IXGBE_LSECRXCTRL_PLSH 0x00000040
638#define IXGBE_LSECRXCTRL_RP 0x00000080
639#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33
640
641
642#define IXGBE_IPSTXIDX 0x08900
643#define IXGBE_IPSTXSALT 0x08904
644#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i)))
645#define IXGBE_IPSRXIDX 0x08E00
646#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i)))
647#define IXGBE_IPSRXSPI 0x08E14
648#define IXGBE_IPSRXIPIDX 0x08E18
649#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i)))
650#define IXGBE_IPSRXSALT 0x08E2C
651#define IXGBE_IPSRXMOD 0x08E30
652
653#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4
654
655
656#define IXGBE_RTRPCS 0x02430
657#define IXGBE_RTTDCS 0x04900
658#define IXGBE_RTTDCS_ARBDIS 0x00000040
659#define IXGBE_RTTPCS 0x0CD00
660#define IXGBE_RTRUP2TC 0x03020
661#define IXGBE_RTTUP2TC 0x0C800
662#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4))
663#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4))
664#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4))
665#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4))
666#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4))
667#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4))
668#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4))
669#define IXGBE_RTTDQSEL 0x04904
670#define IXGBE_RTTDT1C 0x04908
671#define IXGBE_RTTDT1S 0x0490C
672#define IXGBE_RTTQCNCR 0x08B00
673#define IXGBE_RTTQCNTG 0x04A90
674#define IXGBE_RTTBCNRD 0x0498C
675#define IXGBE_RTTQCNRR 0x0498C
676#define IXGBE_RTTDTECC 0x04990
677#define IXGBE_RTTDTECC_NO_BCN 0x00000100
678#define IXGBE_RTTBCNRC 0x04984
679#define IXGBE_RTTBCNRC_RS_ENA 0x80000000
680#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF
681#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14
682#define IXGBE_RTTBCNRC_RF_INT_MASK \
683 (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
684#define IXGBE_RTTBCNRM 0x04980
685#define IXGBE_RTTQCNRM 0x04980
686
687
688#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10))
689
690#define IXGBE_FCPTRL 0x02410
691#define IXGBE_FCPTRH 0x02414
692#define IXGBE_FCBUFF 0x02418
693#define IXGBE_FCDMARW 0x02420
694#define IXGBE_FCINVST0 0x03FC0
695#define IXGBE_FCINVST(_i) (IXGBE_FCINVST0 + ((_i) * 4))
696#define IXGBE_FCBUFF_VALID (1 << 0)
697#define IXGBE_FCBUFF_BUFFSIZE (3 << 3)
698#define IXGBE_FCBUFF_WRCONTX (1 << 7)
699#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00
700#define IXGBE_FCBUFF_OFFSET 0xffff0000
701#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3
702#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8
703#define IXGBE_FCBUFF_OFFSET_SHIFT 16
704#define IXGBE_FCDMARW_WE (1 << 14)
705#define IXGBE_FCDMARW_RE (1 << 15)
706#define IXGBE_FCDMARW_FCOESEL 0x000001ff
707#define IXGBE_FCDMARW_LASTSIZE 0xffff0000
708#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
709
710
711#define IXGBE_TEOFF 0x04A94
712#define IXGBE_TSOFF 0x04A98
713#define IXGBE_REOFF 0x05158
714#define IXGBE_RSOFF 0x051F8
715
716#define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10))
717#define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4))
718
719#define IXGBE_FCFLT 0x05108
720#define IXGBE_FCFLTRW 0x05110
721#define IXGBE_FCPARAM 0x051d8
722#define IXGBE_FCFLT_VALID (1 << 0)
723#define IXGBE_FCFLT_FIRST (1 << 1)
724#define IXGBE_FCFLT_SEQID 0x00ff0000
725#define IXGBE_FCFLT_SEQCNT 0xff000000
726#define IXGBE_FCFLTRW_RVALDT (1 << 13)
727#define IXGBE_FCFLTRW_WE (1 << 14)
728#define IXGBE_FCFLTRW_RE (1 << 15)
729
730#define IXGBE_FCRXCTRL 0x05100
731#define IXGBE_FCRXCTRL_FCOELLI (1 << 0)
732#define IXGBE_FCRXCTRL_SAVBAD (1 << 1)
733#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2)
734#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)
735#define IXGBE_FCRXCTRL_ALLH (1 << 4)
736#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)
737#define IXGBE_FCRXCTRL_ICRC (1 << 6)
738#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7)
739#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00
740#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
741
742#define IXGBE_FCRECTL 0x0ED00
743#define IXGBE_FCRETA0 0x0ED10
744#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4))
745#define IXGBE_FCRECTL_ENA 0x1
746#define IXGBE_FCRETA_SIZE 8
747#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f
748#define IXGBE_FCRETA_SIZE_X550 32
749
750#define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000
751#define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16
752
753
754#define IXGBE_CRCERRS 0x04000
755#define IXGBE_ILLERRC 0x04004
756#define IXGBE_ERRBC 0x04008
757#define IXGBE_MSPDC 0x04010
758#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4))
759#define IXGBE_MLFC 0x04034
760#define IXGBE_MRFC 0x04038
761#define IXGBE_RLEC 0x04040
762#define IXGBE_LXONTXC 0x03F60
763#define IXGBE_LXONRXC 0x0CF60
764#define IXGBE_LXOFFTXC 0x03F68
765#define IXGBE_LXOFFRXC 0x0CF68
766#define IXGBE_LXONRXCNT 0x041A4
767#define IXGBE_LXOFFRXCNT 0x041A8
768#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4))
769#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4))
770#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4))
771#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4))
772#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4))
773#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4))
774#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4))
775#define IXGBE_PRC64 0x0405C
776#define IXGBE_PRC127 0x04060
777#define IXGBE_PRC255 0x04064
778#define IXGBE_PRC511 0x04068
779#define IXGBE_PRC1023 0x0406C
780#define IXGBE_PRC1522 0x04070
781#define IXGBE_GPRC 0x04074
782#define IXGBE_BPRC 0x04078
783#define IXGBE_MPRC 0x0407C
784#define IXGBE_GPTC 0x04080
785#define IXGBE_GORCL 0x04088
786#define IXGBE_GORCH 0x0408C
787#define IXGBE_GOTCL 0x04090
788#define IXGBE_GOTCH 0x04094
789#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4))
790#define IXGBE_RUC 0x040A4
791#define IXGBE_RFC 0x040A8
792#define IXGBE_ROC 0x040AC
793#define IXGBE_RJC 0x040B0
794#define IXGBE_MNGPRC 0x040B4
795#define IXGBE_MNGPDC 0x040B8
796#define IXGBE_MNGPTC 0x0CF90
797#define IXGBE_TORL 0x040C0
798#define IXGBE_TORH 0x040C4
799#define IXGBE_TPR 0x040D0
800#define IXGBE_TPT 0x040D4
801#define IXGBE_PTC64 0x040D8
802#define IXGBE_PTC127 0x040DC
803#define IXGBE_PTC255 0x040E0
804#define IXGBE_PTC511 0x040E4
805#define IXGBE_PTC1023 0x040E8
806#define IXGBE_PTC1522 0x040EC
807#define IXGBE_MPTC 0x040F0
808#define IXGBE_BPTC 0x040F4
809#define IXGBE_XEC 0x04120
810#define IXGBE_SSVPC 0x08780
811
812#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
813#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
814 (0x08600 + ((_i) * 4)))
815#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4))
816
817#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40))
818#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40))
819#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40))
820#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40))
821#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40))
822#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40))
823#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40))
824#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8))
825#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8))
826#define IXGBE_FCCRC 0x05118
827#define IXGBE_FCOERPDC 0x0241C
828#define IXGBE_FCLAST 0x02424
829#define IXGBE_FCOEPRC 0x02428
830#define IXGBE_FCOEDWRC 0x0242C
831#define IXGBE_FCOEPTC 0x08784
832#define IXGBE_FCOEDWTC 0x08788
833#define IXGBE_O2BGPTC 0x041C4
834#define IXGBE_O2BSPC 0x087B0
835#define IXGBE_B2OSPC 0x041C0
836#define IXGBE_B2OGPRC 0x02F90
837#define IXGBE_PCRC8ECL 0x0E810
838#define IXGBE_PCRC8ECH 0x0E811
839#define IXGBE_PCRC8ECH_MASK 0x1F
840#define IXGBE_LDPCECL 0x0E820
841#define IXGBE_LDPCECH 0x0E821
842
843
844#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
845
846#define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005
847#define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1
848
849#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4
850
851#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7
852#define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6
853#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0
854#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1
855#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2
856#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3
857#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4
858#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5
859#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6
860#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7
861#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4
862#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6
863
864#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20
865#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400
866#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17
867#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10
868#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000
869#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000
870#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000
871#define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400
872#define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800
873#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100
874#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080
875#define IXGBE_MII_RESTART 0x200
876#define IXGBE_MII_AUTONEG_COMPLETE 0x20
877#define IXGBE_MII_AUTONEG_LINK_UP 0x04
878#define IXGBE_MII_AUTONEG_REG 0x0
879
880
881#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4))
882#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4))
883#define IXGBE_MANC 0x05820
884#define IXGBE_MFVAL 0x05824
885#define IXGBE_MANC2H 0x05860
886#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4))
887#define IXGBE_MIPAF 0x058B0
888#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8))
889#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8))
890#define IXGBE_FTFT 0x09400
891#define IXGBE_METF(_i) (0x05190 + ((_i) * 4))
892#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4))
893#define IXGBE_LSWFW 0x15014
894
895
896#define IXGBE_MANC_RCV_TCO_EN 0x00020000
897
898
899#define IXGBE_FWSM_MODE_MASK 0xE
900#define IXGBE_FWSM_FW_MODE_PT 0x4
901
902
903#define IXGBE_HICR 0x15F00
904#define IXGBE_FWSTS 0x15F0C
905#define IXGBE_HSMC0R 0x15F04
906#define IXGBE_HSMC1R 0x15F08
907#define IXGBE_SWSR 0x15F10
908#define IXGBE_HFDR 0x15FE8
909#define IXGBE_FLEX_MNG 0x15800
910
911#define IXGBE_HICR_EN 0x01
912
913#define IXGBE_HICR_C 0x02
914#define IXGBE_HICR_SV 0x04
915#define IXGBE_HICR_FW_RESET_ENABLE 0x40
916#define IXGBE_HICR_FW_RESET 0x80
917
918
919#define IXGBE_GCR 0x11000
920#define IXGBE_GTV 0x11004
921#define IXGBE_FUNCTAG 0x11008
922#define IXGBE_GLT 0x1100C
923#define IXGBE_GSCL_1 0x11010
924#define IXGBE_GSCL_2 0x11014
925#define IXGBE_GSCL_3 0x11018
926#define IXGBE_GSCL_4 0x1101C
927#define IXGBE_GSCN_0 0x11020
928#define IXGBE_GSCN_1 0x11024
929#define IXGBE_GSCN_2 0x11028
930#define IXGBE_GSCN_3 0x1102C
931#define IXGBE_FACTPS_8259X 0x10150
932#define IXGBE_FACTPS_X540 IXGBE_FACTPS_8259X
933#define IXGBE_FACTPS_X550 IXGBE_FACTPS_8259X
934#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS_8259X
935#define IXGBE_FACTPS_X550EM_a 0x15FEC
936#define IXGBE_FACTPS(_hw) IXGBE_BY_MAC((_hw), FACTPS)
937
938#define IXGBE_PCIEANACTL 0x11040
939#define IXGBE_SWSM_8259X 0x10140
940#define IXGBE_SWSM_X540 IXGBE_SWSM_8259X
941#define IXGBE_SWSM_X550 IXGBE_SWSM_8259X
942#define IXGBE_SWSM_X550EM_x IXGBE_SWSM_8259X
943#define IXGBE_SWSM_X550EM_a 0x15F70
944#define IXGBE_SWSM(_hw) IXGBE_BY_MAC((_hw), SWSM)
945#define IXGBE_FWSM_8259X 0x10148
946#define IXGBE_FWSM_X540 IXGBE_FWSM_8259X
947#define IXGBE_FWSM_X550 IXGBE_FWSM_8259X
948#define IXGBE_FWSM_X550EM_x IXGBE_FWSM_8259X
949#define IXGBE_FWSM_X550EM_a 0x15F74
950#define IXGBE_FWSM(_hw) IXGBE_BY_MAC((_hw), FWSM)
951#define IXGBE_GSSR 0x10160
952#define IXGBE_MREVID 0x11064
953#define IXGBE_DCA_ID 0x11070
954#define IXGBE_DCA_CTRL 0x11074
955#define IXGBE_SWFW_SYNC_8259X IXGBE_GSSR
956#define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC_8259X
957#define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC_8259X
958#define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC_8259X
959#define IXGBE_SWFW_SYNC_X550EM_a 0x15F78
960#define IXGBE_SWFW_SYNC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC)
961
962
963#define IXGBE_GCR_EXT 0x11050
964#define IXGBE_GSCL_5_82599 0x11030
965#define IXGBE_GSCL_6_82599 0x11034
966#define IXGBE_GSCL_7_82599 0x11038
967#define IXGBE_GSCL_8_82599 0x1103C
968#define IXGBE_PHYADR_82599 0x11040
969#define IXGBE_PHYDAT_82599 0x11044
970#define IXGBE_PHYCTL_82599 0x11048
971#define IXGBE_PBACLR_82599 0x11068
972
973#define IXGBE_CIAA_8259X 0x11088
974#define IXGBE_CIAA_X540 IXGBE_CIAA_8259X
975#define IXGBE_CIAA_X550 0x11508
976#define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550
977#define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550
978#define IXGBE_CIAA(_hw) IXGBE_BY_MAC((_hw), CIAA)
979
980#define IXGBE_CIAD_8259X 0x1108C
981#define IXGBE_CIAD_X540 IXGBE_CIAD_8259X
982#define IXGBE_CIAD_X550 0x11510
983#define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550
984#define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550
985#define IXGBE_CIAD(_hw) IXGBE_BY_MAC((_hw), CIAD)
986
987#define IXGBE_PICAUSE 0x110B0
988#define IXGBE_PIENA 0x110B8
989#define IXGBE_CDQ_MBR_82599 0x110B4
990#define IXGBE_PCIESPARE 0x110BC
991#define IXGBE_MISC_REG_82599 0x110F0
992#define IXGBE_ECC_CTRL_0_82599 0x11100
993#define IXGBE_ECC_CTRL_1_82599 0x11104
994#define IXGBE_ECC_STATUS_82599 0x110E0
995#define IXGBE_BAR_CTRL_82599 0x110F4
996
997
998#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000
999#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000
1000#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000
1001#define IXGBE_GCR_CAP_VER2 0x00040000
1002
1003#define IXGBE_GCR_EXT_MSIX_EN 0x80000000
1004#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000
1005#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001
1006#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002
1007#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003
1008#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \
1009 IXGBE_GCR_EXT_VT_MODE_64)
1010
1011
1012#define IXGBE_TSYNCRXCTL 0x05188
1013#define IXGBE_TSYNCTXCTL 0x08C00
1014#define IXGBE_RXSTMPL 0x051E8
1015#define IXGBE_RXSTMPH 0x051A4
1016#define IXGBE_RXSATRL 0x051A0
1017#define IXGBE_RXSATRH 0x051A8
1018#define IXGBE_RXMTRL 0x05120
1019#define IXGBE_TXSTMPL 0x08C04
1020#define IXGBE_TXSTMPH 0x08C08
1021#define IXGBE_SYSTIML 0x08C0C
1022#define IXGBE_SYSTIMH 0x08C10
1023#define IXGBE_SYSTIMR 0x08C58
1024#define IXGBE_TIMINCA 0x08C14
1025#define IXGBE_TIMADJL 0x08C18
1026#define IXGBE_TIMADJH 0x08C1C
1027#define IXGBE_TSAUXC 0x08C20
1028#define IXGBE_TRGTTIML0 0x08C24
1029#define IXGBE_TRGTTIMH0 0x08C28
1030#define IXGBE_TRGTTIML1 0x08C2C
1031#define IXGBE_TRGTTIMH1 0x08C30
1032#define IXGBE_CLKTIML 0x08C34
1033#define IXGBE_CLKTIMH 0x08C38
1034#define IXGBE_FREQOUT0 0x08C34
1035#define IXGBE_FREQOUT1 0x08C38
1036#define IXGBE_AUXSTMPL0 0x08C3C
1037#define IXGBE_AUXSTMPH0 0x08C40
1038#define IXGBE_AUXSTMPL1 0x08C44
1039#define IXGBE_AUXSTMPH1 0x08C48
1040#define IXGBE_TSIM 0x08C68
1041
1042
1043#define IXGBE_RDSTATCTL 0x02C20
1044#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4))
1045#define IXGBE_RDHMPN 0x02F08
1046#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
1047#define IXGBE_RDPROBE 0x02F20
1048#define IXGBE_RDMAM 0x02F30
1049#define IXGBE_RDMAD 0x02F34
1050#define IXGBE_TDSTATCTL 0x07C20
1051#define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4))
1052#define IXGBE_TDHMPN 0x07F08
1053#define IXGBE_TDHMPN2 0x082FC
1054#define IXGBE_TXDESCIC 0x082CC
1055#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
1056#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
1057#define IXGBE_TDPROBE 0x07F20
1058#define IXGBE_TXBUFCTRL 0x0C600
1059#define IXGBE_TXBUFDATA0 0x0C610
1060#define IXGBE_TXBUFDATA1 0x0C614
1061#define IXGBE_TXBUFDATA2 0x0C618
1062#define IXGBE_TXBUFDATA3 0x0C61C
1063#define IXGBE_RXBUFCTRL 0x03600
1064#define IXGBE_RXBUFDATA0 0x03610
1065#define IXGBE_RXBUFDATA1 0x03614
1066#define IXGBE_RXBUFDATA2 0x03618
1067#define IXGBE_RXBUFDATA3 0x0361C
1068#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4))
1069#define IXGBE_RFVAL 0x050A4
1070#define IXGBE_MDFTC1 0x042B8
1071#define IXGBE_MDFTC2 0x042C0
1072#define IXGBE_MDFTFIFO1 0x042C4
1073#define IXGBE_MDFTFIFO2 0x042C8
1074#define IXGBE_MDFTS 0x042CC
1075#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4))
1076#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4))
1077#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4))
1078#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4))
1079#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4))
1080#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4))
1081#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4))
1082#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4))
1083#define IXGBE_PCIEECCCTL 0x1106C
1084#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4))
1085#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4))
1086#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4))
1087#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4))
1088#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4))
1089#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4))
1090#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4))
1091#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4))
1092#define IXGBE_PCIEECCCTL0 0x11100
1093#define IXGBE_PCIEECCCTL1 0x11104
1094#define IXGBE_RXDBUECC 0x03F70
1095#define IXGBE_TXDBUECC 0x0CF70
1096#define IXGBE_RXDBUEST 0x03F74
1097#define IXGBE_TXDBUEST 0x0CF74
1098#define IXGBE_PBTXECC 0x0C300
1099#define IXGBE_PBRXECC 0x03300
1100#define IXGBE_GHECCR 0x110B0
1101
1102
1103#define IXGBE_PCS1GCFIG 0x04200
1104#define IXGBE_PCS1GLCTL 0x04208
1105#define IXGBE_PCS1GLSTA 0x0420C
1106#define IXGBE_PCS1GDBG0 0x04210
1107#define IXGBE_PCS1GDBG1 0x04214
1108#define IXGBE_PCS1GANA 0x04218
1109#define IXGBE_PCS1GANLP 0x0421C
1110#define IXGBE_PCS1GANNP 0x04220
1111#define IXGBE_PCS1GANLPNP 0x04224
1112#define IXGBE_HLREG0 0x04240
1113#define IXGBE_HLREG1 0x04244
1114#define IXGBE_PAP 0x04248
1115#define IXGBE_MACA 0x0424C
1116#define IXGBE_APAE 0x04250
1117#define IXGBE_ARD 0x04254
1118#define IXGBE_AIS 0x04258
1119#define IXGBE_MSCA 0x0425C
1120#define IXGBE_MSRWD 0x04260
1121#define IXGBE_MLADD 0x04264
1122#define IXGBE_MHADD 0x04268
1123#define IXGBE_MAXFRS 0x04268
1124#define IXGBE_TREG 0x0426C
1125#define IXGBE_PCSS1 0x04288
1126#define IXGBE_PCSS2 0x0428C
1127#define IXGBE_XPCSS 0x04290
1128#define IXGBE_MFLCN 0x04294
1129#define IXGBE_SERDESC 0x04298
1130#define IXGBE_MACS 0x0429C
1131#define IXGBE_AUTOC 0x042A0
1132#define IXGBE_LINKS 0x042A4
1133#define IXGBE_LINKS2 0x04324
1134#define IXGBE_AUTOC2 0x042A8
1135#define IXGBE_AUTOC3 0x042AC
1136#define IXGBE_ANLP1 0x042B0
1137#define IXGBE_ANLP2 0x042B4
1138#define IXGBE_MACC 0x04330
1139#define IXGBE_ATLASCTL 0x04800
1140#define IXGBE_MMNGC 0x042D0
1141#define IXGBE_ANLPNP1 0x042D4
1142#define IXGBE_ANLPNP2 0x042D8
1143#define IXGBE_KRPCSFC 0x042E0
1144#define IXGBE_KRPCSS 0x042E4
1145#define IXGBE_FECS1 0x042E8
1146#define IXGBE_FECS2 0x042EC
1147#define IXGBE_SMADARCTL 0x14F10
1148#define IXGBE_MPVC 0x04318
1149#define IXGBE_SGMIIC 0x04314
1150
1151
1152#define IXGBE_RXNFGPC 0x041B0
1153#define IXGBE_RXNFGBCL 0x041B4
1154#define IXGBE_RXNFGBCH 0x041B8
1155#define IXGBE_RXDGPC 0x02F50
1156#define IXGBE_RXDGBCL 0x02F54
1157#define IXGBE_RXDGBCH 0x02F58
1158#define IXGBE_RXDDGPC 0x02F5C
1159#define IXGBE_RXDDGBCL 0x02F60
1160#define IXGBE_RXDDGBCH 0x02F64
1161#define IXGBE_RXLPBKGPC 0x02F68
1162#define IXGBE_RXLPBKGBCL 0x02F6C
1163#define IXGBE_RXLPBKGBCH 0x02F70
1164#define IXGBE_RXDLPBKGPC 0x02F74
1165#define IXGBE_RXDLPBKGBCL 0x02F78
1166#define IXGBE_RXDLPBKGBCH 0x02F7C
1167#define IXGBE_TXDGPC 0x087A0
1168#define IXGBE_TXDGBCL 0x087A4
1169#define IXGBE_TXDGBCH 0x087A8
1170
1171#define IXGBE_RXDSTATCTRL 0x02F40
1172
1173
1174#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
1175
1176
1177#define IXGBE_CORECTL 0x014F00
1178
1179#define IXGBE_BARCTRL 0x110F4
1180#define IXGBE_BARCTRL_FLSIZE 0x0700
1181#define IXGBE_BARCTRL_FLSIZE_SHIFT 8
1182#define IXGBE_BARCTRL_CSRSIZE 0x2000
1183
1184
1185#define IXGBE_RSCCTL_RSCEN 0x01
1186#define IXGBE_RSCCTL_MAXDESC_1 0x00
1187#define IXGBE_RSCCTL_MAXDESC_4 0x04
1188#define IXGBE_RSCCTL_MAXDESC_8 0x08
1189#define IXGBE_RSCCTL_MAXDESC_16 0x0C
1190
1191
1192#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F
1193#define IXGBE_RSCDBU_RSCACKDIS 0x00000080
1194
1195
1196#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000
1197#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002
1198#define IXGBE_RDRXCTL_PSP 0x00000004
1199#define IXGBE_RDRXCTL_MVMEN 0x00000020
1200#define IXGBE_RDRXCTL_DMAIDONE 0x00000008
1201#define IXGBE_RDRXCTL_AGGDIS 0x00010000
1202#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000
1203#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000
1204#define IXGBE_RDRXCTL_RSCACKC 0x02000000
1205#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000
1206
1207
1208#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4)
1209#define IXGBE_RQTC_TC0_MASK (0x7 << 0)
1210#define IXGBE_RQTC_TC1_MASK (0x7 << 4)
1211#define IXGBE_RQTC_TC2_MASK (0x7 << 8)
1212#define IXGBE_RQTC_TC3_MASK (0x7 << 12)
1213#define IXGBE_RQTC_TC4_MASK (0x7 << 16)
1214#define IXGBE_RQTC_TC5_MASK (0x7 << 20)
1215#define IXGBE_RQTC_TC6_MASK (0x7 << 24)
1216#define IXGBE_RQTC_TC7_MASK (0x7 << 28)
1217
1218
1219#define IXGBE_PSRTYPE_RQPL_MASK 0x7
1220#define IXGBE_PSRTYPE_RQPL_SHIFT 29
1221
1222
1223#define IXGBE_CTRL_GIO_DIS 0x00000004
1224#define IXGBE_CTRL_LNK_RST 0x00000008
1225#define IXGBE_CTRL_RST 0x04000000
1226#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
1227
1228
1229#define IXGBE_FACTPS_MNGCG 0x20000000
1230#define IXGBE_FACTPS_LFS 0x40000000
1231
1232
1233#define IXGBE_MHADD_MFS_MASK 0xFFFF0000
1234#define IXGBE_MHADD_MFS_SHIFT 16
1235
1236
1237#define IXGBE_CTRL_EXT_PFRSTD 0x00004000
1238#define IXGBE_CTRL_EXT_NS_DIS 0x00010000
1239#define IXGBE_CTRL_EXT_RO_DIS 0x00020000
1240#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000
1241
1242
1243#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000
1244#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001
1245
1246#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00
1247#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02
1248
1249#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F
1250#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000
1251#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24
1252#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5)
1253#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6)
1254#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7)
1255#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9)
1256#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13)
1257#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15)
1258
1259#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F
1260#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000
1261#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24
1262#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5)
1263#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9)
1264#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11)
1265#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13)
1266#define IXGBE_DCA_MAX_QUEUES_82598 16
1267
1268
1269#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF
1270#define IXGBE_MSCA_NP_ADDR_SHIFT 0
1271#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000
1272#define IXGBE_MSCA_DEV_TYPE_SHIFT 16
1273#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000
1274#define IXGBE_MSCA_PHY_ADDR_SHIFT 21
1275#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000
1276#define IXGBE_MSCA_OP_CODE_SHIFT 26
1277#define IXGBE_MSCA_ADDR_CYCLE 0x00000000
1278#define IXGBE_MSCA_WRITE 0x04000000
1279#define IXGBE_MSCA_READ 0x0C000000
1280#define IXGBE_MSCA_READ_AUTOINC 0x08000000
1281#define IXGBE_MSCA_ST_CODE_MASK 0x30000000
1282#define IXGBE_MSCA_ST_CODE_SHIFT 28
1283#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000
1284#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000
1285#define IXGBE_MSCA_MDI_COMMAND 0x40000000
1286#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000
1287
1288
1289#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
1290#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
1291#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
1292#define IXGBE_MSRWD_READ_DATA_SHIFT 16
1293
1294
1295#define IXGBE_ATLAS_PDN_LPBK 0x24
1296#define IXGBE_ATLAS_PDN_10G 0xB
1297#define IXGBE_ATLAS_PDN_1G 0xC
1298#define IXGBE_ATLAS_PDN_AN 0xD
1299
1300
1301#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
1302#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
1303#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
1304#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
1305#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
1306
1307
1308#define IXGBE_CORECTL_WRITE_CMD 0x00010000
1309
1310
1311
1312#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
1313#define IXGBE_MDIO_PCS_DEV_TYPE 0x3
1314#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
1315#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
1316#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E
1317#define IXGBE_TWINAX_DEV 1
1318
1319#define IXGBE_MDIO_COMMAND_TIMEOUT 100
1320
1321#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0
1322#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1
1323#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008
1324#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010
1325#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
1326#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
1327
1328#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0
1329#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1
1330#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800
1331#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00
1332#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01
1333#define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1
1334#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10
1335#define IXGBE_MDIO_AUTO_NEG_LP 0x13
1336#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C
1337
1338#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800
1339#define IXGBE_AUTO_NEG_LP_STATUS 0xE820
1340#define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000
1341#define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02
1342#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3
1343#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479
1344#define IXGBE_MDIO_POWER_UP_STALL 0x8000
1345#define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00
1346#define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00
1347#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01
1348#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01
1349#define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00
1350#define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010
1351#define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000
1352#define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850
1353#define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007
1354#define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400
1355
1356#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000
1357#define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4
1358#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1
1359#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200
1360#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000
1361#define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010
1362
1363#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A
1364#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B
1365#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C
1366#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401
1367#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1
1368#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9
1369#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001
1370
1371
1372#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400
1373#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17
1374#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000
1375#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000
1376#define IXGBE_MII_AUTONEG_REG 0x0
1377
1378#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
1379#define IXGBE_MAX_PHY_ADDR 32
1380
1381
1382#define TN1010_PHY_ID 0x00A19410
1383#define TNX_FW_REV 0xB
1384#define X540_PHY_ID 0x01540200
1385#define X550_PHY_ID 0x01540220
1386#define X557_PHY_ID 0x01540240
1387#define QT2022_PHY_ID 0x0043A400
1388#define ATH_PHY_ID 0x03429050
1389#define AQ_FW_REV 0x20
1390
1391
1392#define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
1393
1394
1395#define IXGBE_PHY_INIT_OFFSET_NL 0x002B
1396#define IXGBE_PHY_INIT_END_NL 0xFFFF
1397#define IXGBE_CONTROL_MASK_NL 0xF000
1398#define IXGBE_DATA_MASK_NL 0x0FFF
1399#define IXGBE_CONTROL_SHIFT_NL 12
1400#define IXGBE_DELAY_NL 0
1401#define IXGBE_DATA_NL 1
1402#define IXGBE_CONTROL_NL 0x000F
1403#define IXGBE_CONTROL_EOL_NL 0x0FFF
1404#define IXGBE_CONTROL_SOL_NL 0x0000
1405
1406
1407#define IXGBE_SDP0_GPIEN_8259X 0x00000001
1408#define IXGBE_SDP1_GPIEN_8259X 0x00000002
1409#define IXGBE_SDP2_GPIEN_8259X 0x00000004
1410#define IXGBE_SDP0_GPIEN_X540 0x00000002
1411#define IXGBE_SDP1_GPIEN_X540 0x00000004
1412#define IXGBE_SDP2_GPIEN_X540 0x00000008
1413#define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540
1414#define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540
1415#define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540
1416#define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540
1417#define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540
1418#define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540
1419#define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540
1420#define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540
1421#define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540
1422#define IXGBE_SDP0_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN)
1423#define IXGBE_SDP1_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN)
1424#define IXGBE_SDP2_GPIEN(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN)
1425
1426#define IXGBE_GPIE_MSIX_MODE 0x00000010
1427#define IXGBE_GPIE_OCD 0x00000020
1428#define IXGBE_GPIE_EIMEN 0x00000040
1429#define IXGBE_GPIE_EIAME 0x40000000
1430#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
1431#define IXGBE_GPIE_RSC_DELAY_SHIFT 11
1432#define IXGBE_GPIE_VTMODE_MASK 0x0000C000
1433#define IXGBE_GPIE_VTMODE_16 0x00004000
1434#define IXGBE_GPIE_VTMODE_32 0x00008000
1435#define IXGBE_GPIE_VTMODE_64 0x0000C000
1436
1437
1438#define IXGBE_TXPBSIZE_20KB 0x00005000
1439#define IXGBE_TXPBSIZE_40KB 0x0000A000
1440#define IXGBE_RXPBSIZE_48KB 0x0000C000
1441#define IXGBE_RXPBSIZE_64KB 0x00010000
1442#define IXGBE_RXPBSIZE_80KB 0x00014000
1443#define IXGBE_RXPBSIZE_128KB 0x00020000
1444#define IXGBE_RXPBSIZE_MAX 0x00080000
1445#define IXGBE_TXPBSIZE_MAX 0x00028000
1446
1447#define IXGBE_TXPKT_SIZE_MAX 0xA
1448#define IXGBE_MAX_PB 8
1449
1450
1451enum {
1452 PBA_STRATEGY_EQUAL = 0,
1453#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL
1454 PBA_STRATEGY_WEIGHTED = 1,
1455#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED
1456};
1457
1458
1459#define IXGBE_TFCS_TXOFF 0x00000001
1460#define IXGBE_TFCS_TXOFF0 0x00000100
1461#define IXGBE_TFCS_TXOFF1 0x00000200
1462#define IXGBE_TFCS_TXOFF2 0x00000400
1463#define IXGBE_TFCS_TXOFF3 0x00000800
1464#define IXGBE_TFCS_TXOFF4 0x00001000
1465#define IXGBE_TFCS_TXOFF5 0x00002000
1466#define IXGBE_TFCS_TXOFF6 0x00004000
1467#define IXGBE_TFCS_TXOFF7 0x00008000
1468
1469
1470#define IXGBE_TCPTIMER_KS 0x00000100
1471#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
1472#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
1473#define IXGBE_TCPTIMER_LOOP 0x00000800
1474#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
1475
1476
1477#define IXGBE_HLREG0_TXCRCEN 0x00000001
1478#define IXGBE_HLREG0_RXCRCSTRP 0x00000002
1479#define IXGBE_HLREG0_JUMBOEN 0x00000004
1480#define IXGBE_HLREG0_TXPADEN 0x00000400
1481#define IXGBE_HLREG0_TXPAUSEEN 0x00001000
1482#define IXGBE_HLREG0_RXPAUSEEN 0x00004000
1483#define IXGBE_HLREG0_LPBK 0x00008000
1484#define IXGBE_HLREG0_MDCSPD 0x00010000
1485#define IXGBE_HLREG0_CONTMDC 0x00020000
1486#define IXGBE_HLREG0_CTRLFLTR 0x00040000
1487#define IXGBE_HLREG0_PREPEND 0x00F00000
1488#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000
1489#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000
1490#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000
1491#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000
1492
1493
1494#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
1495#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
1496
1497
1498#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000
1499#define IXGBE_VT_CTL_REPLEN 0x40000000
1500#define IXGBE_VT_CTL_VT_ENABLE 0x00000001
1501#define IXGBE_VT_CTL_POOL_SHIFT 7
1502#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
1503
1504
1505#define IXGBE_VMOLR_AUPE 0x01000000
1506#define IXGBE_VMOLR_ROMPE 0x02000000
1507#define IXGBE_VMOLR_ROPE 0x04000000
1508#define IXGBE_VMOLR_BAM 0x08000000
1509#define IXGBE_VMOLR_MPE 0x10000000
1510
1511
1512#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF
1513
1514#define IXGBE_VF_INIT_TIMEOUT 200
1515
1516
1517#define IXGBE_RDHMPN_RDICADDR 0x007FF800
1518#define IXGBE_RDHMPN_RDICRDREQ 0x00800000
1519#define IXGBE_RDHMPN_RDICADDR_SHIFT 11
1520#define IXGBE_TDHMPN_TDICADDR 0x003FF800
1521#define IXGBE_TDHMPN_TDICRDREQ 0x00800000
1522#define IXGBE_TDHMPN_TDICADDR_SHIFT 11
1523
1524#define IXGBE_RDMAM_MEM_SEL_SHIFT 13
1525#define IXGBE_RDMAM_DWORD_SHIFT 9
1526#define IXGBE_RDMAM_DESC_COMP_FIFO 1
1527#define IXGBE_RDMAM_DFC_CMD_FIFO 2
1528#define IXGBE_RDMAM_TCN_STATUS_RAM 4
1529#define IXGBE_RDMAM_WB_COLL_FIFO 5
1530#define IXGBE_RDMAM_QSC_CNT_RAM 6
1531#define IXGBE_RDMAM_QSC_QUEUE_CNT 8
1532#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA
1533#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135
1534#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4
1535#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48
1536#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7
1537#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256
1538#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9
1539#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8
1540#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4
1541#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64
1542#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4
1543#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32
1544#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4
1545#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128
1546#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8
1547
1548#define IXGBE_TXDESCIC_READY 0x80000000
1549
1550
1551#define IXGBE_RXCSUM_IPPCSE 0x00001000
1552#define IXGBE_RXCSUM_PCSD 0x00002000
1553
1554
1555#define IXGBE_FCRTL_XONE 0x80000000
1556#define IXGBE_FCRTH_FCEN 0x80000000
1557
1558
1559#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF
1560
1561
1562#define IXGBE_RMCS_RRM 0x00000002
1563
1564#define IXGBE_RMCS_RAC 0x00000004
1565#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC
1566#define IXGBE_RMCS_TFCE_802_3X 0x00000008
1567#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010
1568#define IXGBE_RMCS_ARBDIS 0x00000040
1569
1570
1571#define IXGBE_FCCFG_TFCE_802_3X 0x00000008
1572#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010
1573
1574
1575
1576
1577#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF
1578#define IXGBE_EICR_FLOW_DIR 0x00010000
1579#define IXGBE_EICR_RX_MISS 0x00020000
1580#define IXGBE_EICR_PCI 0x00040000
1581#define IXGBE_EICR_MAILBOX 0x00080000
1582#define IXGBE_EICR_LSC 0x00100000
1583#define IXGBE_EICR_LINKSEC 0x00200000
1584#define IXGBE_EICR_MNG 0x00400000
1585#define IXGBE_EICR_TS 0x00800000
1586#define IXGBE_EICR_TIMESYNC 0x01000000
1587#define IXGBE_EICR_GPI_SDP0_8259X 0x01000000
1588#define IXGBE_EICR_GPI_SDP1_8259X 0x02000000
1589#define IXGBE_EICR_GPI_SDP2_8259X 0x04000000
1590#define IXGBE_EICR_GPI_SDP0_X540 0x02000000
1591#define IXGBE_EICR_GPI_SDP1_X540 0x04000000
1592#define IXGBE_EICR_GPI_SDP2_X540 0x08000000
1593#define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540
1594#define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540
1595#define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540
1596#define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540
1597#define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540
1598#define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540
1599#define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540
1600#define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540
1601#define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540
1602#define IXGBE_EICR_GPI_SDP0(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0)
1603#define IXGBE_EICR_GPI_SDP1(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1)
1604#define IXGBE_EICR_GPI_SDP2(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2)
1605
1606#define IXGBE_EICR_ECC 0x10000000
1607#define IXGBE_EICR_PBUR 0x10000000
1608#define IXGBE_EICR_DHER 0x20000000
1609#define IXGBE_EICR_TCP_TIMER 0x40000000
1610#define IXGBE_EICR_OTHER 0x80000000
1611
1612
1613#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1614#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR
1615#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS
1616#define IXGBE_EICS_PCI IXGBE_EICR_PCI
1617#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX
1618#define IXGBE_EICS_LSC IXGBE_EICR_LSC
1619#define IXGBE_EICS_MNG IXGBE_EICR_MNG
1620#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC
1621#define IXGBE_EICS_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw)
1622#define IXGBE_EICS_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw)
1623#define IXGBE_EICS_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw)
1624#define IXGBE_EICS_ECC IXGBE_EICR_ECC
1625#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR
1626#define IXGBE_EICS_DHER IXGBE_EICR_DHER
1627#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER
1628#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER
1629
1630
1631#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1632#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR
1633#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS
1634#define IXGBE_EIMS_PCI IXGBE_EICR_PCI
1635#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX
1636#define IXGBE_EIMS_LSC IXGBE_EICR_LSC
1637#define IXGBE_EIMS_MNG IXGBE_EICR_MNG
1638#define IXGBE_EIMS_TS IXGBE_EICR_TS
1639#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC
1640#define IXGBE_EIMS_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw)
1641#define IXGBE_EIMS_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw)
1642#define IXGBE_EIMS_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw)
1643#define IXGBE_EIMS_ECC IXGBE_EICR_ECC
1644#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR
1645#define IXGBE_EIMS_DHER IXGBE_EICR_DHER
1646#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER
1647#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER
1648
1649
1650#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE
1651#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR
1652#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS
1653#define IXGBE_EIMC_PCI IXGBE_EICR_PCI
1654#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX
1655#define IXGBE_EIMC_LSC IXGBE_EICR_LSC
1656#define IXGBE_EIMC_MNG IXGBE_EICR_MNG
1657#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC
1658#define IXGBE_EIMC_GPI_SDP0(_hw) IXGBE_EICR_GPI_SDP0(_hw)
1659#define IXGBE_EIMC_GPI_SDP1(_hw) IXGBE_EICR_GPI_SDP1(_hw)
1660#define IXGBE_EIMC_GPI_SDP2(_hw) IXGBE_EICR_GPI_SDP2(_hw)
1661#define IXGBE_EIMC_ECC IXGBE_EICR_ECC
1662#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR
1663#define IXGBE_EIMC_DHER IXGBE_EICR_DHER
1664#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER
1665#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER
1666
1667#define IXGBE_EIMS_ENABLE_MASK ( \
1668 IXGBE_EIMS_RTX_QUEUE | \
1669 IXGBE_EIMS_LSC | \
1670 IXGBE_EIMS_TCP_TIMER | \
1671 IXGBE_EIMS_OTHER)
1672
1673
1674#define IXGBE_IMIR_PORT_IM_EN 0x00010000
1675#define IXGBE_IMIR_PORT_BP 0x00020000
1676#define IXGBE_IMIREXT_SIZE_BP 0x00001000
1677#define IXGBE_IMIREXT_CTRL_URG 0x00002000
1678#define IXGBE_IMIREXT_CTRL_ACK 0x00004000
1679#define IXGBE_IMIREXT_CTRL_PSH 0x00008000
1680#define IXGBE_IMIREXT_CTRL_RST 0x00010000
1681#define IXGBE_IMIREXT_CTRL_SYN 0x00020000
1682#define IXGBE_IMIREXT_CTRL_FIN 0x00040000
1683#define IXGBE_IMIREXT_CTRL_BP 0x00080000
1684#define IXGBE_IMIR_SIZE_BP_82599 0x00001000
1685#define IXGBE_IMIR_CTRL_URG_82599 0x00002000
1686#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000
1687#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000
1688#define IXGBE_IMIR_CTRL_RST_82599 0x00010000
1689#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000
1690#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000
1691#define IXGBE_IMIR_CTRL_BP_82599 0x00080000
1692#define IXGBE_IMIR_LLI_EN_82599 0x00100000
1693#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F
1694#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21
1695#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007
1696#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008
1697
1698#define IXGBE_MAX_FTQF_FILTERS 128
1699#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003
1700#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000
1701#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001
1702#define IXGBE_FTQF_PROTOCOL_SCTP 2
1703#define IXGBE_FTQF_PRIORITY_MASK 0x00000007
1704#define IXGBE_FTQF_PRIORITY_SHIFT 2
1705#define IXGBE_FTQF_POOL_MASK 0x0000003F
1706#define IXGBE_FTQF_POOL_SHIFT 8
1707#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F
1708#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25
1709#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E
1710#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D
1711#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B
1712#define IXGBE_FTQF_DEST_PORT_MASK 0x17
1713#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F
1714#define IXGBE_FTQF_POOL_MASK_EN 0x40000000
1715#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000
1716
1717
1718#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
1719
1720
1721#define IXGBE_IVAR_REG_NUM 25
1722#define IXGBE_IVAR_REG_NUM_82599 64
1723#define IXGBE_IVAR_TXRX_ENTRY 96
1724#define IXGBE_IVAR_RX_ENTRY 64
1725#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
1726#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
1727#define IXGBE_IVAR_TX_ENTRY 32
1728
1729#define IXGBE_IVAR_TCP_TIMER_INDEX 96
1730#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97
1731
1732#define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
1733
1734#define IXGBE_IVAR_ALLOC_VAL 0x80
1735
1736
1737#define IXGBE_MAX_ETQF_FILTERS 8
1738#define IXGBE_ETQF_FCOE 0x08000000
1739#define IXGBE_ETQF_BCN 0x10000000
1740#define IXGBE_ETQF_TX_ANTISPOOF 0x20000000
1741#define IXGBE_ETQF_1588 0x40000000
1742#define IXGBE_ETQF_FILTER_EN 0x80000000
1743#define IXGBE_ETQF_POOL_ENABLE (1 << 26)
1744#define IXGBE_ETQF_POOL_SHIFT 20
1745
1746#define IXGBE_ETQS_RX_QUEUE 0x007F0000
1747#define IXGBE_ETQS_RX_QUEUE_SHIFT 16
1748#define IXGBE_ETQS_LLI 0x20000000
1749#define IXGBE_ETQS_QUEUE_EN 0x80000000
1750
1751
1752
1753
1754
1755
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765#define IXGBE_ETQF_FILTER_EAPOL 0
1766#define IXGBE_ETQF_FILTER_FCOE 2
1767#define IXGBE_ETQF_FILTER_1588 3
1768#define IXGBE_ETQF_FILTER_FIP 4
1769#define IXGBE_ETQF_FILTER_LLDP 5
1770#define IXGBE_ETQF_FILTER_LACP 6
1771#define IXGBE_ETQF_FILTER_FC 7
1772
1773
1774#define IXGBE_VLNCTRL_VET 0x0000FFFF
1775#define IXGBE_VLNCTRL_CFI 0x10000000
1776#define IXGBE_VLNCTRL_CFIEN 0x20000000
1777#define IXGBE_VLNCTRL_VFE 0x40000000
1778#define IXGBE_VLNCTRL_VME 0x80000000
1779
1780
1781#define IXGBE_VLVF_VIEN 0x80000000
1782#define IXGBE_VLVF_ENTRIES 64
1783#define IXGBE_VLVF_VLANID_MASK 0x00000FFF
1784
1785
1786#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000
1787#define IXGBE_VMVIR_VLANA_NEVER 0x80000000
1788
1789#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100
1790
1791
1792#define IXGBE_STATUS_LAN_ID 0x0000000C
1793#define IXGBE_STATUS_LAN_ID_SHIFT 2
1794#define IXGBE_STATUS_GIO 0x00080000
1795
1796#define IXGBE_STATUS_LAN_ID_0 0x00000000
1797#define IXGBE_STATUS_LAN_ID_1 0x00000004
1798
1799
1800#define IXGBE_ESDP_SDP0 0x00000001
1801#define IXGBE_ESDP_SDP1 0x00000002
1802#define IXGBE_ESDP_SDP2 0x00000004
1803#define IXGBE_ESDP_SDP3 0x00000008
1804#define IXGBE_ESDP_SDP4 0x00000010
1805#define IXGBE_ESDP_SDP5 0x00000020
1806#define IXGBE_ESDP_SDP6 0x00000040
1807#define IXGBE_ESDP_SDP0_DIR 0x00000100
1808#define IXGBE_ESDP_SDP1_DIR 0x00000200
1809#define IXGBE_ESDP_SDP4_DIR 0x00000004
1810#define IXGBE_ESDP_SDP5_DIR 0x00002000
1811#define IXGBE_ESDP_SDP0_NATIVE 0x00010000
1812#define IXGBE_ESDP_SDP1_NATIVE 0x00020000
1813
1814
1815#define IXGBE_LED_IVRT_BASE 0x00000040
1816#define IXGBE_LED_BLINK_BASE 0x00000080
1817#define IXGBE_LED_MODE_MASK_BASE 0x0000000F
1818#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
1819#define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
1820#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
1821#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
1822#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
1823
1824
1825#define IXGBE_LED_LINK_UP 0x0
1826#define IXGBE_LED_LINK_10G 0x1
1827#define IXGBE_LED_MAC 0x2
1828#define IXGBE_LED_FILTER 0x3
1829#define IXGBE_LED_LINK_ACTIVE 0x4
1830#define IXGBE_LED_LINK_1G 0x5
1831#define IXGBE_LED_ON 0xE
1832#define IXGBE_LED_OFF 0xF
1833
1834
1835#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
1836#define IXGBE_AUTOC_KX4_SUPP 0x80000000
1837#define IXGBE_AUTOC_KX_SUPP 0x40000000
1838#define IXGBE_AUTOC_PAUSE 0x30000000
1839#define IXGBE_AUTOC_ASM_PAUSE 0x20000000
1840#define IXGBE_AUTOC_SYM_PAUSE 0x10000000
1841#define IXGBE_AUTOC_RF 0x08000000
1842#define IXGBE_AUTOC_PD_TMR 0x06000000
1843#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
1844#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
1845#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
1846#define IXGBE_AUTOC_FECA 0x00040000
1847#define IXGBE_AUTOC_FECR 0x00020000
1848#define IXGBE_AUTOC_KR_SUPP 0x00010000
1849#define IXGBE_AUTOC_AN_RESTART 0x00001000
1850#define IXGBE_AUTOC_FLU 0x00000001
1851#define IXGBE_AUTOC_LMS_SHIFT 13
1852#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
1853#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1854#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT)
1855#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1856#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1857#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
1858#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
1859#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
1860#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
1861#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
1862#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
1863#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1864
1865#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200
1866#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
1867#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
1868#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
1869#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1870#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1871#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
1872#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1873#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1874#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1875#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
1876
1877#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000
1878#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000
1879#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
1880#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1881#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1882#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
1883#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000
1884#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
1885
1886#define IXGBE_MACC_FLU 0x00000001
1887#define IXGBE_MACC_FSV_10G 0x00030000
1888#define IXGBE_MACC_FS 0x00040000
1889#define IXGBE_MAC_RX2TX_LPBK 0x00000002
1890
1891
1892#define IXGBE_MMNGC_MNG_VETO 0x00000001
1893
1894
1895#define IXGBE_LINKS_KX_AN_COMP 0x80000000
1896#define IXGBE_LINKS_UP 0x40000000
1897#define IXGBE_LINKS_SPEED 0x20000000
1898#define IXGBE_LINKS_MODE 0x18000000
1899#define IXGBE_LINKS_RX_MODE 0x06000000
1900#define IXGBE_LINKS_TX_MODE 0x01800000
1901#define IXGBE_LINKS_XGXS_EN 0x00400000
1902#define IXGBE_LINKS_SGMII_EN 0x02000000
1903#define IXGBE_LINKS_PCS_1G_EN 0x00200000
1904#define IXGBE_LINKS_1G_AN_EN 0x00100000
1905#define IXGBE_LINKS_KX_AN_IDLE 0x00080000
1906#define IXGBE_LINKS_1G_SYNC 0x00040000
1907#define IXGBE_LINKS_10G_ALIGN 0x00020000
1908#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
1909#define IXGBE_LINKS_TL_FAULT 0x00001000
1910#define IXGBE_LINKS_SIGNAL 0x00000F00
1911
1912#define IXGBE_LINKS_SPEED_NON_STD 0x08000000
1913#define IXGBE_LINKS_SPEED_82599 0x30000000
1914#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
1915#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
1916#define IXGBE_LINKS_SPEED_100_82599 0x10000000
1917#define IXGBE_LINK_UP_TIME 90
1918#define IXGBE_AUTO_NEG_TIME 45
1919
1920#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040
1921
1922
1923#define IXGBE_PCS1GLSTA_LINK_OK 1
1924#define IXGBE_PCS1GLSTA_SYNK_OK 0x10
1925#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000
1926#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000
1927#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000
1928#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
1929#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000
1930
1931#define IXGBE_PCS1GANA_SYM_PAUSE 0x80
1932#define IXGBE_PCS1GANA_ASM_PAUSE 0x100
1933
1934
1935#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000
1936#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1
1937#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20
1938#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40
1939#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000
1940#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000
1941
1942
1943#define IXGBE_ANLP1_PAUSE 0x0C00
1944#define IXGBE_ANLP1_SYM_PAUSE 0x0400
1945#define IXGBE_ANLP1_ASM_PAUSE 0x0800
1946#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000
1947
1948
1949#define IXGBE_SWSM_SMBI 0x00000001
1950#define IXGBE_SWSM_SWESMBI 0x00000002
1951#define IXGBE_SWSM_WMNG 0x00000004
1952#define IXGBE_SWFW_REGSMP 0x80000000
1953
1954
1955#define IXGBE_GSSR_EEP_SM 0x0001
1956#define IXGBE_GSSR_PHY0_SM 0x0002
1957#define IXGBE_GSSR_PHY1_SM 0x0004
1958#define IXGBE_GSSR_MAC_CSR_SM 0x0008
1959#define IXGBE_GSSR_FLASH_SM 0x0010
1960#define IXGBE_GSSR_SW_MNG_SM 0x0400
1961#define IXGBE_GSSR_SHARED_I2C_SM 0x1806
1962#define IXGBE_GSSR_I2C_MASK 0x1800
1963#define IXGBE_GSSR_NVM_PHY_MASK 0xF
1964
1965
1966#define IXGBE_FWSTS_FWRI 0x00000200
1967
1968
1969#define IXGBE_EEC_SK 0x00000001
1970#define IXGBE_EEC_CS 0x00000002
1971#define IXGBE_EEC_DI 0x00000004
1972#define IXGBE_EEC_DO 0x00000008
1973#define IXGBE_EEC_FWE_MASK 0x00000030
1974#define IXGBE_EEC_FWE_DIS 0x00000010
1975#define IXGBE_EEC_FWE_EN 0x00000020
1976#define IXGBE_EEC_FWE_SHIFT 4
1977#define IXGBE_EEC_REQ 0x00000040
1978#define IXGBE_EEC_GNT 0x00000080
1979#define IXGBE_EEC_PRES 0x00000100
1980#define IXGBE_EEC_ARD 0x00000200
1981#define IXGBE_EEC_FLUP 0x00800000
1982#define IXGBE_EEC_SEC1VAL 0x02000000
1983#define IXGBE_EEC_FLUDONE 0x04000000
1984
1985#define IXGBE_EEC_ADDR_SIZE 0x00000400
1986#define IXGBE_EEC_SIZE 0x00007800
1987#define IXGBE_EERD_MAX_ADDR 0x00003FFF
1988
1989#define IXGBE_EEC_SIZE_SHIFT 11
1990#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
1991#define IXGBE_EEPROM_OPCODE_BITS 8
1992
1993
1994#define IXGBE_PBANUM_LENGTH 11
1995
1996
1997#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
1998#define IXGBE_EEPROM_CHECKSUM 0x3F
1999#define IXGBE_EEPROM_SUM 0xBABA
2000#define IXGBE_PCIE_ANALOG_PTR 0x03
2001#define IXGBE_ATLAS0_CONFIG_PTR 0x04
2002#define IXGBE_PHY_PTR 0x04
2003#define IXGBE_ATLAS1_CONFIG_PTR 0x05
2004#define IXGBE_OPTION_ROM_PTR 0x05
2005#define IXGBE_PCIE_GENERAL_PTR 0x06
2006#define IXGBE_PCIE_CONFIG0_PTR 0x07
2007#define IXGBE_PCIE_CONFIG1_PTR 0x08
2008#define IXGBE_CORE0_PTR 0x09
2009#define IXGBE_CORE1_PTR 0x0A
2010#define IXGBE_MAC0_PTR 0x0B
2011#define IXGBE_MAC1_PTR 0x0C
2012#define IXGBE_CSR0_CONFIG_PTR 0x0D
2013#define IXGBE_CSR1_CONFIG_PTR 0x0E
2014#define IXGBE_PCIE_ANALOG_PTR_X550 0x02
2015#define IXGBE_SHADOW_RAM_SIZE_X550 0x4000
2016#define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24
2017#define IXGBE_PCIE_CONFIG_SIZE 0x08
2018#define IXGBE_EEPROM_LAST_WORD 0x41
2019#define IXGBE_FW_PTR 0x0F
2020#define IXGBE_PBANUM0_PTR 0x15
2021#define IXGBE_PBANUM1_PTR 0x16
2022#define IXGBE_FREE_SPACE_PTR 0X3E
2023
2024
2025#define IXGBE_ETS_CFG 0x26
2026#define IXGBE_ETS_LTHRES_DELTA_MASK 0x07C0
2027#define IXGBE_ETS_LTHRES_DELTA_SHIFT 6
2028#define IXGBE_ETS_TYPE_MASK 0x0038
2029#define IXGBE_ETS_TYPE_SHIFT 3
2030#define IXGBE_ETS_TYPE_EMC 0x000
2031#define IXGBE_ETS_TYPE_EMC_SHIFTED 0x000
2032#define IXGBE_ETS_NUM_SENSORS_MASK 0x0007
2033#define IXGBE_ETS_DATA_LOC_MASK 0x3C00
2034#define IXGBE_ETS_DATA_LOC_SHIFT 10
2035#define IXGBE_ETS_DATA_INDEX_MASK 0x0300
2036#define IXGBE_ETS_DATA_INDEX_SHIFT 8
2037#define IXGBE_ETS_DATA_HTHRESH_MASK 0x00FF
2038
2039#define IXGBE_SAN_MAC_ADDR_PTR 0x28
2040#define IXGBE_DEVICE_CAPS 0x2C
2041#define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
2042#define IXGBE_PCIE_MSIX_82599_CAPS 0x72
2043#define IXGBE_MAX_MSIX_VECTORS_82599 0x40
2044#define IXGBE_PCIE_MSIX_82598_CAPS 0x62
2045#define IXGBE_MAX_MSIX_VECTORS_82598 0x13
2046
2047
2048#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF
2049
2050
2051#define IXGBE_ISCSI_BOOT_CAPS 0x0033
2052#define IXGBE_ISCSI_SETUP_PORT_0 0x0030
2053#define IXGBE_ISCSI_SETUP_PORT_1 0x0034
2054
2055
2056#define IXGBE_EEPROM_MAX_RETRY_SPI 5000
2057#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
2058#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03
2059#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02
2060#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08
2061#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06
2062
2063#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
2064#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05
2065#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01
2066#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20
2067#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8
2068#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB
2069
2070
2071#define IXGBE_EEPROM_RW_REG_DATA 16
2072#define IXGBE_EEPROM_RW_REG_DONE 2
2073#define IXGBE_EEPROM_RW_REG_START 1
2074#define IXGBE_EEPROM_RW_ADDR_SHIFT 2
2075#define IXGBE_NVM_POLL_WRITE 1
2076#define IXGBE_NVM_POLL_READ 0
2077
2078#define NVM_INIT_CTRL_3 0x38
2079#define NVM_INIT_CTRL_3_LPLU 0x8
2080#define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40
2081#define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100
2082
2083#define IXGBE_EEPROM_PAGE_SIZE_MAX 128
2084#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512
2085#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256
2086
2087#define IXGBE_EEPROM_CTRL_2 1
2088#define IXGBE_EEPROM_CCD_BIT 2
2089
2090#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
2091#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000
2092#endif
2093
2094#ifndef IXGBE_EERD_EEWR_ATTEMPTS
2095
2096
2097#define IXGBE_EERD_EEWR_ATTEMPTS 100000
2098#endif
2099
2100#ifndef IXGBE_FLUDONE_ATTEMPTS
2101
2102#define IXGBE_FLUDONE_ATTEMPTS 20000
2103#endif
2104
2105#define IXGBE_PCIE_CTRL2 0x5
2106#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8
2107#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2
2108#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1
2109
2110#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0
2111#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3
2112#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1
2113#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2
2114#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
2115#define IXGBE_FW_LESM_STATE_1 0x1
2116#define IXGBE_FW_LESM_STATE_ENABLED 0x8000
2117#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
2118#define IXGBE_FW_PATCH_VERSION_4 0x7
2119#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33
2120#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20
2121#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17
2122#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0
2123#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1
2124#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27
2125#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0
2126#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1
2127#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4
2128#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7
2129#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8
2130#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0
2131#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1
2132
2133#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4
2134#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8
2135#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC
2136
2137
2138#define IXGBE_PCI_DEVICE_STATUS 0xAA
2139#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020
2140#define IXGBE_PCI_LINK_STATUS 0xB2
2141#define IXGBE_PCI_DEVICE_CONTROL2 0xC8
2142#define IXGBE_PCI_LINK_WIDTH 0x3F0
2143#define IXGBE_PCI_LINK_WIDTH_1 0x10
2144#define IXGBE_PCI_LINK_WIDTH_2 0x20
2145#define IXGBE_PCI_LINK_WIDTH_4 0x40
2146#define IXGBE_PCI_LINK_WIDTH_8 0x80
2147#define IXGBE_PCI_LINK_SPEED 0xF
2148#define IXGBE_PCI_LINK_SPEED_2500 0x1
2149#define IXGBE_PCI_LINK_SPEED_5000 0x2
2150#define IXGBE_PCI_LINK_SPEED_8000 0x3
2151#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E
2152#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
2153#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005
2154
2155#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf
2156#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0
2157#define IXGBE_PCIDEVCTRL2_50_100us 0x1
2158#define IXGBE_PCIDEVCTRL2_1_2ms 0x2
2159#define IXGBE_PCIDEVCTRL2_16_32ms 0x5
2160#define IXGBE_PCIDEVCTRL2_65_130ms 0x6
2161#define IXGBE_PCIDEVCTRL2_260_520ms 0x9
2162#define IXGBE_PCIDEVCTRL2_1_2s 0xa
2163#define IXGBE_PCIDEVCTRL2_4_8s 0xd
2164#define IXGBE_PCIDEVCTRL2_17_34s 0xe
2165
2166
2167#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
2168
2169
2170#define IXGBE_RAH_VIND_MASK 0x003C0000
2171#define IXGBE_RAH_VIND_SHIFT 18
2172#define IXGBE_RAH_AV 0x80000000
2173#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
2174
2175
2176#define IXGBE_RFCTL_ISCSI_DIS 0x00000001
2177#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
2178#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
2179#define IXGBE_RFCTL_RSC_DIS 0x00000020
2180#define IXGBE_RFCTL_NFSW_DIS 0x00000040
2181#define IXGBE_RFCTL_NFSR_DIS 0x00000080
2182#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
2183#define IXGBE_RFCTL_NFS_VER_SHIFT 8
2184#define IXGBE_RFCTL_NFS_VER_2 0
2185#define IXGBE_RFCTL_NFS_VER_3 1
2186#define IXGBE_RFCTL_NFS_VER_4 2
2187#define IXGBE_RFCTL_IPV6_DIS 0x00000400
2188#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
2189#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
2190#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
2191#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
2192
2193
2194#define IXGBE_TXDCTL_ENABLE 0x02000000
2195#define IXGBE_TXDCTL_SWFLSH 0x04000000
2196#define IXGBE_TXDCTL_WTHRESH_SHIFT 16
2197
2198#define IXGBE_TX_PAD_ENABLE 0x00000400
2199#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004
2200
2201#define IXGBE_MAX_FRAME_SZ 0x40040000
2202
2203#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1
2204#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2
2205
2206
2207#define IXGBE_RXCTRL_RXEN 0x00000001
2208#define IXGBE_RXCTRL_DMBYPS 0x00000002
2209#define IXGBE_RXDCTL_ENABLE 0x02000000
2210#define IXGBE_RXDCTL_SWFLSH 0x04000000
2211#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF
2212#define IXGBE_RXDCTL_RLPML_EN 0x00008000
2213#define IXGBE_RXDCTL_VME 0x40000000
2214
2215#define IXGBE_TSAUXC_EN_CLK 0x00000004
2216#define IXGBE_TSAUXC_SYNCLK 0x00000008
2217#define IXGBE_TSAUXC_SDP0_INT 0x00000040
2218#define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000
2219
2220#define IXGBE_TSYNCTXCTL_VALID 0x00000001
2221#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010
2222
2223#define IXGBE_TSYNCRXCTL_VALID 0x00000001
2224#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E
2225#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00
2226#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02
2227#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04
2228#define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08
2229#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A
2230#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010
2231#define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000
2232
2233#define IXGBE_TSIM_TXTS 0x00000002
2234
2235#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF
2236#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00
2237#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01
2238#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02
2239#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03
2240#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04
2241
2242#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00
2243#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000
2244#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100
2245#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200
2246#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300
2247#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800
2248#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900
2249#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00
2250#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00
2251#define IXGBE_RXMTRL_V2_SIGNALING_MSG 0x0C00
2252#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00
2253
2254#define IXGBE_FCTRL_SBP 0x00000002
2255#define IXGBE_FCTRL_MPE 0x00000100
2256#define IXGBE_FCTRL_UPE 0x00000200
2257#define IXGBE_FCTRL_BAM 0x00000400
2258#define IXGBE_FCTRL_PMCF 0x00001000
2259#define IXGBE_FCTRL_DPF 0x00002000
2260
2261#define IXGBE_FCTRL_RPFCE 0x00004000
2262#define IXGBE_FCTRL_RFCE 0x00008000
2263#define IXGBE_MFLCN_PMCF 0x00000001
2264#define IXGBE_MFLCN_DPF 0x00000002
2265#define IXGBE_MFLCN_RPFCE 0x00000004
2266#define IXGBE_MFLCN_RFCE 0x00000008
2267#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4
2268
2269#define IXGBE_MFLCN_RPFCE_SHIFT 4
2270
2271
2272#define IXGBE_MRQC_RSSEN 0x00000001
2273#define IXGBE_MRQC_MRQE_MASK 0xF
2274#define IXGBE_MRQC_RT8TCEN 0x00000002
2275#define IXGBE_MRQC_RT4TCEN 0x00000003
2276#define IXGBE_MRQC_RTRSS8TCEN 0x00000004
2277#define IXGBE_MRQC_RTRSS4TCEN 0x00000005
2278#define IXGBE_MRQC_VMDQEN 0x00000008
2279#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A
2280#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B
2281#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C
2282#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D
2283#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
2284#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
2285#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
2286#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
2287#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
2288#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
2289#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
2290#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
2291#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
2292#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
2293#define IXGBE_MRQC_MULTIPLE_RSS 0x00002000
2294#define IXGBE_MRQC_L3L4TXSWEN 0x00008000
2295
2296#define IXGBE_FWSM_TS_ENABLED 0x1
2297
2298
2299#define IXGBE_QDE_ENABLE 0x00000001
2300#define IXGBE_QDE_HIDE_VLAN 0x00000002
2301#define IXGBE_QDE_IDX_MASK 0x00007F00
2302#define IXGBE_QDE_IDX_SHIFT 8
2303#define IXGBE_QDE_WRITE 0x00010000
2304
2305#define IXGBE_TXD_POPTS_IXSM 0x01
2306#define IXGBE_TXD_POPTS_TXSM 0x02
2307#define IXGBE_TXD_CMD_EOP 0x01000000
2308#define IXGBE_TXD_CMD_IFCS 0x02000000
2309#define IXGBE_TXD_CMD_IC 0x04000000
2310#define IXGBE_TXD_CMD_RS 0x08000000
2311#define IXGBE_TXD_CMD_DEXT 0x20000000
2312#define IXGBE_TXD_CMD_VLE 0x40000000
2313#define IXGBE_TXD_STAT_DD 0x00000001
2314
2315#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000
2316#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000
2317#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000
2318#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000
2319#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000
2320
2321#define IXGBE_MTQC_RT_ENA 0x1
2322#define IXGBE_MTQC_VT_ENA 0x2
2323#define IXGBE_MTQC_64Q_1PB 0x0
2324#define IXGBE_MTQC_32VF 0x8
2325#define IXGBE_MTQC_64VF 0x4
2326#define IXGBE_MTQC_8TC_8TQ 0xC
2327#define IXGBE_MTQC_4TC_4TQ 0x8
2328
2329
2330#define IXGBE_RXD_STAT_DD 0x01
2331#define IXGBE_RXD_STAT_EOP 0x02
2332#define IXGBE_RXD_STAT_FLM 0x04
2333#define IXGBE_RXD_STAT_VP 0x08
2334#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0
2335#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004
2336#define IXGBE_RXD_STAT_UDPCS 0x10
2337#define IXGBE_RXD_STAT_L4CS 0x20
2338#define IXGBE_RXD_STAT_IPCS 0x40
2339#define IXGBE_RXD_STAT_PIF 0x80
2340#define IXGBE_RXD_STAT_CRCV 0x100
2341#define IXGBE_RXD_STAT_OUTERIPCS 0x100
2342#define IXGBE_RXD_STAT_VEXT 0x200
2343#define IXGBE_RXD_STAT_UDPV 0x400
2344#define IXGBE_RXD_STAT_DYNINT 0x800
2345#define IXGBE_RXD_STAT_LLINT 0x800
2346#define IXGBE_RXD_STAT_TSIP 0x08000
2347#define IXGBE_RXD_STAT_TS 0x10000
2348#define IXGBE_RXD_STAT_SECP 0x20000
2349#define IXGBE_RXD_STAT_LB 0x40000
2350#define IXGBE_RXD_STAT_ACK 0x8000
2351#define IXGBE_RXD_ERR_CE 0x01
2352#define IXGBE_RXD_ERR_LE 0x02
2353#define IXGBE_RXD_ERR_PE 0x08
2354#define IXGBE_RXD_ERR_OSE 0x10
2355#define IXGBE_RXD_ERR_USE 0x20
2356#define IXGBE_RXD_ERR_TCPE 0x40
2357#define IXGBE_RXD_ERR_IPE 0x80
2358#define IXGBE_RXDADV_ERR_MASK 0xfff00000
2359#define IXGBE_RXDADV_ERR_SHIFT 20
2360#define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000
2361#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000
2362#define IXGBE_RXDADV_ERR_FCERR 0x00700000
2363#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000
2364#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000
2365#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000
2366#define IXGBE_RXDADV_ERR_HBO 0x00800000
2367#define IXGBE_RXDADV_ERR_CE 0x01000000
2368#define IXGBE_RXDADV_ERR_LE 0x02000000
2369#define IXGBE_RXDADV_ERR_PE 0x08000000
2370#define IXGBE_RXDADV_ERR_OSE 0x10000000
2371#define IXGBE_RXDADV_ERR_USE 0x20000000
2372#define IXGBE_RXDADV_ERR_TCPE 0x40000000
2373#define IXGBE_RXDADV_ERR_IPE 0x80000000
2374#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF
2375#define IXGBE_RXD_PRI_MASK 0xE000
2376#define IXGBE_RXD_PRI_SHIFT 13
2377#define IXGBE_RXD_CFI_MASK 0x1000
2378#define IXGBE_RXD_CFI_SHIFT 12
2379
2380#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD
2381#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP
2382#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM
2383#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP
2384#define IXGBE_RXDADV_STAT_MASK 0x000fffff
2385#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040
2386#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030
2387#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000
2388#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010
2389#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020
2390#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030
2391#define IXGBE_RXDADV_STAT_TS 0x00010000
2392
2393
2394#define IXGBE_PSRTYPE_TCPHDR 0x00000010
2395#define IXGBE_PSRTYPE_UDPHDR 0x00000020
2396#define IXGBE_PSRTYPE_IPV4HDR 0x00000100
2397#define IXGBE_PSRTYPE_IPV6HDR 0x00000200
2398#define IXGBE_PSRTYPE_L2HDR 0x00001000
2399
2400
2401#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10
2402#define IXGBE_SRRCTL_RDMTS_SHIFT 22
2403#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000
2404#define IXGBE_SRRCTL_DROP_EN 0x10000000
2405#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
2406#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
2407#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
2408#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
2409#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
2410#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
2411#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
2412#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
2413
2414#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
2415#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
2416
2417#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
2418#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
2419#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0
2420#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
2421#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000
2422#define IXGBE_RXDADV_RSCCNT_SHIFT 17
2423#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
2424#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
2425#define IXGBE_RXDADV_SPH 0x8000
2426
2427
2428#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
2429#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
2430#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
2431#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
2432#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
2433#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
2434#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
2435#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
2436#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
2437#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
2438
2439
2440#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
2441#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010
2442#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020
2443#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040
2444#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080
2445#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100
2446#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200
2447#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400
2448#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800
2449#define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800
2450#define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000
2451#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000
2452#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000
2453#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000
2454#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000
2455#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070
2456#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4
2457
2458
2459#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000
2460#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000
2461#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000
2462#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000
2463#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000
2464
2465
2466#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
2467 IXGBE_RXD_ERR_CE | \
2468 IXGBE_RXD_ERR_LE | \
2469 IXGBE_RXD_ERR_PE | \
2470 IXGBE_RXD_ERR_OSE | \
2471 IXGBE_RXD_ERR_USE)
2472
2473#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
2474 IXGBE_RXDADV_ERR_CE | \
2475 IXGBE_RXDADV_ERR_LE | \
2476 IXGBE_RXDADV_ERR_PE | \
2477 IXGBE_RXDADV_ERR_OSE | \
2478 IXGBE_RXDADV_ERR_USE)
2479
2480
2481#define IXGBE_MCSTCTRL_MFE 0x4
2482
2483
2484#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
2485#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
2486#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
2487
2488
2489#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF
2490#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000
2491#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D
2492#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
2493
2494
2495#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4)
2496#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4))
2497#define IXGBE_VFLRE(_i) ((((_i) & 1) ? 0x001C0 : 0x00600))
2498#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4))
2499
2500#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P)))
2501#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P)))
2502#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P)))
2503#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P)))
2504
2505#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \
2506 (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index)))
2507#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
2508 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
2509
2510#define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \
2511 (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
2512#define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \
2513 (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
2514
2515enum ixgbe_fdir_pballoc_type {
2516 IXGBE_FDIR_PBALLOC_NONE = 0,
2517 IXGBE_FDIR_PBALLOC_64K = 1,
2518 IXGBE_FDIR_PBALLOC_128K = 2,
2519 IXGBE_FDIR_PBALLOC_256K = 3,
2520};
2521#define IXGBE_FDIR_PBALLOC_SIZE_SHIFT 16
2522
2523
2524#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001
2525#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002
2526#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003
2527#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008
2528#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010
2529#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020
2530#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080
2531#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8
2532#define IXGBE_FDIRCTRL_FLEX_SHIFT 16
2533#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000
2534#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24
2535#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000
2536#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28
2537
2538#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16
2539#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16
2540#define IXGBE_FDIRIP6M_DIPM_SHIFT 16
2541#define IXGBE_FDIRM_VLANID 0x00000001
2542#define IXGBE_FDIRM_VLANP 0x00000002
2543#define IXGBE_FDIRM_POOL 0x00000004
2544#define IXGBE_FDIRM_L4P 0x00000008
2545#define IXGBE_FDIRM_FLEX 0x00000010
2546#define IXGBE_FDIRM_DIPv6 0x00000020
2547
2548#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF
2549#define IXGBE_FDIRFREE_FREE_SHIFT 0
2550#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000
2551#define IXGBE_FDIRFREE_COLL_SHIFT 16
2552#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F
2553#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0
2554#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000
2555#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16
2556#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF
2557#define IXGBE_FDIRUSTAT_ADD_SHIFT 0
2558#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000
2559#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16
2560#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF
2561#define IXGBE_FDIRFSTAT_FADD_SHIFT 0
2562#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00
2563#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8
2564#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16
2565#define IXGBE_FDIRVLAN_FLEX_SHIFT 16
2566#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15
2567#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16
2568
2569#define IXGBE_FDIRCMD_CMD_MASK 0x00000003
2570#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001
2571#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002
2572#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003
2573#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004
2574#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008
2575#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010
2576#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020
2577#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040
2578#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060
2579#define IXGBE_FDIRCMD_IPV6 0x00000080
2580#define IXGBE_FDIRCMD_CLEARHT 0x00000100
2581#define IXGBE_FDIRCMD_DROP 0x00000200
2582#define IXGBE_FDIRCMD_INT 0x00000400
2583#define IXGBE_FDIRCMD_LAST 0x00000800
2584#define IXGBE_FDIRCMD_COLLISION 0x00001000
2585#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000
2586#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5
2587#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16
2588#define IXGBE_FDIRCMD_RX_TUNNEL_FILTER_SHIFT 23
2589#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24
2590#define IXGBE_FDIR_INIT_DONE_POLL 10
2591#define IXGBE_FDIRCMD_CMD_POLL 10
2592#define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000
2593
2594#define IXGBE_FDIR_DROP_QUEUE 127
2595
2596
2597#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792
2598#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448
2599#define IXGBE_HI_COMMAND_TIMEOUT 500
2600#define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000
2601#define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000
2602#define IXGBE_HI_FLASH_APPLY_TIMEOUT 0
2603
2604
2605#define FW_CEM_HDR_LEN 0x4
2606#define FW_CEM_CMD_DRIVER_INFO 0xDD
2607#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5
2608#define FW_CEM_CMD_RESERVED 0x0
2609#define FW_CEM_UNUSED_VER 0x0
2610#define FW_CEM_MAX_RETRIES 3
2611#define FW_CEM_RESP_STATUS_SUCCESS 0x1
2612#define FW_READ_SHADOW_RAM_CMD 0x31
2613#define FW_READ_SHADOW_RAM_LEN 0x6
2614#define FW_WRITE_SHADOW_RAM_CMD 0x33
2615#define FW_WRITE_SHADOW_RAM_LEN 0xA
2616#define FW_SHADOW_RAM_DUMP_CMD 0x36
2617#define FW_SHADOW_RAM_DUMP_LEN 0
2618#define FW_DEFAULT_CHECKSUM 0xFF
2619#define FW_NVM_DATA_OFFSET 3
2620#define FW_MAX_READ_BUFFER_SIZE 1024
2621#define FW_DISABLE_RXEN_CMD 0xDE
2622#define FW_DISABLE_RXEN_LEN 0x1
2623
2624
2625struct ixgbe_hic_hdr {
2626 u8 cmd;
2627 u8 buf_len;
2628 union {
2629 u8 cmd_resv;
2630 u8 ret_status;
2631 } cmd_or_resp;
2632 u8 checksum;
2633};
2634
2635struct ixgbe_hic_hdr2_req {
2636 u8 cmd;
2637 u8 buf_lenh;
2638 u8 buf_lenl;
2639 u8 checksum;
2640};
2641
2642struct ixgbe_hic_hdr2_rsp {
2643 u8 cmd;
2644 u8 buf_lenl;
2645 u8 buf_lenh_status;
2646 u8 checksum;
2647};
2648
2649union ixgbe_hic_hdr2 {
2650 struct ixgbe_hic_hdr2_req req;
2651 struct ixgbe_hic_hdr2_rsp rsp;
2652};
2653
2654struct ixgbe_hic_drv_info {
2655 struct ixgbe_hic_hdr hdr;
2656 u8 port_num;
2657 u8 ver_sub;
2658 u8 ver_build;
2659 u8 ver_min;
2660 u8 ver_maj;
2661 u8 pad;
2662 u16 pad2;
2663};
2664
2665
2666struct ixgbe_hic_read_shadow_ram {
2667 union ixgbe_hic_hdr2 hdr;
2668 u32 address;
2669 u16 length;
2670 u16 pad2;
2671 u16 data;
2672 u16 pad3;
2673};
2674
2675struct ixgbe_hic_write_shadow_ram {
2676 union ixgbe_hic_hdr2 hdr;
2677 __be32 address;
2678 __be16 length;
2679 u16 pad2;
2680 u16 data;
2681 u16 pad3;
2682};
2683
2684struct ixgbe_hic_disable_rxen {
2685 struct ixgbe_hic_hdr hdr;
2686 u8 port_number;
2687 u8 pad2;
2688 u16 pad3;
2689};
2690
2691
2692union ixgbe_adv_tx_desc {
2693 struct {
2694 __le64 buffer_addr;
2695 __le32 cmd_type_len;
2696 __le32 olinfo_status;
2697 } read;
2698 struct {
2699 __le64 rsvd;
2700 __le32 nxtseq_seed;
2701 __le32 status;
2702 } wb;
2703};
2704
2705
2706union ixgbe_adv_rx_desc {
2707 struct {
2708 __le64 pkt_addr;
2709 __le64 hdr_addr;
2710 } read;
2711 struct {
2712 struct {
2713 union {
2714 __le32 data;
2715 struct {
2716 __le16 pkt_info;
2717 __le16 hdr_info;
2718 } hs_rss;
2719 } lo_dword;
2720 union {
2721 __le32 rss;
2722 struct {
2723 __le16 ip_id;
2724 __le16 csum;
2725 } csum_ip;
2726 } hi_dword;
2727 } lower;
2728 struct {
2729 __le32 status_error;
2730 __le16 length;
2731 __le16 vlan;
2732 } upper;
2733 } wb;
2734};
2735
2736
2737struct ixgbe_adv_tx_context_desc {
2738 __le32 vlan_macip_lens;
2739 __le32 seqnum_seed;
2740 __le32 type_tucmd_mlhl;
2741 __le32 mss_l4len_idx;
2742};
2743
2744
2745#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF
2746#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000
2747#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000
2748#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF
2749#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF
2750#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000
2751#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000
2752#define IXGBE_ADVTXD_DTYP_DATA 0x00300000
2753#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP
2754#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS
2755#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS
2756#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000
2757#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT
2758#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE
2759#define IXGBE_ADVTXD_DCMD_TSE 0x80000000
2760#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD
2761#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002
2762#define IXGBE_ADVTXD_STAT_RSV 0x0000000C
2763#define IXGBE_ADVTXD_IDX_SHIFT 4
2764#define IXGBE_ADVTXD_CC 0x00000080
2765#define IXGBE_ADVTXD_POPTS_SHIFT 8
2766#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
2767 IXGBE_ADVTXD_POPTS_SHIFT)
2768#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
2769 IXGBE_ADVTXD_POPTS_SHIFT)
2770#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000
2771#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800
2772#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000
2773#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800
2774#define IXGBE_ADVTXD_POPTS_RSV 0x00002000
2775#define IXGBE_ADVTXD_PAYLEN_SHIFT 14
2776#define IXGBE_ADVTXD_MACLEN_SHIFT 9
2777#define IXGBE_ADVTXD_VLAN_SHIFT 16
2778#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400
2779#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000
2780#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000
2781#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800
2782#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000
2783#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800
2784#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000
2785#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400
2786#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000
2787#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000
2788#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000
2789#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10)
2790#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10)
2791#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10)
2792#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10)
2793#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10)
2794#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10)
2795#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10)
2796#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10)
2797#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10)
2798#define IXGBE_ADVTXD_L4LEN_SHIFT 8
2799#define IXGBE_ADVTXD_MSS_SHIFT 16
2800
2801
2802typedef u32 ixgbe_autoneg_advertised;
2803
2804typedef u32 ixgbe_link_speed;
2805#define IXGBE_LINK_SPEED_UNKNOWN 0
2806#define IXGBE_LINK_SPEED_100_FULL 0x0008
2807#define IXGBE_LINK_SPEED_1GB_FULL 0x0020
2808#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400
2809#define IXGBE_LINK_SPEED_5GB_FULL 0x0800
2810#define IXGBE_LINK_SPEED_10GB_FULL 0x0080
2811#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
2812 IXGBE_LINK_SPEED_10GB_FULL)
2813#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
2814 IXGBE_LINK_SPEED_1GB_FULL | \
2815 IXGBE_LINK_SPEED_10GB_FULL)
2816
2817
2818
2819
2820
2821
2822#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
2823#define IXGBE_B2BT(BT) (BT * 8)
2824
2825
2826#define IXGBE_PFC_D 672
2827
2828
2829#define IXGBE_CABLE_DC 5556
2830#define IXGBE_CABLE_DO 5000
2831
2832
2833#define IXGBE_PHY_DC 25600
2834#define IXGBE_MAC_DC 8192
2835#define IXGBE_XAUI_DC (2 * 2048)
2836
2837#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
2838
2839
2840#define IXGBE_PHY_D 12800
2841#define IXGBE_MAC_D 4096
2842#define IXGBE_XAUI_D (2 * 1024)
2843
2844#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
2845
2846
2847#define IXGBE_HD 6144
2848
2849
2850#define IXGBE_PCI_DELAY 10000
2851
2852
2853#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
2854 ((36 * \
2855 (IXGBE_B2BT(_max_frame_link) + \
2856 IXGBE_PFC_D + \
2857 (2 * IXGBE_CABLE_DC) + \
2858 (2 * IXGBE_ID_X540) + \
2859 IXGBE_HD) / 25 + 1) + \
2860 2 * IXGBE_B2BT(_max_frame_tc))
2861
2862
2863#define IXGBE_DV(_max_frame_link, _max_frame_tc) \
2864 ((36 * \
2865 (IXGBE_B2BT(_max_frame_link) + \
2866 IXGBE_PFC_D + \
2867 (2 * IXGBE_CABLE_DC) + \
2868 (2 * IXGBE_ID) + \
2869 IXGBE_HD) / 25 + 1) + \
2870 2 * IXGBE_B2BT(_max_frame_tc))
2871
2872
2873#define IXGBE_LOW_DV_X540(_max_frame_tc) \
2874 (2 * IXGBE_B2BT(_max_frame_tc) + \
2875 (36 * IXGBE_PCI_DELAY / 25) + 1)
2876#define IXGBE_LOW_DV(_max_frame_tc) \
2877 (2 * IXGBE_LOW_DV_X540(_max_frame_tc))
2878
2879
2880#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2
2881#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
2882
2883
2884#define IXGBE_ATR_HASH_MASK 0x7fff
2885#define IXGBE_ATR_L4TYPE_MASK 0x3
2886#define IXGBE_ATR_L4TYPE_UDP 0x1
2887#define IXGBE_ATR_L4TYPE_TCP 0x2
2888#define IXGBE_ATR_L4TYPE_SCTP 0x3
2889#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
2890#define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10
2891enum ixgbe_atr_flow_type {
2892 IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0,
2893 IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1,
2894 IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2,
2895 IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
2896 IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4,
2897 IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5,
2898 IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6,
2899 IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
2900};
2901
2902
2903union ixgbe_atr_input {
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917 struct {
2918 u8 vm_pool;
2919 u8 flow_type;
2920 __be16 vlan_id;
2921 __be32 dst_ip[4];
2922 __be32 src_ip[4];
2923 __be16 src_port;
2924 __be16 dst_port;
2925 __be16 flex_bytes;
2926 __be16 bkt_hash;
2927 } formatted;
2928 __be32 dword_stream[11];
2929};
2930
2931
2932union ixgbe_atr_hash_dword {
2933 struct {
2934 u8 vm_pool;
2935 u8 flow_type;
2936 __be16 vlan_id;
2937 } formatted;
2938 __be32 ip;
2939 struct {
2940 __be16 src;
2941 __be16 dst;
2942 } port;
2943 __be16 flex_bytes;
2944 __be32 dword;
2945};
2946
2947#define IXGBE_MVALS_INIT(m) \
2948 IXGBE_CAT(EEC, m), \
2949 IXGBE_CAT(FLA, m), \
2950 IXGBE_CAT(GRC, m), \
2951 IXGBE_CAT(SRAMREL, m), \
2952 IXGBE_CAT(FACTPS, m), \
2953 IXGBE_CAT(SWSM, m), \
2954 IXGBE_CAT(SWFW_SYNC, m), \
2955 IXGBE_CAT(FWSM, m), \
2956 IXGBE_CAT(SDP0_GPIEN, m), \
2957 IXGBE_CAT(SDP1_GPIEN, m), \
2958 IXGBE_CAT(SDP2_GPIEN, m), \
2959 IXGBE_CAT(EICR_GPI_SDP0, m), \
2960 IXGBE_CAT(EICR_GPI_SDP1, m), \
2961 IXGBE_CAT(EICR_GPI_SDP2, m), \
2962 IXGBE_CAT(CIAA, m), \
2963 IXGBE_CAT(CIAD, m), \
2964 IXGBE_CAT(I2C_CLK_IN, m), \
2965 IXGBE_CAT(I2C_CLK_OUT, m), \
2966 IXGBE_CAT(I2C_DATA_IN, m), \
2967 IXGBE_CAT(I2C_DATA_OUT, m), \
2968 IXGBE_CAT(I2C_DATA_OE_N_EN, m), \
2969 IXGBE_CAT(I2C_BB_EN, m), \
2970 IXGBE_CAT(I2C_CLK_OE_N_EN, m), \
2971 IXGBE_CAT(I2CCTL, m)
2972
2973enum ixgbe_mvals {
2974 IXGBE_MVALS_INIT(IDX),
2975 IXGBE_MVALS_IDX_LIMIT
2976};
2977
2978enum ixgbe_eeprom_type {
2979 ixgbe_eeprom_uninitialized = 0,
2980 ixgbe_eeprom_spi,
2981 ixgbe_flash,
2982 ixgbe_eeprom_none
2983};
2984
2985enum ixgbe_mac_type {
2986 ixgbe_mac_unknown = 0,
2987 ixgbe_mac_82598EB,
2988 ixgbe_mac_82599EB,
2989 ixgbe_mac_X540,
2990 ixgbe_mac_X550,
2991 ixgbe_mac_X550EM_x,
2992 ixgbe_num_macs
2993};
2994
2995enum ixgbe_phy_type {
2996 ixgbe_phy_unknown = 0,
2997 ixgbe_phy_none,
2998 ixgbe_phy_tn,
2999 ixgbe_phy_aq,
3000 ixgbe_phy_x550em_kr,
3001 ixgbe_phy_x550em_kx4,
3002 ixgbe_phy_x550em_ext_t,
3003 ixgbe_phy_cu_unknown,
3004 ixgbe_phy_qt,
3005 ixgbe_phy_xaui,
3006 ixgbe_phy_nl,
3007 ixgbe_phy_sfp_passive_tyco,
3008 ixgbe_phy_sfp_passive_unknown,
3009 ixgbe_phy_sfp_active_unknown,
3010 ixgbe_phy_sfp_avago,
3011 ixgbe_phy_sfp_ftl,
3012 ixgbe_phy_sfp_ftl_active,
3013 ixgbe_phy_sfp_unknown,
3014 ixgbe_phy_sfp_intel,
3015 ixgbe_phy_qsfp_passive_unknown,
3016 ixgbe_phy_qsfp_active_unknown,
3017 ixgbe_phy_qsfp_intel,
3018 ixgbe_phy_qsfp_unknown,
3019 ixgbe_phy_sfp_unsupported,
3020 ixgbe_phy_generic
3021};
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036enum ixgbe_sfp_type {
3037 ixgbe_sfp_type_da_cu = 0,
3038 ixgbe_sfp_type_sr = 1,
3039 ixgbe_sfp_type_lr = 2,
3040 ixgbe_sfp_type_da_cu_core0 = 3,
3041 ixgbe_sfp_type_da_cu_core1 = 4,
3042 ixgbe_sfp_type_srlr_core0 = 5,
3043 ixgbe_sfp_type_srlr_core1 = 6,
3044 ixgbe_sfp_type_da_act_lmt_core0 = 7,
3045 ixgbe_sfp_type_da_act_lmt_core1 = 8,
3046 ixgbe_sfp_type_1g_cu_core0 = 9,
3047 ixgbe_sfp_type_1g_cu_core1 = 10,
3048 ixgbe_sfp_type_1g_sx_core0 = 11,
3049 ixgbe_sfp_type_1g_sx_core1 = 12,
3050 ixgbe_sfp_type_1g_lx_core0 = 13,
3051 ixgbe_sfp_type_1g_lx_core1 = 14,
3052 ixgbe_sfp_type_not_present = 0xFFFE,
3053 ixgbe_sfp_type_unknown = 0xFFFF
3054};
3055
3056enum ixgbe_media_type {
3057 ixgbe_media_type_unknown = 0,
3058 ixgbe_media_type_fiber,
3059 ixgbe_media_type_fiber_qsfp,
3060 ixgbe_media_type_fiber_lco,
3061 ixgbe_media_type_copper,
3062 ixgbe_media_type_backplane,
3063 ixgbe_media_type_cx4,
3064 ixgbe_media_type_virtual
3065};
3066
3067
3068enum ixgbe_fc_mode {
3069 ixgbe_fc_none = 0,
3070 ixgbe_fc_rx_pause,
3071 ixgbe_fc_tx_pause,
3072 ixgbe_fc_full,
3073 ixgbe_fc_default
3074};
3075
3076
3077#define IXGBE_SMARTSPEED_MAX_RETRIES 3
3078enum ixgbe_smart_speed {
3079 ixgbe_smart_speed_auto = 0,
3080 ixgbe_smart_speed_on,
3081 ixgbe_smart_speed_off
3082};
3083
3084
3085enum ixgbe_bus_type {
3086 ixgbe_bus_type_unknown = 0,
3087 ixgbe_bus_type_pci_express,
3088 ixgbe_bus_type_internal,
3089 ixgbe_bus_type_reserved
3090};
3091
3092
3093enum ixgbe_bus_speed {
3094 ixgbe_bus_speed_unknown = 0,
3095 ixgbe_bus_speed_33 = 33,
3096 ixgbe_bus_speed_66 = 66,
3097 ixgbe_bus_speed_100 = 100,
3098 ixgbe_bus_speed_120 = 120,
3099 ixgbe_bus_speed_133 = 133,
3100 ixgbe_bus_speed_2500 = 2500,
3101 ixgbe_bus_speed_5000 = 5000,
3102 ixgbe_bus_speed_8000 = 8000,
3103 ixgbe_bus_speed_reserved
3104};
3105
3106
3107enum ixgbe_bus_width {
3108 ixgbe_bus_width_unknown = 0,
3109 ixgbe_bus_width_pcie_x1 = 1,
3110 ixgbe_bus_width_pcie_x2 = 2,
3111 ixgbe_bus_width_pcie_x4 = 4,
3112 ixgbe_bus_width_pcie_x8 = 8,
3113 ixgbe_bus_width_32 = 32,
3114 ixgbe_bus_width_64 = 64,
3115 ixgbe_bus_width_reserved
3116};
3117
3118struct ixgbe_addr_filter_info {
3119 u32 num_mc_addrs;
3120 u32 rar_used_count;
3121 u32 mta_in_use;
3122 u32 overflow_promisc;
3123 bool uc_set_promisc;
3124 bool user_set_promisc;
3125};
3126
3127
3128struct ixgbe_bus_info {
3129 enum ixgbe_bus_speed speed;
3130 enum ixgbe_bus_width width;
3131 enum ixgbe_bus_type type;
3132
3133 u16 func;
3134 u16 lan_id;
3135};
3136
3137
3138struct ixgbe_fc_info {
3139 u32 high_water[MAX_TRAFFIC_CLASS];
3140 u32 low_water[MAX_TRAFFIC_CLASS];
3141 u16 pause_time;
3142 bool send_xon;
3143 bool strict_ieee;
3144 bool disable_fc_autoneg;
3145 bool fc_was_autonegged;
3146 enum ixgbe_fc_mode current_mode;
3147 enum ixgbe_fc_mode requested_mode;
3148};
3149
3150
3151struct ixgbe_hw_stats {
3152 u64 crcerrs;
3153 u64 illerrc;
3154 u64 errbc;
3155 u64 mspdc;
3156 u64 mpctotal;
3157 u64 mpc[8];
3158 u64 mlfc;
3159 u64 mrfc;
3160 u64 rlec;
3161 u64 lxontxc;
3162 u64 lxonrxc;
3163 u64 lxofftxc;
3164 u64 lxoffrxc;
3165 u64 pxontxc[8];
3166 u64 pxonrxc[8];
3167 u64 pxofftxc[8];
3168 u64 pxoffrxc[8];
3169 u64 prc64;
3170 u64 prc127;
3171 u64 prc255;
3172 u64 prc511;
3173 u64 prc1023;
3174 u64 prc1522;
3175 u64 gprc;
3176 u64 bprc;
3177 u64 mprc;
3178 u64 gptc;
3179 u64 gorc;
3180 u64 gotc;
3181 u64 rnbc[8];
3182 u64 ruc;
3183 u64 rfc;
3184 u64 roc;
3185 u64 rjc;
3186 u64 mngprc;
3187 u64 mngpdc;
3188 u64 mngptc;
3189 u64 tor;
3190 u64 tpr;
3191 u64 tpt;
3192 u64 ptc64;
3193 u64 ptc127;
3194 u64 ptc255;
3195 u64 ptc511;
3196 u64 ptc1023;
3197 u64 ptc1522;
3198 u64 mptc;
3199 u64 bptc;
3200 u64 xec;
3201 u64 rqsmr[16];
3202 u64 tqsmr[8];
3203 u64 qprc[16];
3204 u64 qptc[16];
3205 u64 qbrc[16];
3206 u64 qbtc[16];
3207 u64 qprdc[16];
3208 u64 pxon2offc[8];
3209 u64 fdirustat_add;
3210 u64 fdirustat_remove;
3211 u64 fdirfstat_fadd;
3212 u64 fdirfstat_fremove;
3213 u64 fdirmatch;
3214 u64 fdirmiss;
3215 u64 fccrc;
3216 u64 fcoerpdc;
3217 u64 fcoeprc;
3218 u64 fcoeptc;
3219 u64 fcoedwrc;
3220 u64 fcoedwtc;
3221 u64 fcoe_noddp;
3222 u64 fcoe_noddp_ext_buff;
3223 u64 b2ospc;
3224 u64 b2ogprc;
3225 u64 o2bgptc;
3226 u64 o2bspc;
3227};
3228
3229
3230struct ixgbe_hw;
3231
3232
3233typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
3234 u32 *vmdq);
3235
3236
3237struct ixgbe_eeprom_operations {
3238 s32 (*init_params)(struct ixgbe_hw *);
3239 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
3240 s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3241 s32 (*write)(struct ixgbe_hw *, u16, u16);
3242 s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
3243 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
3244 s32 (*update_checksum)(struct ixgbe_hw *);
3245 s32 (*calc_checksum)(struct ixgbe_hw *);
3246};
3247
3248struct ixgbe_mac_operations {
3249 s32 (*init_hw)(struct ixgbe_hw *);
3250 s32 (*reset_hw)(struct ixgbe_hw *);
3251 s32 (*start_hw)(struct ixgbe_hw *);
3252 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
3253 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
3254 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
3255 s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
3256 s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
3257 s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
3258 s32 (*stop_adapter)(struct ixgbe_hw *);
3259 s32 (*get_bus_info)(struct ixgbe_hw *);
3260 void (*set_lan_id)(struct ixgbe_hw *);
3261 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
3262 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
3263 s32 (*setup_sfp)(struct ixgbe_hw *);
3264 s32 (*disable_rx_buff)(struct ixgbe_hw *);
3265 s32 (*enable_rx_buff)(struct ixgbe_hw *);
3266 s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
3267 s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32);
3268 void (*release_swfw_sync)(struct ixgbe_hw *, u32);
3269 s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *);
3270 s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool);
3271
3272
3273 void (*disable_tx_laser)(struct ixgbe_hw *);
3274 void (*enable_tx_laser)(struct ixgbe_hw *);
3275 void (*flap_tx_laser)(struct ixgbe_hw *);
3276 void (*stop_link_on_d3)(struct ixgbe_hw *);
3277 s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3278 s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3279 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
3280 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
3281 bool *);
3282 void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed);
3283
3284
3285 void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
3286
3287
3288 s32 (*led_on)(struct ixgbe_hw *, u32);
3289 s32 (*led_off)(struct ixgbe_hw *, u32);
3290 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
3291 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
3292
3293
3294 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
3295 s32 (*clear_rar)(struct ixgbe_hw *, u32);
3296 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
3297 s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
3298 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
3299 s32 (*init_rx_addrs)(struct ixgbe_hw *);
3300 s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
3301 s32 (*enable_mc)(struct ixgbe_hw *);
3302 s32 (*disable_mc)(struct ixgbe_hw *);
3303 s32 (*clear_vfta)(struct ixgbe_hw *);
3304 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool);
3305 s32 (*init_uta_tables)(struct ixgbe_hw *);
3306 void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
3307 void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
3308
3309
3310 s32 (*fc_enable)(struct ixgbe_hw *);
3311
3312
3313 s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
3314 s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
3315 s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
3316 void (*disable_rx)(struct ixgbe_hw *hw);
3317 void (*enable_rx)(struct ixgbe_hw *hw);
3318 void (*set_source_address_pruning)(struct ixgbe_hw *, bool,
3319 unsigned int);
3320 void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int);
3321
3322
3323 s32 (*dmac_config)(struct ixgbe_hw *hw);
3324 s32 (*dmac_update_tcs)(struct ixgbe_hw *hw);
3325 s32 (*dmac_config_tcs)(struct ixgbe_hw *hw);
3326};
3327
3328struct ixgbe_phy_operations {
3329 s32 (*identify)(struct ixgbe_hw *);
3330 s32 (*identify_sfp)(struct ixgbe_hw *);
3331 s32 (*init)(struct ixgbe_hw *);
3332 s32 (*reset)(struct ixgbe_hw *);
3333 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
3334 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
3335 s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
3336 s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
3337 s32 (*setup_link)(struct ixgbe_hw *);
3338 s32 (*setup_internal_link)(struct ixgbe_hw *);
3339 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
3340 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
3341 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
3342 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
3343 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
3344 s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
3345 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
3346 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
3347 s32 (*read_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val);
3348 s32 (*write_i2c_combined)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val);
3349 s32 (*check_overtemp)(struct ixgbe_hw *);
3350 s32 (*set_phy_power)(struct ixgbe_hw *, bool on);
3351 s32 (*enter_lplu)(struct ixgbe_hw *);
3352 s32 (*handle_lasi)(struct ixgbe_hw *hw);
3353 s32 (*read_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3354 u16 *value);
3355 s32 (*write_i2c_combined_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg,
3356 u16 value);
3357};
3358
3359struct ixgbe_eeprom_info {
3360 struct ixgbe_eeprom_operations ops;
3361 enum ixgbe_eeprom_type type;
3362 u32 semaphore_delay;
3363 u16 word_size;
3364 u16 address_bits;
3365 u16 word_page_size;
3366 u16 ctrl_word_3;
3367};
3368
3369#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01
3370struct ixgbe_mac_info {
3371 struct ixgbe_mac_operations ops;
3372 enum ixgbe_mac_type type;
3373 u8 addr[ETH_ALEN];
3374 u8 perm_addr[ETH_ALEN];
3375 u8 san_addr[ETH_ALEN];
3376
3377 u16 wwnn_prefix;
3378
3379 u16 wwpn_prefix;
3380 u16 max_msix_vectors;
3381#define IXGBE_MAX_MTA 128
3382 u32 mta_shadow[IXGBE_MAX_MTA];
3383 s32 mc_filter_type;
3384 u32 mcft_size;
3385 u32 vft_size;
3386 u32 num_rar_entries;
3387 u32 rar_highwater;
3388 u32 rx_pb_size;
3389 u32 max_tx_queues;
3390 u32 max_rx_queues;
3391 u32 orig_autoc;
3392 u32 orig_autoc2;
3393 bool orig_link_settings_stored;
3394 bool autotry_restart;
3395 u8 flags;
3396 u8 san_mac_rar_index;
3397 struct ixgbe_thermal_sensor_data thermal_sensor_data;
3398 bool set_lben;
3399};
3400
3401struct ixgbe_phy_info {
3402 struct ixgbe_phy_operations ops;
3403 struct mdio_if_info mdio;
3404 enum ixgbe_phy_type type;
3405 u32 id;
3406 enum ixgbe_sfp_type sfp_type;
3407 bool sfp_setup_needed;
3408 u32 revision;
3409 enum ixgbe_media_type media_type;
3410 u32 phy_semaphore_mask;
3411 bool reset_disable;
3412 ixgbe_autoneg_advertised autoneg_advertised;
3413 ixgbe_link_speed speeds_supported;
3414 enum ixgbe_smart_speed smart_speed;
3415 bool smart_speed_active;
3416 bool multispeed_fiber;
3417 bool reset_if_overtemp;
3418 bool qsfp_shared_i2c_bus;
3419 u32 nw_mng_if_sel;
3420};
3421
3422#include "ixgbe_mbx.h"
3423
3424struct ixgbe_mbx_operations {
3425 s32 (*init_params)(struct ixgbe_hw *hw);
3426 s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16);
3427 s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
3428 s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3429 s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
3430 s32 (*check_for_msg)(struct ixgbe_hw *, u16);
3431 s32 (*check_for_ack)(struct ixgbe_hw *, u16);
3432 s32 (*check_for_rst)(struct ixgbe_hw *, u16);
3433};
3434
3435struct ixgbe_mbx_stats {
3436 u32 msgs_tx;
3437 u32 msgs_rx;
3438
3439 u32 acks;
3440 u32 reqs;
3441 u32 rsts;
3442};
3443
3444struct ixgbe_mbx_info {
3445 struct ixgbe_mbx_operations ops;
3446 struct ixgbe_mbx_stats stats;
3447 u32 timeout;
3448 u32 usec_delay;
3449 u32 v2p_mailbox;
3450 u16 size;
3451};
3452
3453struct ixgbe_hw {
3454 u8 __iomem *hw_addr;
3455 void *back;
3456 struct ixgbe_mac_info mac;
3457 struct ixgbe_addr_filter_info addr_ctrl;
3458 struct ixgbe_fc_info fc;
3459 struct ixgbe_phy_info phy;
3460 struct ixgbe_eeprom_info eeprom;
3461 struct ixgbe_bus_info bus;
3462 struct ixgbe_mbx_info mbx;
3463 const u32 *mvals;
3464 u16 device_id;
3465 u16 vendor_id;
3466 u16 subsystem_device_id;
3467 u16 subsystem_vendor_id;
3468 u8 revision_id;
3469 bool adapter_stopped;
3470 bool force_full_reset;
3471 bool allow_unsupported_sfp;
3472 bool wol_enabled;
3473};
3474
3475struct ixgbe_info {
3476 enum ixgbe_mac_type mac;
3477 s32 (*get_invariants)(struct ixgbe_hw *);
3478 struct ixgbe_mac_operations *mac_ops;
3479 struct ixgbe_eeprom_operations *eeprom_ops;
3480 struct ixgbe_phy_operations *phy_ops;
3481 struct ixgbe_mbx_operations *mbx_ops;
3482 const u32 *mvals;
3483};
3484
3485
3486
3487#define IXGBE_ERR_EEPROM -1
3488#define IXGBE_ERR_EEPROM_CHECKSUM -2
3489#define IXGBE_ERR_PHY -3
3490#define IXGBE_ERR_CONFIG -4
3491#define IXGBE_ERR_PARAM -5
3492#define IXGBE_ERR_MAC_TYPE -6
3493#define IXGBE_ERR_UNKNOWN_PHY -7
3494#define IXGBE_ERR_LINK_SETUP -8
3495#define IXGBE_ERR_ADAPTER_STOPPED -9
3496#define IXGBE_ERR_INVALID_MAC_ADDR -10
3497#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
3498#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
3499#define IXGBE_ERR_INVALID_LINK_SETTINGS -13
3500#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
3501#define IXGBE_ERR_RESET_FAILED -15
3502#define IXGBE_ERR_SWFW_SYNC -16
3503#define IXGBE_ERR_PHY_ADDR_INVALID -17
3504#define IXGBE_ERR_I2C -18
3505#define IXGBE_ERR_SFP_NOT_SUPPORTED -19
3506#define IXGBE_ERR_SFP_NOT_PRESENT -20
3507#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21
3508#define IXGBE_ERR_NO_SAN_ADDR_PTR -22
3509#define IXGBE_ERR_FDIR_REINIT_FAILED -23
3510#define IXGBE_ERR_EEPROM_VERSION -24
3511#define IXGBE_ERR_NO_SPACE -25
3512#define IXGBE_ERR_OVERTEMP -26
3513#define IXGBE_ERR_FC_NOT_NEGOTIATED -27
3514#define IXGBE_ERR_FC_NOT_SUPPORTED -28
3515#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30
3516#define IXGBE_ERR_PBA_SECTION -31
3517#define IXGBE_ERR_INVALID_ARGUMENT -32
3518#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33
3519#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38
3520#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
3521
3522#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4))
3523#define IXGBE_FUSES0_300MHZ BIT(5)
3524#define IXGBE_FUSES0_REV_MASK (3 << 6)
3525
3526#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010)
3527#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C)
3528#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634)
3529#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638)
3530#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00)
3531#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00)
3532#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520)
3533#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00)
3534
3535#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9)
3536#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11)
3537
3538#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8)
3539#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8)
3540#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8)
3541#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14)
3542#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15)
3543#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16)
3544#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18)
3545#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24)
3546#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26)
3547#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29)
3548#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31)
3549
3550#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6)
3551#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15)
3552#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16)
3553
3554#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4)
3555#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2)
3556
3557#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16)
3558
3559#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1)
3560#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2)
3561#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3)
3562#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31)
3563
3564#define IXGBE_KX4_LINK_CNTL_1 0x4C
3565#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX (1 << 16)
3566#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 (1 << 17)
3567#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX (1 << 24)
3568#define IXGBE_KX4_LINK_CNTL_1_TETH_EEE_CAP_KX4 (1 << 25)
3569#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE (1 << 29)
3570#define IXGBE_KX4_LINK_CNTL_1_TETH_FORCE_LINK_UP (1 << 30)
3571#define IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART (1 << 31)
3572
3573#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144
3574#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148
3575
3576#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0
3577#define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF
3578#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18
3579#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \
3580 (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT)
3581#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20
3582#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \
3583 (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT)
3584#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28
3585#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7
3586#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31
3587#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT)
3588#define IXGBE_SB_IOSF_TARGET_KR_PHY 0
3589#define IXGBE_SB_IOSF_TARGET_KX4_UNIPHY 1
3590#define IXGBE_SB_IOSF_TARGET_KX4_PCS0 2
3591#define IXGBE_SB_IOSF_TARGET_KX4_PCS1 3
3592
3593#define IXGBE_NW_MNG_IF_SEL 0x00011178
3594#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE BIT(24)
3595#endif
3596