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37#include <linux/hardirq.h>
38#include <linux/export.h>
39
40#include <linux/mlx4/cmd.h>
41#include <linux/mlx4/cq.h>
42
43#include "mlx4.h"
44#include "icm.h"
45
46#define MLX4_CQ_STATUS_OK ( 0 << 28)
47#define MLX4_CQ_STATUS_OVERFLOW ( 9 << 28)
48#define MLX4_CQ_STATUS_WRITE_FAIL (10 << 28)
49#define MLX4_CQ_FLAG_CC ( 1 << 18)
50#define MLX4_CQ_FLAG_OI ( 1 << 17)
51#define MLX4_CQ_STATE_ARMED ( 9 << 8)
52#define MLX4_CQ_STATE_ARMED_SOL ( 6 << 8)
53#define MLX4_EQ_STATE_FIRED (10 << 8)
54
55#define TASKLET_MAX_TIME 2
56#define TASKLET_MAX_TIME_JIFFIES msecs_to_jiffies(TASKLET_MAX_TIME)
57
58void mlx4_cq_tasklet_cb(unsigned long data)
59{
60 unsigned long flags;
61 unsigned long end = jiffies + TASKLET_MAX_TIME_JIFFIES;
62 struct mlx4_eq_tasklet *ctx = (struct mlx4_eq_tasklet *)data;
63 struct mlx4_cq *mcq, *temp;
64
65 spin_lock_irqsave(&ctx->lock, flags);
66 list_splice_tail_init(&ctx->list, &ctx->process_list);
67 spin_unlock_irqrestore(&ctx->lock, flags);
68
69 list_for_each_entry_safe(mcq, temp, &ctx->process_list, tasklet_ctx.list) {
70 list_del_init(&mcq->tasklet_ctx.list);
71 mcq->tasklet_ctx.comp(mcq);
72 if (atomic_dec_and_test(&mcq->refcount))
73 complete(&mcq->free);
74 if (time_after(jiffies, end))
75 break;
76 }
77
78 if (!list_empty(&ctx->process_list))
79 tasklet_schedule(&ctx->task);
80}
81
82static void mlx4_add_cq_to_tasklet(struct mlx4_cq *cq)
83{
84 unsigned long flags;
85 struct mlx4_eq_tasklet *tasklet_ctx = cq->tasklet_ctx.priv;
86
87 spin_lock_irqsave(&tasklet_ctx->lock, flags);
88
89
90
91
92
93 if (list_empty_careful(&cq->tasklet_ctx.list)) {
94 atomic_inc(&cq->refcount);
95 list_add_tail(&cq->tasklet_ctx.list, &tasklet_ctx->list);
96 }
97 spin_unlock_irqrestore(&tasklet_ctx->lock, flags);
98}
99
100void mlx4_cq_completion(struct mlx4_dev *dev, u32 cqn)
101{
102 struct mlx4_cq *cq;
103
104 cq = radix_tree_lookup(&mlx4_priv(dev)->cq_table.tree,
105 cqn & (dev->caps.num_cqs - 1));
106 if (!cq) {
107 mlx4_dbg(dev, "Completion event for bogus CQ %08x\n", cqn);
108 return;
109 }
110
111 ++cq->arm_sn;
112
113 cq->comp(cq);
114}
115
116void mlx4_cq_event(struct mlx4_dev *dev, u32 cqn, int event_type)
117{
118 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
119 struct mlx4_cq *cq;
120
121 spin_lock(&cq_table->lock);
122
123 cq = radix_tree_lookup(&cq_table->tree, cqn & (dev->caps.num_cqs - 1));
124 if (cq)
125 atomic_inc(&cq->refcount);
126
127 spin_unlock(&cq_table->lock);
128
129 if (!cq) {
130 mlx4_warn(dev, "Async event for bogus CQ %08x\n", cqn);
131 return;
132 }
133
134 cq->event(cq, event_type);
135
136 if (atomic_dec_and_test(&cq->refcount))
137 complete(&cq->free);
138}
139
140static int mlx4_SW2HW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
141 int cq_num)
142{
143 return mlx4_cmd(dev, mailbox->dma, cq_num, 0,
144 MLX4_CMD_SW2HW_CQ, MLX4_CMD_TIME_CLASS_A,
145 MLX4_CMD_WRAPPED);
146}
147
148static int mlx4_MODIFY_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
149 int cq_num, u32 opmod)
150{
151 return mlx4_cmd(dev, mailbox->dma, cq_num, opmod, MLX4_CMD_MODIFY_CQ,
152 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
153}
154
155static int mlx4_HW2SW_CQ(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
156 int cq_num)
157{
158 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0,
159 cq_num, mailbox ? 0 : 1, MLX4_CMD_HW2SW_CQ,
160 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
161}
162
163int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
164 u16 count, u16 period)
165{
166 struct mlx4_cmd_mailbox *mailbox;
167 struct mlx4_cq_context *cq_context;
168 int err;
169
170 mailbox = mlx4_alloc_cmd_mailbox(dev);
171 if (IS_ERR(mailbox))
172 return PTR_ERR(mailbox);
173
174 cq_context = mailbox->buf;
175 cq_context->cq_max_count = cpu_to_be16(count);
176 cq_context->cq_period = cpu_to_be16(period);
177
178 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 1);
179
180 mlx4_free_cmd_mailbox(dev, mailbox);
181 return err;
182}
183EXPORT_SYMBOL_GPL(mlx4_cq_modify);
184
185int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
186 int entries, struct mlx4_mtt *mtt)
187{
188 struct mlx4_cmd_mailbox *mailbox;
189 struct mlx4_cq_context *cq_context;
190 u64 mtt_addr;
191 int err;
192
193 mailbox = mlx4_alloc_cmd_mailbox(dev);
194 if (IS_ERR(mailbox))
195 return PTR_ERR(mailbox);
196
197 cq_context = mailbox->buf;
198 cq_context->logsize_usrpage = cpu_to_be32(ilog2(entries) << 24);
199 cq_context->log_page_size = mtt->page_shift - 12;
200 mtt_addr = mlx4_mtt_addr(dev, mtt);
201 cq_context->mtt_base_addr_h = mtt_addr >> 32;
202 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
203
204 err = mlx4_MODIFY_CQ(dev, mailbox, cq->cqn, 0);
205
206 mlx4_free_cmd_mailbox(dev, mailbox);
207 return err;
208}
209EXPORT_SYMBOL_GPL(mlx4_cq_resize);
210
211int __mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
212{
213 struct mlx4_priv *priv = mlx4_priv(dev);
214 struct mlx4_cq_table *cq_table = &priv->cq_table;
215 int err;
216
217 *cqn = mlx4_bitmap_alloc(&cq_table->bitmap);
218 if (*cqn == -1)
219 return -ENOMEM;
220
221 err = mlx4_table_get(dev, &cq_table->table, *cqn, GFP_KERNEL);
222 if (err)
223 goto err_out;
224
225 err = mlx4_table_get(dev, &cq_table->cmpt_table, *cqn, GFP_KERNEL);
226 if (err)
227 goto err_put;
228 return 0;
229
230err_put:
231 mlx4_table_put(dev, &cq_table->table, *cqn);
232
233err_out:
234 mlx4_bitmap_free(&cq_table->bitmap, *cqn, MLX4_NO_RR);
235 return err;
236}
237
238static int mlx4_cq_alloc_icm(struct mlx4_dev *dev, int *cqn)
239{
240 u64 out_param;
241 int err;
242
243 if (mlx4_is_mfunc(dev)) {
244 err = mlx4_cmd_imm(dev, 0, &out_param, RES_CQ,
245 RES_OP_RESERVE_AND_MAP, MLX4_CMD_ALLOC_RES,
246 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
247 if (err)
248 return err;
249 else {
250 *cqn = get_param_l(&out_param);
251 return 0;
252 }
253 }
254 return __mlx4_cq_alloc_icm(dev, cqn);
255}
256
257void __mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
258{
259 struct mlx4_priv *priv = mlx4_priv(dev);
260 struct mlx4_cq_table *cq_table = &priv->cq_table;
261
262 mlx4_table_put(dev, &cq_table->cmpt_table, cqn);
263 mlx4_table_put(dev, &cq_table->table, cqn);
264 mlx4_bitmap_free(&cq_table->bitmap, cqn, MLX4_NO_RR);
265}
266
267static void mlx4_cq_free_icm(struct mlx4_dev *dev, int cqn)
268{
269 u64 in_param = 0;
270 int err;
271
272 if (mlx4_is_mfunc(dev)) {
273 set_param_l(&in_param, cqn);
274 err = mlx4_cmd(dev, in_param, RES_CQ, RES_OP_RESERVE_AND_MAP,
275 MLX4_CMD_FREE_RES,
276 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
277 if (err)
278 mlx4_warn(dev, "Failed freeing cq:%d\n", cqn);
279 } else
280 __mlx4_cq_free_icm(dev, cqn);
281}
282
283int mlx4_cq_alloc(struct mlx4_dev *dev, int nent,
284 struct mlx4_mtt *mtt, struct mlx4_uar *uar, u64 db_rec,
285 struct mlx4_cq *cq, unsigned vector, int collapsed,
286 int timestamp_en)
287{
288 struct mlx4_priv *priv = mlx4_priv(dev);
289 struct mlx4_cq_table *cq_table = &priv->cq_table;
290 struct mlx4_cmd_mailbox *mailbox;
291 struct mlx4_cq_context *cq_context;
292 u64 mtt_addr;
293 int err;
294
295 if (vector >= dev->caps.num_comp_vectors)
296 return -EINVAL;
297
298 cq->vector = vector;
299
300 err = mlx4_cq_alloc_icm(dev, &cq->cqn);
301 if (err)
302 return err;
303
304 spin_lock_irq(&cq_table->lock);
305 err = radix_tree_insert(&cq_table->tree, cq->cqn, cq);
306 spin_unlock_irq(&cq_table->lock);
307 if (err)
308 goto err_icm;
309
310 mailbox = mlx4_alloc_cmd_mailbox(dev);
311 if (IS_ERR(mailbox)) {
312 err = PTR_ERR(mailbox);
313 goto err_radix;
314 }
315
316 cq_context = mailbox->buf;
317 cq_context->flags = cpu_to_be32(!!collapsed << 18);
318 if (timestamp_en)
319 cq_context->flags |= cpu_to_be32(1 << 19);
320
321 cq_context->logsize_usrpage =
322 cpu_to_be32((ilog2(nent) << 24) |
323 mlx4_to_hw_uar_index(dev, uar->index));
324 cq_context->comp_eqn = priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].eqn;
325 cq_context->log_page_size = mtt->page_shift - MLX4_ICM_PAGE_SHIFT;
326
327 mtt_addr = mlx4_mtt_addr(dev, mtt);
328 cq_context->mtt_base_addr_h = mtt_addr >> 32;
329 cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
330 cq_context->db_rec_addr = cpu_to_be64(db_rec);
331
332 err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
333 mlx4_free_cmd_mailbox(dev, mailbox);
334 if (err)
335 goto err_radix;
336
337 cq->cons_index = 0;
338 cq->arm_sn = 1;
339 cq->uar = uar;
340 atomic_set(&cq->refcount, 1);
341 init_completion(&cq->free);
342 cq->comp = mlx4_add_cq_to_tasklet;
343 cq->tasklet_ctx.priv =
344 &priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].tasklet_ctx;
345 INIT_LIST_HEAD(&cq->tasklet_ctx.list);
346
347
348 cq->irq = priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(vector)].irq;
349 return 0;
350
351err_radix:
352 spin_lock_irq(&cq_table->lock);
353 radix_tree_delete(&cq_table->tree, cq->cqn);
354 spin_unlock_irq(&cq_table->lock);
355
356err_icm:
357 mlx4_cq_free_icm(dev, cq->cqn);
358
359 return err;
360}
361EXPORT_SYMBOL_GPL(mlx4_cq_alloc);
362
363void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq)
364{
365 struct mlx4_priv *priv = mlx4_priv(dev);
366 struct mlx4_cq_table *cq_table = &priv->cq_table;
367 int err;
368
369 err = mlx4_HW2SW_CQ(dev, NULL, cq->cqn);
370 if (err)
371 mlx4_warn(dev, "HW2SW_CQ failed (%d) for CQN %06x\n", err, cq->cqn);
372
373 synchronize_irq(priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq);
374 if (priv->eq_table.eq[MLX4_CQ_TO_EQ_VECTOR(cq->vector)].irq !=
375 priv->eq_table.eq[MLX4_EQ_ASYNC].irq)
376 synchronize_irq(priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
377
378 spin_lock_irq(&cq_table->lock);
379 radix_tree_delete(&cq_table->tree, cq->cqn);
380 spin_unlock_irq(&cq_table->lock);
381
382 if (atomic_dec_and_test(&cq->refcount))
383 complete(&cq->free);
384 wait_for_completion(&cq->free);
385
386 mlx4_cq_free_icm(dev, cq->cqn);
387}
388EXPORT_SYMBOL_GPL(mlx4_cq_free);
389
390int mlx4_init_cq_table(struct mlx4_dev *dev)
391{
392 struct mlx4_cq_table *cq_table = &mlx4_priv(dev)->cq_table;
393 int err;
394
395 spin_lock_init(&cq_table->lock);
396 INIT_RADIX_TREE(&cq_table->tree, GFP_ATOMIC);
397 if (mlx4_is_slave(dev))
398 return 0;
399
400 err = mlx4_bitmap_init(&cq_table->bitmap, dev->caps.num_cqs,
401 dev->caps.num_cqs - 1, dev->caps.reserved_cqs, 0);
402 if (err)
403 return err;
404
405 return 0;
406}
407
408void mlx4_cleanup_cq_table(struct mlx4_dev *dev)
409{
410 if (mlx4_is_slave(dev))
411 return;
412
413 mlx4_bitmap_cleanup(&mlx4_priv(dev)->cq_table.bitmap);
414}
415
