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9#ifndef _QED_HSI_H
10#define _QED_HSI_H
11
12#include <linux/types.h>
13#include <linux/io.h>
14#include <linux/bitops.h>
15#include <linux/delay.h>
16#include <linux/kernel.h>
17#include <linux/list.h>
18#include <linux/slab.h>
19#include <linux/qed/common_hsi.h>
20#include <linux/qed/eth_common.h>
21
22struct qed_hwfn;
23struct qed_ptt;
24
25
26
27
28
29enum common_event_opcode {
30 COMMON_EVENT_PF_START,
31 COMMON_EVENT_PF_STOP,
32 COMMON_EVENT_RESERVED,
33 COMMON_EVENT_RESERVED2,
34 COMMON_EVENT_RESERVED3,
35 COMMON_EVENT_RESERVED4,
36 COMMON_EVENT_RESERVED5,
37 COMMON_EVENT_RESERVED6,
38 COMMON_EVENT_EMPTY,
39 MAX_COMMON_EVENT_OPCODE
40};
41
42
43enum common_ramrod_cmd_id {
44 COMMON_RAMROD_UNUSED,
45 COMMON_RAMROD_PF_START ,
46 COMMON_RAMROD_PF_STOP ,
47 COMMON_RAMROD_RESERVED,
48 COMMON_RAMROD_RESERVED2,
49 COMMON_RAMROD_RESERVED3,
50 COMMON_RAMROD_EMPTY,
51 MAX_COMMON_RAMROD_CMD_ID
52};
53
54
55struct ystorm_core_conn_st_ctx {
56 __le32 reserved[4];
57};
58
59
60struct pstorm_core_conn_st_ctx {
61 __le32 reserved[4];
62};
63
64
65struct xstorm_core_conn_st_ctx {
66 __le32 spq_base_lo ;
67 __le32 spq_base_hi ;
68 struct regpair consolid_base_addr;
69 __le16 spq_cons ;
70 __le16 consolid_cons ;
71 __le32 reserved0[55] ;
72};
73
74struct xstorm_core_conn_ag_ctx {
75 u8 reserved0 ;
76 u8 core_state ;
77 u8 flags0;
78#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
79#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
80#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1
81#define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1
82#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1
83#define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2
84#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
85#define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
86#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1
87#define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4
88#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1
89#define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5
90#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1
91#define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6
92#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1
93#define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7
94 u8 flags1;
95#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1
96#define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0
97#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1
98#define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1
99#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1
100#define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2
101#define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1
102#define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3
103#define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1
104#define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4
105#define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1
106#define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5
107#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
108#define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
109#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
110#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
111 u8 flags2;
112#define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
113#define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0
114#define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
115#define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2
116#define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
117#define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4
118#define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
119#define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6
120 u8 flags3;
121#define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
122#define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0
123#define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
124#define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2
125#define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
126#define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4
127#define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
128#define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6
129 u8 flags4;
130#define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
131#define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0
132#define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
133#define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2
134#define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
135#define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4
136#define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3
137#define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6
138 u8 flags5;
139#define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3
140#define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0
141#define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3
142#define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2
143#define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3
144#define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4
145#define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3
146#define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6
147 u8 flags6;
148#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3
149#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0
150#define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3
151#define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2
152#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3
153#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4
154#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
155#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
156 u8 flags7;
157#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
158#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
159#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3
160#define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2
161#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3
162#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4
163#define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
164#define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6
165#define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
166#define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7
167 u8 flags8;
168#define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
169#define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0
170#define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
171#define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1
172#define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
173#define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2
174#define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
175#define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3
176#define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
177#define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4
178#define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
179#define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5
180#define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
181#define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6
182#define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
183#define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7
184 u8 flags9;
185#define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
186#define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0
187#define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1
188#define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1
189#define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1
190#define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2
191#define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1
192#define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3
193#define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1
194#define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4
195#define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1
196#define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5
197#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1
198#define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6
199#define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1
200#define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7
201 u8 flags10;
202#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
203#define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
204#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
205#define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
206#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
207#define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
208#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1
209#define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3
210#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
211#define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
212#define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1
213#define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5
214#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1
215#define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6
216#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1
217#define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7
218 u8 flags11;
219#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1
220#define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0
221#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1
222#define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1
223#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
224#define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
225#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
226#define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3
227#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
228#define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4
229#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
230#define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5
231#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
232#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
233#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1
234#define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7
235 u8 flags12;
236#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1
237#define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0
238#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1
239#define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1
240#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
241#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
242#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
243#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
244#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1
245#define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4
246#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1
247#define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5
248#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1
249#define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6
250#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1
251#define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7
252 u8 flags13;
253#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1
254#define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0
255#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1
256#define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1
257#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
258#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
259#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
260#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
261#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
262#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
263#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
264#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
265#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
266#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
267#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
268#define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
269 u8 flags14;
270#define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1
271#define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0
272#define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1
273#define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1
274#define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1
275#define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2
276#define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1
277#define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3
278#define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1
279#define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4
280#define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1
281#define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5
282#define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3
283#define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6
284 u8 byte2 ;
285 __le16 physical_q0 ;
286 __le16 consolid_prod ;
287 __le16 reserved16 ;
288 __le16 tx_bd_cons ;
289 __le16 tx_bd_or_spq_prod ;
290 __le16 word5 ;
291 __le16 conn_dpi ;
292 u8 byte3 ;
293 u8 byte4 ;
294 u8 byte5 ;
295 u8 byte6 ;
296 __le32 reg0 ;
297 __le32 reg1 ;
298 __le32 reg2 ;
299 __le32 reg3 ;
300 __le32 reg4 ;
301 __le32 reg5 ;
302 __le32 reg6 ;
303 __le16 word7 ;
304 __le16 word8 ;
305 __le16 word9 ;
306 __le16 word10 ;
307 __le32 reg7 ;
308 __le32 reg8 ;
309 __le32 reg9 ;
310 u8 byte7 ;
311 u8 byte8 ;
312 u8 byte9 ;
313 u8 byte10 ;
314 u8 byte11 ;
315 u8 byte12 ;
316 u8 byte13 ;
317 u8 byte14 ;
318 u8 byte15 ;
319 u8 byte16 ;
320 __le16 word11 ;
321 __le32 reg10 ;
322 __le32 reg11 ;
323 __le32 reg12 ;
324 __le32 reg13 ;
325 __le32 reg14 ;
326 __le32 reg15 ;
327 __le32 reg16 ;
328 __le32 reg17 ;
329 __le32 reg18 ;
330 __le32 reg19 ;
331 __le16 word12 ;
332 __le16 word13 ;
333 __le16 word14 ;
334 __le16 word15 ;
335};
336
337struct tstorm_core_conn_ag_ctx {
338 u8 byte0 ;
339 u8 byte1 ;
340 u8 flags0;
341#define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
342#define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
343#define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
344#define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
345#define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1
346#define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2
347#define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1
348#define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3
349#define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1
350#define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4
351#define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1
352#define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5
353#define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
354#define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6
355 u8 flags1;
356#define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
357#define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0
358#define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
359#define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2
360#define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
361#define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4
362#define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
363#define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6
364 u8 flags2;
365#define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
366#define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0
367#define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
368#define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2
369#define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3
370#define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4
371#define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3
372#define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6
373 u8 flags3;
374#define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3
375#define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0
376#define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3
377#define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2
378#define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
379#define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4
380#define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
381#define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5
382#define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
383#define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6
384#define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
385#define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7
386 u8 flags4;
387#define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
388#define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0
389#define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
390#define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1
391#define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
392#define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2
393#define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1
394#define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3
395#define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1
396#define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4
397#define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1
398#define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5
399#define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1
400#define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6
401#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
402#define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
403 u8 flags5;
404#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
405#define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
406#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
407#define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
408#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
409#define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
410#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
411#define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
412#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
413#define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
414#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
415#define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
416#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
417#define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
418#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
419#define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
420 __le32 reg0 ;
421 __le32 reg1 ;
422 __le32 reg2 ;
423 __le32 reg3 ;
424 __le32 reg4 ;
425 __le32 reg5 ;
426 __le32 reg6 ;
427 __le32 reg7 ;
428 __le32 reg8 ;
429 u8 byte2 ;
430 u8 byte3 ;
431 __le16 word0 ;
432 u8 byte4 ;
433 u8 byte5 ;
434 __le16 word1 ;
435 __le16 word2 ;
436 __le16 word3 ;
437 __le32 reg9 ;
438 __le32 reg10 ;
439};
440
441struct ustorm_core_conn_ag_ctx {
442 u8 reserved ;
443 u8 byte1 ;
444 u8 flags0;
445#define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1
446#define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0
447#define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1
448#define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1
449#define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3
450#define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2
451#define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3
452#define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4
453#define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3
454#define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6
455 u8 flags1;
456#define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3
457#define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0
458#define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3
459#define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2
460#define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3
461#define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4
462#define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3
463#define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6
464 u8 flags2;
465#define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1
466#define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0
467#define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1
468#define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1
469#define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1
470#define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2
471#define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1
472#define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3
473#define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1
474#define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4
475#define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1
476#define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5
477#define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1
478#define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6
479#define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1
480#define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7
481 u8 flags3;
482#define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1
483#define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0
484#define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1
485#define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1
486#define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1
487#define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2
488#define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1
489#define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3
490#define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1
491#define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4
492#define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1
493#define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5
494#define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1
495#define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6
496#define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1
497#define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7
498 u8 byte2 ;
499 u8 byte3 ;
500 __le16 word0 ;
501 __le16 word1 ;
502 __le32 rx_producers ;
503 __le32 reg1 ;
504 __le32 reg2 ;
505 __le32 reg3 ;
506 __le16 word2 ;
507 __le16 word3 ;
508};
509
510
511struct mstorm_core_conn_st_ctx {
512 __le32 reserved[24];
513};
514
515
516struct ustorm_core_conn_st_ctx {
517 __le32 reserved[4];
518};
519
520
521struct core_conn_context {
522 struct ystorm_core_conn_st_ctx ystorm_st_context;
523 struct regpair ystorm_st_padding[2] ;
524 struct pstorm_core_conn_st_ctx pstorm_st_context;
525 struct regpair pstorm_st_padding[2];
526 struct xstorm_core_conn_st_ctx xstorm_st_context;
527 struct xstorm_core_conn_ag_ctx xstorm_ag_context;
528 struct tstorm_core_conn_ag_ctx tstorm_ag_context;
529 struct ustorm_core_conn_ag_ctx ustorm_ag_context;
530 struct mstorm_core_conn_st_ctx mstorm_st_context;
531 struct ustorm_core_conn_st_ctx ustorm_st_context;
532 struct regpair ustorm_st_padding[2] ;
533};
534
535struct eth_mstorm_per_queue_stat {
536 struct regpair ttl0_discard;
537 struct regpair packet_too_big_discard;
538 struct regpair no_buff_discard;
539 struct regpair not_active_discard;
540 struct regpair tpa_coalesced_pkts;
541 struct regpair tpa_coalesced_events;
542 struct regpair tpa_aborts_num;
543 struct regpair tpa_coalesced_bytes;
544};
545
546struct eth_pstorm_per_queue_stat {
547 struct regpair sent_ucast_bytes;
548 struct regpair sent_mcast_bytes;
549 struct regpair sent_bcast_bytes;
550 struct regpair sent_ucast_pkts;
551 struct regpair sent_mcast_pkts;
552 struct regpair sent_bcast_pkts;
553 struct regpair error_drop_pkts;
554};
555
556struct eth_ustorm_per_queue_stat {
557 struct regpair rcv_ucast_bytes;
558 struct regpair rcv_mcast_bytes;
559 struct regpair rcv_bcast_bytes;
560 struct regpair rcv_ucast_pkts;
561 struct regpair rcv_mcast_pkts;
562 struct regpair rcv_bcast_pkts;
563};
564
565
566struct event_ring_next_addr {
567 struct regpair addr ;
568 __le32 reserved[2] ;
569};
570
571union event_ring_element {
572 struct event_ring_entry entry ;
573 struct event_ring_next_addr next_addr;
574};
575
576enum personality_type {
577 BAD_PERSONALITY_TYP,
578 PERSONALITY_RESERVED,
579 PERSONALITY_RESERVED2,
580 PERSONALITY_RDMA_AND_ETH ,
581 PERSONALITY_RESERVED3,
582 PERSONALITY_CORE,
583 PERSONALITY_ETH ,
584 PERSONALITY_RESERVED4,
585 MAX_PERSONALITY_TYPE
586};
587
588struct pf_start_tunnel_config {
589 u8 set_vxlan_udp_port_flg;
590 u8 set_geneve_udp_port_flg;
591 u8 tx_enable_vxlan ;
592 u8 tx_enable_l2geneve;
593 u8 tx_enable_ipgeneve;
594 u8 tx_enable_l2gre ;
595 u8 tx_enable_ipgre ;
596 u8 tunnel_clss_vxlan ;
597 u8 tunnel_clss_l2geneve;
598 u8 tunnel_clss_ipgeneve;
599 u8 tunnel_clss_l2gre;
600 u8 tunnel_clss_ipgre;
601 __le16 vxlan_udp_port ;
602 __le16 geneve_udp_port ;
603};
604
605
606struct pf_start_ramrod_data {
607 struct regpair event_ring_pbl_addr;
608 struct regpair consolid_q_pbl_addr;
609 struct pf_start_tunnel_config tunnel_config;
610 __le16 event_ring_sb_id;
611 u8 base_vf_id;
612 u8 num_vfs;
613 u8 event_ring_num_pages;
614 u8 event_ring_sb_index;
615 u8 path_id;
616 u8 warning_as_error;
617 u8 dont_log_ramrods;
618 u8 personality;
619 __le16 log_type_mask;
620 u8 mf_mode ;
621 u8 integ_phase ;
622 u8 allow_npar_tx_switching;
623 u8 inner_to_outer_pri_map[8];
624 u8 pri_map_valid;
625 u32 outer_tag;
626 u8 reserved0[4];
627};
628
629enum ports_mode {
630 ENGX2_PORTX1 ,
631 ENGX2_PORTX2 ,
632 ENGX1_PORTX1 ,
633 ENGX1_PORTX2 ,
634 ENGX1_PORTX4 ,
635 MAX_PORTS_MODE
636};
637
638
639struct ramrod_header {
640 __le32 cid ;
641 u8 cmd_id ;
642 u8 protocol_id ;
643 __le16 echo ;
644};
645
646
647struct slow_path_element {
648 struct ramrod_header hdr ;
649 struct regpair data_ptr;
650};
651
652struct tstorm_per_port_stat {
653 struct regpair trunc_error_discard;
654 struct regpair mac_error_discard;
655 struct regpair mftag_filter_discard;
656 struct regpair eth_mac_filter_discard;
657 struct regpair ll2_mac_filter_discard;
658 struct regpair ll2_conn_disabled_discard;
659 struct regpair iscsi_irregular_pkt;
660 struct regpair fcoe_irregular_pkt;
661 struct regpair roce_irregular_pkt;
662 struct regpair eth_irregular_pkt;
663 struct regpair toe_irregular_pkt;
664 struct regpair preroce_irregular_pkt;
665};
666
667struct atten_status_block {
668 __le32 atten_bits;
669 __le32 atten_ack;
670 __le16 reserved0;
671 __le16 sb_index ;
672 __le32 reserved1;
673};
674
675enum block_addr {
676 GRCBASE_GRC = 0x50000,
677 GRCBASE_MISCS = 0x9000,
678 GRCBASE_MISC = 0x8000,
679 GRCBASE_DBU = 0xa000,
680 GRCBASE_PGLUE_B = 0x2a8000,
681 GRCBASE_CNIG = 0x218000,
682 GRCBASE_CPMU = 0x30000,
683 GRCBASE_NCSI = 0x40000,
684 GRCBASE_OPTE = 0x53000,
685 GRCBASE_BMB = 0x540000,
686 GRCBASE_PCIE = 0x54000,
687 GRCBASE_MCP = 0xe00000,
688 GRCBASE_MCP2 = 0x52000,
689 GRCBASE_PSWHST = 0x2a0000,
690 GRCBASE_PSWHST2 = 0x29e000,
691 GRCBASE_PSWRD = 0x29c000,
692 GRCBASE_PSWRD2 = 0x29d000,
693 GRCBASE_PSWWR = 0x29a000,
694 GRCBASE_PSWWR2 = 0x29b000,
695 GRCBASE_PSWRQ = 0x280000,
696 GRCBASE_PSWRQ2 = 0x240000,
697 GRCBASE_PGLCS = 0x0,
698 GRCBASE_PTU = 0x560000,
699 GRCBASE_DMAE = 0xc000,
700 GRCBASE_TCM = 0x1180000,
701 GRCBASE_MCM = 0x1200000,
702 GRCBASE_UCM = 0x1280000,
703 GRCBASE_XCM = 0x1000000,
704 GRCBASE_YCM = 0x1080000,
705 GRCBASE_PCM = 0x1100000,
706 GRCBASE_QM = 0x2f0000,
707 GRCBASE_TM = 0x2c0000,
708 GRCBASE_DORQ = 0x100000,
709 GRCBASE_BRB = 0x340000,
710 GRCBASE_SRC = 0x238000,
711 GRCBASE_PRS = 0x1f0000,
712 GRCBASE_TSDM = 0xfb0000,
713 GRCBASE_MSDM = 0xfc0000,
714 GRCBASE_USDM = 0xfd0000,
715 GRCBASE_XSDM = 0xf80000,
716 GRCBASE_YSDM = 0xf90000,
717 GRCBASE_PSDM = 0xfa0000,
718 GRCBASE_TSEM = 0x1700000,
719 GRCBASE_MSEM = 0x1800000,
720 GRCBASE_USEM = 0x1900000,
721 GRCBASE_XSEM = 0x1400000,
722 GRCBASE_YSEM = 0x1500000,
723 GRCBASE_PSEM = 0x1600000,
724 GRCBASE_RSS = 0x238800,
725 GRCBASE_TMLD = 0x4d0000,
726 GRCBASE_MULD = 0x4e0000,
727 GRCBASE_YULD = 0x4c8000,
728 GRCBASE_XYLD = 0x4c0000,
729 GRCBASE_PRM = 0x230000,
730 GRCBASE_PBF_PB1 = 0xda0000,
731 GRCBASE_PBF_PB2 = 0xda4000,
732 GRCBASE_RPB = 0x23c000,
733 GRCBASE_BTB = 0xdb0000,
734 GRCBASE_PBF = 0xd80000,
735 GRCBASE_RDIF = 0x300000,
736 GRCBASE_TDIF = 0x310000,
737 GRCBASE_CDU = 0x580000,
738 GRCBASE_CCFC = 0x2e0000,
739 GRCBASE_TCFC = 0x2d0000,
740 GRCBASE_IGU = 0x180000,
741 GRCBASE_CAU = 0x1c0000,
742 GRCBASE_UMAC = 0x51000,
743 GRCBASE_XMAC = 0x210000,
744 GRCBASE_DBG = 0x10000,
745 GRCBASE_NIG = 0x500000,
746 GRCBASE_WOL = 0x600000,
747 GRCBASE_BMBN = 0x610000,
748 GRCBASE_IPC = 0x20000,
749 GRCBASE_NWM = 0x800000,
750 GRCBASE_NWS = 0x700000,
751 GRCBASE_MS = 0x6a0000,
752 GRCBASE_PHY_PCIE = 0x620000,
753 GRCBASE_MISC_AEU = 0x8000,
754 GRCBASE_BAR0_MAP = 0x1c00000,
755 MAX_BLOCK_ADDR
756};
757
758enum block_id {
759 BLOCK_GRC,
760 BLOCK_MISCS,
761 BLOCK_MISC,
762 BLOCK_DBU,
763 BLOCK_PGLUE_B,
764 BLOCK_CNIG,
765 BLOCK_CPMU,
766 BLOCK_NCSI,
767 BLOCK_OPTE,
768 BLOCK_BMB,
769 BLOCK_PCIE,
770 BLOCK_MCP,
771 BLOCK_MCP2,
772 BLOCK_PSWHST,
773 BLOCK_PSWHST2,
774 BLOCK_PSWRD,
775 BLOCK_PSWRD2,
776 BLOCK_PSWWR,
777 BLOCK_PSWWR2,
778 BLOCK_PSWRQ,
779 BLOCK_PSWRQ2,
780 BLOCK_PGLCS,
781 BLOCK_PTU,
782 BLOCK_DMAE,
783 BLOCK_TCM,
784 BLOCK_MCM,
785 BLOCK_UCM,
786 BLOCK_XCM,
787 BLOCK_YCM,
788 BLOCK_PCM,
789 BLOCK_QM,
790 BLOCK_TM,
791 BLOCK_DORQ,
792 BLOCK_BRB,
793 BLOCK_SRC,
794 BLOCK_PRS,
795 BLOCK_TSDM,
796 BLOCK_MSDM,
797 BLOCK_USDM,
798 BLOCK_XSDM,
799 BLOCK_YSDM,
800 BLOCK_PSDM,
801 BLOCK_TSEM,
802 BLOCK_MSEM,
803 BLOCK_USEM,
804 BLOCK_XSEM,
805 BLOCK_YSEM,
806 BLOCK_PSEM,
807 BLOCK_RSS,
808 BLOCK_TMLD,
809 BLOCK_MULD,
810 BLOCK_YULD,
811 BLOCK_XYLD,
812 BLOCK_PRM,
813 BLOCK_PBF_PB1,
814 BLOCK_PBF_PB2,
815 BLOCK_RPB,
816 BLOCK_BTB,
817 BLOCK_PBF,
818 BLOCK_RDIF,
819 BLOCK_TDIF,
820 BLOCK_CDU,
821 BLOCK_CCFC,
822 BLOCK_TCFC,
823 BLOCK_IGU,
824 BLOCK_CAU,
825 BLOCK_UMAC,
826 BLOCK_XMAC,
827 BLOCK_DBG,
828 BLOCK_NIG,
829 BLOCK_WOL,
830 BLOCK_BMBN,
831 BLOCK_IPC,
832 BLOCK_NWM,
833 BLOCK_NWS,
834 BLOCK_MS,
835 BLOCK_PHY_PCIE,
836 BLOCK_MISC_AEU,
837 BLOCK_BAR0_MAP,
838 MAX_BLOCK_ID
839};
840
841enum command_type_bit {
842 IGU_COMMAND_TYPE_NOP = 0,
843 IGU_COMMAND_TYPE_SET = 1,
844 MAX_COMMAND_TYPE_BIT
845};
846
847struct dmae_cmd {
848 __le32 opcode;
849#define DMAE_CMD_SRC_MASK 0x1
850#define DMAE_CMD_SRC_SHIFT 0
851#define DMAE_CMD_DST_MASK 0x3
852#define DMAE_CMD_DST_SHIFT 1
853#define DMAE_CMD_C_DST_MASK 0x1
854#define DMAE_CMD_C_DST_SHIFT 3
855#define DMAE_CMD_CRC_RESET_MASK 0x1
856#define DMAE_CMD_CRC_RESET_SHIFT 4
857#define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1
858#define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5
859#define DMAE_CMD_DST_ADDR_RESET_MASK 0x1
860#define DMAE_CMD_DST_ADDR_RESET_SHIFT 6
861#define DMAE_CMD_COMP_FUNC_MASK 0x1
862#define DMAE_CMD_COMP_FUNC_SHIFT 7
863#define DMAE_CMD_COMP_WORD_EN_MASK 0x1
864#define DMAE_CMD_COMP_WORD_EN_SHIFT 8
865#define DMAE_CMD_COMP_CRC_EN_MASK 0x1
866#define DMAE_CMD_COMP_CRC_EN_SHIFT 9
867#define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7
868#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
869#define DMAE_CMD_RESERVED1_MASK 0x1
870#define DMAE_CMD_RESERVED1_SHIFT 13
871#define DMAE_CMD_ENDIANITY_MODE_MASK 0x3
872#define DMAE_CMD_ENDIANITY_MODE_SHIFT 14
873#define DMAE_CMD_ERR_HANDLING_MASK 0x3
874#define DMAE_CMD_ERR_HANDLING_SHIFT 16
875#define DMAE_CMD_PORT_ID_MASK 0x3
876#define DMAE_CMD_PORT_ID_SHIFT 18
877#define DMAE_CMD_SRC_PF_ID_MASK 0xF
878#define DMAE_CMD_SRC_PF_ID_SHIFT 20
879#define DMAE_CMD_DST_PF_ID_MASK 0xF
880#define DMAE_CMD_DST_PF_ID_SHIFT 24
881#define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1
882#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
883#define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1
884#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
885#define DMAE_CMD_RESERVED2_MASK 0x3
886#define DMAE_CMD_RESERVED2_SHIFT 30
887 __le32 src_addr_lo;
888 __le32 src_addr_hi;
889 __le32 dst_addr_lo;
890 __le32 dst_addr_hi;
891 __le16 length ;
892 __le16 opcode_b;
893#define DMAE_CMD_SRC_VF_ID_MASK 0xFF
894#define DMAE_CMD_SRC_VF_ID_SHIFT 0
895#define DMAE_CMD_DST_VF_ID_MASK 0xFF
896#define DMAE_CMD_DST_VF_ID_SHIFT 8
897 __le32 comp_addr_lo ;
898 __le32 comp_addr_hi;
899 __le32 comp_val ;
900 __le32 crc32 ;
901 __le32 crc_32_c ;
902 __le16 crc16 ;
903 __le16 crc16_c ;
904 __le16 crc10 ;
905 __le16 reserved;
906 __le16 xsum16 ;
907 __le16 xsum8 ;
908};
909
910struct igu_cleanup {
911 __le32 sb_id_and_flags;
912#define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF
913#define IGU_CLEANUP_RESERVED0_SHIFT 0
914#define IGU_CLEANUP_CLEANUP_SET_MASK 0x1
915#define IGU_CLEANUP_CLEANUP_SET_SHIFT 27
916#define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7
917#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28
918#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1
919#define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31
920 __le32 reserved1;
921};
922
923union igu_command {
924 struct igu_prod_cons_update prod_cons_update;
925 struct igu_cleanup cleanup;
926};
927
928struct igu_command_reg_ctrl {
929 __le16 opaque_fid;
930 __le16 igu_command_reg_ctrl_fields;
931#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF
932#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
933#define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7
934#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12
935#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1
936#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
937};
938
939struct igu_mapping_line {
940 __le32 igu_mapping_line_fields;
941#define IGU_MAPPING_LINE_VALID_MASK 0x1
942#define IGU_MAPPING_LINE_VALID_SHIFT 0
943#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF
944#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1
945#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF
946#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9
947#define IGU_MAPPING_LINE_PF_VALID_MASK 0x1
948#define IGU_MAPPING_LINE_PF_VALID_SHIFT 17
949#define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F
950#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18
951#define IGU_MAPPING_LINE_RESERVED_MASK 0xFF
952#define IGU_MAPPING_LINE_RESERVED_SHIFT 24
953};
954
955struct igu_msix_vector {
956 struct regpair address;
957 __le32 data;
958 __le32 msix_vector_fields;
959#define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1
960#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0
961#define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF
962#define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1
963#define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF
964#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16
965#define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF
966#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24
967};
968
969enum init_modes {
970 MODE_BB_A0,
971 MODE_BB_B0,
972 MODE_RESERVED2,
973 MODE_ASIC,
974 MODE_RESERVED3,
975 MODE_RESERVED4,
976 MODE_RESERVED5,
977 MODE_RESERVED6,
978 MODE_SF,
979 MODE_MF_SD,
980 MODE_MF_SI,
981 MODE_PORTS_PER_ENG_1,
982 MODE_PORTS_PER_ENG_2,
983 MODE_PORTS_PER_ENG_4,
984 MODE_100G,
985 MODE_EAGLE_ENG1_WORKAROUND,
986 MAX_INIT_MODES
987};
988
989enum init_phases {
990 PHASE_ENGINE,
991 PHASE_PORT,
992 PHASE_PF,
993 PHASE_RESERVED,
994 PHASE_QM_PF,
995 MAX_INIT_PHASES
996};
997
998
999struct prs_reg_encapsulation_type_en {
1000 u8 flags;
1001#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1
1002#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0
1003#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1
1004#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1
1005#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1
1006#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2
1007#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1
1008#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3
1009#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1
1010#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4
1011#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1
1012#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5
1013#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3
1014#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6
1015};
1016
1017enum pxp_tph_st_hint {
1018 TPH_ST_HINT_BIDIR ,
1019 TPH_ST_HINT_REQUESTER ,
1020 TPH_ST_HINT_TARGET,
1021 TPH_ST_HINT_TARGET_PRIO,
1022 MAX_PXP_TPH_ST_HINT
1023};
1024
1025
1026struct qm_rf_bypass_mask {
1027 u8 flags;
1028#define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1
1029#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0
1030#define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1
1031#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1
1032#define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1
1033#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2
1034#define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1
1035#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3
1036#define QM_RF_BYPASS_MASK_PFRL_MASK 0x1
1037#define QM_RF_BYPASS_MASK_PFRL_SHIFT 4
1038#define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1
1039#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5
1040#define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1
1041#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6
1042#define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1
1043#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7
1044};
1045
1046
1047struct qm_rf_opportunistic_mask {
1048 __le16 flags;
1049#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1
1050#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0
1051#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1
1052#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1
1053#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1
1054#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2
1055#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1
1056#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3
1057#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1
1058#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4
1059#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1
1060#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5
1061#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1
1062#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6
1063#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1
1064#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7
1065#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1
1066#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8
1067#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F
1068#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9
1069};
1070
1071
1072struct qm_rf_pq_map {
1073 u32 reg;
1074#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1
1075#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
1076#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF
1077#define QM_RF_PQ_MAP_RL_ID_SHIFT 1
1078#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
1079#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
1080#define QM_RF_PQ_MAP_VOQ_MASK 0x1F
1081#define QM_RF_PQ_MAP_VOQ_SHIFT 18
1082#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3
1083#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
1084#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1
1085#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
1086#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
1087#define QM_RF_PQ_MAP_RESERVED_SHIFT 26
1088};
1089
1090
1091struct sdm_agg_int_comp_params {
1092 __le16 params;
1093#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F
1094#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0
1095#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1
1096#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1097#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF
1098#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7
1099};
1100
1101
1102struct sdm_op_gen {
1103 __le32 command;
1104#define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF
1105#define SDM_OP_GEN_COMP_PARAM_SHIFT 0
1106#define SDM_OP_GEN_COMP_TYPE_MASK 0xF
1107#define SDM_OP_GEN_COMP_TYPE_SHIFT 16
1108#define SDM_OP_GEN_RESERVED_MASK 0xFFF
1109#define SDM_OP_GEN_RESERVED_SHIFT 20
1110};
1111
1112
1113
1114
1115#define GRC_ADDR_BITS 23
1116#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
1117
1118
1119#define ANY_PHASE_ID 0xffff
1120
1121
1122#define INIT_PATTERN_SIZE_BITS 4
1123#define MAX_INIT_PATTERN_SIZE BIT(INIT_PATTERN_SIZE_BITS)
1124
1125
1126#define MAX_ZIPPED_SIZE 8192
1127
1128
1129#define NUM_OF_PXP_WIN 19
1130#define PXP_WIN_DWORD_SIZE_BITS 10
1131#define PXP_WIN_DWORD_SIZE BIT(PXP_WIN_DWORD_SIZE_BITS)
1132#define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2)
1133#define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4)
1134
1135
1136
1137
1138#define DUMP_SEQ_LEN_BITS 8
1139#define DUMP_SEQ_LEN_MAX_VAL ((1 << DUMP_SEQ_LEN_BITS) - 1)
1140
1141
1142#define DUMP_MEM_LEN_BITS 18
1143#define DUMP_MEM_LEN_MAX_VAL ((1 << DUMP_MEM_LEN_BITS) - 1)
1144
1145
1146#define REG_TYPE_ID_BITS 6
1147#define REG_TYPE_ID_MAX_VAL ((1 << REG_TYPE_ID_BITS) - 1)
1148
1149
1150#define BLOCK_ID_BITS 8
1151#define BLOCK_ID_MAX_VAL ((1 << BLOCK_ID_BITS) - 1)
1152
1153
1154
1155
1156#define MAX_IDLE_CHK_PRED_IMM 3
1157
1158
1159#define MAX_IDLE_CHK_READ_REGS 3
1160
1161
1162#define MAX_IDLE_CHK_LOOPS 0x10000
1163
1164
1165#define MAX_IDLE_CHK_INCREMENT 0x10000
1166
1167
1168#define IDLE_CHK_UNDEFINED_LINE_IDX 0xffffff
1169
1170
1171#define IDLE_CHK_MAX_DUMP_REGS 2
1172
1173
1174#define IDLE_CHK_QM_RD_WR_PTR 0
1175#define IDLE_CHK_QM_RD_WR_BANK 1
1176
1177
1178
1179
1180
1181
1182#define NUM_OF_VLAN_PRIORITIES 8
1183
1184
1185
1186
1187#define MCP_TRACE_META_IMAGE_SIGNATURE 0x669955aa
1188
1189
1190struct bin_buffer_hdr {
1191 u32 offset;
1192 u32 length ;
1193};
1194
1195
1196enum bin_buffer_type {
1197 BIN_BUF_FW_VER_INFO ,
1198 BIN_BUF_INIT_CMD ,
1199 BIN_BUF_INIT_VAL ,
1200 BIN_BUF_INIT_MODE_TREE ,
1201 BIN_BUF_IRO ,
1202 MAX_BIN_BUFFER_TYPE
1203};
1204
1205
1206enum chip_ids {
1207 CHIP_BB_A0 ,
1208 CHIP_BB_B0 ,
1209 CHIP_K2 ,
1210 MAX_CHIP_IDS
1211};
1212
1213struct init_array_raw_hdr {
1214 __le32 data;
1215#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF
1216#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
1217#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF
1218#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
1219};
1220
1221struct init_array_standard_hdr {
1222 __le32 data;
1223#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF
1224#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
1225#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF
1226#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
1227};
1228
1229struct init_array_zipped_hdr {
1230 __le32 data;
1231#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF
1232#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
1233#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF
1234#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
1235};
1236
1237struct init_array_pattern_hdr {
1238 __le32 data;
1239#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF
1240#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
1241#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF
1242#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
1243#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF
1244#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
1245};
1246
1247union init_array_hdr {
1248 struct init_array_raw_hdr raw ;
1249 struct init_array_standard_hdr standard;
1250 struct init_array_zipped_hdr zipped ;
1251 struct init_array_pattern_hdr pattern ;
1252};
1253
1254enum init_array_types {
1255 INIT_ARR_STANDARD ,
1256 INIT_ARR_ZIPPED ,
1257 INIT_ARR_PATTERN ,
1258 MAX_INIT_ARRAY_TYPES
1259};
1260
1261
1262struct init_callback_op {
1263 __le32 op_data;
1264#define INIT_CALLBACK_OP_OP_MASK 0xF
1265#define INIT_CALLBACK_OP_OP_SHIFT 0
1266#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
1267#define INIT_CALLBACK_OP_RESERVED_SHIFT 4
1268 __le16 callback_id ;
1269 __le16 block_id ;
1270};
1271
1272
1273struct init_delay_op {
1274 __le32 op_data;
1275#define INIT_DELAY_OP_OP_MASK 0xF
1276#define INIT_DELAY_OP_OP_SHIFT 0
1277#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
1278#define INIT_DELAY_OP_RESERVED_SHIFT 4
1279 __le32 delay ;
1280};
1281
1282
1283struct init_if_mode_op {
1284 __le32 op_data;
1285#define INIT_IF_MODE_OP_OP_MASK 0xF
1286#define INIT_IF_MODE_OP_OP_SHIFT 0
1287#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
1288#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
1289#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF
1290#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
1291 __le16 reserved2;
1292 __le16 modes_buf_offset;
1293};
1294
1295
1296struct init_if_phase_op {
1297 __le32 op_data;
1298#define INIT_IF_PHASE_OP_OP_MASK 0xF
1299#define INIT_IF_PHASE_OP_OP_SHIFT 0
1300#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1
1301#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
1302#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
1303#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
1304#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF
1305#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
1306 __le32 phase_data;
1307#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF
1308#define INIT_IF_PHASE_OP_PHASE_SHIFT 0
1309#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
1310#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
1311#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF
1312#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
1313};
1314
1315
1316enum init_mode_ops {
1317 INIT_MODE_OP_NOT ,
1318 INIT_MODE_OP_OR ,
1319 INIT_MODE_OP_AND ,
1320 MAX_INIT_MODE_OPS
1321};
1322
1323
1324struct init_raw_op {
1325 __le32 op_data;
1326#define INIT_RAW_OP_OP_MASK 0xF
1327#define INIT_RAW_OP_OP_SHIFT 0
1328#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF
1329#define INIT_RAW_OP_PARAM1_SHIFT 4
1330 __le32 param2 ;
1331};
1332
1333
1334struct init_op_array_params {
1335 __le16 size ;
1336 __le16 offset ;
1337};
1338
1339
1340union init_write_args {
1341 __le32 inline_val;
1342 __le32 zeros_count;
1343 __le32 array_offset;
1344 struct init_op_array_params runtime;
1345};
1346
1347
1348struct init_write_op {
1349 __le32 data;
1350#define INIT_WRITE_OP_OP_MASK 0xF
1351#define INIT_WRITE_OP_OP_SHIFT 0
1352#define INIT_WRITE_OP_SOURCE_MASK 0x7
1353#define INIT_WRITE_OP_SOURCE_SHIFT 4
1354#define INIT_WRITE_OP_RESERVED_MASK 0x1
1355#define INIT_WRITE_OP_RESERVED_SHIFT 7
1356#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1
1357#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
1358#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF
1359#define INIT_WRITE_OP_ADDRESS_SHIFT 9
1360 union init_write_args args ;
1361};
1362
1363
1364struct init_read_op {
1365 __le32 op_data;
1366#define INIT_READ_OP_OP_MASK 0xF
1367#define INIT_READ_OP_OP_SHIFT 0
1368#define INIT_READ_OP_POLL_TYPE_MASK 0xF
1369#define INIT_READ_OP_POLL_TYPE_SHIFT 4
1370#define INIT_READ_OP_RESERVED_MASK 0x1
1371#define INIT_READ_OP_RESERVED_SHIFT 8
1372#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF
1373#define INIT_READ_OP_ADDRESS_SHIFT 9
1374 __le32 expected_val;
1375};
1376
1377
1378union init_op {
1379 struct init_raw_op raw ;
1380 struct init_write_op write ;
1381 struct init_read_op read ;
1382 struct init_if_mode_op if_mode ;
1383 struct init_if_phase_op if_phase ;
1384 struct init_callback_op callback ;
1385 struct init_delay_op delay ;
1386};
1387
1388
1389enum init_op_types {
1390 INIT_OP_READ ,
1391 INIT_OP_WRITE ,
1392 INIT_OP_IF_MODE,
1393 INIT_OP_IF_PHASE,
1394 INIT_OP_DELAY ,
1395 INIT_OP_CALLBACK ,
1396 MAX_INIT_OP_TYPES
1397};
1398
1399enum init_poll_types {
1400 INIT_POLL_NONE ,
1401 INIT_POLL_EQ ,
1402 INIT_POLL_OR ,
1403 INIT_POLL_AND ,
1404 MAX_INIT_POLL_TYPES
1405};
1406
1407
1408enum init_source_types {
1409 INIT_SRC_INLINE ,
1410 INIT_SRC_ZEROS ,
1411 INIT_SRC_ARRAY ,
1412 INIT_SRC_RUNTIME ,
1413 MAX_INIT_SOURCE_TYPES
1414};
1415
1416
1417struct iro {
1418 u32 base ;
1419 u16 m1 ;
1420 u16 m2 ;
1421 u16 m3 ;
1422 u16 size ;
1423};
1424
1425
1426struct init_qm_port_params {
1427 u8 active ;
1428 u8 num_active_phys_tcs;
1429 u16 num_pbf_cmd_lines;
1430 u16 num_btb_blocks;
1431 __le16 reserved;
1432};
1433
1434
1435struct init_qm_pq_params {
1436 u8 vport_id ;
1437 u8 tc_id ;
1438 u8 wrr_group ;
1439 u8 reserved;
1440};
1441
1442
1443struct init_qm_vport_params {
1444 u32 vport_rl;
1445 u16 vport_wfq;
1446 u16 first_tx_pq_id[NUM_OF_TCS];
1447};
1448
1449
1450#define GTT_BAR0_MAP_REG_IGU_CMD \
1451 0x00f000UL
1452
1453#define GTT_BAR0_MAP_REG_TSDM_RAM \
1454 0x010000UL
1455
1456#define GTT_BAR0_MAP_REG_MSDM_RAM \
1457 0x011000UL
1458
1459#define GTT_BAR0_MAP_REG_MSDM_RAM_1024 \
1460 0x012000UL
1461
1462#define GTT_BAR0_MAP_REG_USDM_RAM \
1463 0x013000UL
1464
1465#define GTT_BAR0_MAP_REG_USDM_RAM_1024 \
1466 0x014000UL
1467
1468#define GTT_BAR0_MAP_REG_USDM_RAM_2048 \
1469 0x015000UL
1470
1471#define GTT_BAR0_MAP_REG_XSDM_RAM \
1472 0x016000UL
1473
1474#define GTT_BAR0_MAP_REG_YSDM_RAM \
1475 0x017000UL
1476
1477#define GTT_BAR0_MAP_REG_PSDM_RAM \
1478 0x018000UL
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495u32 qed_qm_pf_mem_size(u8 pf_id,
1496 u32 num_pf_cids,
1497 u32 num_vf_cids,
1498 u32 num_tids,
1499 u16 num_pf_pqs,
1500 u16 num_vf_pqs);
1501
1502struct qed_qm_common_rt_init_params {
1503 u8 max_ports_per_engine;
1504 u8 max_phys_tcs_per_port;
1505 bool pf_rl_en;
1506 bool pf_wfq_en;
1507 bool vport_rl_en;
1508 bool vport_wfq_en;
1509 struct init_qm_port_params *port_params;
1510};
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528int qed_qm_common_rt_init(
1529 struct qed_hwfn *p_hwfn,
1530 struct qed_qm_common_rt_init_params *p_params);
1531
1532struct qed_qm_pf_rt_init_params {
1533 u8 port_id;
1534 u8 pf_id;
1535 u8 max_phys_tcs_per_port;
1536 bool is_first_pf;
1537 u32 num_pf_cids;
1538 u32 num_vf_cids;
1539 u32 num_tids;
1540 u16 start_pq;
1541 u16 num_pf_pqs;
1542 u16 num_vf_pqs;
1543 u8 start_vport;
1544 u8 num_vports;
1545 u8 pf_wfq;
1546 u32 pf_rl;
1547 struct init_qm_pq_params *pq_params;
1548 struct init_qm_vport_params *vport_params;
1549};
1550
1551int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
1552 struct qed_ptt *p_ptt,
1553 struct qed_qm_pf_rt_init_params *p_params);
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
1566 struct qed_ptt *p_ptt,
1567 u8 pf_id,
1568 u32 pf_rl);
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
1582 struct qed_ptt *p_ptt,
1583 u8 vport_id,
1584 u32 vport_rl);
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
1600 struct qed_ptt *p_ptt,
1601 bool is_release_cmd,
1602 bool is_tx_pq,
1603 u16 start_pq,
1604 u16 num_pqs);
1605
1606
1607#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
1608#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
1609
1610#define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
1611#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
1612
1613#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
1614 (IRO[2].base + ((port_id) * IRO[2].m1))
1615#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
1616
1617#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
1618 (IRO[3].base + ((vf_id) * IRO[3].m1))
1619#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
1620
1621#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
1622#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
1623
1624#define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
1625#define USTORM_EQE_CONS_SIZE (IRO[5].size)
1626
1627#define USTORM_COMMON_QUEUE_CONS_OFFSET(global_queue_id) \
1628 (IRO[6].base + ((global_queue_id) * IRO[6].m1))
1629#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[6].size)
1630
1631#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[7].base)
1632#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[7].size)
1633
1634#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
1635#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
1636
1637#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
1638#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
1639
1640#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
1641#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
1642
1643#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
1644#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
1645
1646#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
1647#define USTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
1648
1649#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
1650 (IRO[13].base + ((core_rx_queue_id) * IRO[13].m1))
1651#define TSTORM_LL2_RX_PRODS_SIZE (IRO[13].size)
1652
1653#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1654 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
1655#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[14].size)
1656
1657#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
1658 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
1659#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
1660
1661#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
1662 (IRO[16].base + ((core_tx_stats_id) * IRO[16].m1))
1663#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
1664
1665#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1666 (IRO[17].base + ((stat_counter_id) * IRO[17].m1))
1667#define MSTORM_QUEUE_STAT_SIZE (IRO[17].size)
1668
1669#define MSTORM_PRODS_OFFSET(queue_id) (IRO[18].base + ((queue_id) * IRO[18].m1))
1670#define MSTORM_PRODS_SIZE (IRO[18].size)
1671
1672#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[19].base)
1673#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[19].size)
1674
1675#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1676 (IRO[20].base + ((stat_counter_id) * IRO[20].m1))
1677#define USTORM_QUEUE_STAT_SIZE (IRO[20].size)
1678
1679#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1680 (IRO[21].base + ((queue_id) * IRO[21].m1))
1681#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[21].size)
1682
1683#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
1684 (IRO[22].base + ((stat_counter_id) * IRO[22].m1))
1685#define PSTORM_QUEUE_STAT_SIZE (IRO[22].size)
1686
1687#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[23].base)
1688#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[23].size)
1689
1690#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[24].base + ((pf_id) * IRO[24].m1))
1691#define ETH_RX_RATE_LIMIT_SIZE (IRO[24].size)
1692
1693#define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
1694 (IRO[25].base + ((queue_id) * IRO[25].m1))
1695#define YSTORM_ETH_QUEUE_ZONE_SIZE (IRO[25].size)
1696
1697#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1698 (IRO[26].base + ((rss_id) * IRO[26].m1))
1699#define YSTORM_TOE_CQ_PROD_SIZE (IRO[26].size)
1700
1701#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
1702 (IRO[27].base + ((rss_id) * IRO[27].m1))
1703#define USTORM_TOE_CQ_PROD_SIZE (IRO[27].size)
1704
1705#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
1706 (IRO[28].base + ((pf_id) * IRO[28].m1))
1707#define USTORM_TOE_GRQ_PROD_SIZE (IRO[28].size)
1708
1709#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
1710 (IRO[29].base + ((cmdq_queue_id) * IRO[29].m1))
1711#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[29].size)
1712
1713#define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id) \
1714 (IRO[30].base + ((rq_queue_id) * IRO[30].m1))
1715#define MSTORM_SCSI_RQ_CONS_SIZE (IRO[30].size)
1716
1717#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1718 (IRO[31].base + ((func_id) * IRO[31].m1) + ((bdq_id) * IRO[31].m2))
1719#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[31].size)
1720
1721#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
1722 (IRO[32].base + ((func_id) * IRO[32].m1) + ((bdq_id) * IRO[32].m2))
1723#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[32].size)
1724
1725#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1726 (IRO[33].base + ((pf_id) * IRO[33].m1))
1727#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[33].size)
1728
1729#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1730 (IRO[34].base + ((pf_id) * IRO[34].m1))
1731#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[34].size)
1732
1733#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
1734 (IRO[35].base + ((pf_id) * IRO[35].m1))
1735#define USTORM_ISCSI_RX_STATS_SIZE (IRO[35].size)
1736
1737#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1738 (IRO[36].base + ((pf_id) * IRO[36].m1))
1739#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[36].size)
1740
1741#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1742 (IRO[37].base + ((pf_id) * IRO[37].m1))
1743#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[37].size)
1744
1745#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
1746 (IRO[38].base + ((pf_id) * IRO[38].m1))
1747#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[38].size)
1748
1749#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1750 (IRO[39].base + ((pf_id) * IRO[39].m1))
1751#define TSTORM_FCOE_RX_STATS_SIZE (IRO[39].size)
1752
1753#define MSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
1754 (IRO[40].base + ((pf_id) * IRO[40].m1))
1755#define MSTORM_FCOE_RX_STATS_SIZE (IRO[40].size)
1756
1757#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
1758 (IRO[41].base + ((pf_id) * IRO[41].m1))
1759#define PSTORM_FCOE_TX_STATS_SIZE (IRO[41].size)
1760
1761#define PSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1762 (IRO[42].base + ((stat_counter_id) * IRO[42].m1))
1763#define PSTORM_ROCE_STAT_SIZE (IRO[42].size)
1764
1765#define TSTORM_ROCE_STAT_OFFSET(stat_counter_id) \
1766 (IRO[43].base + ((stat_counter_id) * IRO[43].m1))
1767#define TSTORM_ROCE_STAT_SIZE (IRO[43].size)
1768
1769static const struct iro iro_arr[44] = {
1770 { 0x10, 0x0, 0x0, 0x0, 0x8 },
1771 { 0x47c8, 0x60, 0x0, 0x0, 0x60 },
1772 { 0x5e30, 0x20, 0x0, 0x0, 0x20 },
1773 { 0x510, 0x8, 0x0, 0x0, 0x4 },
1774 { 0x490, 0x8, 0x0, 0x0, 0x4 },
1775 { 0x10, 0x8, 0x0, 0x0, 0x2 },
1776 { 0x90, 0x8, 0x0, 0x0, 0x2 },
1777 { 0x4940, 0x0, 0x0, 0x0, 0x78 },
1778 { 0x3de0, 0x0, 0x0, 0x0, 0x78 },
1779 { 0x2998, 0x0, 0x0, 0x0, 0x78 },
1780 { 0x4750, 0x0, 0x0, 0x0, 0x78 },
1781 { 0x56d0, 0x0, 0x0, 0x0, 0x78 },
1782 { 0x7e50, 0x0, 0x0, 0x0, 0x78 },
1783 { 0x100, 0x8, 0x0, 0x0, 0x8 },
1784 { 0x5c10, 0x10, 0x0, 0x0, 0x10 },
1785 { 0xb508, 0x30, 0x0, 0x0, 0x30 },
1786 { 0x95c0, 0x30, 0x0, 0x0, 0x30 },
1787 { 0x58a0, 0x40, 0x0, 0x0, 0x40 },
1788 { 0x200, 0x10, 0x0, 0x0, 0x8 },
1789 { 0xa230, 0x0, 0x0, 0x0, 0x4 },
1790 { 0x8058, 0x40, 0x0, 0x0, 0x30 },
1791 { 0xd00, 0x8, 0x0, 0x0, 0x8 },
1792 { 0x2b30, 0x80, 0x0, 0x0, 0x38 },
1793 { 0xa808, 0x0, 0x0, 0x0, 0xf0 },
1794 { 0xa8f8, 0x8, 0x0, 0x0, 0x8 },
1795 { 0x80, 0x8, 0x0, 0x0, 0x8 },
1796 { 0xac0, 0x8, 0x0, 0x0, 0x8 },
1797 { 0x2580, 0x8, 0x0, 0x0, 0x8 },
1798 { 0x2500, 0x8, 0x0, 0x0, 0x8 },
1799 { 0x440, 0x8, 0x0, 0x0, 0x2 },
1800 { 0x1800, 0x8, 0x0, 0x0, 0x2 },
1801 { 0x1a00, 0x10, 0x8, 0x0, 0x2 },
1802 { 0x640, 0x10, 0x8, 0x0, 0x2 },
1803 { 0xd9b8, 0x38, 0x0, 0x0, 0x24 },
1804 { 0x11048, 0x10, 0x0, 0x0, 0x8 },
1805 { 0x11678, 0x38, 0x0, 0x0, 0x18 },
1806 { 0xaec0, 0x30, 0x0, 0x0, 0x10 },
1807 { 0x8700, 0x28, 0x0, 0x0, 0x18 },
1808 { 0xec00, 0x10, 0x0, 0x0, 0x10 },
1809 { 0xde38, 0x40, 0x0, 0x0, 0x30 },
1810 { 0x121a8, 0x38, 0x0, 0x0, 0x8 },
1811 { 0xf068, 0x20, 0x0, 0x0, 0x20 },
1812 { 0x2b68, 0x80, 0x0, 0x0, 0x10 },
1813 { 0x4ab8, 0x10, 0x0, 0x0, 0x10 },
1814};
1815
1816
1817#define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
1818#define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
1819#define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
1820#define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
1821#define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
1822#define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
1823#define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
1824#define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
1825#define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
1826#define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
1827#define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
1828#define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
1829#define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
1830#define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
1831#define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
1832#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
1833#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
1834#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
1835#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
1836#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
1837#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
1838#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
1839#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
1840#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
1841#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
1842#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
1843#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
1844#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
1845#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
1846#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
1847#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
1848#define CAU_REG_PI_MEMORY_RT_OFFSET 2233
1849#define CAU_REG_PI_MEMORY_RT_SIZE 4416
1850#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
1851#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
1852#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
1853#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
1854#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
1855#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
1856#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
1857#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
1858#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
1859#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
1860#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
1861#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
1862#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
1863#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
1864#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
1865#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
1866#define SRC_REG_FIRSTFREE_RT_OFFSET 6665
1867#define SRC_REG_FIRSTFREE_RT_SIZE 2
1868#define SRC_REG_LASTFREE_RT_OFFSET 6667
1869#define SRC_REG_LASTFREE_RT_SIZE 2
1870#define SRC_REG_COUNTFREE_RT_OFFSET 6669
1871#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
1872#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
1873#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
1874#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
1875#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
1876#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
1877#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6676
1878#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6677
1879#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6678
1880#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6679
1881#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6680
1882#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6681
1883#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6682
1884#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6683
1885#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6684
1886#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6685
1887#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6686
1888#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6687
1889#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6688
1890#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
1891#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
1892#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6691
1893#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6692
1894#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6693
1895#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6694
1896#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6695
1897#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6696
1898#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6697
1899#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6698
1900#define PSWRQ2_REG_WR_MBS0_RT_OFFSET 6699
1901#define PSWRQ2_REG_RD_MBS0_RT_OFFSET 6700
1902#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6701
1903#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6702
1904#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6703
1905#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
1906#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28703
1907#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28704
1908#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28705
1909#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28706
1910#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28707
1911#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28708
1912#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28709
1913#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28710
1914#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28711
1915#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28712
1916#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28713
1917#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
1918#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29129
1919#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
1920#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29641
1921#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29642
1922#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29643
1923#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29644
1924#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29645
1925#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29646
1926#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29647
1927#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29648
1928#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29649
1929#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29650
1930#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29651
1931#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29652
1932#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29653
1933#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29654
1934#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29655
1935#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29656
1936#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29657
1937#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29658
1938#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29659
1939#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29660
1940#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29661
1941#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29662
1942#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29663
1943#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29664
1944#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29665
1945#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29666
1946#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29667
1947#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29668
1948#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29669
1949#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29670
1950#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29671
1951#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29672
1952#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29673
1953#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29674
1954#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29675
1955#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29676
1956#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29677
1957#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29678
1958#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29679
1959#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29680
1960#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29681
1961#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29682
1962#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29683
1963#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29684
1964#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29685
1965#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29686
1966#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29687
1967#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29688
1968#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29689
1969#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29690
1970#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29691
1971#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29692
1972#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29693
1973#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29694
1974#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29695
1975#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29696
1976#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29697
1977#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29698
1978#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29699
1979#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29700
1980#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29701
1981#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29702
1982#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29703
1983#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29704
1984#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29705
1985#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29706
1986#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29707
1987#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29708
1988#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
1989#define QM_REG_VOQCRDLINE_RT_OFFSET 29836
1990#define QM_REG_VOQCRDLINE_RT_SIZE 20
1991#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29856
1992#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
1993#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29876
1994#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29877
1995#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29878
1996#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29879
1997#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29880
1998#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29881
1999#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29882
2000#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29883
2001#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29884
2002#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29885
2003#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29886
2004#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29887
2005#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29888
2006#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29889
2007#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29890
2008#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29891
2009#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29892
2010#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29893
2011#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29894
2012#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29895
2013#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29896
2014#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29897
2015#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29898
2016#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29899
2017#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29900
2018#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29901
2019#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29902
2020#define QM_REG_PQTX2PF_0_RT_OFFSET 29903
2021#define QM_REG_PQTX2PF_1_RT_OFFSET 29904
2022#define QM_REG_PQTX2PF_2_RT_OFFSET 29905
2023#define QM_REG_PQTX2PF_3_RT_OFFSET 29906
2024#define QM_REG_PQTX2PF_4_RT_OFFSET 29907
2025#define QM_REG_PQTX2PF_5_RT_OFFSET 29908
2026#define QM_REG_PQTX2PF_6_RT_OFFSET 29909
2027#define QM_REG_PQTX2PF_7_RT_OFFSET 29910
2028#define QM_REG_PQTX2PF_8_RT_OFFSET 29911
2029#define QM_REG_PQTX2PF_9_RT_OFFSET 29912
2030#define QM_REG_PQTX2PF_10_RT_OFFSET 29913
2031#define QM_REG_PQTX2PF_11_RT_OFFSET 29914
2032#define QM_REG_PQTX2PF_12_RT_OFFSET 29915
2033#define QM_REG_PQTX2PF_13_RT_OFFSET 29916
2034#define QM_REG_PQTX2PF_14_RT_OFFSET 29917
2035#define QM_REG_PQTX2PF_15_RT_OFFSET 29918
2036#define QM_REG_PQTX2PF_16_RT_OFFSET 29919
2037#define QM_REG_PQTX2PF_17_RT_OFFSET 29920
2038#define QM_REG_PQTX2PF_18_RT_OFFSET 29921
2039#define QM_REG_PQTX2PF_19_RT_OFFSET 29922
2040#define QM_REG_PQTX2PF_20_RT_OFFSET 29923
2041#define QM_REG_PQTX2PF_21_RT_OFFSET 29924
2042#define QM_REG_PQTX2PF_22_RT_OFFSET 29925
2043#define QM_REG_PQTX2PF_23_RT_OFFSET 29926
2044#define QM_REG_PQTX2PF_24_RT_OFFSET 29927
2045#define QM_REG_PQTX2PF_25_RT_OFFSET 29928
2046#define QM_REG_PQTX2PF_26_RT_OFFSET 29929
2047#define QM_REG_PQTX2PF_27_RT_OFFSET 29930
2048#define QM_REG_PQTX2PF_28_RT_OFFSET 29931
2049#define QM_REG_PQTX2PF_29_RT_OFFSET 29932
2050#define QM_REG_PQTX2PF_30_RT_OFFSET 29933
2051#define QM_REG_PQTX2PF_31_RT_OFFSET 29934
2052#define QM_REG_PQTX2PF_32_RT_OFFSET 29935
2053#define QM_REG_PQTX2PF_33_RT_OFFSET 29936
2054#define QM_REG_PQTX2PF_34_RT_OFFSET 29937
2055#define QM_REG_PQTX2PF_35_RT_OFFSET 29938
2056#define QM_REG_PQTX2PF_36_RT_OFFSET 29939
2057#define QM_REG_PQTX2PF_37_RT_OFFSET 29940
2058#define QM_REG_PQTX2PF_38_RT_OFFSET 29941
2059#define QM_REG_PQTX2PF_39_RT_OFFSET 29942
2060#define QM_REG_PQTX2PF_40_RT_OFFSET 29943
2061#define QM_REG_PQTX2PF_41_RT_OFFSET 29944
2062#define QM_REG_PQTX2PF_42_RT_OFFSET 29945
2063#define QM_REG_PQTX2PF_43_RT_OFFSET 29946
2064#define QM_REG_PQTX2PF_44_RT_OFFSET 29947
2065#define QM_REG_PQTX2PF_45_RT_OFFSET 29948
2066#define QM_REG_PQTX2PF_46_RT_OFFSET 29949
2067#define QM_REG_PQTX2PF_47_RT_OFFSET 29950
2068#define QM_REG_PQTX2PF_48_RT_OFFSET 29951
2069#define QM_REG_PQTX2PF_49_RT_OFFSET 29952
2070#define QM_REG_PQTX2PF_50_RT_OFFSET 29953
2071#define QM_REG_PQTX2PF_51_RT_OFFSET 29954
2072#define QM_REG_PQTX2PF_52_RT_OFFSET 29955
2073#define QM_REG_PQTX2PF_53_RT_OFFSET 29956
2074#define QM_REG_PQTX2PF_54_RT_OFFSET 29957
2075#define QM_REG_PQTX2PF_55_RT_OFFSET 29958
2076#define QM_REG_PQTX2PF_56_RT_OFFSET 29959
2077#define QM_REG_PQTX2PF_57_RT_OFFSET 29960
2078#define QM_REG_PQTX2PF_58_RT_OFFSET 29961
2079#define QM_REG_PQTX2PF_59_RT_OFFSET 29962
2080#define QM_REG_PQTX2PF_60_RT_OFFSET 29963
2081#define QM_REG_PQTX2PF_61_RT_OFFSET 29964
2082#define QM_REG_PQTX2PF_62_RT_OFFSET 29965
2083#define QM_REG_PQTX2PF_63_RT_OFFSET 29966
2084#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29967
2085#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29968
2086#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29969
2087#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29970
2088#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29971
2089#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29972
2090#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29973
2091#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29974
2092#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29975
2093#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29976
2094#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29977
2095#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29978
2096#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29979
2097#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29980
2098#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29981
2099#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29982
2100#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29983
2101#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29984
2102#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29985
2103#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29986
2104#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29987
2105#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29988
2106#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29989
2107#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29990
2108#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29991
2109#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29992
2110#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29993
2111#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29994
2112#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29995
2113#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
2114#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30251
2115#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
2116#define QM_REG_RLGLBLCRD_RT_OFFSET 30507
2117#define QM_REG_RLGLBLCRD_RT_SIZE 256
2118#define QM_REG_RLGLBLENABLE_RT_OFFSET 30763
2119#define QM_REG_RLPFPERIOD_RT_OFFSET 30764
2120#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30765
2121#define QM_REG_RLPFINCVAL_RT_OFFSET 30766
2122#define QM_REG_RLPFINCVAL_RT_SIZE 16
2123#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30782
2124#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
2125#define QM_REG_RLPFCRD_RT_OFFSET 30798
2126#define QM_REG_RLPFCRD_RT_SIZE 16
2127#define QM_REG_RLPFENABLE_RT_OFFSET 30814
2128#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30815
2129#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30816
2130#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
2131#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30832
2132#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
2133#define QM_REG_WFQPFCRD_RT_OFFSET 30848
2134#define QM_REG_WFQPFCRD_RT_SIZE 160
2135#define QM_REG_WFQPFENABLE_RT_OFFSET 31008
2136#define QM_REG_WFQVPENABLE_RT_OFFSET 31009
2137#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31010
2138#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
2139#define QM_REG_TXPQMAP_RT_OFFSET 31522
2140#define QM_REG_TXPQMAP_RT_SIZE 512
2141#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32034
2142#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
2143#define QM_REG_WFQVPCRD_RT_OFFSET 32546
2144#define QM_REG_WFQVPCRD_RT_SIZE 512
2145#define QM_REG_WFQVPMAP_RT_OFFSET 33058
2146#define QM_REG_WFQVPMAP_RT_SIZE 512
2147#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33570
2148#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
2149#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33730
2150#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33731
2151#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33732
2152#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33733
2153#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33734
2154#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33735
2155#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33736
2156#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33737
2157#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
2158#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33741
2159#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
2160#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33745
2161#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
2162#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33749
2163#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33750
2164#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
2165#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33782
2166#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
2167#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33798
2168#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
2169#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33814
2170#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
2171#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33830
2172#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
2173#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33846
2174#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33847
2175#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33848
2176#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33849
2177#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33850
2178#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33851
2179#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33852
2180#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33853
2181#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33854
2182#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33855
2183#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33856
2184#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33857
2185#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33858
2186#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33859
2187#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33860
2188#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33861
2189#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33862
2190#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33863
2191#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33864
2192#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33865
2193#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33866
2194#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33867
2195#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33868
2196#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33869
2197#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33870
2198#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33871
2199#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33872
2200#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33873
2201#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33874
2202#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33875
2203#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33876
2204#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33877
2205#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33878
2206#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33879
2207#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33880
2208#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33881
2209#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33882
2210#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33883
2211#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33884
2212#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33885
2213#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33886
2214#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33887
2215#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33888
2216#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33889
2217#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33890
2218#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33891
2219#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33892
2220#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33893
2221#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33894
2222#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33895
2223#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33896
2224#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33897
2225#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33898
2226#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33899
2227#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33900
2228#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33901
2229#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33902
2230#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33903
2231#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33904
2232#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33905
2233#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33906
2234#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33907
2235#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33908
2236#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33909
2237#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33910
2238#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33911
2239#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33912
2240#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33913
2241#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33914
2242#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33915
2243#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33916
2244#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33917
2245#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33918
2246#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33919
2247#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33920
2248#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33921
2249#define XCM_REG_CON_PHY_Q3_RT_OFFSET 33922
2250
2251#define RUNTIME_ARRAY_SIZE 33923
2252
2253
2254struct tstorm_eth_conn_st_ctx {
2255 __le32 reserved[4];
2256};
2257
2258
2259struct pstorm_eth_conn_st_ctx {
2260 __le32 reserved[8];
2261};
2262
2263
2264struct xstorm_eth_conn_st_ctx {
2265 __le32 reserved[60];
2266};
2267
2268struct xstorm_eth_conn_ag_ctx {
2269 u8 reserved0 ;
2270 u8 eth_state ;
2271 u8 flags0;
2272#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1
2273#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0
2274#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1
2275#define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1
2276#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1
2277#define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2
2278#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1
2279#define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3
2280#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1
2281#define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4
2282#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1
2283#define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5
2284#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1
2285#define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6
2286#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1
2287#define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7
2288 u8 flags1;
2289#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1
2290#define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0
2291#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1
2292#define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1
2293#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1
2294#define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2
2295#define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1
2296#define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3
2297#define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1
2298#define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4
2299#define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1
2300#define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5
2301#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1
2302#define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
2303#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1
2304#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7
2305 u8 flags2;
2306#define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
2307#define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0
2308#define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
2309#define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2
2310#define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
2311#define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4
2312#define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
2313#define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6
2314 u8 flags3;
2315#define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
2316#define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0
2317#define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
2318#define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2
2319#define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
2320#define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4
2321#define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
2322#define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6
2323 u8 flags4;
2324#define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
2325#define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0
2326#define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
2327#define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2
2328#define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
2329#define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4
2330#define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3
2331#define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6
2332 u8 flags5;
2333#define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3
2334#define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0
2335#define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3
2336#define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2
2337#define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3
2338#define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4
2339#define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3
2340#define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6
2341 u8 flags6;
2342#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3
2343#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0
2344#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3
2345#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2
2346#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3
2347#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4
2348#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3
2349#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6
2350 u8 flags7;
2351#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3
2352#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0
2353#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3
2354#define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2
2355#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3
2356#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4
2357#define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
2358#define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6
2359#define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
2360#define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7
2361 u8 flags8;
2362#define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
2363#define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0
2364#define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
2365#define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1
2366#define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
2367#define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2
2368#define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
2369#define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3
2370#define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
2371#define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4
2372#define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
2373#define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5
2374#define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
2375#define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6
2376#define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
2377#define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7
2378 u8 flags9;
2379#define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
2380#define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0
2381#define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1
2382#define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1
2383#define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1
2384#define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2
2385#define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1
2386#define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3
2387#define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1
2388#define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4
2389#define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1
2390#define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5
2391#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1
2392#define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6
2393#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1
2394#define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7
2395 u8 flags10;
2396#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1
2397#define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0
2398#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1
2399#define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1
2400#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1
2401#define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2
2402#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1
2403#define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3
2404#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1
2405#define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4
2406#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1
2407#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5
2408#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1
2409#define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6
2410#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1
2411#define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7
2412 u8 flags11;
2413#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1
2414#define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0
2415#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1
2416#define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1
2417#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1
2418#define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
2419#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
2420#define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3
2421#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
2422#define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4
2423#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
2424#define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5
2425#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1
2426#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6
2427#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1
2428#define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7
2429 u8 flags12;
2430#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1
2431#define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0
2432#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1
2433#define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1
2434#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1
2435#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2
2436#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1
2437#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3
2438#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1
2439#define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4
2440#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1
2441#define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5
2442#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1
2443#define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6
2444#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1
2445#define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7
2446 u8 flags13;
2447#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1
2448#define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0
2449#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1
2450#define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1
2451#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1
2452#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2
2453#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1
2454#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3
2455#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1
2456#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4
2457#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1
2458#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5
2459#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1
2460#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6
2461#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1
2462#define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7
2463 u8 flags14;
2464#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1
2465#define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0
2466#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1
2467#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1
2468#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1
2469#define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2
2470#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1
2471#define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3
2472#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1
2473#define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4
2474#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1
2475#define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
2476#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3
2477#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
2478 u8 edpm_event_id ;
2479 __le16 physical_q0 ;
2480 __le16 word1 ;
2481 __le16 edpm_num_bds ;
2482 __le16 tx_bd_cons ;
2483 __le16 tx_bd_prod ;
2484 __le16 go_to_bd_cons ;
2485 __le16 conn_dpi ;
2486 u8 byte3 ;
2487 u8 byte4 ;
2488 u8 byte5 ;
2489 u8 byte6 ;
2490 __le32 reg0 ;
2491 __le32 reg1 ;
2492 __le32 reg2 ;
2493 __le32 reg3 ;
2494 __le32 reg4 ;
2495 __le32 reg5 ;
2496 __le32 reg6 ;
2497 __le16 word7 ;
2498 __le16 word8 ;
2499 __le16 word9 ;
2500 __le16 word10 ;
2501 __le32 reg7 ;
2502 __le32 reg8 ;
2503 __le32 reg9 ;
2504 u8 byte7 ;
2505 u8 byte8 ;
2506 u8 byte9 ;
2507 u8 byte10 ;
2508 u8 byte11 ;
2509 u8 byte12 ;
2510 u8 byte13 ;
2511 u8 byte14 ;
2512 u8 byte15 ;
2513 u8 byte16 ;
2514 __le16 word11 ;
2515 __le32 reg10 ;
2516 __le32 reg11 ;
2517 __le32 reg12 ;
2518 __le32 reg13 ;
2519 __le32 reg14 ;
2520 __le32 reg15 ;
2521 __le32 reg16 ;
2522 __le32 reg17 ;
2523 __le32 reg18 ;
2524 __le32 reg19 ;
2525 __le16 word12 ;
2526 __le16 word13 ;
2527 __le16 word14 ;
2528 __le16 word15 ;
2529};
2530
2531
2532struct ystorm_eth_conn_st_ctx {
2533 __le32 reserved[8];
2534};
2535
2536struct ystorm_eth_conn_ag_ctx {
2537 u8 byte0 ;
2538 u8 byte1 ;
2539 u8 flags0;
2540#define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
2541#define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2542#define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
2543#define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2544#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
2545#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2
2546#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3
2547#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4
2548#define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
2549#define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
2550 u8 flags1;
2551#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
2552#define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0
2553#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1
2554#define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1
2555#define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
2556#define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2557#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
2558#define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3
2559#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
2560#define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4
2561#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
2562#define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5
2563#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
2564#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
2565#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
2566#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
2567 u8 byte2 ;
2568 u8 byte3 ;
2569 __le16 word0 ;
2570 __le32 terminate_spqe ;
2571 __le32 reg1 ;
2572 __le16 tx_bd_cons_upd ;
2573 __le16 word2 ;
2574 __le16 word3 ;
2575 __le16 word4 ;
2576 __le32 reg2 ;
2577 __le32 reg3 ;
2578};
2579
2580struct tstorm_eth_conn_ag_ctx {
2581 u8 byte0 ;
2582 u8 byte1 ;
2583 u8 flags0;
2584#define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
2585#define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2586#define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
2587#define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2588#define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1
2589#define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2
2590#define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1
2591#define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3
2592#define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1
2593#define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4
2594#define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1
2595#define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5
2596#define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3
2597#define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6
2598 u8 flags1;
2599#define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3
2600#define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0
2601#define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
2602#define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2
2603#define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
2604#define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4
2605#define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3
2606#define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6
2607 u8 flags2;
2608#define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3
2609#define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0
2610#define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3
2611#define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2
2612#define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3
2613#define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4
2614#define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3
2615#define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6
2616 u8 flags3;
2617#define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3
2618#define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0
2619#define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3
2620#define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2
2621#define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1
2622#define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4
2623#define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1
2624#define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5
2625#define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
2626#define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6
2627#define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
2628#define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7
2629 u8 flags4;
2630#define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1
2631#define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0
2632#define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1
2633#define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1
2634#define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1
2635#define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2
2636#define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1
2637#define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3
2638#define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1
2639#define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4
2640#define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1
2641#define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5
2642#define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1
2643#define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6
2644#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
2645#define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
2646 u8 flags5;
2647#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
2648#define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2649#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
2650#define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2651#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
2652#define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2653#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
2654#define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2655#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
2656#define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2657#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1
2658#define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5
2659#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
2660#define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2661#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
2662#define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
2663 __le32 reg0 ;
2664 __le32 reg1 ;
2665 __le32 reg2 ;
2666 __le32 reg3 ;
2667 __le32 reg4 ;
2668 __le32 reg5 ;
2669 __le32 reg6 ;
2670 __le32 reg7 ;
2671 __le32 reg8 ;
2672 u8 byte2 ;
2673 u8 byte3 ;
2674 __le16 rx_bd_cons ;
2675 u8 byte4 ;
2676 u8 byte5 ;
2677 __le16 rx_bd_prod ;
2678 __le16 word2 ;
2679 __le16 word3 ;
2680 __le32 reg9 ;
2681 __le32 reg10 ;
2682};
2683
2684struct ustorm_eth_conn_ag_ctx {
2685 u8 byte0 ;
2686 u8 byte1 ;
2687 u8 flags0;
2688#define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
2689#define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
2690#define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1
2691#define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1
2692#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3
2693#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2
2694#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3
2695#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4
2696#define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3
2697#define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6
2698 u8 flags1;
2699#define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3
2700#define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0
2701#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3
2702#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2
2703#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3
2704#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4
2705#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3
2706#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6
2707 u8 flags2;
2708#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1
2709#define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0
2710#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1
2711#define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1
2712#define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1
2713#define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2
2714#define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1
2715#define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3
2716#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1
2717#define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4
2718#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1
2719#define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5
2720#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1
2721#define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6
2722#define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1
2723#define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7
2724 u8 flags3;
2725#define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1
2726#define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0
2727#define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1
2728#define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1
2729#define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1
2730#define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2
2731#define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
2732#define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3
2733#define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1
2734#define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4
2735#define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1
2736#define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5
2737#define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1
2738#define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6
2739#define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1
2740#define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7
2741 u8 byte2 ;
2742 u8 byte3 ;
2743 __le16 word0 ;
2744 __le16 tx_bd_cons ;
2745 __le32 reg0 ;
2746 __le32 reg1 ;
2747 __le32 reg2 ;
2748 __le32 tx_int_coallecing_timeset ;
2749 __le16 tx_drv_bd_cons ;
2750 __le16 rx_drv_cqe_cons ;
2751};
2752
2753
2754struct ustorm_eth_conn_st_ctx {
2755 __le32 reserved[40];
2756};
2757
2758
2759struct mstorm_eth_conn_st_ctx {
2760 __le32 reserved[8];
2761};
2762
2763
2764struct eth_conn_context {
2765 struct tstorm_eth_conn_st_ctx tstorm_st_context;
2766 struct regpair tstorm_st_padding[2];
2767 struct pstorm_eth_conn_st_ctx pstorm_st_context;
2768 struct xstorm_eth_conn_st_ctx xstorm_st_context;
2769 struct xstorm_eth_conn_ag_ctx xstorm_ag_context;
2770 struct ystorm_eth_conn_st_ctx ystorm_st_context;
2771 struct ystorm_eth_conn_ag_ctx ystorm_ag_context;
2772 struct tstorm_eth_conn_ag_ctx tstorm_ag_context;
2773 struct ustorm_eth_conn_ag_ctx ustorm_ag_context;
2774 struct ustorm_eth_conn_st_ctx ustorm_st_context;
2775 struct mstorm_eth_conn_st_ctx mstorm_st_context;
2776};
2777
2778enum eth_filter_action {
2779 ETH_FILTER_ACTION_REMOVE,
2780 ETH_FILTER_ACTION_ADD,
2781 ETH_FILTER_ACTION_REMOVE_ALL,
2782 MAX_ETH_FILTER_ACTION
2783};
2784
2785struct eth_filter_cmd {
2786 u8 type ;
2787 u8 vport_id ;
2788 u8 action ;
2789 u8 reserved0;
2790 __le32 vni;
2791 __le16 mac_lsb;
2792 __le16 mac_mid;
2793 __le16 mac_msb;
2794 __le16 vlan_id;
2795};
2796
2797struct eth_filter_cmd_header {
2798 u8 rx;
2799 u8 tx;
2800 u8 cmd_cnt;
2801 u8 assert_on_error;
2802 u8 reserved1[4];
2803};
2804
2805enum eth_filter_type {
2806 ETH_FILTER_TYPE_MAC,
2807 ETH_FILTER_TYPE_VLAN,
2808 ETH_FILTER_TYPE_PAIR,
2809 ETH_FILTER_TYPE_INNER_MAC,
2810 ETH_FILTER_TYPE_INNER_VLAN,
2811 ETH_FILTER_TYPE_INNER_PAIR,
2812 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
2813 ETH_FILTER_TYPE_MAC_VNI_PAIR,
2814 ETH_FILTER_TYPE_VNI,
2815 MAX_ETH_FILTER_TYPE
2816};
2817
2818enum eth_ramrod_cmd_id {
2819 ETH_RAMROD_UNUSED,
2820 ETH_RAMROD_VPORT_START ,
2821 ETH_RAMROD_VPORT_UPDATE ,
2822 ETH_RAMROD_VPORT_STOP ,
2823 ETH_RAMROD_RX_QUEUE_START ,
2824 ETH_RAMROD_RX_QUEUE_STOP ,
2825 ETH_RAMROD_TX_QUEUE_START ,
2826 ETH_RAMROD_TX_QUEUE_STOP ,
2827 ETH_RAMROD_FILTERS_UPDATE ,
2828 ETH_RAMROD_RX_QUEUE_UPDATE ,
2829 ETH_RAMROD_RESERVED,
2830 ETH_RAMROD_RESERVED2,
2831 ETH_RAMROD_RESERVED3,
2832 ETH_RAMROD_RESERVED4,
2833 ETH_RAMROD_RESERVED5,
2834 ETH_RAMROD_RESERVED6,
2835 ETH_RAMROD_RESERVED7,
2836 ETH_RAMROD_RESERVED8,
2837 MAX_ETH_RAMROD_CMD_ID
2838};
2839
2840enum eth_tx_err {
2841 ETH_TX_ERR_DROP ,
2842 ETH_TX_ERR_ASSERT_MALICIOUS,
2843 MAX_ETH_TX_ERR
2844};
2845
2846struct eth_tx_err_vals {
2847 __le16 values;
2848#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1
2849#define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0
2850#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1
2851#define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1
2852#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1
2853#define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2
2854#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1
2855#define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3
2856#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1
2857#define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4
2858#define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1
2859#define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5
2860#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1
2861#define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6
2862#define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF
2863#define ETH_TX_ERR_VALS_RESERVED_SHIFT 7
2864};
2865
2866struct eth_vport_rss_config {
2867 __le16 capabilities;
2868#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1
2869#define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0
2870#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1
2871#define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1
2872#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1
2873#define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2
2874#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1
2875#define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3
2876#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1
2877#define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4
2878#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1
2879#define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5
2880#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1
2881#define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6
2882#define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF
2883#define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7
2884 u8 rss_id;
2885 u8 rss_mode;
2886 u8 update_rss_key;
2887 u8 update_rss_ind_table;
2888 u8 update_rss_capabilities;
2889 u8 tbl_size;
2890 __le32 reserved2[2];
2891 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
2892 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
2893 __le32 reserved3[2];
2894};
2895
2896enum eth_vport_rss_mode {
2897 ETH_VPORT_RSS_MODE_DISABLED,
2898 ETH_VPORT_RSS_MODE_REGULAR,
2899 MAX_ETH_VPORT_RSS_MODE
2900};
2901
2902struct eth_vport_rx_mode {
2903 __le16 state;
2904#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1
2905#define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0
2906#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2907#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2908#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1
2909#define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2
2910#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1
2911#define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3
2912#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2913#define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4
2914#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2915#define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5
2916#define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF
2917#define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6
2918 __le16 reserved2[3];
2919};
2920
2921struct eth_vport_tpa_param {
2922 u8 tpa_ipv4_en_flg;
2923 u8 tpa_ipv6_en_flg;
2924 u8 tpa_ipv4_tunn_en_flg;
2925 u8 tpa_ipv6_tunn_en_flg;
2926 u8 tpa_pkt_split_flg;
2927 u8 tpa_hdr_data_split_flg;
2928 u8 tpa_gro_consistent_flg;
2929 u8 tpa_max_aggs_num;
2930 u16 tpa_max_size;
2931 u16 tpa_min_size_to_start;
2932 u16 tpa_min_size_to_cont;
2933 u8 max_buff_num;
2934 u8 reserved;
2935};
2936
2937struct eth_vport_tx_mode {
2938 __le16 state;
2939#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1
2940#define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0
2941#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1
2942#define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1
2943#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1
2944#define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2
2945#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1
2946#define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3
2947#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1
2948#define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4
2949#define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF
2950#define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5
2951 __le16 reserved2[3];
2952};
2953
2954struct rx_queue_start_ramrod_data {
2955 __le16 rx_queue_id;
2956 __le16 num_of_pbl_pages;
2957 __le16 bd_max_bytes;
2958 __le16 sb_id;
2959 u8 sb_index;
2960 u8 vport_id;
2961 u8 default_rss_queue_flg;
2962 u8 complete_cqe_flg;
2963 u8 complete_event_flg;
2964 u8 stats_counter_id;
2965 u8 pin_context;
2966 u8 pxp_tph_valid_bd;
2967 u8 pxp_tph_valid_pkt;
2968 u8 pxp_st_hint;
2969 __le16 pxp_st_index;
2970 u8 pmd_mode;
2971 u8 notify_en;
2972 u8 toggle_val;
2973 u8 reserved[7];
2974 __le16 reserved1;
2975 struct regpair cqe_pbl_addr;
2976 struct regpair bd_base;
2977 struct regpair reserved2;
2978};
2979
2980struct rx_queue_stop_ramrod_data {
2981 __le16 rx_queue_id;
2982 u8 complete_cqe_flg;
2983 u8 complete_event_flg;
2984 u8 vport_id;
2985 u8 reserved[3];
2986};
2987
2988struct rx_queue_update_ramrod_data {
2989 __le16 rx_queue_id;
2990 u8 complete_cqe_flg;
2991 u8 complete_event_flg;
2992 u8 vport_id;
2993 u8 reserved[4];
2994 u8 reserved1;
2995 u8 reserved2;
2996 u8 reserved3;
2997 __le16 reserved4;
2998 __le16 reserved5;
2999 struct regpair reserved6;
3000};
3001
3002struct tx_queue_start_ramrod_data {
3003 __le16 sb_id;
3004 u8 sb_index;
3005 u8 vport_id;
3006 u8 reserved0;
3007 u8 stats_counter_id;
3008 __le16 qm_pq_id;
3009 u8 flags;
3010#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1
3011#define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0
3012#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1
3013#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1
3014#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1
3015#define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2
3016#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1
3017#define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3
3018#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1
3019#define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4
3020#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1
3021#define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5
3022#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3
3023#define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6
3024 u8 pxp_st_hint;
3025 u8 pxp_tph_valid_bd;
3026 u8 pxp_tph_valid_pkt;
3027 __le16 pxp_st_index;
3028 __le16 comp_agg_size;
3029 __le16 queue_zone_id;
3030 __le16 test_dup_count;
3031 __le16 pbl_size;
3032 __le16 tx_queue_id;
3033 struct regpair pbl_base_addr;
3034 struct regpair bd_cons_address;
3035};
3036
3037struct tx_queue_stop_ramrod_data {
3038 __le16 reserved[4];
3039};
3040
3041struct vport_filter_update_ramrod_data {
3042 struct eth_filter_cmd_header filter_cmd_hdr;
3043 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
3044};
3045
3046struct vport_start_ramrod_data {
3047 u8 vport_id;
3048 u8 sw_fid;
3049 __le16 mtu;
3050 u8 drop_ttl0_en;
3051 u8 inner_vlan_removal_en;
3052 struct eth_vport_rx_mode rx_mode;
3053 struct eth_vport_tx_mode tx_mode;
3054 struct eth_vport_tpa_param tpa_param;
3055 __le16 default_vlan;
3056 u8 tx_switching_en;
3057 u8 anti_spoofing_en;
3058 u8 default_vlan_en;
3059 u8 handle_ptp_pkts;
3060 u8 silent_vlan_removal_en;
3061 u8 untagged;
3062 struct eth_tx_err_vals tx_err_behav;
3063 u8 zero_placement_offset;
3064 u8 reserved[7];
3065};
3066
3067struct vport_stop_ramrod_data {
3068 u8 vport_id;
3069 u8 reserved[7];
3070};
3071
3072struct vport_update_ramrod_data_cmn {
3073 u8 vport_id;
3074 u8 update_rx_active_flg;
3075 u8 rx_active_flg;
3076 u8 update_tx_active_flg;
3077 u8 tx_active_flg;
3078 u8 update_rx_mode_flg;
3079 u8 update_tx_mode_flg;
3080 u8 update_approx_mcast_flg;
3081 u8 update_rss_flg;
3082 u8 update_inner_vlan_removal_en_flg;
3083 u8 inner_vlan_removal_en;
3084 u8 update_tpa_param_flg;
3085 u8 update_tpa_en_flg;
3086 u8 update_tx_switching_en_flg;
3087 u8 tx_switching_en;
3088 u8 update_anti_spoofing_en_flg;
3089 u8 anti_spoofing_en;
3090 u8 update_handle_ptp_pkts;
3091 u8 handle_ptp_pkts;
3092 u8 update_default_vlan_en_flg;
3093 u8 default_vlan_en;
3094 u8 update_default_vlan_flg;
3095 __le16 default_vlan;
3096 u8 update_accept_any_vlan_flg;
3097 u8 accept_any_vlan;
3098 u8 silent_vlan_removal_en;
3099 u8 update_mtu_flg;
3100 __le16 mtu;
3101 u8 reserved[2];
3102};
3103
3104struct vport_update_ramrod_mcast {
3105 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
3106};
3107
3108struct vport_update_ramrod_data {
3109 struct vport_update_ramrod_data_cmn common;
3110 struct eth_vport_rx_mode rx_mode;
3111 struct eth_vport_tx_mode tx_mode;
3112 struct eth_vport_tpa_param tpa_param;
3113 struct vport_update_ramrod_mcast approx_mcast;
3114 struct eth_vport_rss_config rss_config;
3115};
3116
3117#define VF_MAX_STATIC 192
3118
3119#define MCP_GLOB_PATH_MAX 2
3120#define MCP_PORT_MAX 2
3121#define MCP_GLOB_PORT_MAX 4
3122#define MCP_GLOB_FUNC_MAX 16
3123
3124typedef u32 offsize_t;
3125
3126#define OFFSIZE_OFFSET_SHIFT 0
3127#define OFFSIZE_OFFSET_MASK 0x0000ffff
3128
3129#define OFFSIZE_SIZE_SHIFT 16
3130#define OFFSIZE_SIZE_MASK 0xffff0000
3131
3132
3133#define SECTION_OFFSET(_offsize) ((((_offsize & \
3134 OFFSIZE_OFFSET_MASK) >> \
3135 OFFSIZE_OFFSET_SHIFT) << 2))
3136
3137
3138#define QED_SECTION_SIZE(_offsize) (((_offsize & \
3139 OFFSIZE_SIZE_MASK) >> \
3140 OFFSIZE_SIZE_SHIFT) << 2)
3141
3142
3143
3144
3145#define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \
3146 SECTION_OFFSET(_offsize) + \
3147 (QED_SECTION_SIZE(_offsize) * idx))
3148
3149
3150
3151
3152#define SECTION_OFFSIZE_ADDR(_pub_base, _section) (_pub_base + \
3153 offsetof(struct \
3154 mcp_public_data, \
3155 sections[_section]))
3156
3157struct pmm_phy_cfg {
3158 u32 speed;
3159#define PMM_SPEED_AUTONEG 0
3160
3161 u32 pause;
3162#define PMM_PAUSE_NONE 0x0
3163#define PMM_PAUSE_AUTONEG 0x1
3164#define PMM_PAUSE_RX 0x2
3165#define PMM_PAUSE_TX 0x4
3166
3167 u32 adv_speed;
3168 u32 loopback_mode;
3169#define PMM_LOOPBACK_NONE 0
3170#define PMM_LOOPBACK_INT_PHY 1
3171#define PMM_LOOPBACK_EXT_PHY 2
3172#define PMM_LOOPBACK_EXT 3
3173#define PMM_LOOPBACK_MAC 4
3174
3175
3176 u32 feature_config_flags;
3177};
3178
3179struct port_mf_cfg {
3180 u32 dynamic_cfg;
3181#define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff
3182#define PORT_MF_CFG_OV_TAG_SHIFT 0
3183#define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK
3184
3185 u32 reserved[1];
3186};
3187
3188
3189
3190
3191struct pmm_stats {
3192 u64 r64;
3193 u64 r127;
3194 u64 r255;
3195 u64 r511;
3196 u64 r1023;
3197 u64 r1518;
3198 u64 r1522;
3199 u64 r2047;
3200 u64 r4095;
3201 u64 r9216;
3202 u64 r16383;
3203 u64 rfcs;
3204 u64 rxcf;
3205 u64 rxpf;
3206 u64 rxpp;
3207 u64 raln;
3208 u64 rfcr;
3209 u64 rovr;
3210 u64 rjbr;
3211 u64 rund;
3212 u64 rfrg;
3213 u64 t64;
3214 u64 t127;
3215 u64 t255;
3216 u64 t511;
3217 u64 t1023;
3218 u64 t1518;
3219 u64 t2047;
3220 u64 t4095;
3221 u64 t9216;
3222 u64 t16383;
3223 u64 txpf;
3224 u64 txpp;
3225 u64 tlpiec;
3226 u64 tncl;
3227 u64 rbyte;
3228 u64 rxuca;
3229 u64 rxmca;
3230 u64 rxbca;
3231 u64 rxpok;
3232 u64 tbyte;
3233 u64 txuca;
3234 u64 txmca;
3235 u64 txbca;
3236 u64 txcf;
3237};
3238
3239struct brb_stats {
3240 u64 brb_truncate[8];
3241 u64 brb_discard[8];
3242};
3243
3244struct port_stats {
3245 struct brb_stats brb;
3246 struct pmm_stats pmm;
3247};
3248
3249#define CMT_TEAM0 0
3250#define CMT_TEAM1 1
3251#define CMT_TEAM_MAX 2
3252
3253struct couple_mode_teaming {
3254 u8 port_cmt[MCP_GLOB_PORT_MAX];
3255#define PORT_CMT_IN_TEAM BIT(0)
3256
3257#define PORT_CMT_PORT_ROLE BIT(1)
3258#define PORT_CMT_PORT_INACTIVE (0 << 1)
3259#define PORT_CMT_PORT_ACTIVE BIT(1)
3260
3261#define PORT_CMT_TEAM_MASK BIT(2)
3262#define PORT_CMT_TEAM0 (0 << 2)
3263#define PORT_CMT_TEAM1 BIT(2)
3264};
3265
3266
3267
3268
3269#define LLDP_CHASSIS_ID_STAT_LEN 4
3270#define LLDP_PORT_ID_STAT_LEN 4
3271#define DCBX_MAX_APP_PROTOCOL 32
3272#define MAX_SYSTEM_LLDP_TLV_DATA 32
3273
3274enum lldp_agent_e {
3275 LLDP_NEAREST_BRIDGE = 0,
3276 LLDP_NEAREST_NON_TPMR_BRIDGE,
3277 LLDP_NEAREST_CUSTOMER_BRIDGE,
3278 LLDP_MAX_LLDP_AGENTS
3279};
3280
3281struct lldp_config_params_s {
3282 u32 config;
3283#define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff
3284#define LLDP_CONFIG_TX_INTERVAL_SHIFT 0
3285#define LLDP_CONFIG_HOLD_MASK 0x00000f00
3286#define LLDP_CONFIG_HOLD_SHIFT 8
3287#define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000
3288#define LLDP_CONFIG_MAX_CREDIT_SHIFT 12
3289#define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000
3290#define LLDP_CONFIG_ENABLE_RX_SHIFT 30
3291#define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000
3292#define LLDP_CONFIG_ENABLE_TX_SHIFT 31
3293 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3294 u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
3295};
3296
3297struct lldp_status_params_s {
3298 u32 prefix_seq_num;
3299 u32 status;
3300
3301
3302 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
3303
3304
3305 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
3306 u32 suffix_seq_num;
3307};
3308
3309struct dcbx_ets_feature {
3310 u32 flags;
3311#define DCBX_ETS_ENABLED_MASK 0x00000001
3312#define DCBX_ETS_ENABLED_SHIFT 0
3313#define DCBX_ETS_WILLING_MASK 0x00000002
3314#define DCBX_ETS_WILLING_SHIFT 1
3315#define DCBX_ETS_ERROR_MASK 0x00000004
3316#define DCBX_ETS_ERROR_SHIFT 2
3317#define DCBX_ETS_CBS_MASK 0x00000008
3318#define DCBX_ETS_CBS_SHIFT 3
3319#define DCBX_ETS_MAX_TCS_MASK 0x000000f0
3320#define DCBX_ETS_MAX_TCS_SHIFT 4
3321 u32 pri_tc_tbl[1];
3322#define DCBX_ISCSI_OOO_TC 4
3323#define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
3324 u32 tc_bw_tbl[2];
3325 u32 tc_tsa_tbl[2];
3326#define DCBX_ETS_TSA_STRICT 0
3327#define DCBX_ETS_TSA_CBS 1
3328#define DCBX_ETS_TSA_ETS 2
3329};
3330
3331struct dcbx_app_priority_entry {
3332 u32 entry;
3333#define DCBX_APP_PRI_MAP_MASK 0x000000ff
3334#define DCBX_APP_PRI_MAP_SHIFT 0
3335#define DCBX_APP_PRI_0 0x01
3336#define DCBX_APP_PRI_1 0x02
3337#define DCBX_APP_PRI_2 0x04
3338#define DCBX_APP_PRI_3 0x08
3339#define DCBX_APP_PRI_4 0x10
3340#define DCBX_APP_PRI_5 0x20
3341#define DCBX_APP_PRI_6 0x40
3342#define DCBX_APP_PRI_7 0x80
3343#define DCBX_APP_SF_MASK 0x00000300
3344#define DCBX_APP_SF_SHIFT 8
3345#define DCBX_APP_SF_ETHTYPE 0
3346#define DCBX_APP_SF_PORT 1
3347#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
3348#define DCBX_APP_PROTOCOL_ID_SHIFT 16
3349};
3350
3351
3352struct dcbx_app_priority_feature {
3353 u32 flags;
3354#define DCBX_APP_ENABLED_MASK 0x00000001
3355#define DCBX_APP_ENABLED_SHIFT 0
3356#define DCBX_APP_WILLING_MASK 0x00000002
3357#define DCBX_APP_WILLING_SHIFT 1
3358#define DCBX_APP_ERROR_MASK 0x00000004
3359#define DCBX_APP_ERROR_SHIFT 2
3360
3361
3362
3363
3364#define DCBX_APP_MAX_TCS_MASK 0x0000f000
3365#define DCBX_APP_MAX_TCS_SHIFT 12
3366#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
3367#define DCBX_APP_NUM_ENTRIES_SHIFT 16
3368 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
3369};
3370
3371
3372struct dcbx_features {
3373
3374 struct dcbx_ets_feature ets;
3375
3376
3377 u32 pfc;
3378#define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff
3379#define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0
3380#define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01
3381#define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02
3382#define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04
3383#define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08
3384#define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10
3385#define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20
3386#define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40
3387#define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80
3388
3389#define DCBX_PFC_FLAGS_MASK 0x0000ff00
3390#define DCBX_PFC_FLAGS_SHIFT 8
3391#define DCBX_PFC_CAPS_MASK 0x00000f00
3392#define DCBX_PFC_CAPS_SHIFT 8
3393#define DCBX_PFC_MBC_MASK 0x00004000
3394#define DCBX_PFC_MBC_SHIFT 14
3395#define DCBX_PFC_WILLING_MASK 0x00008000
3396#define DCBX_PFC_WILLING_SHIFT 15
3397#define DCBX_PFC_ENABLED_MASK 0x00010000
3398#define DCBX_PFC_ENABLED_SHIFT 16
3399#define DCBX_PFC_ERROR_MASK 0x00020000
3400#define DCBX_PFC_ERROR_SHIFT 17
3401
3402
3403 struct dcbx_app_priority_feature app;
3404};
3405
3406struct dcbx_local_params {
3407 u32 config;
3408#define DCBX_CONFIG_VERSION_MASK 0x00000003
3409#define DCBX_CONFIG_VERSION_SHIFT 0
3410#define DCBX_CONFIG_VERSION_DISABLED 0
3411#define DCBX_CONFIG_VERSION_IEEE 1
3412#define DCBX_CONFIG_VERSION_CEE 2
3413
3414 u32 flags;
3415 struct dcbx_features features;
3416};
3417
3418struct dcbx_mib {
3419 u32 prefix_seq_num;
3420 u32 flags;
3421 struct dcbx_features features;
3422 u32 suffix_seq_num;
3423};
3424
3425struct lldp_system_tlvs_buffer_s {
3426 u16 valid;
3427 u16 length;
3428 u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
3429};
3430
3431
3432
3433
3434
3435
3436struct public_global {
3437 u32 max_path;
3438#define MAX_PATH_BIG_BEAR 2
3439#define MAX_PATH_K2 1
3440 u32 max_ports;
3441#define MODE_1P 1
3442#define MODE_2P 2
3443#define MODE_3P 3
3444#define MODE_4P 4
3445 u32 debug_mb_offset;
3446 u32 phymod_dbg_mb_offset;
3447 struct couple_mode_teaming cmt;
3448 s32 internal_temperature;
3449 u32 mfw_ver;
3450 u32 running_bundle_id;
3451};
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472
3473
3474struct fw_flr_mb {
3475 u32 aggint;
3476 u32 opgen_addr;
3477 u32 accum_ack;
3478#define ACCUM_ACK_PF_BASE 0
3479#define ACCUM_ACK_PF_SHIFT 0
3480
3481#define ACCUM_ACK_VF_BASE 8
3482#define ACCUM_ACK_VF_SHIFT 3
3483
3484#define ACCUM_ACK_IOV_DIS_BASE 256
3485#define ACCUM_ACK_IOV_DIS_SHIFT 8
3486};
3487
3488struct public_path {
3489 struct fw_flr_mb flr_mb;
3490 u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
3491
3492 u32 process_kill;
3493#define PROCESS_KILL_COUNTER_MASK 0x0000ffff
3494#define PROCESS_KILL_COUNTER_SHIFT 0
3495#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
3496#define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16
3497#define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
3498};
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510struct public_port {
3511 u32 validity_map;
3512
3513
3514#define MCP_VALIDITY_PCI_CFG 0x00100000
3515#define MCP_VALIDITY_MB 0x00200000
3516#define MCP_VALIDITY_DEV_INFO 0x00400000
3517#define MCP_VALIDITY_RESERVED 0x00000007
3518
3519
3520#define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
3521#define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
3522#define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
3523#define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
3524
3525
3526#define MCP_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
3527#define MCP_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
3528#define MCP_VALIDITY_ACTIVE_MFW_NCSI 0x00000040
3529#define MCP_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
3530
3531 u32 link_status;
3532#define LINK_STATUS_LINK_UP \
3533 0x00000001
3534#define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e
3535#define LINK_STATUS_SPEED_AND_DUPLEX_1000THD BIT(1)
3536#define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1)
3537#define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1)
3538#define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1)
3539#define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1)
3540#define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1)
3541#define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1)
3542#define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1)
3543
3544#define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
3545
3546#define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
3547#define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
3548
3549#define LINK_STATUS_PFC_ENABLED \
3550 0x00000100
3551#define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
3552#define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
3553#define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800
3554#define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000
3555#define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000
3556#define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000
3557#define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000
3558#define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000
3559
3560#define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
3561#define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
3562#define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE BIT(18)
3563#define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
3564#define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
3565
3566#define LINK_STATUS_SFP_TX_FAULT \
3567 0x00100000
3568#define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000
3569#define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000
3570
3571 u32 link_status1;
3572 u32 ext_phy_fw_version;
3573 u32 drv_phy_cfg_addr;
3574
3575 u32 port_stx;
3576
3577 u32 stat_nig_timer;
3578
3579 struct port_mf_cfg port_mf_config;
3580 struct port_stats stats;
3581
3582 u32 media_type;
3583#define MEDIA_UNSPECIFIED 0x0
3584#define MEDIA_SFPP_10G_FIBER 0x1
3585#define MEDIA_XFP_FIBER 0x2
3586#define MEDIA_DA_TWINAX 0x3
3587#define MEDIA_BASE_T 0x4
3588#define MEDIA_SFP_1G_FIBER 0x5
3589#define MEDIA_KR 0xf0
3590#define MEDIA_NOT_PRESENT 0xff
3591
3592 u32 lfa_status;
3593#define LFA_LINK_FLAP_REASON_OFFSET 0
3594#define LFA_LINK_FLAP_REASON_MASK 0x000000ff
3595#define LFA_NO_REASON (0 << 0)
3596#define LFA_LINK_DOWN BIT(0)
3597#define LFA_FORCE_INIT BIT(1)
3598#define LFA_LOOPBACK_MISMATCH BIT(2)
3599#define LFA_SPEED_MISMATCH BIT(3)
3600#define LFA_FLOW_CTRL_MISMATCH BIT(4)
3601#define LFA_ADV_SPEED_MISMATCH BIT(5)
3602#define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
3603#define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
3604#define LINK_FLAP_COUNT_OFFSET 16
3605#define LINK_FLAP_COUNT_MASK 0x00ff0000
3606
3607 u32 link_change_count;
3608
3609
3610 struct lldp_config_params_s lldp_config_params[
3611 LLDP_MAX_LLDP_AGENTS];
3612 struct lldp_status_params_s lldp_status_params[
3613 LLDP_MAX_LLDP_AGENTS];
3614 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
3615
3616
3617 struct dcbx_local_params local_admin_dcbx_mib;
3618 struct dcbx_mib remote_dcbx_mib;
3619 struct dcbx_mib operational_dcbx_mib;
3620
3621 u32 fc_npiv_nvram_tbl_addr;
3622 u32 fc_npiv_nvram_tbl_size;
3623 u32 transceiver_data;
3624#define PMM_TRANSCEIVER_STATE_MASK 0x000000FF
3625#define PMM_TRANSCEIVER_STATE_SHIFT 0x00000000
3626#define PMM_TRANSCEIVER_STATE_PRESENT 0x00000001
3627};
3628
3629
3630
3631
3632
3633
3634
3635struct public_func {
3636 u32 iscsi_boot_signature;
3637 u32 iscsi_boot_block_offset;
3638
3639 u32 mtu_size;
3640 u32 c2s_pcp_map_lower;
3641 u32 c2s_pcp_map_upper;
3642 u32 c2s_pcp_map_default;
3643 u32 reserved[4];
3644
3645 u32 config;
3646
3647
3648
3649#define FUNC_MF_CFG_FUNC_HIDE 0x00000001
3650#define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002
3651#define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001
3652
3653#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
3654#define FUNC_MF_CFG_PROTOCOL_SHIFT 4
3655#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
3656#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
3657#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
3658#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
3659#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
3660
3661
3662
3663#define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00
3664#define FUNC_MF_CFG_MIN_BW_SHIFT 8
3665#define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
3666#define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000
3667#define FUNC_MF_CFG_MAX_BW_SHIFT 16
3668#define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000
3669
3670 u32 status;
3671#define FUNC_STATUS_VLINK_DOWN 0x00000001
3672
3673 u32 mac_upper;
3674#define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
3675#define FUNC_MF_CFG_UPPERMAC_SHIFT 0
3676#define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
3677 u32 mac_lower;
3678#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
3679
3680 u32 fcoe_wwn_port_name_upper;
3681 u32 fcoe_wwn_port_name_lower;
3682
3683 u32 fcoe_wwn_node_name_upper;
3684 u32 fcoe_wwn_node_name_lower;
3685
3686 u32 ovlan_stag;
3687#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
3688#define FUNC_MF_CFG_OV_STAG_SHIFT 0
3689#define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK
3690
3691 u32 pf_allocation;
3692
3693 u32 preserve_data;
3694
3695 u32 driver_last_activity_ts;
3696
3697 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
3698
3699 u32 drv_id;
3700#define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff
3701#define DRV_ID_PDA_COMP_VER_SHIFT 0
3702
3703#define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000
3704#define DRV_ID_MCP_HSI_VER_SHIFT 16
3705#define DRV_ID_MCP_HSI_VER_CURRENT BIT(DRV_ID_MCP_HSI_VER_SHIFT)
3706
3707#define DRV_ID_DRV_TYPE_MASK 0x7f000000
3708#define DRV_ID_DRV_TYPE_SHIFT 24
3709#define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT)
3710#define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT)
3711#define DRV_ID_DRV_TYPE_WINDOWS (2 << DRV_ID_DRV_TYPE_SHIFT)
3712#define DRV_ID_DRV_TYPE_DIAG (3 << DRV_ID_DRV_TYPE_SHIFT)
3713#define DRV_ID_DRV_TYPE_PREBOOT (4 << DRV_ID_DRV_TYPE_SHIFT)
3714#define DRV_ID_DRV_TYPE_SOLARIS (5 << DRV_ID_DRV_TYPE_SHIFT)
3715#define DRV_ID_DRV_TYPE_VMWARE (6 << DRV_ID_DRV_TYPE_SHIFT)
3716#define DRV_ID_DRV_TYPE_FREEBSD (7 << DRV_ID_DRV_TYPE_SHIFT)
3717#define DRV_ID_DRV_TYPE_AIX (8 << DRV_ID_DRV_TYPE_SHIFT)
3718
3719#define DRV_ID_DRV_INIT_HW_MASK 0x80000000
3720#define DRV_ID_DRV_INIT_HW_SHIFT 31
3721#define DRV_ID_DRV_INIT_HW_FLAG BIT(DRV_ID_DRV_INIT_HW_SHIFT)
3722};
3723
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735
3736struct mcp_mac {
3737 u32 mac_upper;
3738 u32 mac_lower;
3739};
3740
3741struct mcp_val64 {
3742 u32 lo;
3743 u32 hi;
3744};
3745
3746struct mcp_file_att {
3747 u32 nvm_start_addr;
3748 u32 len;
3749};
3750
3751#define MCP_DRV_VER_STR_SIZE 16
3752#define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
3753#define MCP_DRV_NVM_BUF_LEN 32
3754struct drv_version_stc {
3755 u32 version;
3756 u8 name[MCP_DRV_VER_STR_SIZE - 4];
3757};
3758
3759union drv_union_data {
3760 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
3761 struct mcp_mac wol_mac;
3762
3763 struct pmm_phy_cfg drv_phy_cfg;
3764
3765 struct mcp_val64 val64;
3766
3767 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
3768
3769 struct mcp_file_att file_att;
3770
3771 u32 ack_vf_disabled[VF_MAX_STATIC / 32];
3772
3773 struct drv_version_stc drv_version;
3774};
3775
3776struct public_drv_mb {
3777 u32 drv_mb_header;
3778#define DRV_MSG_CODE_MASK 0xffff0000
3779#define DRV_MSG_CODE_LOAD_REQ 0x10000000
3780#define DRV_MSG_CODE_LOAD_DONE 0x11000000
3781#define DRV_MSG_CODE_INIT_HW 0x12000000
3782#define DRV_MSG_CODE_UNLOAD_REQ 0x20000000
3783#define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
3784#define DRV_MSG_CODE_INIT_PHY 0x22000000
3785
3786
3787#define DRV_MSG_CODE_LINK_RESET 0x23000000
3788
3789#define DRV_MSG_CODE_SET_LLDP 0x24000000
3790#define DRV_MSG_CODE_SET_DCBX 0x25000000
3791
3792#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
3793
3794#define DRV_MSG_CODE_INITIATE_FLR 0x02000000
3795#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
3796#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
3797#define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
3798#define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000
3799#define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000
3800#define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000
3801#define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000
3802#define DRV_MSG_CODE_NVM_DEL_FILE 0x00080000
3803#define DRV_MSG_CODE_MCP_RESET 0x00090000
3804#define DRV_MSG_CODE_SET_SECURE_MODE 0x000a0000
3805#define DRV_MSG_CODE_PHY_RAW_READ 0x000b0000
3806#define DRV_MSG_CODE_PHY_RAW_WRITE 0x000c0000
3807#define DRV_MSG_CODE_PHY_CORE_READ 0x000d0000
3808#define DRV_MSG_CODE_PHY_CORE_WRITE 0x000e0000
3809#define DRV_MSG_CODE_SET_VERSION 0x000f0000
3810
3811#define DRV_MSG_CODE_SET_LED_MODE 0x00200000
3812
3813#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
3814
3815 u32 drv_mb_param;
3816
3817
3818#define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000
3819#define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001
3820#define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002
3821#define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003
3822
3823
3824#define DRV_MB_PARAM_UNLOAD_NON_D3_POWER 0x00000001
3825
3826
3827#define DRV_MB_PARAM_INIT_PHY_FORCE 0x00000001
3828#define DRV_MB_PARAM_INIT_PHY_DONT_CARE 0x00000002
3829
3830
3831#define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001
3832#define DRV_MB_PARAM_LLDP_SEND_SHIFT 0
3833#define DRV_MB_PARAM_LLDP_AGENT_MASK 0x00000006
3834#define DRV_MB_PARAM_LLDP_AGENT_SHIFT 1
3835#define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x00000008
3836#define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3
3837
3838#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_MASK 0x000000FF
3839#define DRV_MB_PARAM_NIG_DRAIN_PERIOD_MS_SHIFT 0
3840
3841#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MFW 0x1
3842#define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_IMAGE 0x2
3843
3844#define DRV_MB_PARAM_NVM_OFFSET_SHIFT 0
3845#define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF
3846#define DRV_MB_PARAM_NVM_LEN_SHIFT 24
3847#define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000
3848
3849#define DRV_MB_PARAM_PHY_ADDR_SHIFT 0
3850#define DRV_MB_PARAM_PHY_ADDR_MASK 0x1FF0FFFF
3851#define DRV_MB_PARAM_PHY_LANE_SHIFT 16
3852#define DRV_MB_PARAM_PHY_LANE_MASK 0x000F0000
3853#define DRV_MB_PARAM_PHY_SELECT_PORT_SHIFT 29
3854#define DRV_MB_PARAM_PHY_SELECT_PORT_MASK 0x20000000
3855#define DRV_MB_PARAM_PHY_PORT_SHIFT 30
3856#define DRV_MB_PARAM_PHY_PORT_MASK 0xc0000000
3857
3858
3859#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0
3860#define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF
3861#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8
3862#define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00
3863
3864#define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0
3865#define DRV_MB_PARAM_SET_LED_MODE_ON 0x1
3866#define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2
3867
3868 u32 fw_mb_header;
3869#define FW_MSG_CODE_MASK 0xffff0000
3870#define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000
3871#define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
3872#define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
3873#define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000
3874#define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10210000
3875#define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000
3876#define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
3877#define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000
3878#define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000
3879#define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000
3880#define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
3881#define FW_MSG_CODE_INIT_PHY_DONE 0x21200000
3882#define FW_MSG_CODE_INIT_PHY_ERR_INVALID_ARGS 0x21300000
3883#define FW_MSG_CODE_LINK_RESET_DONE 0x23000000
3884#define FW_MSG_CODE_SET_LLDP_DONE 0x24000000
3885#define FW_MSG_CODE_SET_LLDP_UNSUPPORTED_AGENT 0x24010000
3886#define FW_MSG_CODE_SET_DCBX_DONE 0x25000000
3887#define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
3888#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
3889#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
3890#define FW_MSG_CODE_FLR_ACK 0x02000000
3891#define FW_MSG_CODE_FLR_NACK 0x02100000
3892
3893#define FW_MSG_CODE_NVM_OK 0x00010000
3894#define FW_MSG_CODE_NVM_INVALID_MODE 0x00020000
3895#define FW_MSG_CODE_NVM_PREV_CMD_WAS_NOT_FINISHED 0x00030000
3896#define FW_MSG_CODE_NVM_FAILED_TO_ALLOCATE_PAGE 0x00040000
3897#define FW_MSG_CODE_NVM_INVALID_DIR_FOUND 0x00050000
3898#define FW_MSG_CODE_NVM_PAGE_NOT_FOUND 0x00060000
3899#define FW_MSG_CODE_NVM_FAILED_PARSING_BNDLE_HEADER 0x00070000
3900#define FW_MSG_CODE_NVM_FAILED_PARSING_IMAGE_HEADER 0x00080000
3901#define FW_MSG_CODE_NVM_PARSING_OUT_OF_SYNC 0x00090000
3902#define FW_MSG_CODE_NVM_FAILED_UPDATING_DIR 0x000a0000
3903#define FW_MSG_CODE_NVM_FAILED_TO_FREE_PAGE 0x000b0000
3904#define FW_MSG_CODE_NVM_FILE_NOT_FOUND 0x000c0000
3905#define FW_MSG_CODE_NVM_OPERATION_FAILED 0x000d0000
3906#define FW_MSG_CODE_NVM_FAILED_UNALIGNED 0x000e0000
3907#define FW_MSG_CODE_NVM_BAD_OFFSET 0x000f0000
3908#define FW_MSG_CODE_NVM_BAD_SIGNATURE 0x00100000
3909#define FW_MSG_CODE_NVM_FILE_READ_ONLY 0x00200000
3910#define FW_MSG_CODE_NVM_UNKNOWN_FILE 0x00300000
3911#define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000
3912#define FW_MSG_CODE_MCP_RESET_REJECT 0x00600000
3913#define FW_MSG_CODE_PHY_OK 0x00110000
3914#define FW_MSG_CODE_PHY_ERROR 0x00120000
3915#define FW_MSG_CODE_SET_SECURE_MODE_ERROR 0x00130000
3916#define FW_MSG_CODE_SET_SECURE_MODE_OK 0x00140000
3917#define FW_MSG_MODE_PHY_PRIVILEGE_ERROR 0x00150000
3918#define FW_MSG_CODE_OK 0x00160000
3919
3920#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
3921
3922 u32 fw_mb_param;
3923
3924 u32 drv_pulse_mb;
3925#define DRV_PULSE_SEQ_MASK 0x00007fff
3926#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
3927#define DRV_PULSE_ALWAYS_ALIVE 0x00008000
3928 u32 mcp_pulse_mb;
3929#define MCP_PULSE_SEQ_MASK 0x00007fff
3930#define MCP_PULSE_ALWAYS_ALIVE 0x00008000
3931#define MCP_EVENT_MASK 0xffff0000
3932#define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
3933
3934 union drv_union_data union_data;
3935};
3936
3937
3938
3939
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953enum MFW_DRV_MSG_TYPE {
3954 MFW_DRV_MSG_LINK_CHANGE,
3955 MFW_DRV_MSG_FLR_FW_ACK_FAILED,
3956 MFW_DRV_MSG_VF_DISABLED,
3957 MFW_DRV_MSG_LLDP_DATA_UPDATED,
3958 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
3959 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
3960 MFW_DRV_MSG_ERROR_RECOVERY,
3961 MFW_DRV_MSG_BW_UPDATE,
3962 MFW_DRV_MSG_S_TAG_UPDATE,
3963 MFW_DRV_MSG_GET_LAN_STATS,
3964 MFW_DRV_MSG_GET_FCOE_STATS,
3965 MFW_DRV_MSG_GET_ISCSI_STATS,
3966 MFW_DRV_MSG_GET_RDMA_STATS,
3967 MFW_DRV_MSG_FAILURE_DETECTED,
3968 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
3969 MFW_DRV_MSG_MAX
3970};
3971
3972#define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1)
3973#define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2)
3974#define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3)
3975#define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id))
3976
3977struct public_mfw_mb {
3978 u32 sup_msgs;
3979 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
3980 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
3981};
3982
3983
3984
3985
3986
3987
3988enum public_sections {
3989 PUBLIC_DRV_MB,
3990 PUBLIC_MFW_MB,
3991 PUBLIC_GLOBAL,
3992 PUBLIC_PATH,
3993 PUBLIC_PORT,
3994 PUBLIC_FUNC,
3995 PUBLIC_MAX_SECTIONS
3996};
3997
3998struct drv_ver_info_stc {
3999 u32 ver;
4000 u8 name[32];
4001};
4002
4003struct mcp_public_data {
4004
4005 u32 num_sections;
4006 offsize_t sections[PUBLIC_MAX_SECTIONS];
4007 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
4008 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
4009 struct public_global global;
4010 struct public_path path[MCP_GLOB_PATH_MAX];
4011 struct public_port port[MCP_GLOB_PORT_MAX];
4012 struct public_func func[MCP_GLOB_FUNC_MAX];
4013 struct drv_ver_info_stc drv_info;
4014};
4015
4016struct nvm_cfg_mac_address {
4017 u32 mac_addr_hi;
4018#define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF
4019#define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0
4020
4021 u32 mac_addr_lo;
4022};
4023
4024
4025
4026
4027
4028struct nvm_cfg1_glob {
4029 u32 generic_cont0;
4030#define NVM_CFG1_GLOB_BOARD_SWAP_MASK 0x0000000F
4031#define NVM_CFG1_GLOB_BOARD_SWAP_OFFSET 0
4032#define NVM_CFG1_GLOB_BOARD_SWAP_NONE 0x0
4033#define NVM_CFG1_GLOB_BOARD_SWAP_PATH 0x1
4034#define NVM_CFG1_GLOB_BOARD_SWAP_PORT 0x2
4035#define NVM_CFG1_GLOB_BOARD_SWAP_BOTH 0x3
4036#define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0
4037#define NVM_CFG1_GLOB_MF_MODE_OFFSET 4
4038#define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0
4039#define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1
4040#define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2
4041#define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3
4042#define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4
4043#define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5
4044#define NVM_CFG1_GLOB_MF_MODE_BD 0x6
4045#define NVM_CFG1_GLOB_MF_MODE_UFP 0x7
4046#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_MASK 0x00001000
4047#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_OFFSET 12
4048#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_DISABLED 0x0
4049#define NVM_CFG1_GLOB_FAN_FAILURE_ENFORCEMENT_ENABLED 0x1
4050#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_MASK 0x001FE000
4051#define NVM_CFG1_GLOB_AVS_MARGIN_LOW_OFFSET 13
4052#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_MASK 0x1FE00000
4053#define NVM_CFG1_GLOB_AVS_MARGIN_HIGH_OFFSET 21
4054#define NVM_CFG1_GLOB_ENABLE_SRIOV_MASK 0x20000000
4055#define NVM_CFG1_GLOB_ENABLE_SRIOV_OFFSET 29
4056#define NVM_CFG1_GLOB_ENABLE_SRIOV_DISABLED 0x0
4057#define NVM_CFG1_GLOB_ENABLE_SRIOV_ENABLED 0x1
4058#define NVM_CFG1_GLOB_ENABLE_ATC_MASK 0x40000000
4059#define NVM_CFG1_GLOB_ENABLE_ATC_OFFSET 30
4060#define NVM_CFG1_GLOB_ENABLE_ATC_DISABLED 0x0
4061#define NVM_CFG1_GLOB_ENABLE_ATC_ENABLED 0x1
4062#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_MASK 0x80000000
4063#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_OFFSET 31
4064#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_DISABLED 0x0
4065#define NVM_CFG1_GLOB_CLOCK_SLOWDOWN_ENABLED 0x1
4066
4067 u32 engineering_change[3];
4068
4069 u32 manufacturing_id;
4070
4071 u32 serial_number[4];
4072
4073 u32 pcie_cfg;
4074#define NVM_CFG1_GLOB_PCI_GEN_MASK 0x00000003
4075#define NVM_CFG1_GLOB_PCI_GEN_OFFSET 0
4076#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN1 0x0
4077#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN2 0x1
4078#define NVM_CFG1_GLOB_PCI_GEN_PCI_GEN3 0x2
4079#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_MASK 0x00000004
4080#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_OFFSET 2
4081#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_DISABLED 0x0
4082#define NVM_CFG1_GLOB_BEACON_WOL_ENABLED_ENABLED 0x1
4083#define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
4084#define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
4085#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
4086#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
4087#define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
4088#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
4089#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_MASK 0x00000020
4090#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_OFFSET 5
4091#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_DISABLED 0x0
4092#define NVM_CFG1_GLOB_PREVENT_PCIE_L1_MENTRY_ENABLED 0x1
4093#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
4094#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
4095#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_MASK 0x00001C00
4096#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_OFFSET 10
4097#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_HW 0x0
4098#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_0DB 0x1
4099#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_3_5DB 0x2
4100#define NVM_CFG1_GLOB_PCIE_PREEMPHASIS_6_0DB 0x3
4101#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_MASK 0x001FE000
4102#define NVM_CFG1_GLOB_WWN_NODE_PREFIX0_OFFSET 13
4103#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_MASK 0x1FE00000
4104#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
4105#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
4106#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
4107
4108 u32 mgmt_traffic;
4109#define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
4110#define NVM_CFG1_GLOB_RESERVED60_OFFSET 0
4111#define NVM_CFG1_GLOB_RESERVED60_100KHZ 0x0
4112#define NVM_CFG1_GLOB_RESERVED60_400KHZ 0x1
4113#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_MASK 0x000001FE
4114#define NVM_CFG1_GLOB_WWN_PORT_PREFIX0_OFFSET 1
4115#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_MASK 0x0001FE00
4116#define NVM_CFG1_GLOB_WWN_PORT_PREFIX1_OFFSET 9
4117#define NVM_CFG1_GLOB_SMBUS_ADDRESS_MASK 0x01FE0000
4118#define NVM_CFG1_GLOB_SMBUS_ADDRESS_OFFSET 17
4119#define NVM_CFG1_GLOB_SIDEBAND_MODE_MASK 0x06000000
4120#define NVM_CFG1_GLOB_SIDEBAND_MODE_OFFSET 25
4121#define NVM_CFG1_GLOB_SIDEBAND_MODE_DISABLED 0x0
4122#define NVM_CFG1_GLOB_SIDEBAND_MODE_RMII 0x1
4123#define NVM_CFG1_GLOB_SIDEBAND_MODE_SGMII 0x2
4124
4125 u32 core_cfg;
4126#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
4127#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
4128#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0
4129#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1
4130#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2
4131#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F 0x3
4132#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E 0x4
4133#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G 0x5
4134#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G 0xB
4135#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G 0xC
4136#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G 0xD
4137#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK 0x00000100
4138#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET 8
4139#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4140#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4141#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK 0x00000200
4142#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET 9
4143#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED 0x0
4144#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED 0x1
4145#define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK 0x0003FC00
4146#define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10
4147#define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000
4148#define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18
4149#define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
4150#define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
4151#define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
4152#define NVM_CFG1_GLOB_AVS_MODE_OPEN_LOOP 0x1
4153#define NVM_CFG1_GLOB_AVS_MODE_DISABLED 0x3
4154#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_MASK 0x60000000
4155#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_OFFSET 29
4156#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_DISABLED 0x0
4157#define NVM_CFG1_GLOB_OVERRIDE_SECURE_MODE_ENABLED 0x1
4158
4159 u32 e_lane_cfg1;
4160#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4161#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4162#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4163#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4164#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4165#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4166#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4167#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4168#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4169#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4170#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4171#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4172#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4173#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4174#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4175#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4176
4177 u32 e_lane_cfg2;
4178#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4179#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4180#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4181#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4182#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4183#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4184#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4185#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4186#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4187#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4188#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4189#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4190#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4191#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4192#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4193#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4194#define NVM_CFG1_GLOB_SMBUS_MODE_MASK 0x00000F00
4195#define NVM_CFG1_GLOB_SMBUS_MODE_OFFSET 8
4196#define NVM_CFG1_GLOB_SMBUS_MODE_DISABLED 0x0
4197#define NVM_CFG1_GLOB_SMBUS_MODE_100KHZ 0x1
4198#define NVM_CFG1_GLOB_SMBUS_MODE_400KHZ 0x2
4199#define NVM_CFG1_GLOB_NCSI_MASK 0x0000F000
4200#define NVM_CFG1_GLOB_NCSI_OFFSET 12
4201#define NVM_CFG1_GLOB_NCSI_DISABLED 0x0
4202#define NVM_CFG1_GLOB_NCSI_ENABLED 0x1
4203
4204 u32 f_lane_cfg1;
4205#define NVM_CFG1_GLOB_RX_LANE0_SWAP_MASK 0x0000000F
4206#define NVM_CFG1_GLOB_RX_LANE0_SWAP_OFFSET 0
4207#define NVM_CFG1_GLOB_RX_LANE1_SWAP_MASK 0x000000F0
4208#define NVM_CFG1_GLOB_RX_LANE1_SWAP_OFFSET 4
4209#define NVM_CFG1_GLOB_RX_LANE2_SWAP_MASK 0x00000F00
4210#define NVM_CFG1_GLOB_RX_LANE2_SWAP_OFFSET 8
4211#define NVM_CFG1_GLOB_RX_LANE3_SWAP_MASK 0x0000F000
4212#define NVM_CFG1_GLOB_RX_LANE3_SWAP_OFFSET 12
4213#define NVM_CFG1_GLOB_TX_LANE0_SWAP_MASK 0x000F0000
4214#define NVM_CFG1_GLOB_TX_LANE0_SWAP_OFFSET 16
4215#define NVM_CFG1_GLOB_TX_LANE1_SWAP_MASK 0x00F00000
4216#define NVM_CFG1_GLOB_TX_LANE1_SWAP_OFFSET 20
4217#define NVM_CFG1_GLOB_TX_LANE2_SWAP_MASK 0x0F000000
4218#define NVM_CFG1_GLOB_TX_LANE2_SWAP_OFFSET 24
4219#define NVM_CFG1_GLOB_TX_LANE3_SWAP_MASK 0xF0000000
4220#define NVM_CFG1_GLOB_TX_LANE3_SWAP_OFFSET 28
4221
4222 u32 f_lane_cfg2;
4223#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_MASK 0x00000001
4224#define NVM_CFG1_GLOB_RX_LANE0_POL_FLIP_OFFSET 0
4225#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_MASK 0x00000002
4226#define NVM_CFG1_GLOB_RX_LANE1_POL_FLIP_OFFSET 1
4227#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_MASK 0x00000004
4228#define NVM_CFG1_GLOB_RX_LANE2_POL_FLIP_OFFSET 2
4229#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_MASK 0x00000008
4230#define NVM_CFG1_GLOB_RX_LANE3_POL_FLIP_OFFSET 3
4231#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_MASK 0x00000010
4232#define NVM_CFG1_GLOB_TX_LANE0_POL_FLIP_OFFSET 4
4233#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_MASK 0x00000020
4234#define NVM_CFG1_GLOB_TX_LANE1_POL_FLIP_OFFSET 5
4235#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_MASK 0x00000040
4236#define NVM_CFG1_GLOB_TX_LANE2_POL_FLIP_OFFSET 6
4237#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_MASK 0x00000080
4238#define NVM_CFG1_GLOB_TX_LANE3_POL_FLIP_OFFSET 7
4239
4240 u32 eagle_preemphasis;
4241#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4242#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4243#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4244#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4245#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4246#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4247#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4248#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4249
4250 u32 eagle_driver_current;
4251#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4252#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4253#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4254#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4255#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4256#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4257#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4258#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4259
4260 u32 falcon_preemphasis;
4261#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
4262#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
4263#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
4264#define NVM_CFG1_GLOB_LANE1_PREEMP_OFFSET 8
4265#define NVM_CFG1_GLOB_LANE2_PREEMP_MASK 0x00FF0000
4266#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
4267#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
4268#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
4269
4270 u32 falcon_driver_current;
4271#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
4272#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
4273#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
4274#define NVM_CFG1_GLOB_LANE1_AMP_OFFSET 8
4275#define NVM_CFG1_GLOB_LANE2_AMP_MASK 0x00FF0000
4276#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
4277#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
4278#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
4279
4280 u32 pci_id;
4281#define NVM_CFG1_GLOB_VENDOR_ID_MASK 0x0000FFFF
4282#define NVM_CFG1_GLOB_VENDOR_ID_OFFSET 0
4283
4284 u32 pci_subsys_id;
4285#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_MASK 0x0000FFFF
4286#define NVM_CFG1_GLOB_SUBSYSTEM_VENDOR_ID_OFFSET 0
4287#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_MASK 0xFFFF0000
4288#define NVM_CFG1_GLOB_SUBSYSTEM_DEVICE_ID_OFFSET 16
4289
4290 u32 bar;
4291#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_MASK 0x0000000F
4292#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_OFFSET 0
4293#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_DISABLED 0x0
4294#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2K 0x1
4295#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4K 0x2
4296#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8K 0x3
4297#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16K 0x4
4298#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32K 0x5
4299#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_64K 0x6
4300#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_128K 0x7
4301#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_256K 0x8
4302#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_512K 0x9
4303#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_1M 0xA
4304#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_2M 0xB
4305#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_4M 0xC
4306#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_8M 0xD
4307#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_16M 0xE
4308#define NVM_CFG1_GLOB_EXPANSION_ROM_SIZE_32M 0xF
4309#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_MASK 0x000000F0
4310#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_OFFSET 4
4311#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_DISABLED 0x0
4312#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4K 0x1
4313#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8K 0x2
4314#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16K 0x3
4315#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32K 0x4
4316#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64K 0x5
4317#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_128K 0x6
4318#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_256K 0x7
4319#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_512K 0x8
4320#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_1M 0x9
4321#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_2M 0xA
4322#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_4M 0xB
4323#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_8M 0xC
4324#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_16M 0xD
4325#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_32M 0xE
4326#define NVM_CFG1_GLOB_VF_PCI_BAR2_SIZE_64M 0xF
4327#define NVM_CFG1_GLOB_BAR2_SIZE_MASK 0x00000F00
4328#define NVM_CFG1_GLOB_BAR2_SIZE_OFFSET 8
4329#define NVM_CFG1_GLOB_BAR2_SIZE_DISABLED 0x0
4330#define NVM_CFG1_GLOB_BAR2_SIZE_64K 0x1
4331#define NVM_CFG1_GLOB_BAR2_SIZE_128K 0x2
4332#define NVM_CFG1_GLOB_BAR2_SIZE_256K 0x3
4333#define NVM_CFG1_GLOB_BAR2_SIZE_512K 0x4
4334#define NVM_CFG1_GLOB_BAR2_SIZE_1M 0x5
4335#define NVM_CFG1_GLOB_BAR2_SIZE_2M 0x6
4336#define NVM_CFG1_GLOB_BAR2_SIZE_4M 0x7
4337#define NVM_CFG1_GLOB_BAR2_SIZE_8M 0x8
4338#define NVM_CFG1_GLOB_BAR2_SIZE_16M 0x9
4339#define NVM_CFG1_GLOB_BAR2_SIZE_32M 0xA
4340#define NVM_CFG1_GLOB_BAR2_SIZE_64M 0xB
4341#define NVM_CFG1_GLOB_BAR2_SIZE_128M 0xC
4342#define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
4343#define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
4344#define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
4345
4346 u32 eagle_txfir_main;
4347#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4348#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4349#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4350#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4351#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4352#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4353#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4354#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4355
4356 u32 eagle_txfir_post;
4357#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4358#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4359#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4360#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4361#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4362#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4363#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4364#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4365
4366 u32 falcon_txfir_main;
4367#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
4368#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
4369#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
4370#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_OFFSET 8
4371#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_MASK 0x00FF0000
4372#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
4373#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
4374#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
4375
4376 u32 falcon_txfir_post;
4377#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
4378#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
4379#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
4380#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_OFFSET 8
4381#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_MASK 0x00FF0000
4382#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
4383#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
4384#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
4385
4386 u32 manufacture_ver;
4387#define NVM_CFG1_GLOB_MANUF0_VER_MASK 0x0000003F
4388#define NVM_CFG1_GLOB_MANUF0_VER_OFFSET 0
4389#define NVM_CFG1_GLOB_MANUF1_VER_MASK 0x00000FC0
4390#define NVM_CFG1_GLOB_MANUF1_VER_OFFSET 6
4391#define NVM_CFG1_GLOB_MANUF2_VER_MASK 0x0003F000
4392#define NVM_CFG1_GLOB_MANUF2_VER_OFFSET 12
4393#define NVM_CFG1_GLOB_MANUF3_VER_MASK 0x00FC0000
4394#define NVM_CFG1_GLOB_MANUF3_VER_OFFSET 18
4395#define NVM_CFG1_GLOB_MANUF4_VER_MASK 0x3F000000
4396#define NVM_CFG1_GLOB_MANUF4_VER_OFFSET 24
4397
4398 u32 manufacture_time;
4399#define NVM_CFG1_GLOB_MANUF0_TIME_MASK 0x0000003F
4400#define NVM_CFG1_GLOB_MANUF0_TIME_OFFSET 0
4401#define NVM_CFG1_GLOB_MANUF1_TIME_MASK 0x00000FC0
4402#define NVM_CFG1_GLOB_MANUF1_TIME_OFFSET 6
4403#define NVM_CFG1_GLOB_MANUF2_TIME_MASK 0x0003F000
4404#define NVM_CFG1_GLOB_MANUF2_TIME_OFFSET 12
4405
4406 u32 led_global_settings;
4407#define NVM_CFG1_GLOB_LED_SWAP_0_MASK 0x0000000F
4408#define NVM_CFG1_GLOB_LED_SWAP_0_OFFSET 0
4409#define NVM_CFG1_GLOB_LED_SWAP_1_MASK 0x000000F0
4410#define NVM_CFG1_GLOB_LED_SWAP_1_OFFSET 4
4411#define NVM_CFG1_GLOB_LED_SWAP_2_MASK 0x00000F00
4412#define NVM_CFG1_GLOB_LED_SWAP_2_OFFSET 8
4413#define NVM_CFG1_GLOB_LED_SWAP_3_MASK 0x0000F000
4414#define NVM_CFG1_GLOB_LED_SWAP_3_OFFSET 12
4415
4416 u32 generic_cont1;
4417#define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
4418#define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
4419
4420 u32 mbi_version;
4421#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
4422#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
4423#define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00
4424#define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8
4425#define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000
4426#define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16
4427
4428 u32 mbi_date;
4429
4430 u32 misc_sig;
4431
4432
4433#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_MASK 0x000000FF
4434#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_0_OFFSET 0
4435#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_MASK 0x0000FF00
4436#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO_1_OFFSET 8
4437#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__NA 0x0
4438#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO0 0x1
4439#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO1 0x2
4440#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO2 0x3
4441#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO3 0x4
4442#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO4 0x5
4443#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO5 0x6
4444#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO6 0x7
4445#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO7 0x8
4446#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO8 0x9
4447#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO9 0xA
4448#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO10 0xB
4449#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO11 0xC
4450#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO12 0xD
4451#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO13 0xE
4452#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO14 0xF
4453#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO15 0x10
4454#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO16 0x11
4455#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO17 0x12
4456#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO18 0x13
4457#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO19 0x14
4458#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO20 0x15
4459#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO21 0x16
4460#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO22 0x17
4461#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO23 0x18
4462#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO24 0x19
4463#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO25 0x1A
4464#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO26 0x1B
4465#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO27 0x1C
4466#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO28 0x1D
4467#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO29 0x1E
4468#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO30 0x1F
4469#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
4470 u32 device_capabilities;
4471#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
4472 u32 power_dissipated;
4473 u32 power_consumed;
4474 u32 efi_version;
4475 u32 reserved[42];
4476};
4477
4478struct nvm_cfg1_path {
4479 u32 reserved[30];
4480};
4481
4482struct nvm_cfg1_port {
4483 u32 reserved__m_relocated_to_option_123;
4484 u32 reserved__m_relocated_to_option_124;
4485 u32 generic_cont0;
4486#define NVM_CFG1_PORT_LED_MODE_MASK 0x000000FF
4487#define NVM_CFG1_PORT_LED_MODE_OFFSET 0
4488#define NVM_CFG1_PORT_LED_MODE_MAC1 0x0
4489#define NVM_CFG1_PORT_LED_MODE_PHY1 0x1
4490#define NVM_CFG1_PORT_LED_MODE_PHY2 0x2
4491#define NVM_CFG1_PORT_LED_MODE_PHY3 0x3
4492#define NVM_CFG1_PORT_LED_MODE_MAC2 0x4
4493#define NVM_CFG1_PORT_LED_MODE_PHY4 0x5
4494#define NVM_CFG1_PORT_LED_MODE_PHY5 0x6
4495#define NVM_CFG1_PORT_LED_MODE_PHY6 0x7
4496#define NVM_CFG1_PORT_LED_MODE_MAC3 0x8
4497#define NVM_CFG1_PORT_LED_MODE_PHY7 0x9
4498#define NVM_CFG1_PORT_LED_MODE_PHY8 0xA
4499#define NVM_CFG1_PORT_LED_MODE_PHY9 0xB
4500#define NVM_CFG1_PORT_LED_MODE_MAC4 0xC
4501#define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
4502#define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
4503#define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
4504#define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
4505#define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
4506#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
4507#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
4508#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
4509#define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1
4510#define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2
4511#define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3
4512#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
4513#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
4514#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
4515 u32 pcie_cfg;
4516#define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
4517#define NVM_CFG1_PORT_RESERVED15_OFFSET 0
4518
4519 u32 features;
4520#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_MASK 0x00000001
4521#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_OFFSET 0
4522#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_DISABLED 0x0
4523#define NVM_CFG1_PORT_ENABLE_WOL_ON_ACPI_PATTERN_ENABLED 0x1
4524#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_MASK 0x00000002
4525#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_OFFSET 1
4526#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_DISABLED 0x0
4527#define NVM_CFG1_PORT_MAGIC_PACKET_WOL_ENABLED 0x1
4528
4529 u32 speed_cap_mask;
4530#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF
4531#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
4532#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1
4533#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2
4534#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
4535#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
4536#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
4537#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40
4538#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
4539#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
4540#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
4541#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_10G 0x2
4542#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
4543#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
4544#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
4545#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40
4546
4547 u32 link_settings;
4548#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
4549#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
4550#define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0
4551#define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1
4552#define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2
4553#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
4554#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
4555#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
4556#define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7
4557#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
4558#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
4559#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1
4560#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2
4561#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4
4562#define NVM_CFG1_PORT_MFW_LINK_SPEED_MASK 0x00000780
4563#define NVM_CFG1_PORT_MFW_LINK_SPEED_OFFSET 7
4564#define NVM_CFG1_PORT_MFW_LINK_SPEED_AUTONEG 0x0
4565#define NVM_CFG1_PORT_MFW_LINK_SPEED_1G 0x1
4566#define NVM_CFG1_PORT_MFW_LINK_SPEED_10G 0x2
4567#define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
4568#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
4569#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
4570#define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7
4571#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
4572#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
4573#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
4574#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
4575#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
4576#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
4577#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
4578#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
4579#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
4580
4581 u32 phy_cfg;
4582#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
4583#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
4584#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_HIGIG 0x1
4585#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_SCRAMBLER 0x2
4586#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_FIBER 0x4
4587#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_CL72_AN 0x8
4588#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_DISABLE_FEC_AN 0x10
4589#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_MASK 0x00FF0000
4590#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_OFFSET 16
4591#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_BYPASS 0x0
4592#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR 0x2
4593#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR2 0x3
4594#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_KR4 0x4
4595#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XFI 0x8
4596#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SFI 0x9
4597#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_1000X 0xB
4598#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_SGMII 0xC
4599#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLAUI 0x11
4600#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_XLPPI 0x12
4601#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CAUI 0x21
4602#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_CPPI 0x22
4603#define NVM_CFG1_PORT_SERDES_NET_INTERFACE_25GAUI 0x31
4604#define NVM_CFG1_PORT_AN_MODE_MASK 0xFF000000
4605#define NVM_CFG1_PORT_AN_MODE_OFFSET 24
4606#define NVM_CFG1_PORT_AN_MODE_NONE 0x0
4607#define NVM_CFG1_PORT_AN_MODE_CL73 0x1
4608#define NVM_CFG1_PORT_AN_MODE_CL37 0x2
4609#define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
4610#define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4
4611#define NVM_CFG1_PORT_AN_MODE_HPAM 0x5
4612#define NVM_CFG1_PORT_AN_MODE_SGMII 0x6
4613
4614 u32 mgmt_traffic;
4615#define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
4616#define NVM_CFG1_PORT_RESERVED61_OFFSET 0
4617
4618 u32 ext_phy;
4619#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_MASK 0x000000FF
4620#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_OFFSET 0
4621#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_NONE 0x0
4622#define NVM_CFG1_PORT_EXTERNAL_PHY_TYPE_BCM84844 0x1
4623#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_MASK 0x0000FF00
4624#define NVM_CFG1_PORT_EXTERNAL_PHY_ADDRESS_OFFSET 8
4625
4626 u32 mba_cfg1;
4627#define NVM_CFG1_PORT_PREBOOT_OPROM_MASK 0x00000001
4628#define NVM_CFG1_PORT_PREBOOT_OPROM_OFFSET 0
4629#define NVM_CFG1_PORT_PREBOOT_OPROM_DISABLED 0x0
4630#define NVM_CFG1_PORT_PREBOOT_OPROM_ENABLED 0x1
4631#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_MASK 0x00000006
4632#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_TYPE_OFFSET 1
4633#define NVM_CFG1_PORT_MBA_DELAY_TIME_MASK 0x00000078
4634#define NVM_CFG1_PORT_MBA_DELAY_TIME_OFFSET 3
4635#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_MASK 0x00000080
4636#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_OFFSET 7
4637#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_S 0x0
4638#define NVM_CFG1_PORT_MBA_SETUP_HOT_KEY_CTRL_B 0x1
4639#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_MASK 0x00000100
4640#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_OFFSET 8
4641#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_DISABLED 0x0
4642#define NVM_CFG1_PORT_MBA_HIDE_SETUP_PROMPT_ENABLED 0x1
4643#define NVM_CFG1_PORT_RESERVED5_MASK 0x0001FE00
4644#define NVM_CFG1_PORT_RESERVED5_OFFSET 9
4645#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_MASK 0x001E0000
4646#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_OFFSET 17
4647#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_AUTONEG 0x0
4648#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_1G 0x1
4649#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_10G 0x2
4650#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
4651#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
4652#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
4653#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G 0x7
4654#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
4655#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
4656#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
4657
4658 u32 mba_cfg2;
4659#define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
4660#define NVM_CFG1_PORT_RESERVED65_OFFSET 0
4661#define NVM_CFG1_PORT_RESERVED66_MASK 0x00010000
4662#define NVM_CFG1_PORT_RESERVED66_OFFSET 16
4663
4664 u32 vf_cfg;
4665#define NVM_CFG1_PORT_RESERVED8_MASK 0x0000FFFF
4666#define NVM_CFG1_PORT_RESERVED8_OFFSET 0
4667#define NVM_CFG1_PORT_RESERVED6_MASK 0x000F0000
4668#define NVM_CFG1_PORT_RESERVED6_OFFSET 16
4669
4670 struct nvm_cfg_mac_address lldp_mac_address;
4671
4672 u32 led_port_settings;
4673#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_MASK 0x000000FF
4674#define NVM_CFG1_PORT_LANE_LED_SPD_0_SEL_OFFSET 0
4675#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_MASK 0x0000FF00
4676#define NVM_CFG1_PORT_LANE_LED_SPD_1_SEL_OFFSET 8
4677#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_MASK 0x00FF0000
4678#define NVM_CFG1_PORT_LANE_LED_SPD_2_SEL_OFFSET 16
4679#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_1G 0x1
4680#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_10G 0x2
4681#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
4682#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
4683#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
4684#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40
4685
4686 u32 transceiver_00;
4687
4688
4689#define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
4690#define NVM_CFG1_PORT_TRANS_MODULE_ABS_OFFSET 0
4691#define NVM_CFG1_PORT_TRANS_MODULE_ABS_NA 0x0
4692#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO0 0x1
4693#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO1 0x2
4694#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO2 0x3
4695#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO3 0x4
4696#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO4 0x5
4697#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO5 0x6
4698#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO6 0x7
4699#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO7 0x8
4700#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO8 0x9
4701#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO9 0xA
4702#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO10 0xB
4703#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO11 0xC
4704#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO12 0xD
4705#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO13 0xE
4706#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO14 0xF
4707#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO15 0x10
4708#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO16 0x11
4709#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO17 0x12
4710#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO18 0x13
4711#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO19 0x14
4712#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO20 0x15
4713#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO21 0x16
4714#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO22 0x17
4715#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO23 0x18
4716#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO24 0x19
4717#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO25 0x1A
4718#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO26 0x1B
4719#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO27 0x1C
4720#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO28 0x1D
4721#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO29 0x1E
4722#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO30 0x1F
4723#define NVM_CFG1_PORT_TRANS_MODULE_ABS_GPIO31 0x20
4724
4725#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_MASK 0x00000F00
4726#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_0_OFFSET 8
4727#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_MASK 0x0000F000
4728#define NVM_CFG1_PORT_I2C_MUX_SEL_VALUE_1_OFFSET 12
4729
4730 u32 reserved[133];
4731};
4732
4733struct nvm_cfg1_func {
4734 struct nvm_cfg_mac_address mac_address;
4735
4736 u32 rsrv1;
4737#define NVM_CFG1_FUNC_RESERVED1_MASK 0x0000FFFF
4738#define NVM_CFG1_FUNC_RESERVED1_OFFSET 0
4739#define NVM_CFG1_FUNC_RESERVED2_MASK 0xFFFF0000
4740#define NVM_CFG1_FUNC_RESERVED2_OFFSET 16
4741
4742 u32 rsrv2;
4743#define NVM_CFG1_FUNC_RESERVED3_MASK 0x0000FFFF
4744#define NVM_CFG1_FUNC_RESERVED3_OFFSET 0
4745#define NVM_CFG1_FUNC_RESERVED4_MASK 0xFFFF0000
4746#define NVM_CFG1_FUNC_RESERVED4_OFFSET 16
4747
4748 u32 device_id;
4749#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_MASK 0x0000FFFF
4750#define NVM_CFG1_FUNC_MF_VENDOR_DEVICE_ID_OFFSET 0
4751#define NVM_CFG1_FUNC_RESERVED77_MASK 0xFFFF0000
4752#define NVM_CFG1_FUNC_RESERVED77_OFFSET 16
4753
4754 u32 cmn_cfg;
4755#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
4756#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
4757#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
4758#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
4759#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
4760#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
4761#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
4762#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
4763#define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
4764#define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
4765#define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
4766#define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
4767#define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
4768#define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
4769#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
4770#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
4771#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
4772#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_OFFSET 31
4773#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_DISABLED 0x0
4774#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_ENABLED 0x1
4775
4776 u32 pci_cfg;
4777#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
4778#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
4779#define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80
4780#define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7
4781#define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
4782#define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
4783#define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
4784#define NVM_CFG1_FUNC_BAR1_SIZE_64K 0x1
4785#define NVM_CFG1_FUNC_BAR1_SIZE_128K 0x2
4786#define NVM_CFG1_FUNC_BAR1_SIZE_256K 0x3
4787#define NVM_CFG1_FUNC_BAR1_SIZE_512K 0x4
4788#define NVM_CFG1_FUNC_BAR1_SIZE_1M 0x5
4789#define NVM_CFG1_FUNC_BAR1_SIZE_2M 0x6
4790#define NVM_CFG1_FUNC_BAR1_SIZE_4M 0x7
4791#define NVM_CFG1_FUNC_BAR1_SIZE_8M 0x8
4792#define NVM_CFG1_FUNC_BAR1_SIZE_16M 0x9
4793#define NVM_CFG1_FUNC_BAR1_SIZE_32M 0xA
4794#define NVM_CFG1_FUNC_BAR1_SIZE_64M 0xB
4795#define NVM_CFG1_FUNC_BAR1_SIZE_128M 0xC
4796#define NVM_CFG1_FUNC_BAR1_SIZE_256M 0xD
4797#define NVM_CFG1_FUNC_BAR1_SIZE_512M 0xE
4798#define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
4799#define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
4800#define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
4801
4802 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
4803
4804 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
4805 u32 preboot_generic_cfg;
4806 u32 reserved[8];
4807};
4808
4809struct nvm_cfg1 {
4810 struct nvm_cfg1_glob glob;
4811
4812 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
4813
4814 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
4815
4816 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
4817};
4818
4819
4820
4821
4822
4823enum nvm_cfg_sections {
4824 NVM_CFG_SECTION_NVM_CFG1,
4825 NVM_CFG_SECTION_MAX
4826};
4827
4828struct nvm_cfg {
4829 u32 num_sections;
4830 u32 sections_offset[NVM_CFG_SECTION_MAX];
4831 struct nvm_cfg1 cfg1;
4832};
4833
4834#define PORT_0 0
4835#define PORT_1 1
4836#define PORT_2 2
4837#define PORT_3 3
4838
4839extern struct spad_layout g_spad;
4840
4841#define MCP_SPAD_SIZE 0x00028000
4842
4843#define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
4844
4845#define TO_OFFSIZE(_offset, _size) \
4846 (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
4847 (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
4848
4849enum spad_sections {
4850 SPAD_SECTION_TRACE,
4851 SPAD_SECTION_NVM_CFG,
4852 SPAD_SECTION_PUBLIC,
4853 SPAD_SECTION_PRIVATE,
4854 SPAD_SECTION_MAX
4855};
4856
4857struct spad_layout {
4858 struct nvm_cfg nvm_cfg;
4859 struct mcp_public_data public_data;
4860};
4861
4862#define CRC_MAGIC_VALUE 0xDEBB20E3
4863#define CRC32_POLYNOMIAL 0xEDB88320
4864#define NVM_CRC_SIZE (sizeof(u32))
4865
4866enum nvm_sw_arbitrator {
4867 NVM_SW_ARB_HOST,
4868 NVM_SW_ARB_MCP,
4869 NVM_SW_ARB_UART,
4870 NVM_SW_ARB_RESERVED
4871};
4872
4873
4874
4875
4876struct legacy_bootstrap_region {
4877 u32 magic_value;
4878#define NVM_MAGIC_VALUE 0x669955aa
4879 u32 sram_start_addr;
4880 u32 code_len;
4881 u32 code_start_addr;
4882 u32 crc;
4883};
4884
4885
4886
4887
4888struct nvm_code_entry {
4889 u32 image_type;
4890 u32 nvm_start_addr;
4891 u32 len;
4892 u32 sram_start_addr;
4893 u32 sram_run_addr;
4894};
4895
4896enum nvm_image_type {
4897 NVM_TYPE_TIM1 = 0x01,
4898 NVM_TYPE_TIM2 = 0x02,
4899 NVM_TYPE_MIM1 = 0x03,
4900 NVM_TYPE_MIM2 = 0x04,
4901 NVM_TYPE_MBA = 0x05,
4902 NVM_TYPE_MODULES_PN = 0x06,
4903 NVM_TYPE_VPD = 0x07,
4904 NVM_TYPE_MFW_TRACE1 = 0x08,
4905 NVM_TYPE_MFW_TRACE2 = 0x09,
4906 NVM_TYPE_NVM_CFG1 = 0x0a,
4907 NVM_TYPE_L2B = 0x0b,
4908 NVM_TYPE_DIR1 = 0x0c,
4909 NVM_TYPE_EAGLE_FW1 = 0x0d,
4910 NVM_TYPE_FALCON_FW1 = 0x0e,
4911 NVM_TYPE_PCIE_FW1 = 0x0f,
4912 NVM_TYPE_HW_SET = 0x10,
4913 NVM_TYPE_LIM = 0x11,
4914 NVM_TYPE_AVS_FW1 = 0x12,
4915 NVM_TYPE_DIR2 = 0x13,
4916 NVM_TYPE_CCM = 0x14,
4917 NVM_TYPE_EAGLE_FW2 = 0x15,
4918 NVM_TYPE_FALCON_FW2 = 0x16,
4919 NVM_TYPE_PCIE_FW2 = 0x17,
4920 NVM_TYPE_AVS_FW2 = 0x18,
4921
4922 NVM_TYPE_MAX,
4923};
4924
4925#define MAX_NVM_DIR_ENTRIES 200
4926
4927struct nvm_dir {
4928 s32 seq;
4929#define NVM_DIR_NEXT_MFW_MASK 0x00000001
4930#define NVM_DIR_SEQ_MASK 0xfffffffe
4931#define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
4932
4933#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
4934
4935 u32 num_images;
4936 u32 rsrv;
4937 struct nvm_code_entry code[1];
4938};
4939
4940#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + \
4941 (_num_images - \
4942 1) * sizeof(struct nvm_code_entry) + \
4943 NVM_CRC_SIZE)
4944
4945struct nvm_vpd_image {
4946 u32 format_revision;
4947#define VPD_IMAGE_VERSION 1
4948
4949
4950 u8 vpd_data[1];
4951};
4952
4953
4954
4955
4956#define DIR_ID_1 (0)
4957#define DIR_ID_2 (1)
4958#define MAX_DIR_IDS (2)
4959
4960#define MFW_BUNDLE_1 (0)
4961#define MFW_BUNDLE_2 (1)
4962#define MAX_MFW_BUNDLES (2)
4963
4964#define FLASH_PAGE_SIZE 0x1000
4965#define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE)
4966#define ASIC_MIM_MAX_SIZE (300 * FLASH_PAGE_SIZE)
4967#define FPGA_MIM_MAX_SIZE (25 * FLASH_PAGE_SIZE)
4968
4969#define LIM_MAX_SIZE ((2 * \
4970 FLASH_PAGE_SIZE) - \
4971 sizeof(struct legacy_bootstrap_region) - \
4972 NVM_RSV_SIZE)
4973#define LIM_OFFSET (NVM_OFFSET(lim_image))
4974#define NVM_RSV_SIZE (44)
4975#define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : \
4976 FPGA_MIM_MAX_SIZE)
4977#define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + \
4978 ((idx == \
4979 NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
4980#define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + \
4981 MIM_MAX_SIZE(is_asic) * 2)
4982
4983union nvm_dir_union {
4984 struct nvm_dir dir;
4985 u8 page[FLASH_PAGE_SIZE];
4986};
4987
4988
4989
4990
4991
4992
4993
4994
4995
4996
4997
4998
4999
5000
5001
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015
5016
5017
5018
5019
5020struct nvm_image {
5021
5022
5023 struct legacy_bootstrap_region bootstrap;
5024 u8 rsrv[NVM_RSV_SIZE];
5025 u8 lim_image[LIM_MAX_SIZE];
5026 union nvm_dir_union dir[MAX_MFW_BUNDLES];
5027
5028
5029
5030
5031};
5032
5033#define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image *)0)->f))))
5034
5035struct hw_set_info {
5036 u32 reg_type;
5037#define GRC_REG_TYPE 1
5038#define PHY_REG_TYPE 2
5039#define PCI_REG_TYPE 4
5040
5041 u32 bank_num;
5042 u32 pf_num;
5043 u32 operation;
5044#define READ_OP 1
5045#define WRITE_OP 2
5046#define RMW_SET_OP 3
5047#define RMW_CLR_OP 4
5048
5049 u32 reg_addr;
5050 u32 reg_data;
5051
5052 u32 reset_type;
5053#define POR_RESET_TYPE BIT(0)
5054#define HARD_RESET_TYPE BIT(1)
5055#define CORE_RESET_TYPE BIT(2)
5056#define MCP_RESET_TYPE BIT(3)
5057#define PERSET_ASSERT BIT(4)
5058#define PERSET_DEASSERT BIT(5)
5059};
5060
5061struct hw_set_image {
5062 u32 format_version;
5063#define HW_SET_IMAGE_VERSION 1
5064 u32 no_hw_sets;
5065
5066
5067 struct hw_set_info hw_sets[1];
5068};
5069
5070#endif
5071