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23#include <linux/io.h>
24#include "common.h"
25#include "dwmac_dma.h"
26
27#define GMAC_HI_REG_AE 0x80000000
28
29int dwmac_dma_reset(void __iomem *ioaddr)
30{
31 u32 value = readl(ioaddr + DMA_BUS_MODE);
32 int limit;
33
34
35 value |= DMA_BUS_MODE_SFT_RESET;
36 writel(value, ioaddr + DMA_BUS_MODE);
37 limit = 10;
38 while (limit--) {
39 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
40 break;
41 mdelay(10);
42 }
43
44 if (limit < 0)
45 return -EBUSY;
46
47 return 0;
48}
49
50
51void dwmac_enable_dma_transmission(void __iomem *ioaddr)
52{
53 writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
54}
55
56void dwmac_enable_dma_irq(void __iomem *ioaddr)
57{
58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
59}
60
61void dwmac_disable_dma_irq(void __iomem *ioaddr)
62{
63 writel(0, ioaddr + DMA_INTR_ENA);
64}
65
66void dwmac_dma_start_tx(void __iomem *ioaddr)
67{
68 u32 value = readl(ioaddr + DMA_CONTROL);
69 value |= DMA_CONTROL_ST;
70 writel(value, ioaddr + DMA_CONTROL);
71}
72
73void dwmac_dma_stop_tx(void __iomem *ioaddr)
74{
75 u32 value = readl(ioaddr + DMA_CONTROL);
76 value &= ~DMA_CONTROL_ST;
77 writel(value, ioaddr + DMA_CONTROL);
78}
79
80void dwmac_dma_start_rx(void __iomem *ioaddr)
81{
82 u32 value = readl(ioaddr + DMA_CONTROL);
83 value |= DMA_CONTROL_SR;
84 writel(value, ioaddr + DMA_CONTROL);
85}
86
87void dwmac_dma_stop_rx(void __iomem *ioaddr)
88{
89 u32 value = readl(ioaddr + DMA_CONTROL);
90 value &= ~DMA_CONTROL_SR;
91 writel(value, ioaddr + DMA_CONTROL);
92}
93
94#ifdef DWMAC_DMA_DEBUG
95static void show_tx_process_state(unsigned int status)
96{
97 unsigned int state;
98 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
99
100 switch (state) {
101 case 0:
102 pr_debug("- TX (Stopped): Reset or Stop command\n");
103 break;
104 case 1:
105 pr_debug("- TX (Running):Fetching the Tx desc\n");
106 break;
107 case 2:
108 pr_debug("- TX (Running): Waiting for end of tx\n");
109 break;
110 case 3:
111 pr_debug("- TX (Running): Reading the data "
112 "and queuing the data into the Tx buf\n");
113 break;
114 case 6:
115 pr_debug("- TX (Suspended): Tx Buff Underflow "
116 "or an unavailable Transmit descriptor\n");
117 break;
118 case 7:
119 pr_debug("- TX (Running): Closing Tx descriptor\n");
120 break;
121 default:
122 break;
123 }
124}
125
126static void show_rx_process_state(unsigned int status)
127{
128 unsigned int state;
129 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
130
131 switch (state) {
132 case 0:
133 pr_debug("- RX (Stopped): Reset or Stop command\n");
134 break;
135 case 1:
136 pr_debug("- RX (Running): Fetching the Rx desc\n");
137 break;
138 case 2:
139 pr_debug("- RX (Running):Checking for end of pkt\n");
140 break;
141 case 3:
142 pr_debug("- RX (Running): Waiting for Rx pkt\n");
143 break;
144 case 4:
145 pr_debug("- RX (Suspended): Unavailable Rx buf\n");
146 break;
147 case 5:
148 pr_debug("- RX (Running): Closing Rx descriptor\n");
149 break;
150 case 6:
151 pr_debug("- RX(Running): Flushing the current frame"
152 " from the Rx buf\n");
153 break;
154 case 7:
155 pr_debug("- RX (Running): Queuing the Rx frame"
156 " from the Rx buf into memory\n");
157 break;
158 default:
159 break;
160 }
161}
162#endif
163
164int dwmac_dma_interrupt(void __iomem *ioaddr,
165 struct stmmac_extra_stats *x)
166{
167 int ret = 0;
168
169 u32 intr_status = readl(ioaddr + DMA_STATUS);
170
171#ifdef DWMAC_DMA_DEBUG
172
173 pr_debug("%s: [CSR5: 0x%08x]\n", __func__, intr_status);
174 show_tx_process_state(intr_status);
175 show_rx_process_state(intr_status);
176#endif
177
178 if (unlikely(intr_status & DMA_STATUS_AIS)) {
179 if (unlikely(intr_status & DMA_STATUS_UNF)) {
180 ret = tx_hard_error_bump_tc;
181 x->tx_undeflow_irq++;
182 }
183 if (unlikely(intr_status & DMA_STATUS_TJT))
184 x->tx_jabber_irq++;
185
186 if (unlikely(intr_status & DMA_STATUS_OVF))
187 x->rx_overflow_irq++;
188
189 if (unlikely(intr_status & DMA_STATUS_RU))
190 x->rx_buf_unav_irq++;
191 if (unlikely(intr_status & DMA_STATUS_RPS))
192 x->rx_process_stopped_irq++;
193 if (unlikely(intr_status & DMA_STATUS_RWT))
194 x->rx_watchdog_irq++;
195 if (unlikely(intr_status & DMA_STATUS_ETI))
196 x->tx_early_irq++;
197 if (unlikely(intr_status & DMA_STATUS_TPS)) {
198 x->tx_process_stopped_irq++;
199 ret = tx_hard_error;
200 }
201 if (unlikely(intr_status & DMA_STATUS_FBI)) {
202 x->fatal_bus_error_irq++;
203 ret = tx_hard_error;
204 }
205 }
206
207 if (likely(intr_status & DMA_STATUS_NIS)) {
208 x->normal_irq_n++;
209 if (likely(intr_status & DMA_STATUS_RI)) {
210 u32 value = readl(ioaddr + DMA_INTR_ENA);
211
212 if (likely(value & DMA_INTR_ENA_RIE)) {
213 x->rx_normal_irq_n++;
214 ret |= handle_rx;
215 }
216 }
217 if (likely(intr_status & DMA_STATUS_TI)) {
218 x->tx_normal_irq_n++;
219 ret |= handle_tx;
220 }
221 if (unlikely(intr_status & DMA_STATUS_ERI))
222 x->rx_early_irq++;
223 }
224
225 if (unlikely(intr_status &
226 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
227 pr_warn("%s: unexpected status %08x\n", __func__, intr_status);
228
229
230 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
231
232 return ret;
233}
234
235void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr)
236{
237 u32 csr6 = readl(ioaddr + DMA_CONTROL);
238 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
239
240 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
241}
242
243void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6],
244 unsigned int high, unsigned int low)
245{
246 unsigned long data;
247
248 data = (addr[5] << 8) | addr[4];
249
250
251
252
253 writel(data | GMAC_HI_REG_AE, ioaddr + high);
254 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
255 writel(data, ioaddr + low);
256}
257
258
259void stmmac_set_mac(void __iomem *ioaddr, bool enable)
260{
261 u32 value = readl(ioaddr + MAC_CTRL_REG);
262
263 if (enable)
264 value |= MAC_RNABLE_RX | MAC_ENABLE_TX;
265 else
266 value &= ~(MAC_ENABLE_TX | MAC_RNABLE_RX);
267
268 writel(value, ioaddr + MAC_CTRL_REG);
269}
270
271void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr,
272 unsigned int high, unsigned int low)
273{
274 unsigned int hi_addr, lo_addr;
275
276
277 hi_addr = readl(ioaddr + high);
278 lo_addr = readl(ioaddr + low);
279
280
281 addr[0] = lo_addr & 0xff;
282 addr[1] = (lo_addr >> 8) & 0xff;
283 addr[2] = (lo_addr >> 16) & 0xff;
284 addr[3] = (lo_addr >> 24) & 0xff;
285 addr[4] = hi_addr & 0xff;
286 addr[5] = (hi_addr >> 8) & 0xff;
287}
288
289