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32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/sched.h>
35#include <linux/string.h>
36#include <linux/timer.h>
37#include <linux/errno.h>
38#include <linux/in.h>
39#include <linux/ioport.h>
40#include <linux/slab.h>
41#include <linux/mm.h>
42#include <linux/interrupt.h>
43#include <linux/init.h>
44#include <linux/netdevice.h>
45#include <linux/etherdevice.h>
46#include <linux/skbuff.h>
47#include <linux/ethtool.h>
48#include <linux/highmem.h>
49#include <linux/proc_fs.h>
50#include <linux/ctype.h>
51#include <linux/spinlock.h>
52#include <linux/dma-mapping.h>
53#include <linux/clk.h>
54#include <linux/platform_device.h>
55#include <linux/regmap.h>
56#include <linux/semaphore.h>
57#include <linux/phy.h>
58#include <linux/bitops.h>
59#include <linux/io.h>
60#include <linux/uaccess.h>
61#include <linux/pm_runtime.h>
62#include <linux/davinci_emac.h>
63#include <linux/of.h>
64#include <linux/of_address.h>
65#include <linux/of_device.h>
66#include <linux/of_mdio.h>
67#include <linux/of_irq.h>
68#include <linux/of_net.h>
69#include <linux/mfd/syscon.h>
70
71#include <asm/irq.h>
72#include <asm/page.h>
73
74#include "cpsw.h"
75#include "davinci_cpdma.h"
76
77static int debug_level;
78module_param(debug_level, int, 0);
79MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)");
80
81
82#define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \
83 NETIF_MSG_PROBE | \
84 NETIF_MSG_LINK | \
85 NETIF_MSG_TIMER | \
86 NETIF_MSG_IFDOWN | \
87 NETIF_MSG_IFUP | \
88 NETIF_MSG_RX_ERR | \
89 NETIF_MSG_TX_ERR | \
90 NETIF_MSG_TX_QUEUED | \
91 NETIF_MSG_INTR | \
92 NETIF_MSG_TX_DONE | \
93 NETIF_MSG_RX_STATUS | \
94 NETIF_MSG_PKTDATA | \
95 NETIF_MSG_HW | \
96 NETIF_MSG_WOL)
97
98
99#define EMAC_MAJOR_VERSION 6
100#define EMAC_MINOR_VERSION 1
101#define EMAC_MODULE_VERSION "6.1"
102MODULE_VERSION(EMAC_MODULE_VERSION);
103static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
104
105
106#define EMAC_DEF_PASS_CRC (0)
107#define EMAC_DEF_QOS_EN (0)
108#define EMAC_DEF_NO_BUFF_CHAIN (0)
109#define EMAC_DEF_MACCTRL_FRAME_EN (0)
110#define EMAC_DEF_SHORT_FRAME_EN (0)
111#define EMAC_DEF_ERROR_FRAME_EN (0)
112#define EMAC_DEF_PROM_EN (0)
113#define EMAC_DEF_PROM_CH (0)
114#define EMAC_DEF_BCAST_EN (1)
115#define EMAC_DEF_BCAST_CH (0)
116#define EMAC_DEF_MCAST_EN (1)
117#define EMAC_DEF_MCAST_CH (0)
118
119#define EMAC_DEF_TXPRIO_FIXED (1)
120#define EMAC_DEF_TXPACING_EN (0)
121
122#define EMAC_DEF_BUFFER_OFFSET (0)
123#define EMAC_DEF_MIN_ETHPKTSIZE (60)
124#define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4)
125#define EMAC_DEF_TX_CH (0)
126#define EMAC_DEF_RX_CH (0)
127#define EMAC_DEF_RX_NUM_DESC (128)
128#define EMAC_DEF_MAX_TX_CH (1)
129#define EMAC_DEF_MAX_RX_CH (1)
130#define EMAC_POLL_WEIGHT (64)
131
132
133#define EMAC_DEF_TX_MAX_SERVICE (32)
134#define EMAC_DEF_RX_MAX_SERVICE (64)
135
136
137#define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF)
138#define EMAC_NUM_MULTICAST_BITS (64)
139#define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1)
140#define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1)
141#define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2)
142#define EMAC_RX_UNICAST_CLEAR_ALL (0xFF)
143#define EMAC_INT_MASK_CLEAR (0xFF)
144
145
146#define EMAC_RXMBP_PASSCRC_MASK BIT(30)
147#define EMAC_RXMBP_QOSEN_MASK BIT(29)
148#define EMAC_RXMBP_NOCHAIN_MASK BIT(28)
149#define EMAC_RXMBP_CMFEN_MASK BIT(24)
150#define EMAC_RXMBP_CSFEN_MASK BIT(23)
151#define EMAC_RXMBP_CEFEN_MASK BIT(22)
152#define EMAC_RXMBP_CAFEN_MASK BIT(21)
153#define EMAC_RXMBP_PROMCH_SHIFT (16)
154#define EMAC_RXMBP_PROMCH_MASK (0x7 << 16)
155#define EMAC_RXMBP_BROADEN_MASK BIT(13)
156#define EMAC_RXMBP_BROADCH_SHIFT (8)
157#define EMAC_RXMBP_BROADCH_MASK (0x7 << 8)
158#define EMAC_RXMBP_MULTIEN_MASK BIT(5)
159#define EMAC_RXMBP_MULTICH_SHIFT (0)
160#define EMAC_RXMBP_MULTICH_MASK (0x7)
161#define EMAC_RXMBP_CHMASK (0x7)
162
163
164# define EMAC_MBP_RXPROMISC (0x00200000)
165# define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16)
166# define EMAC_MBP_RXBCAST (0x00002000)
167# define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8)
168# define EMAC_MBP_RXMCAST (0x00000020)
169# define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7)
170
171
172#define EMAC_MACCONTROL_TXPTYPE BIT(9)
173#define EMAC_MACCONTROL_TXPACEEN BIT(6)
174#define EMAC_MACCONTROL_GMIIEN BIT(5)
175#define EMAC_MACCONTROL_GIGABITEN BIT(7)
176#define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0)
177#define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15)
178
179
180#define EMAC_DM646X_MACCONTORL_GIG BIT(7)
181#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
182
183
184#define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000)
185#define EMAC_MACSTATUS_TXERRCODE_SHIFT (20)
186#define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
187#define EMAC_MACSTATUS_TXERRCH_SHIFT (16)
188#define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000)
189#define EMAC_MACSTATUS_RXERRCODE_SHIFT (12)
190#define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
191#define EMAC_MACSTATUS_RXERRCH_SHIFT (8)
192
193
194#define EMAC_RX_MAX_LEN_MASK (0xFFFF)
195#define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF)
196
197
198#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17)
199#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16)
200#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8)
201#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0)
202
203
204#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH)
205#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH)
206#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26)
207#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27)
208
209
210#define EMAC_CPPI_SOP_BIT BIT(31)
211#define EMAC_CPPI_EOP_BIT BIT(30)
212#define EMAC_CPPI_OWNERSHIP_BIT BIT(29)
213#define EMAC_CPPI_EOQ_BIT BIT(28)
214#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
215#define EMAC_CPPI_PASS_CRC_BIT BIT(26)
216#define EMAC_RX_BD_BUF_SIZE (0xFFFF)
217#define EMAC_BD_LENGTH_FOR_CACHE (16)
218#define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF)
219
220
221#define EMAC_MAX_TXRX_CHANNELS (8)
222#define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64)
223
224
225#define EMAC_MACINVECTOR 0x90
226
227#define EMAC_DM646X_MACEOIVECTOR 0x94
228
229#define EMAC_MACINTSTATRAW 0xB0
230#define EMAC_MACINTSTATMASKED 0xB4
231#define EMAC_MACINTMASKSET 0xB8
232#define EMAC_MACINTMASKCLEAR 0xBC
233
234#define EMAC_RXMBPENABLE 0x100
235#define EMAC_RXUNICASTSET 0x104
236#define EMAC_RXUNICASTCLEAR 0x108
237#define EMAC_RXMAXLEN 0x10C
238#define EMAC_RXBUFFEROFFSET 0x110
239#define EMAC_RXFILTERLOWTHRESH 0x114
240
241#define EMAC_MACCONTROL 0x160
242#define EMAC_MACSTATUS 0x164
243#define EMAC_EMCONTROL 0x168
244#define EMAC_FIFOCONTROL 0x16C
245#define EMAC_MACCONFIG 0x170
246#define EMAC_SOFTRESET 0x174
247#define EMAC_MACSRCADDRLO 0x1D0
248#define EMAC_MACSRCADDRHI 0x1D4
249#define EMAC_MACHASH1 0x1D8
250#define EMAC_MACHASH2 0x1DC
251#define EMAC_MACADDRLO 0x500
252#define EMAC_MACADDRHI 0x504
253#define EMAC_MACINDEX 0x508
254
255
256#define EMAC_RXGOODFRAMES 0x200
257#define EMAC_RXBCASTFRAMES 0x204
258#define EMAC_RXMCASTFRAMES 0x208
259#define EMAC_RXPAUSEFRAMES 0x20C
260#define EMAC_RXCRCERRORS 0x210
261#define EMAC_RXALIGNCODEERRORS 0x214
262#define EMAC_RXOVERSIZED 0x218
263#define EMAC_RXJABBER 0x21C
264#define EMAC_RXUNDERSIZED 0x220
265#define EMAC_RXFRAGMENTS 0x224
266#define EMAC_RXFILTERED 0x228
267#define EMAC_RXQOSFILTERED 0x22C
268#define EMAC_RXOCTETS 0x230
269#define EMAC_TXGOODFRAMES 0x234
270#define EMAC_TXBCASTFRAMES 0x238
271#define EMAC_TXMCASTFRAMES 0x23C
272#define EMAC_TXPAUSEFRAMES 0x240
273#define EMAC_TXDEFERRED 0x244
274#define EMAC_TXCOLLISION 0x248
275#define EMAC_TXSINGLECOLL 0x24C
276#define EMAC_TXMULTICOLL 0x250
277#define EMAC_TXEXCESSIVECOLL 0x254
278#define EMAC_TXLATECOLL 0x258
279#define EMAC_TXUNDERRUN 0x25C
280#define EMAC_TXCARRIERSENSE 0x260
281#define EMAC_TXOCTETS 0x264
282#define EMAC_NETOCTETS 0x280
283#define EMAC_RXSOFOVERRUNS 0x284
284#define EMAC_RXMOFOVERRUNS 0x288
285#define EMAC_RXDMAOVERRUNS 0x28C
286
287
288#define EMAC_CTRL_EWCTL (0x4)
289#define EMAC_CTRL_EWINTTCNT (0x8)
290
291
292#define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF
293#define EMAC_DM644X_INTMIN_INTVL 0x1
294#define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK)
295
296
297#define EMAC_DM646X_CMINTCTRL 0x0C
298#define EMAC_DM646X_CMRXINTEN 0x14
299#define EMAC_DM646X_CMTXINTEN 0x18
300#define EMAC_DM646X_CMRXINTMAX 0x70
301#define EMAC_DM646X_CMTXINTMAX 0x74
302
303
304#define EMAC_DM646X_INTPACEEN (0x3 << 16)
305#define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0)
306#define EMAC_DM646X_CMINTMAX_CNT 63
307#define EMAC_DM646X_CMINTMIN_CNT 2
308#define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT)
309#define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1)
310
311
312
313#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
314#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
315
316
317#define EMAC_STATS_CLR_MASK (0xFFFFFFFF)
318
319
320
321
322
323struct emac_priv {
324 u32 msg_enable;
325 struct net_device *ndev;
326 struct platform_device *pdev;
327 struct napi_struct napi;
328 char mac_addr[6];
329 void __iomem *remap_addr;
330 u32 emac_base_phys;
331 void __iomem *emac_base;
332 void __iomem *ctrl_base;
333 struct cpdma_ctlr *dma;
334 struct cpdma_chan *txchan;
335 struct cpdma_chan *rxchan;
336 u32 link;
337 u32 speed;
338 u32 duplex;
339 u32 rx_buf_size;
340 u32 isr_count;
341 u32 coal_intvl;
342 u32 bus_freq_mhz;
343 u8 rmii_en;
344 u8 version;
345 u32 mac_hash1;
346 u32 mac_hash2;
347 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
348 u32 rx_addr_type;
349 const char *phy_id;
350 struct device_node *phy_node;
351 struct phy_device *phydev;
352 spinlock_t lock;
353
354 void (*int_enable) (void);
355 void (*int_disable) (void);
356};
357
358
359static char *emac_txhost_errcodes[16] = {
360 "No error", "SOP error", "Ownership bit not set in SOP buffer",
361 "Zero Next Buffer Descriptor Pointer Without EOP",
362 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
363 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
364 "Reserved", "Reserved", "Reserved", "Reserved"
365};
366
367
368static char *emac_rxhost_errcodes[16] = {
369 "No error", "Reserved", "Ownership bit not set in input buffer",
370 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
371 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
372 "Reserved", "Reserved", "Reserved", "Reserved"
373};
374
375
376#define emac_read(reg) ioread32(priv->emac_base + (reg))
377#define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg))
378
379#define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg)))
380#define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg)))
381
382
383
384
385
386
387
388
389static void emac_dump_regs(struct emac_priv *priv)
390{
391 struct device *emac_dev = &priv->ndev->dev;
392
393
394 dev_info(emac_dev, "EMAC Basic registers\n");
395 if (priv->version == EMAC_VERSION_1) {
396 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n",
397 emac_ctrl_read(EMAC_CTRL_EWCTL),
398 emac_ctrl_read(EMAC_CTRL_EWINTTCNT));
399 }
400 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n",
401 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL));
402 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\
403 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE),
404 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN));
405 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\
406 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL),
407 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG));
408 dev_info(emac_dev, "EMAC Statistics\n");
409 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n",
410 emac_read(EMAC_RXGOODFRAMES));
411 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n",
412 emac_read(EMAC_RXBCASTFRAMES));
413 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n",
414 emac_read(EMAC_RXMCASTFRAMES));
415 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n",
416 emac_read(EMAC_RXPAUSEFRAMES));
417 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n",
418 emac_read(EMAC_RXCRCERRORS));
419 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n",
420 emac_read(EMAC_RXALIGNCODEERRORS));
421 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n",
422 emac_read(EMAC_RXOVERSIZED));
423 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n",
424 emac_read(EMAC_RXJABBER));
425 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n",
426 emac_read(EMAC_RXUNDERSIZED));
427 dev_info(emac_dev, "EMAC: rx_fragments:%d\n",
428 emac_read(EMAC_RXFRAGMENTS));
429 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n",
430 emac_read(EMAC_RXFILTERED));
431 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n",
432 emac_read(EMAC_RXQOSFILTERED));
433 dev_info(emac_dev, "EMAC: rx_octets:%d\n",
434 emac_read(EMAC_RXOCTETS));
435 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n",
436 emac_read(EMAC_TXGOODFRAMES));
437 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n",
438 emac_read(EMAC_TXBCASTFRAMES));
439 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n",
440 emac_read(EMAC_TXMCASTFRAMES));
441 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n",
442 emac_read(EMAC_TXPAUSEFRAMES));
443 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n",
444 emac_read(EMAC_TXDEFERRED));
445 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n",
446 emac_read(EMAC_TXCOLLISION));
447 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n",
448 emac_read(EMAC_TXSINGLECOLL));
449 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n",
450 emac_read(EMAC_TXMULTICOLL));
451 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n",
452 emac_read(EMAC_TXEXCESSIVECOLL));
453 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n",
454 emac_read(EMAC_TXLATECOLL));
455 dev_info(emac_dev, "EMAC: tx_underrun:%d\n",
456 emac_read(EMAC_TXUNDERRUN));
457 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n",
458 emac_read(EMAC_TXCARRIERSENSE));
459 dev_info(emac_dev, "EMAC: tx_octets:%d\n",
460 emac_read(EMAC_TXOCTETS));
461 dev_info(emac_dev, "EMAC: net_octets:%d\n",
462 emac_read(EMAC_NETOCTETS));
463 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n",
464 emac_read(EMAC_RXSOFOVERRUNS));
465 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n",
466 emac_read(EMAC_RXMOFOVERRUNS));
467 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n",
468 emac_read(EMAC_RXDMAOVERRUNS));
469
470 cpdma_ctlr_dump(priv->dma);
471}
472
473
474
475
476
477
478
479
480
481static void emac_get_drvinfo(struct net_device *ndev,
482 struct ethtool_drvinfo *info)
483{
484 strlcpy(info->driver, emac_version_string, sizeof(info->driver));
485 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version));
486}
487
488
489
490
491
492
493
494
495
496static int emac_get_settings(struct net_device *ndev,
497 struct ethtool_cmd *ecmd)
498{
499 struct emac_priv *priv = netdev_priv(ndev);
500 if (priv->phydev)
501 return phy_ethtool_gset(priv->phydev, ecmd);
502 else
503 return -EOPNOTSUPP;
504
505}
506
507
508
509
510
511
512
513
514
515static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
516{
517 struct emac_priv *priv = netdev_priv(ndev);
518 if (priv->phydev)
519 return phy_ethtool_sset(priv->phydev, ecmd);
520 else
521 return -EOPNOTSUPP;
522
523}
524
525
526
527
528
529
530
531
532
533static int emac_get_coalesce(struct net_device *ndev,
534 struct ethtool_coalesce *coal)
535{
536 struct emac_priv *priv = netdev_priv(ndev);
537
538 coal->rx_coalesce_usecs = priv->coal_intvl;
539 return 0;
540
541}
542
543
544
545
546
547
548
549
550
551static int emac_set_coalesce(struct net_device *ndev,
552 struct ethtool_coalesce *coal)
553{
554 struct emac_priv *priv = netdev_priv(ndev);
555 u32 int_ctrl, num_interrupts = 0;
556 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0;
557
558 if (!coal->rx_coalesce_usecs)
559 return -EINVAL;
560
561 coal_intvl = coal->rx_coalesce_usecs;
562
563 switch (priv->version) {
564 case EMAC_VERSION_2:
565 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL);
566 prescale = priv->bus_freq_mhz * 4;
567
568 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL)
569 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL;
570
571 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) {
572
573
574
575
576 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale;
577
578 if (addnl_dvdr > 1) {
579 prescale *= addnl_dvdr;
580 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL
581 * addnl_dvdr))
582 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL
583 * addnl_dvdr);
584 } else {
585 addnl_dvdr = 1;
586 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL;
587 }
588 }
589
590 num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
591
592 int_ctrl |= EMAC_DM646X_INTPACEEN;
593 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK);
594 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK);
595 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl);
596
597 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts);
598 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts);
599
600 break;
601 default:
602 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT);
603 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK);
604 prescale = coal_intvl * priv->bus_freq_mhz;
605 if (prescale > EMAC_DM644X_EWINTCNT_MASK) {
606 prescale = EMAC_DM644X_EWINTCNT_MASK;
607 coal_intvl = prescale / priv->bus_freq_mhz;
608 }
609 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale));
610
611 break;
612 }
613
614 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl);
615 priv->coal_intvl = coal_intvl;
616
617 return 0;
618
619}
620
621
622
623
624
625
626static const struct ethtool_ops ethtool_ops = {
627 .get_drvinfo = emac_get_drvinfo,
628 .get_settings = emac_get_settings,
629 .set_settings = emac_set_settings,
630 .get_link = ethtool_op_get_link,
631 .get_coalesce = emac_get_coalesce,
632 .set_coalesce = emac_set_coalesce,
633 .get_ts_info = ethtool_op_get_ts_info,
634};
635
636
637
638
639
640
641
642
643
644static void emac_update_phystatus(struct emac_priv *priv)
645{
646 u32 mac_control;
647 u32 new_duplex;
648 u32 cur_duplex;
649 struct net_device *ndev = priv->ndev;
650
651 mac_control = emac_read(EMAC_MACCONTROL);
652 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
653 DUPLEX_FULL : DUPLEX_HALF;
654 if (priv->phydev)
655 new_duplex = priv->phydev->duplex;
656 else
657 new_duplex = DUPLEX_FULL;
658
659
660 if ((priv->link) && (new_duplex != cur_duplex)) {
661 priv->duplex = new_duplex;
662 if (DUPLEX_FULL == priv->duplex)
663 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
664 else
665 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
666 }
667
668 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
669 mac_control = emac_read(EMAC_MACCONTROL);
670 mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
671 EMAC_DM646X_MACCONTORL_GIGFORCE);
672 } else {
673
674 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
675 EMAC_DM646X_MACCONTORL_GIG);
676
677 if (priv->rmii_en && (priv->speed == SPEED_100))
678 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
679 else
680 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
681 }
682
683
684 emac_write(EMAC_MACCONTROL, mac_control);
685
686 if (priv->link) {
687
688 if (!netif_carrier_ok(ndev))
689 netif_carrier_on(ndev);
690
691 if (netif_running(ndev) && netif_queue_stopped(ndev))
692 netif_wake_queue(ndev);
693 } else {
694
695 if (netif_carrier_ok(ndev))
696 netif_carrier_off(ndev);
697 if (!netif_queue_stopped(ndev))
698 netif_stop_queue(ndev);
699 }
700}
701
702
703
704
705
706
707
708
709static u32 hash_get(u8 *addr)
710{
711 u32 hash;
712 u8 tmpval;
713 int cnt;
714 hash = 0;
715
716 for (cnt = 0; cnt < 2; cnt++) {
717 tmpval = *addr++;
718 hash ^= (tmpval >> 2) ^ (tmpval << 4);
719 tmpval = *addr++;
720 hash ^= (tmpval >> 4) ^ (tmpval << 2);
721 tmpval = *addr++;
722 hash ^= (tmpval >> 6) ^ (tmpval);
723 }
724
725 return hash & 0x3F;
726}
727
728
729
730
731
732
733
734
735
736static int hash_add(struct emac_priv *priv, u8 *mac_addr)
737{
738 struct device *emac_dev = &priv->ndev->dev;
739 u32 rc = 0;
740 u32 hash_bit;
741 u32 hash_value = hash_get(mac_addr);
742
743 if (hash_value >= EMAC_NUM_MULTICAST_BITS) {
744 if (netif_msg_drv(priv)) {
745 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\
746 "Hash %08x, should not be greater than %08x",
747 hash_value, (EMAC_NUM_MULTICAST_BITS - 1));
748 }
749 return -1;
750 }
751
752
753 if (priv->multicast_hash_cnt[hash_value] == 0) {
754 rc = 1;
755 if (hash_value < 32) {
756 hash_bit = BIT(hash_value);
757 priv->mac_hash1 |= hash_bit;
758 } else {
759 hash_bit = BIT((hash_value - 32));
760 priv->mac_hash2 |= hash_bit;
761 }
762 }
763
764
765 ++priv->multicast_hash_cnt[hash_value];
766
767 return rc;
768}
769
770
771
772
773
774
775
776
777
778static int hash_del(struct emac_priv *priv, u8 *mac_addr)
779{
780 u32 hash_value;
781 u32 hash_bit;
782
783 hash_value = hash_get(mac_addr);
784 if (priv->multicast_hash_cnt[hash_value] > 0) {
785
786 --priv->multicast_hash_cnt[hash_value];
787 }
788
789
790
791 if (priv->multicast_hash_cnt[hash_value] > 0)
792 return 0;
793
794 if (hash_value < 32) {
795 hash_bit = BIT(hash_value);
796 priv->mac_hash1 &= ~hash_bit;
797 } else {
798 hash_bit = BIT((hash_value - 32));
799 priv->mac_hash2 &= ~hash_bit;
800 }
801
802
803 return 1;
804}
805
806
807#define EMAC_MULTICAST_ADD 0
808#define EMAC_MULTICAST_DEL 1
809#define EMAC_ALL_MULTI_SET 2
810#define EMAC_ALL_MULTI_CLR 3
811
812
813
814
815
816
817
818
819
820
821static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr)
822{
823 struct device *emac_dev = &priv->ndev->dev;
824 int update = -1;
825
826 switch (action) {
827 case EMAC_MULTICAST_ADD:
828 update = hash_add(priv, mac_addr);
829 break;
830 case EMAC_MULTICAST_DEL:
831 update = hash_del(priv, mac_addr);
832 break;
833 case EMAC_ALL_MULTI_SET:
834 update = 1;
835 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE;
836 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE;
837 break;
838 case EMAC_ALL_MULTI_CLR:
839 update = 1;
840 priv->mac_hash1 = 0;
841 priv->mac_hash2 = 0;
842 memset(&(priv->multicast_hash_cnt[0]), 0,
843 sizeof(priv->multicast_hash_cnt[0]) *
844 EMAC_NUM_MULTICAST_BITS);
845 break;
846 default:
847 if (netif_msg_drv(priv))
848 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\
849 ": bad operation %d", action);
850 break;
851 }
852
853
854 if (update > 0) {
855 emac_write(EMAC_MACHASH1, priv->mac_hash1);
856 emac_write(EMAC_MACHASH2, priv->mac_hash2);
857 }
858}
859
860
861
862
863
864
865
866
867static void emac_dev_mcast_set(struct net_device *ndev)
868{
869 u32 mbp_enable;
870 struct emac_priv *priv = netdev_priv(ndev);
871
872 mbp_enable = emac_read(EMAC_RXMBPENABLE);
873 if (ndev->flags & IFF_PROMISC) {
874 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH));
875 mbp_enable |= (EMAC_MBP_RXPROMISC);
876 } else {
877 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC);
878 if ((ndev->flags & IFF_ALLMULTI) ||
879 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) {
880 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
881 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL);
882 } else if (!netdev_mc_empty(ndev)) {
883 struct netdev_hw_addr *ha;
884
885 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST);
886 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
887
888 netdev_for_each_mc_addr(ha, ndev) {
889 emac_add_mcast(priv, EMAC_MULTICAST_ADD,
890 (u8 *) ha->addr);
891 }
892 } else {
893 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST);
894 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL);
895 }
896 }
897
898 emac_write(EMAC_RXMBPENABLE, mbp_enable);
899}
900
901
902
903
904
905
906
907
908
909
910
911
912static void emac_int_disable(struct emac_priv *priv)
913{
914 if (priv->version == EMAC_VERSION_2) {
915 unsigned long flags;
916
917 local_irq_save(flags);
918
919
920
921 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
922 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
923
924 if (priv->int_disable)
925 priv->int_disable();
926
927
928
929
930 emac_write(EMAC_DM646X_MACEOIVECTOR,
931 EMAC_DM646X_MAC_EOI_C0_RXEN);
932
933
934 emac_write(EMAC_DM646X_MACEOIVECTOR,
935 EMAC_DM646X_MAC_EOI_C0_TXEN);
936
937 local_irq_restore(flags);
938
939 } else {
940
941 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
942 }
943}
944
945
946
947
948
949
950
951
952static void emac_int_enable(struct emac_priv *priv)
953{
954 if (priv->version == EMAC_VERSION_2) {
955 if (priv->int_enable)
956 priv->int_enable();
957
958 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
959 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
960
961
962
963
964
965
966 } else {
967
968 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
969 }
970}
971
972
973
974
975
976
977
978
979
980
981
982static irqreturn_t emac_irq(int irq, void *dev_id)
983{
984 struct net_device *ndev = (struct net_device *)dev_id;
985 struct emac_priv *priv = netdev_priv(ndev);
986
987 ++priv->isr_count;
988 if (likely(netif_running(priv->ndev))) {
989 emac_int_disable(priv);
990 napi_schedule(&priv->napi);
991 } else {
992
993 }
994 return IRQ_HANDLED;
995}
996
997static struct sk_buff *emac_rx_alloc(struct emac_priv *priv)
998{
999 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size);
1000 if (WARN_ON(!skb))
1001 return NULL;
1002 skb_reserve(skb, NET_IP_ALIGN);
1003 return skb;
1004}
1005
1006static void emac_rx_handler(void *token, int len, int status)
1007{
1008 struct sk_buff *skb = token;
1009 struct net_device *ndev = skb->dev;
1010 struct emac_priv *priv = netdev_priv(ndev);
1011 struct device *emac_dev = &ndev->dev;
1012 int ret;
1013
1014
1015 if (unlikely(!netif_running(ndev))) {
1016 dev_kfree_skb_any(skb);
1017 return;
1018 }
1019
1020
1021 if (status < 0) {
1022 ndev->stats.rx_errors++;
1023 goto recycle;
1024 }
1025
1026
1027 skb_put(skb, len);
1028 skb->protocol = eth_type_trans(skb, ndev);
1029 netif_receive_skb(skb);
1030 ndev->stats.rx_bytes += len;
1031 ndev->stats.rx_packets++;
1032
1033
1034 skb = emac_rx_alloc(priv);
1035 if (!skb) {
1036 if (netif_msg_rx_err(priv) && net_ratelimit())
1037 dev_err(emac_dev, "failed rx buffer alloc\n");
1038 return;
1039 }
1040
1041recycle:
1042 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1043 skb_tailroom(skb), 0);
1044
1045 WARN_ON(ret == -ENOMEM);
1046 if (unlikely(ret < 0))
1047 dev_kfree_skb_any(skb);
1048}
1049
1050static void emac_tx_handler(void *token, int len, int status)
1051{
1052 struct sk_buff *skb = token;
1053 struct net_device *ndev = skb->dev;
1054
1055
1056
1057
1058 if (unlikely(netif_queue_stopped(ndev)))
1059 netif_wake_queue(ndev);
1060 ndev->stats.tx_packets++;
1061 ndev->stats.tx_bytes += len;
1062 dev_kfree_skb_any(skb);
1063}
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
1076{
1077 struct device *emac_dev = &ndev->dev;
1078 int ret_code;
1079 struct emac_priv *priv = netdev_priv(ndev);
1080
1081
1082 if (unlikely(!priv->link)) {
1083 if (netif_msg_tx_err(priv) && net_ratelimit())
1084 dev_err(emac_dev, "DaVinci EMAC: No link to transmit");
1085 goto fail_tx;
1086 }
1087
1088 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE);
1089 if (unlikely(ret_code < 0)) {
1090 if (netif_msg_tx_err(priv) && net_ratelimit())
1091 dev_err(emac_dev, "DaVinci EMAC: packet pad failed");
1092 goto fail_tx;
1093 }
1094
1095 skb_tx_timestamp(skb);
1096
1097 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len,
1098 0);
1099 if (unlikely(ret_code != 0)) {
1100 if (netif_msg_tx_err(priv) && net_ratelimit())
1101 dev_err(emac_dev, "DaVinci EMAC: desc submit failed");
1102 goto fail_tx;
1103 }
1104
1105
1106
1107
1108 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan)))
1109 netif_stop_queue(ndev);
1110
1111 return NETDEV_TX_OK;
1112
1113fail_tx:
1114 ndev->stats.tx_dropped++;
1115 netif_stop_queue(ndev);
1116 return NETDEV_TX_BUSY;
1117}
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129static void emac_dev_tx_timeout(struct net_device *ndev)
1130{
1131 struct emac_priv *priv = netdev_priv(ndev);
1132 struct device *emac_dev = &ndev->dev;
1133
1134 if (netif_msg_tx_err(priv))
1135 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX");
1136
1137 emac_dump_regs(priv);
1138
1139 ndev->stats.tx_errors++;
1140 emac_int_disable(priv);
1141 cpdma_chan_stop(priv->txchan);
1142 cpdma_chan_start(priv->txchan);
1143 emac_int_enable(priv);
1144}
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1157{
1158 u32 val;
1159 val = ((mac_addr[5] << 8) | (mac_addr[4]));
1160 emac_write(EMAC_MACSRCADDRLO, val);
1161
1162 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1163 (mac_addr[1] << 8) | (mac_addr[0]));
1164 emac_write(EMAC_MACSRCADDRHI, val);
1165 val = emac_read(EMAC_RXUNICASTSET);
1166 val |= BIT(ch);
1167 emac_write(EMAC_RXUNICASTSET, val);
1168 val = emac_read(EMAC_RXUNICASTCLEAR);
1169 val &= ~BIT(ch);
1170 emac_write(EMAC_RXUNICASTCLEAR, val);
1171}
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr)
1184{
1185 u32 val;
1186 emac_write(EMAC_MACINDEX, ch);
1187 val = ((mac_addr[5] << 8) | mac_addr[4]);
1188 emac_write(EMAC_MACADDRLO, val);
1189 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1190 (mac_addr[1] << 8) | (mac_addr[0]));
1191 emac_write(EMAC_MACADDRHI, val);
1192 emac_set_type0addr(priv, ch, mac_addr);
1193}
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207static void emac_set_type2addr(struct emac_priv *priv, u32 ch,
1208 char *mac_addr, int index, int match)
1209{
1210 u32 val;
1211 emac_write(EMAC_MACINDEX, index);
1212 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
1213 (mac_addr[1] << 8) | (mac_addr[0]));
1214 emac_write(EMAC_MACADDRHI, val);
1215 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
1216 (match << 19) | BIT(20));
1217 emac_write(EMAC_MACADDRLO, val);
1218 emac_set_type0addr(priv, ch, mac_addr);
1219}
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr)
1232{
1233 struct device *emac_dev = &priv->ndev->dev;
1234
1235 if (priv->rx_addr_type == 0) {
1236 emac_set_type0addr(priv, ch, mac_addr);
1237 } else if (priv->rx_addr_type == 1) {
1238 u32 cnt;
1239 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
1240 emac_set_type1addr(priv, ch, mac_addr);
1241 } else if (priv->rx_addr_type == 2) {
1242 emac_set_type2addr(priv, ch, mac_addr, ch, 1);
1243 emac_set_type0addr(priv, ch, mac_addr);
1244 } else {
1245 if (netif_msg_drv(priv))
1246 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n");
1247 }
1248}
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259static int emac_dev_setmac_addr(struct net_device *ndev, void *addr)
1260{
1261 struct emac_priv *priv = netdev_priv(ndev);
1262 struct device *emac_dev = &priv->ndev->dev;
1263 struct sockaddr *sa = addr;
1264
1265 if (!is_valid_ether_addr(sa->sa_data))
1266 return -EADDRNOTAVAIL;
1267
1268
1269 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len);
1270 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len);
1271
1272
1273 if (netif_running(ndev)) {
1274 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1275 }
1276
1277 if (netif_msg_drv(priv))
1278 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n",
1279 priv->mac_addr);
1280
1281 return 0;
1282}
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293static int emac_hw_enable(struct emac_priv *priv)
1294{
1295 u32 val, mbp_enable, mac_control;
1296
1297
1298 emac_write(EMAC_SOFTRESET, 1);
1299 while (emac_read(EMAC_SOFTRESET))
1300 cpu_relax();
1301
1302
1303 emac_int_disable(priv);
1304
1305
1306 mac_control =
1307 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
1308 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
1309 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
1310 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
1311 emac_write(EMAC_MACCONTROL, mac_control);
1312
1313 mbp_enable =
1314 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
1315 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
1316 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
1317 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
1318 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
1319 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
1320 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
1321 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
1322 EMAC_RXMBP_PROMCH_SHIFT) |
1323 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
1324 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
1325 EMAC_RXMBP_BROADCH_SHIFT) |
1326 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
1327 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
1328 EMAC_RXMBP_MULTICH_SHIFT));
1329 emac_write(EMAC_RXMBPENABLE, mbp_enable);
1330 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
1331 EMAC_RX_MAX_LEN_MASK));
1332 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
1333 EMAC_RX_BUFFER_OFFSET_MASK));
1334 emac_write(EMAC_RXFILTERLOWTHRESH, 0);
1335 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
1336 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
1337
1338 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
1339
1340 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr);
1341
1342
1343 val = emac_read(EMAC_MACCONTROL);
1344 val |= (EMAC_MACCONTROL_GMIIEN);
1345 emac_write(EMAC_MACCONTROL, val);
1346
1347
1348 napi_enable(&priv->napi);
1349 emac_int_enable(priv);
1350 return 0;
1351
1352}
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367static int emac_poll(struct napi_struct *napi, int budget)
1368{
1369 unsigned int mask;
1370 struct emac_priv *priv = container_of(napi, struct emac_priv, napi);
1371 struct net_device *ndev = priv->ndev;
1372 struct device *emac_dev = &ndev->dev;
1373 u32 status = 0;
1374 u32 num_tx_pkts = 0, num_rx_pkts = 0;
1375
1376
1377 status = emac_read(EMAC_MACINVECTOR);
1378
1379 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
1380
1381 if (priv->version == EMAC_VERSION_2)
1382 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
1383
1384 if (status & mask) {
1385 num_tx_pkts = cpdma_chan_process(priv->txchan,
1386 EMAC_DEF_TX_MAX_SERVICE);
1387 }
1388
1389 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
1390
1391 if (priv->version == EMAC_VERSION_2)
1392 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
1393
1394 if (status & mask) {
1395 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget);
1396 }
1397
1398 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
1399 if (priv->version == EMAC_VERSION_2)
1400 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
1401
1402 if (unlikely(status & mask)) {
1403 u32 ch, cause;
1404 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n");
1405 netif_stop_queue(ndev);
1406 napi_disable(&priv->napi);
1407
1408 status = emac_read(EMAC_MACSTATUS);
1409 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
1410 EMAC_MACSTATUS_TXERRCODE_SHIFT);
1411 if (cause) {
1412 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
1413 EMAC_MACSTATUS_TXERRCH_SHIFT);
1414 if (net_ratelimit()) {
1415 dev_err(emac_dev, "TX Host error %s on ch=%d\n",
1416 &emac_txhost_errcodes[cause][0], ch);
1417 }
1418 }
1419 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
1420 EMAC_MACSTATUS_RXERRCODE_SHIFT);
1421 if (cause) {
1422 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
1423 EMAC_MACSTATUS_RXERRCH_SHIFT);
1424 if (netif_msg_hw(priv) && net_ratelimit())
1425 dev_err(emac_dev, "RX Host error %s on ch=%d\n",
1426 &emac_rxhost_errcodes[cause][0], ch);
1427 }
1428 } else if (num_rx_pkts < budget) {
1429 napi_complete(napi);
1430 emac_int_enable(priv);
1431 }
1432
1433 return num_rx_pkts;
1434}
1435
1436#ifdef CONFIG_NET_POLL_CONTROLLER
1437
1438
1439
1440
1441
1442
1443
1444static void emac_poll_controller(struct net_device *ndev)
1445{
1446 struct emac_priv *priv = netdev_priv(ndev);
1447
1448 emac_int_disable(priv);
1449 emac_irq(ndev->irq, ndev);
1450 emac_int_enable(priv);
1451}
1452#endif
1453
1454static void emac_adjust_link(struct net_device *ndev)
1455{
1456 struct emac_priv *priv = netdev_priv(ndev);
1457 struct phy_device *phydev = priv->phydev;
1458 unsigned long flags;
1459 int new_state = 0;
1460
1461 spin_lock_irqsave(&priv->lock, flags);
1462
1463 if (phydev->link) {
1464
1465 if (phydev->duplex != priv->duplex) {
1466 new_state = 1;
1467 priv->duplex = phydev->duplex;
1468 }
1469 if (phydev->speed != priv->speed) {
1470 new_state = 1;
1471 priv->speed = phydev->speed;
1472 }
1473 if (!priv->link) {
1474 new_state = 1;
1475 priv->link = 1;
1476 }
1477
1478 } else if (priv->link) {
1479 new_state = 1;
1480 priv->link = 0;
1481 priv->speed = 0;
1482 priv->duplex = ~0;
1483 }
1484 if (new_state) {
1485 emac_update_phystatus(priv);
1486 phy_print_status(priv->phydev);
1487 }
1488
1489 spin_unlock_irqrestore(&priv->lock, flags);
1490}
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd)
1507{
1508 struct emac_priv *priv = netdev_priv(ndev);
1509
1510 if (!(netif_running(ndev)))
1511 return -EINVAL;
1512
1513
1514
1515 if (priv->phydev)
1516 return phy_mii_ioctl(priv->phydev, ifrq, cmd);
1517 else
1518 return -EOPNOTSUPP;
1519}
1520
1521static int match_first_device(struct device *dev, void *data)
1522{
1523 return !strncmp(dev_name(dev), "davinci_mdio", 12);
1524}
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536static int emac_dev_open(struct net_device *ndev)
1537{
1538 struct device *emac_dev = &ndev->dev;
1539 u32 cnt;
1540 struct resource *res;
1541 int q, m, ret;
1542 int res_num = 0, irq_num = 0;
1543 int i = 0;
1544 struct emac_priv *priv = netdev_priv(ndev);
1545
1546 ret = pm_runtime_get_sync(&priv->pdev->dev);
1547 if (ret < 0) {
1548 pm_runtime_put_noidle(&priv->pdev->dev);
1549 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1550 __func__, ret);
1551 return ret;
1552 }
1553
1554 netif_carrier_off(ndev);
1555 for (cnt = 0; cnt < ETH_ALEN; cnt++)
1556 ndev->dev_addr[cnt] = priv->mac_addr[cnt];
1557
1558
1559 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
1560
1561 priv->mac_hash1 = 0;
1562 priv->mac_hash2 = 0;
1563 emac_write(EMAC_MACHASH1, 0);
1564 emac_write(EMAC_MACHASH2, 0);
1565
1566 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) {
1567 struct sk_buff *skb = emac_rx_alloc(priv);
1568
1569 if (!skb)
1570 break;
1571
1572 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data,
1573 skb_tailroom(skb), 0);
1574 if (WARN_ON(ret < 0))
1575 break;
1576 }
1577
1578
1579 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ,
1580 res_num))) {
1581 for (irq_num = res->start; irq_num <= res->end; irq_num++) {
1582 if (request_irq(irq_num, emac_irq, 0, ndev->name,
1583 ndev)) {
1584 dev_err(emac_dev,
1585 "DaVinci EMAC: request_irq() failed\n");
1586 ret = -EBUSY;
1587
1588 goto rollback;
1589 }
1590 }
1591 res_num++;
1592 }
1593
1594 res_num--;
1595 irq_num--;
1596
1597
1598 emac_hw_enable(priv);
1599
1600
1601 if (priv->coal_intvl != 0) {
1602 struct ethtool_coalesce coal;
1603
1604 coal.rx_coalesce_usecs = (priv->coal_intvl << 4);
1605 emac_set_coalesce(ndev, &coal);
1606 }
1607
1608 cpdma_ctlr_start(priv->dma);
1609
1610 priv->phydev = NULL;
1611
1612 if (priv->phy_node) {
1613 priv->phydev = of_phy_connect(ndev, priv->phy_node,
1614 &emac_adjust_link, 0, 0);
1615 if (!priv->phydev) {
1616 dev_err(emac_dev, "could not connect to phy %s\n",
1617 priv->phy_node->full_name);
1618 ret = -ENODEV;
1619 goto err;
1620 }
1621 }
1622
1623
1624 if (!priv->phydev && !priv->phy_id) {
1625 struct device *phy;
1626
1627 phy = bus_find_device(&mdio_bus_type, NULL, NULL,
1628 match_first_device);
1629 if (phy)
1630 priv->phy_id = dev_name(phy);
1631 }
1632
1633 if (!priv->phydev && priv->phy_id && *priv->phy_id) {
1634 priv->phydev = phy_connect(ndev, priv->phy_id,
1635 &emac_adjust_link,
1636 PHY_INTERFACE_MODE_MII);
1637
1638 if (IS_ERR(priv->phydev)) {
1639 dev_err(emac_dev, "could not connect to phy %s\n",
1640 priv->phy_id);
1641 ret = PTR_ERR(priv->phydev);
1642 priv->phydev = NULL;
1643 goto err;
1644 }
1645
1646 priv->link = 0;
1647 priv->speed = 0;
1648 priv->duplex = ~0;
1649
1650 phy_attached_info(priv->phydev);
1651 }
1652
1653 if (!priv->phydev) {
1654
1655 dev_notice(emac_dev, "no phy, defaulting to 100/full\n");
1656 priv->link = 1;
1657 priv->speed = SPEED_100;
1658 priv->duplex = DUPLEX_FULL;
1659 emac_update_phystatus(priv);
1660 }
1661
1662 if (!netif_running(ndev))
1663 emac_dump_regs(priv);
1664
1665 if (netif_msg_drv(priv))
1666 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name);
1667
1668 if (priv->phydev)
1669 phy_start(priv->phydev);
1670
1671 return 0;
1672
1673err:
1674 emac_int_disable(priv);
1675 napi_disable(&priv->napi);
1676
1677rollback:
1678 for (q = res_num; q >= 0; q--) {
1679 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q);
1680
1681
1682
1683 if (q != res_num)
1684 irq_num = res->end;
1685
1686 for (m = irq_num; m >= res->start; m--)
1687 free_irq(m, ndev);
1688 }
1689 cpdma_ctlr_stop(priv->dma);
1690 pm_runtime_put(&priv->pdev->dev);
1691 return ret;
1692}
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702
1703static int emac_dev_stop(struct net_device *ndev)
1704{
1705 struct resource *res;
1706 int i = 0;
1707 int irq_num;
1708 struct emac_priv *priv = netdev_priv(ndev);
1709 struct device *emac_dev = &ndev->dev;
1710
1711
1712 netif_stop_queue(ndev);
1713 napi_disable(&priv->napi);
1714
1715 netif_carrier_off(ndev);
1716 emac_int_disable(priv);
1717 cpdma_ctlr_stop(priv->dma);
1718 emac_write(EMAC_SOFTRESET, 1);
1719
1720 if (priv->phydev)
1721 phy_disconnect(priv->phydev);
1722
1723
1724 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) {
1725 for (irq_num = res->start; irq_num <= res->end; irq_num++)
1726 free_irq(irq_num, priv->ndev);
1727 i++;
1728 }
1729
1730 if (netif_msg_drv(priv))
1731 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name);
1732
1733 pm_runtime_put(&priv->pdev->dev);
1734 return 0;
1735}
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev)
1746{
1747 struct emac_priv *priv = netdev_priv(ndev);
1748 u32 mac_control;
1749 u32 stats_clear_mask;
1750 int err;
1751
1752 err = pm_runtime_get_sync(&priv->pdev->dev);
1753 if (err < 0) {
1754 pm_runtime_put_noidle(&priv->pdev->dev);
1755 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n",
1756 __func__, err);
1757 return &ndev->stats;
1758 }
1759
1760
1761
1762 mac_control = emac_read(EMAC_MACCONTROL);
1763
1764 if (mac_control & EMAC_MACCONTROL_GMIIEN)
1765 stats_clear_mask = EMAC_STATS_CLR_MASK;
1766 else
1767 stats_clear_mask = 0;
1768
1769 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
1770 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
1771
1772 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) +
1773 emac_read(EMAC_TXSINGLECOLL) +
1774 emac_read(EMAC_TXMULTICOLL));
1775 emac_write(EMAC_TXCOLLISION, stats_clear_mask);
1776 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
1777 emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
1778
1779 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
1780 emac_read(EMAC_RXJABBER) +
1781 emac_read(EMAC_RXUNDERSIZED));
1782 emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
1783 emac_write(EMAC_RXJABBER, stats_clear_mask);
1784 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
1785
1786 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
1787 emac_read(EMAC_RXMOFOVERRUNS));
1788 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
1789 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
1790
1791 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
1792 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
1793
1794 ndev->stats.tx_carrier_errors +=
1795 emac_read(EMAC_TXCARRIERSENSE);
1796 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
1797
1798 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN);
1799 emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
1800
1801 pm_runtime_put(&priv->pdev->dev);
1802
1803 return &ndev->stats;
1804}
1805
1806static const struct net_device_ops emac_netdev_ops = {
1807 .ndo_open = emac_dev_open,
1808 .ndo_stop = emac_dev_stop,
1809 .ndo_start_xmit = emac_dev_xmit,
1810 .ndo_set_rx_mode = emac_dev_mcast_set,
1811 .ndo_set_mac_address = emac_dev_setmac_addr,
1812 .ndo_do_ioctl = emac_devioctl,
1813 .ndo_tx_timeout = emac_dev_tx_timeout,
1814 .ndo_get_stats = emac_dev_getnetstats,
1815#ifdef CONFIG_NET_POLL_CONTROLLER
1816 .ndo_poll_controller = emac_poll_controller,
1817#endif
1818};
1819
1820static const struct of_device_id davinci_emac_of_match[];
1821
1822static struct emac_platform_data *
1823davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv)
1824{
1825 struct device_node *np;
1826 const struct of_device_id *match;
1827 const struct emac_platform_data *auxdata;
1828 struct emac_platform_data *pdata = NULL;
1829 const u8 *mac_addr;
1830
1831 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
1832 return dev_get_platdata(&pdev->dev);
1833
1834 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1835 if (!pdata)
1836 return NULL;
1837
1838 np = pdev->dev.of_node;
1839 pdata->version = EMAC_VERSION_2;
1840
1841 if (!is_valid_ether_addr(pdata->mac_addr)) {
1842 mac_addr = of_get_mac_address(np);
1843 if (mac_addr)
1844 ether_addr_copy(pdata->mac_addr, mac_addr);
1845 }
1846
1847 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset",
1848 &pdata->ctrl_reg_offset);
1849
1850 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset",
1851 &pdata->ctrl_mod_reg_offset);
1852
1853 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset",
1854 &pdata->ctrl_ram_offset);
1855
1856 of_property_read_u32(np, "ti,davinci-ctrl-ram-size",
1857 &pdata->ctrl_ram_size);
1858
1859 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en);
1860
1861 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram");
1862
1863 priv->phy_node = of_parse_phandle(np, "phy-handle", 0);
1864 if (!priv->phy_node) {
1865 if (!of_phy_is_fixed_link(np))
1866 pdata->phy_id = NULL;
1867 else if (of_phy_register_fixed_link(np) >= 0)
1868 priv->phy_node = of_node_get(np);
1869 }
1870
1871 auxdata = pdev->dev.platform_data;
1872 if (auxdata) {
1873 pdata->interrupt_enable = auxdata->interrupt_enable;
1874 pdata->interrupt_disable = auxdata->interrupt_disable;
1875 }
1876
1877 match = of_match_device(davinci_emac_of_match, &pdev->dev);
1878 if (match && match->data) {
1879 auxdata = match->data;
1880 pdata->version = auxdata->version;
1881 pdata->hw_ram_addr = auxdata->hw_ram_addr;
1882 }
1883
1884 return pdata;
1885}
1886
1887static int davinci_emac_try_get_mac(struct platform_device *pdev,
1888 int instance, u8 *mac_addr)
1889{
1890 if (!pdev->dev.of_node)
1891 return -EINVAL;
1892
1893 return ti_cm_get_macid(&pdev->dev, instance, mac_addr);
1894}
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904static int davinci_emac_probe(struct platform_device *pdev)
1905{
1906 int rc = 0;
1907 struct resource *res, *res_ctrl;
1908 struct net_device *ndev;
1909 struct emac_priv *priv;
1910 unsigned long hw_ram_addr;
1911 struct emac_platform_data *pdata;
1912 struct cpdma_params dma_params;
1913 struct clk *emac_clk;
1914 unsigned long emac_bus_frequency;
1915
1916
1917
1918 emac_clk = devm_clk_get(&pdev->dev, NULL);
1919 if (IS_ERR(emac_clk)) {
1920 dev_err(&pdev->dev, "failed to get EMAC clock\n");
1921 return -EBUSY;
1922 }
1923 emac_bus_frequency = clk_get_rate(emac_clk);
1924 devm_clk_put(&pdev->dev, emac_clk);
1925
1926
1927
1928 ndev = alloc_etherdev(sizeof(struct emac_priv));
1929 if (!ndev)
1930 return -ENOMEM;
1931
1932 platform_set_drvdata(pdev, ndev);
1933 priv = netdev_priv(ndev);
1934 priv->pdev = pdev;
1935 priv->ndev = ndev;
1936 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG);
1937
1938 spin_lock_init(&priv->lock);
1939
1940 pdata = davinci_emac_of_get_pdata(pdev, priv);
1941 if (!pdata) {
1942 dev_err(&pdev->dev, "no platform data\n");
1943 rc = -ENODEV;
1944 goto no_pdata;
1945 }
1946
1947
1948 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN);
1949 priv->phy_id = pdata->phy_id;
1950 priv->rmii_en = pdata->rmii_en;
1951 priv->version = pdata->version;
1952 priv->int_enable = pdata->interrupt_enable;
1953 priv->int_disable = pdata->interrupt_disable;
1954
1955 priv->coal_intvl = 0;
1956 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000);
1957
1958
1959 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1960 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset;
1961 priv->remap_addr = devm_ioremap_resource(&pdev->dev, res);
1962 if (IS_ERR(priv->remap_addr)) {
1963 rc = PTR_ERR(priv->remap_addr);
1964 goto no_pdata;
1965 }
1966
1967 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1968 if (res_ctrl) {
1969 priv->ctrl_base =
1970 devm_ioremap_resource(&pdev->dev, res_ctrl);
1971 if (IS_ERR(priv->ctrl_base)) {
1972 rc = PTR_ERR(priv->ctrl_base);
1973 goto no_pdata;
1974 }
1975 } else {
1976 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset;
1977 }
1978
1979 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset;
1980 ndev->base_addr = (unsigned long)priv->remap_addr;
1981
1982 hw_ram_addr = pdata->hw_ram_addr;
1983 if (!hw_ram_addr)
1984 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset;
1985
1986 memset(&dma_params, 0, sizeof(dma_params));
1987 dma_params.dev = &pdev->dev;
1988 dma_params.dmaregs = priv->emac_base;
1989 dma_params.rxthresh = priv->emac_base + 0x120;
1990 dma_params.rxfree = priv->emac_base + 0x140;
1991 dma_params.txhdp = priv->emac_base + 0x600;
1992 dma_params.rxhdp = priv->emac_base + 0x620;
1993 dma_params.txcp = priv->emac_base + 0x640;
1994 dma_params.rxcp = priv->emac_base + 0x660;
1995 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS;
1996 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE;
1997 dma_params.desc_hw_addr = hw_ram_addr;
1998 dma_params.desc_mem_size = pdata->ctrl_ram_size;
1999 dma_params.desc_align = 16;
2000
2001 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 :
2002 (u32 __force)res->start + pdata->ctrl_ram_offset;
2003
2004 priv->dma = cpdma_ctlr_create(&dma_params);
2005 if (!priv->dma) {
2006 dev_err(&pdev->dev, "error initializing DMA\n");
2007 rc = -ENOMEM;
2008 goto no_pdata;
2009 }
2010
2011 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH),
2012 emac_tx_handler);
2013 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH),
2014 emac_rx_handler);
2015 if (WARN_ON(!priv->txchan || !priv->rxchan)) {
2016 rc = -ENOMEM;
2017 goto no_cpdma_chan;
2018 }
2019
2020 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2021 if (!res) {
2022 dev_err(&pdev->dev, "error getting irq res\n");
2023 rc = -ENOENT;
2024 goto no_cpdma_chan;
2025 }
2026 ndev->irq = res->start;
2027
2028 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr);
2029 if (!rc)
2030 ether_addr_copy(ndev->dev_addr, priv->mac_addr);
2031
2032 if (!is_valid_ether_addr(priv->mac_addr)) {
2033
2034 eth_hw_addr_random(ndev);
2035 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len);
2036 dev_warn(&pdev->dev, "using random MAC addr: %pM\n",
2037 priv->mac_addr);
2038 }
2039
2040 ndev->netdev_ops = &emac_netdev_ops;
2041 ndev->ethtool_ops = ðtool_ops;
2042 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT);
2043
2044 pm_runtime_enable(&pdev->dev);
2045 rc = pm_runtime_get_sync(&pdev->dev);
2046 if (rc < 0) {
2047 pm_runtime_put_noidle(&pdev->dev);
2048 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n",
2049 __func__, rc);
2050 goto no_cpdma_chan;
2051 }
2052
2053
2054 SET_NETDEV_DEV(ndev, &pdev->dev);
2055 rc = register_netdev(ndev);
2056 if (rc) {
2057 dev_err(&pdev->dev, "error in register_netdev\n");
2058 rc = -ENODEV;
2059 pm_runtime_put(&pdev->dev);
2060 goto no_cpdma_chan;
2061 }
2062
2063
2064 if (netif_msg_probe(priv)) {
2065 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device "
2066 "(regs: %p, irq: %d)\n",
2067 (void *)priv->emac_base_phys, ndev->irq);
2068 }
2069 pm_runtime_put(&pdev->dev);
2070
2071 return 0;
2072
2073no_cpdma_chan:
2074 if (priv->txchan)
2075 cpdma_chan_destroy(priv->txchan);
2076 if (priv->rxchan)
2077 cpdma_chan_destroy(priv->rxchan);
2078 cpdma_ctlr_destroy(priv->dma);
2079no_pdata:
2080 free_netdev(ndev);
2081 return rc;
2082}
2083
2084
2085
2086
2087
2088
2089
2090
2091static int davinci_emac_remove(struct platform_device *pdev)
2092{
2093 struct net_device *ndev = platform_get_drvdata(pdev);
2094 struct emac_priv *priv = netdev_priv(ndev);
2095
2096 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n");
2097
2098 if (priv->txchan)
2099 cpdma_chan_destroy(priv->txchan);
2100 if (priv->rxchan)
2101 cpdma_chan_destroy(priv->rxchan);
2102 cpdma_ctlr_destroy(priv->dma);
2103
2104 unregister_netdev(ndev);
2105 pm_runtime_disable(&pdev->dev);
2106 free_netdev(ndev);
2107
2108 return 0;
2109}
2110
2111static int davinci_emac_suspend(struct device *dev)
2112{
2113 struct platform_device *pdev = to_platform_device(dev);
2114 struct net_device *ndev = platform_get_drvdata(pdev);
2115
2116 if (netif_running(ndev))
2117 emac_dev_stop(ndev);
2118
2119 return 0;
2120}
2121
2122static int davinci_emac_resume(struct device *dev)
2123{
2124 struct platform_device *pdev = to_platform_device(dev);
2125 struct net_device *ndev = platform_get_drvdata(pdev);
2126
2127 if (netif_running(ndev))
2128 emac_dev_open(ndev);
2129
2130 return 0;
2131}
2132
2133static const struct dev_pm_ops davinci_emac_pm_ops = {
2134 .suspend = davinci_emac_suspend,
2135 .resume = davinci_emac_resume,
2136};
2137
2138#if IS_ENABLED(CONFIG_OF)
2139static const struct emac_platform_data am3517_emac_data = {
2140 .version = EMAC_VERSION_2,
2141 .hw_ram_addr = 0x01e20000,
2142};
2143
2144static const struct emac_platform_data dm816_emac_data = {
2145 .version = EMAC_VERSION_2,
2146};
2147
2148static const struct of_device_id davinci_emac_of_match[] = {
2149 {.compatible = "ti,davinci-dm6467-emac", },
2150 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, },
2151 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, },
2152 {},
2153};
2154MODULE_DEVICE_TABLE(of, davinci_emac_of_match);
2155#endif
2156
2157
2158static struct platform_driver davinci_emac_driver = {
2159 .driver = {
2160 .name = "davinci_emac",
2161 .pm = &davinci_emac_pm_ops,
2162 .of_match_table = of_match_ptr(davinci_emac_of_match),
2163 },
2164 .probe = davinci_emac_probe,
2165 .remove = davinci_emac_remove,
2166};
2167
2168
2169
2170
2171
2172
2173
2174static int __init davinci_emac_init(void)
2175{
2176 return platform_driver_register(&davinci_emac_driver);
2177}
2178late_initcall(davinci_emac_init);
2179
2180
2181
2182
2183
2184
2185
2186static void __exit davinci_emac_exit(void)
2187{
2188 platform_driver_unregister(&davinci_emac_driver);
2189}
2190module_exit(davinci_emac_exit);
2191
2192MODULE_LICENSE("GPL");
2193MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>");
2194MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>");
2195MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver");
2196