LXR linux/drivers/net/ethernet/xilinx/xilinx

   1/*
   2 * Definitions for Xilinx Axi Ethernet device driver.
   3 *
   4 * Copyright (c) 2009 Secret Lab Technologies, Ltd.
   5 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
   6 */
   7
   8#ifndef XILINX_AXIENET_H
   9#define XILINX_AXIENET_H
  10
  11#include <linux/netdevice.h>
  12#include <linux/spinlock.h>
  13#include <linux/interrupt.h>
  14#include <linux/if_vlan.h>
  15#include <linux/net_tstamp.h>
  16
  17/* Packet size info */
  18#define XAE_HDR_SIZE                    14 /* Size of Ethernet header */
  19#define XAE_TRL_SIZE                     4 /* Size of Ethernet trailer (FCS) */
  20#define XAE_MTU                       1500 /* Max MTU of an Ethernet frame */
  21#define XAE_JUMBO_MTU                 9000 /* Max MTU of a jumbo Eth. frame */
  22
  23#define XAE_MAX_FRAME_SIZE       (XAE_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
  24#define XAE_MAX_VLAN_FRAME_SIZE  (XAE_MTU + VLAN_ETH_HLEN + XAE_TRL_SIZE)
  25#define XAE_MAX_JUMBO_FRAME_SIZE (XAE_JUMBO_MTU + XAE_HDR_SIZE + XAE_TRL_SIZE)
  26
  27/* Configuration options */
  28
  29/* Accept all incoming packets. Default: disabled (cleared) */
  30#define XAE_OPTION_PROMISC                      (1 << 0)
  31
  32/* Jumbo frame support for Tx & Rx. Default: disabled (cleared) */
  33#define XAE_OPTION_JUMBO                        (1 << 1)
  34
  35/* VLAN Rx & Tx frame support. Default: disabled (cleared) */
  36#define XAE_OPTION_VLAN                         (1 << 2)
  37
  38/* Enable recognition of flow control frames on Rx. Default: enabled (set) */
  39#define XAE_OPTION_FLOW_CONTROL                 (1 << 4)
  40
  41/* Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not
  42 * stripped. Default: disabled (set)
  43 */
  44#define XAE_OPTION_FCS_STRIP                    (1 << 5)
  45
  46/* Generate FCS field and add PAD automatically for outgoing frames.
  47 * Default: enabled (set)
  48 */
  49#define XAE_OPTION_FCS_INSERT                   (1 << 6)
  50
  51/* Enable Length/Type error checking for incoming frames. When this option is
  52 * set, the MAC will filter frames that have a mismatched type/length field
  53 * and if XAE_OPTION_REPORT_RXERR is set, the user is notified when these
  54 * types of frames are encountered. When this option is cleared, the MAC will
  55 * allow these types of frames to be received. Default: enabled (set)
  56 */
  57#define XAE_OPTION_LENTYPE_ERR                  (1 << 7)
  58
  59/* Enable the transmitter. Default: enabled (set) */
  60#define XAE_OPTION_TXEN                         (1 << 11)
  61
  62/*  Enable the receiver. Default: enabled (set) */
  63#define XAE_OPTION_RXEN                         (1 << 12)
  64
  65/*  Default options set when device is initialized or reset */
  66#define XAE_OPTION_DEFAULTS                                \
  67                                (XAE_OPTION_TXEN |         \
  68                                 XAE_OPTION_FLOW_CONTROL | \
  69                                 XAE_OPTION_RXEN)
  70
  71/* Axi DMA Register definitions */
  72
  73#define XAXIDMA_TX_CR_OFFSET    0x00000000 /* Channel control */
  74#define XAXIDMA_TX_SR_OFFSET    0x00000004 /* Status */
  75#define XAXIDMA_TX_CDESC_OFFSET 0x00000008 /* Current descriptor pointer */
  76#define XAXIDMA_TX_TDESC_OFFSET 0x00000010 /* Tail descriptor pointer */
  77
  78#define XAXIDMA_RX_CR_OFFSET    0x00000030 /* Channel control */
  79#define XAXIDMA_RX_SR_OFFSET    0x00000034 /* Status */
  80#define XAXIDMA_RX_CDESC_OFFSET 0x00000038 /* Current descriptor pointer */
  81#define XAXIDMA_RX_TDESC_OFFSET 0x00000040 /* Tail descriptor pointer */
  82
  83#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
  84#define XAXIDMA_CR_RESET_MASK   0x00000004 /* Reset DMA engine */
  85
  86#define XAXIDMA_BD_NDESC_OFFSET         0x00 /* Next descriptor pointer */
  87#define XAXIDMA_BD_BUFA_OFFSET          0x08 /* Buffer address */
  88#define XAXIDMA_BD_CTRL_LEN_OFFSET      0x18 /* Control/buffer length */
  89#define XAXIDMA_BD_STS_OFFSET           0x1C /* Status */
  90#define XAXIDMA_BD_USR0_OFFSET          0x20 /* User IP specific word0 */
  91#define XAXIDMA_BD_USR1_OFFSET          0x24 /* User IP specific word1 */
  92#define XAXIDMA_BD_USR2_OFFSET          0x28 /* User IP specific word2 */
  93#define XAXIDMA_BD_USR3_OFFSET          0x2C /* User IP specific word3 */
  94#define XAXIDMA_BD_USR4_OFFSET          0x30 /* User IP specific word4 */
  95#define XAXIDMA_BD_ID_OFFSET            0x34 /* Sw ID */
  96#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET  0x38 /* Whether has stscntrl strm */
  97#define XAXIDMA_BD_HAS_DRE_OFFSET       0x3C /* Whether has DRE */
  98
  99#define XAXIDMA_BD_HAS_DRE_SHIFT        8 /* Whether has DRE shift */
 100#define XAXIDMA_BD_HAS_DRE_MASK         0xF00 /* Whether has DRE mask */
 101#define XAXIDMA_BD_WORDLEN_MASK         0xFF /* Whether has DRE mask */
 102
 103#define XAXIDMA_BD_CTRL_LENGTH_MASK     0x007FFFFF /* Requested len */
 104#define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
 105#define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
 106#define XAXIDMA_BD_CTRL_ALL_MASK        0x0C000000 /* All control bits */
 107
 108#define XAXIDMA_DELAY_MASK              0xFF000000 /* Delay timeout counter */
 109#define XAXIDMA_COALESCE_MASK           0x00FF0000 /* Coalesce counter */
 110
 111#define XAXIDMA_DELAY_SHIFT             24
 112#define XAXIDMA_COALESCE_SHIFT          16
 113
 114#define XAXIDMA_IRQ_IOC_MASK            0x00001000 /* Completion intr */
 115#define XAXIDMA_IRQ_DELAY_MASK          0x00002000 /* Delay interrupt */
 116#define XAXIDMA_IRQ_ERROR_MASK          0x00004000 /* Error interrupt */
 117#define XAXIDMA_IRQ_ALL_MASK            0x00007000 /* All interrupts */
 118
 119/* Default TX/RX Threshold and waitbound values for SGDMA mode */
 120#define XAXIDMA_DFT_TX_THRESHOLD        24
 121#define XAXIDMA_DFT_TX_WAITBOUND        254
 122#define XAXIDMA_DFT_RX_THRESHOLD        1
 123#define XAXIDMA_DFT_RX_WAITBOUND        254
 124
 125#define XAXIDMA_BD_CTRL_TXSOF_MASK      0x08000000 /* First tx packet */
 126#define XAXIDMA_BD_CTRL_TXEOF_MASK      0x04000000 /* Last tx packet */
 127#define XAXIDMA_BD_CTRL_ALL_MASK        0x0C000000 /* All control bits */
 128
 129#define XAXIDMA_BD_STS_ACTUAL_LEN_MASK  0x007FFFFF /* Actual len */
 130#define XAXIDMA_BD_STS_COMPLETE_MASK    0x80000000 /* Completed */
 131#define XAXIDMA_BD_STS_DEC_ERR_MASK     0x40000000 /* Decode error */
 132#define XAXIDMA_BD_STS_SLV_ERR_MASK     0x20000000 /* Slave error */
 133#define XAXIDMA_BD_STS_INT_ERR_MASK     0x10000000 /* Internal err */
 134#define XAXIDMA_BD_STS_ALL_ERR_MASK     0x70000000 /* All errors */
 135#define XAXIDMA_BD_STS_RXSOF_MASK       0x08000000 /* First rx pkt */
 136#define XAXIDMA_BD_STS_RXEOF_MASK       0x04000000 /* Last rx pkt */
 137#define XAXIDMA_BD_STS_ALL_MASK         0xFC000000 /* All status bits */
 138
 139#define XAXIDMA_BD_MINIMUM_ALIGNMENT    0x40
 140
 141/* AXI Tx Timestamp Stream FIFO Register Definitions */
 142#define XAXIFIFO_TXTS_ISR       0x00000000 /* Interrupt Status Register */
 143#define XAXIFIFO_TXTS_RXFD      0x00000020 /* Rx Data Read Port */
 144#define XAXIFIFO_TXTS_RLR       0x00000024 /* Receive Length Register */
 145
 146#define XAXIFIFO_TXTS_INT_RC_MASK       0x04000000
 147#define XAXIFIFO_TXTS_RXFD_MASK         0x7FFFFFFF
 148#define XAXIFIFO_TXTS_TAG_MASK          0xFFFF0000
 149#define XAXIFIFO_TXTS_TAG_SHIFT         16
 150
 151/* Axi Ethernet registers definition */
 152#define XAE_RAF_OFFSET          0x00000000 /* Reset and Address filter */
 153#define XAE_TPF_OFFSET          0x00000004 /* Tx Pause Frame */
 154#define XAE_IFGP_OFFSET         0x00000008 /* Tx Inter-frame gap adjustment*/
 155#define XAE_IS_OFFSET           0x0000000C /* Interrupt status */
 156#define XAE_IP_OFFSET           0x00000010 /* Interrupt pending */
 157#define XAE_IE_OFFSET           0x00000014 /* Interrupt enable */
 158#define XAE_TTAG_OFFSET         0x00000018 /* Tx VLAN TAG */
 159#define XAE_RTAG_OFFSET         0x0000001C /* Rx VLAN TAG */
 160#define XAE_UAWL_OFFSET         0x00000020 /* Unicast address word lower */
 161#define XAE_UAWU_OFFSET         0x00000024 /* Unicast address word upper */
 162#define XAE_TPID0_OFFSET        0x00000028 /* VLAN TPID0 register */
 163#define XAE_TPID1_OFFSET        0x0000002C /* VLAN TPID1 register */
 164#define XAE_PPST_OFFSET         0x00000030 /* PCS PMA Soft Temac Status Reg */
 165#define XAE_RCW0_OFFSET         0x00000400 /* Rx Configuration Word 0 */
 166#define XAE_RCW1_OFFSET         0x00000404 /* Rx Configuration Word 1 */
 167#define XAE_TC_OFFSET           0x00000408 /* Tx Configuration */
 168#define XAE_FCC_OFFSET          0x0000040C /* Flow Control Configuration */
 169#define XAE_EMMC_OFFSET         0x00000410 /* EMAC mode configuration */
 170#define XAE_PHYC_OFFSET         0x00000414 /* RGMII/SGMII configuration */
 171#define XAE_MDIO_MC_OFFSET      0x00000500 /* MII Management Config */
 172#define XAE_MDIO_MCR_OFFSET     0x00000504 /* MII Management Control */
 173#define XAE_MDIO_MWD_OFFSET     0x00000508 /* MII Management Write Data */
 174#define XAE_MDIO_MRD_OFFSET     0x0000050C /* MII Management Read Data */
 175#define XAE_MDIO_MIS_OFFSET     0x00000600 /* MII Management Interrupt Status */
 176/* MII Mgmt Interrupt Pending register offset */
 177#define XAE_MDIO_MIP_OFFSET     0x00000620
 178/* MII Management Interrupt Enable register offset */
 179#define XAE_MDIO_MIE_OFFSET     0x00000640
 180/* MII Management Interrupt Clear register offset. */
 181#define XAE_MDIO_MIC_OFFSET     0x00000660
 182#define XAE_UAW0_OFFSET         0x00000700 /* Unicast address word 0 */
 183#define XAE_UAW1_OFFSET         0x00000704 /* Unicast address word 1 */
 184#define XAE_FMI_OFFSET          0x00000708 /* Filter Mask Index */
 185#define XAE_AF0_OFFSET          0x00000710 /* Address Filter 0 */
 186#define XAE_AF1_OFFSET          0x00000714 /* Address Filter 1 */
 187
 188#define XAE_TX_VLAN_DATA_OFFSET 0x00004000 /* TX VLAN data table address */
 189#define XAE_RX_VLAN_DATA_OFFSET 0x00008000 /* RX VLAN data table address */
 190#define XAE_MCAST_TABLE_OFFSET  0x00020000 /* Multicast table address */
 191
 192/* Bit Masks for Axi Ethernet RAF register */
 193/* Reject receive multicast destination address */
 194#define XAE_RAF_MCSTREJ_MASK            0x00000002
 195/* Reject receive broadcast destination address */
 196#define XAE_RAF_BCSTREJ_MASK            0x00000004
 197#define XAE_RAF_TXVTAGMODE_MASK         0x00000018 /* Tx VLAN TAG mode */
 198#define XAE_RAF_RXVTAGMODE_MASK         0x00000060 /* Rx VLAN TAG mode */
 199#define XAE_RAF_TXVSTRPMODE_MASK        0x00000180 /* Tx VLAN STRIP mode */
 200#define XAE_RAF_RXVSTRPMODE_MASK        0x00000600 /* Rx VLAN STRIP mode */
 201#define XAE_RAF_NEWFNCENBL_MASK         0x00000800 /* New function mode */
 202/* Exteneded Multicast Filtering mode */
 203#define XAE_RAF_EMULTIFLTRENBL_MASK     0x00001000
 204#define XAE_RAF_STATSRST_MASK           0x00002000 /* Stats. Counter Reset */
 205#define XAE_RAF_RXBADFRMEN_MASK         0x00004000 /* Recv Bad Frame Enable */
 206#define XAE_RAF_TXVTAGMODE_SHIFT        3 /* Tx Tag mode shift bits */
 207#define XAE_RAF_RXVTAGMODE_SHIFT        5 /* Rx Tag mode shift bits */
 208#define XAE_RAF_TXVSTRPMODE_SHIFT       7 /* Tx strip mode shift bits*/
 209#define XAE_RAF_RXVSTRPMODE_SHIFT       9 /* Rx Strip mode shift bits*/
 210
 211/* Bit Masks for Axi Ethernet TPF and IFGP registers */
 212#define XAE_TPF_TPFV_MASK               0x0000FFFF /* Tx pause frame value */
 213/* Transmit inter-frame gap adjustment value */
 214#define XAE_IFGP0_IFGP_MASK             0x0000007F
 215
 216/* Bit Masks for Axi Ethernet IS, IE and IP registers, Same masks apply
 217 * for all 3 registers.
 218 */
 219/* Hard register access complete */
 220#define XAE_INT_HARDACSCMPLT_MASK       0x00000001
 221/* Auto negotiation complete */
 222#define XAE_INT_AUTONEG_MASK            0x00000002
 223#define XAE_INT_RXCMPIT_MASK            0x00000004 /* Rx complete */
 224#define XAE_INT_RXRJECT_MASK            0x00000008 /* Rx frame rejected */
 225#define XAE_INT_RXFIFOOVR_MASK          0x00000010 /* Rx fifo overrun */
 226#define XAE_INT_TXCMPIT_MASK            0x00000020 /* Tx complete */
 227#define XAE_INT_RXDCMLOCK_MASK          0x00000040 /* Rx Dcm Lock */
 228#define XAE_INT_MGTRDY_MASK             0x00000080 /* MGT clock Lock */
 229#define XAE_INT_PHYRSTCMPLT_MASK        0x00000100 /* Phy Reset complete */
 230#define XAE_INT_ALL_MASK                0x0000003F /* All the ints */
 231
 232/* INT bits that indicate receive errors */
 233#define XAE_INT_RECV_ERROR_MASK                         \
 234        (XAE_INT_RXRJECT_MASK | XAE_INT_RXFIFOOVR_MASK)
 235
 236/* Bit masks for Axi Ethernet VLAN TPID Word 0 register */
 237#define XAE_TPID_0_MASK         0x0000FFFF /* TPID 0 */
 238#define XAE_TPID_1_MASK         0xFFFF0000 /* TPID 1 */
 239
 240/* Bit masks for Axi Ethernet VLAN TPID Word 1 register */
 241#define XAE_TPID_2_MASK         0x0000FFFF /* TPID 0 */
 242#define XAE_TPID_3_MASK         0xFFFF0000 /* TPID 1 */
 243
 244/* Bit masks for Axi Ethernet RCW1 register */
 245#define XAE_RCW1_INBAND1588_MASK 0x00400000 /* Inband 1588 Enable */
 246#define XAE_RCW1_RST_MASK       0x80000000 /* Reset */
 247#define XAE_RCW1_JUM_MASK       0x40000000 /* Jumbo frame enable */
 248/* In-Band FCS enable (FCS not stripped) */
 249#define XAE_RCW1_FCS_MASK       0x20000000
 250#define XAE_RCW1_RX_MASK        0x10000000 /* Receiver enable */
 251#define XAE_RCW1_VLAN_MASK      0x08000000 /* VLAN frame enable */
 252/* Length/type field valid check disable */
 253#define XAE_RCW1_LT_DIS_MASK    0x02000000
 254/* Control frame Length check disable */
 255#define XAE_RCW1_CL_DIS_MASK    0x01000000
 256/* Pause frame source address bits [47:32]. Bits [31:0] are
 257 * stored in register RCW0
 258 */
 259#define XAE_RCW1_PAUSEADDR_MASK 0x0000FFFF
 260
 261/* Bit masks for Axi Ethernet TC register */
 262#define XAE_TC_INBAND1588_MASK 0x00400000 /* Inband 1588 Enable */
 263#define XAE_TC_RST_MASK         0x80000000 /* Reset */
 264#define XAE_TC_JUM_MASK         0x40000000 /* Jumbo frame enable */
 265/* In-Band FCS enable (FCS not generated) */
 266#define XAE_TC_FCS_MASK         0x20000000
 267#define XAE_TC_TX_MASK          0x10000000 /* Transmitter enable */
 268#define XAE_TC_VLAN_MASK        0x08000000 /* VLAN frame enable */
 269/* Inter-frame gap adjustment enable */
 270#define XAE_TC_IFG_MASK         0x02000000
 271
 272/* Bit masks for Axi Ethernet FCC register */
 273#define XAE_FCC_FCRX_MASK       0x20000000 /* Rx flow control enable */
 274#define XAE_FCC_FCTX_MASK       0x40000000 /* Tx flow control enable */
 275
 276/* Bit masks for Axi Ethernet EMMC register */
 277#define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
 278#define XAE_EMMC_RGMII_MASK     0x20000000 /* RGMII mode enable */
 279#define XAE_EMMC_SGMII_MASK     0x10000000 /* SGMII mode enable */
 280#define XAE_EMMC_GPCS_MASK      0x08000000 /* 1000BaseX mode enable */
 281#define XAE_EMMC_HOST_MASK      0x04000000 /* Host interface enable */
 282#define XAE_EMMC_TX16BIT        0x02000000 /* 16 bit Tx client enable */
 283#define XAE_EMMC_RX16BIT        0x01000000 /* 16 bit Rx client enable */
 284#define XAE_EMMC_LINKSPD_10     0x00000000 /* Link Speed mask for 10 Mbit */
 285#define XAE_EMMC_LINKSPD_100    0x40000000 /* Link Speed mask for 100 Mbit */
 286#define XAE_EMMC_LINKSPD_1000   0x80000000 /* Link Speed mask for 1000 Mbit */
 287
 288/* Bit masks for Axi Ethernet PHYC register */
 289#define XAE_PHYC_SGMIILINKSPEED_MASK    0xC0000000 /* SGMII link speed mask*/
 290#define XAE_PHYC_RGMIILINKSPEED_MASK    0x0000000C /* RGMII link speed */
 291#define XAE_PHYC_RGMIIHD_MASK           0x00000002 /* RGMII Half-duplex */
 292#define XAE_PHYC_RGMIILINK_MASK         0x00000001 /* RGMII link status */
 293#define XAE_PHYC_RGLINKSPD_10           0x00000000 /* RGMII link 10 Mbit */
 294#define XAE_PHYC_RGLINKSPD_100          0x00000004 /* RGMII link 100 Mbit */
 295#define XAE_PHYC_RGLINKSPD_1000         0x00000008 /* RGMII link 1000 Mbit */
 296#define XAE_PHYC_SGLINKSPD_10           0x00000000 /* SGMII link 10 Mbit */
 297#define XAE_PHYC_SGLINKSPD_100          0x40000000 /* SGMII link 100 Mbit */
 298#define XAE_PHYC_SGLINKSPD_1000         0x80000000 /* SGMII link 1000 Mbit */
 299
 300/* Bit masks for Axi Ethernet MDIO interface MC register */
 301#define XAE_MDIO_MC_MDIOEN_MASK         0x00000040 /* MII management enable */
 302#define XAE_MDIO_MC_CLOCK_DIVIDE_MAX    0x3F       /* Maximum MDIO divisor */
 303
 304/* Bit masks for Axi Ethernet MDIO interface MCR register */
 305#define XAE_MDIO_MCR_PHYAD_MASK         0x1F000000 /* Phy Address Mask */
 306#define XAE_MDIO_MCR_PHYAD_SHIFT        24         /* Phy Address Shift */
 307#define XAE_MDIO_MCR_REGAD_MASK         0x001F0000 /* Reg Address Mask */
 308#define XAE_MDIO_MCR_REGAD_SHIFT        16         /* Reg Address Shift */
 309#define XAE_MDIO_MCR_OP_MASK            0x0000C000 /* Operation Code Mask */
 310#define XAE_MDIO_MCR_OP_SHIFT           13         /* Operation Code Shift */
 311#define XAE_MDIO_MCR_OP_READ_MASK       0x00008000 /* Op Code Read Mask */
 312#define XAE_MDIO_MCR_OP_WRITE_MASK      0x00004000 /* Op Code Write Mask */
 313#define XAE_MDIO_MCR_INITIATE_MASK      0x00000800 /* Ready Mask */
 314#define XAE_MDIO_MCR_READY_MASK         0x00000080 /* Ready Mask */
 315
 316/* Bit masks for Axi Ethernet MDIO interface MIS, MIP, MIE, MIC registers */
 317#define XAE_MDIO_INT_MIIM_RDY_MASK      0x00000001 /* MIIM Interrupt */
 318
 319/* Bit masks for Axi Ethernet UAW1 register */
 320/* Station address bits [47:32]; Station address
 321 * bits [31:0] are stored in register UAW0
 322 */
 323#define XAE_UAW1_UNICASTADDR_MASK       0x0000FFFF
 324
 325/* Bit masks for Axi Ethernet FMI register */
 326#define XAE_FMI_PM_MASK                 0x80000000 /* Promis. mode enable */
 327#define XAE_FMI_IND_MASK                0x00000003 /* Index Mask */
 328
 329#define XAE_MDIO_DIV_DFT                29 /* Default MDIO clock divisor */
 330
 331/* Total number of entries in the hardware multicast table. */
 332#define XAE_MULTICAST_CAM_TABLE_NUM     4
 333
 334/* Axi Ethernet Synthesis features */
 335#define XAE_FEATURE_PARTIAL_RX_CSUM     (1 << 0)
 336#define XAE_FEATURE_PARTIAL_TX_CSUM     (1 << 1)
 337#define XAE_FEATURE_FULL_RX_CSUM        (1 << 2)
 338#define XAE_FEATURE_FULL_TX_CSUM        (1 << 3)
 339
 340#define XAE_NO_CSUM_OFFLOAD             0
 341
 342#define XAE_FULL_CSUM_STATUS_MASK       0x00000038
 343#define XAE_IP_UDP_CSUM_VALIDATED       0x00000003
 344#define XAE_IP_TCP_CSUM_VALIDATED       0x00000002
 345
 346#define DELAY_OF_ONE_MILLISEC           1000
 347
 348#define XAXIENET_NAPI_WEIGHT            64
 349
 350/* Defintions of 1588 PTP in Axi Ethernet IP */
 351#define TX_TS_OP_NOOP           0x0
 352#define TX_TS_OP_ONESTEP        0x1
 353#define TX_TS_OP_TWOSTEP        0x2
 354#define TX_TS_CSUM_UPDATE       0x1
 355#define TX_PTP_CSUM_OFFSET      0x28
 356#define TX_PTP_TS_OFFSET        0x4C
 357
 358/* Read/Write access to the registers */
 359#ifndef out_be32
 360#if defined(CONFIG_ARCH_ZYNQ) || defined(CONFIG_ARCH_ZYNQMP)
 361#define in_be32(offset)         __raw_readl(offset)
 362#define out_be32(offset, val)   __raw_writel(val, offset)
 363#endif
 364#endif
 365
 366/**
 367 * struct axidma_bd - Axi Dma buffer descriptor layout
 368 * @next:         MM2S/S2MM Next Descriptor Pointer
 369 * @reserved1:    Reserved and not used
 370 * @phys:         MM2S/S2MM Buffer Address
 371 * @reserved2:    Reserved and not used
 372 * @reserved3:    Reserved and not used
 373 * @reserved4:    Reserved and not used
 374 * @cntrl:        MM2S/S2MM Control value
 375 * @status:       MM2S/S2MM Status value
 376 * @app0:         MM2S/S2MM User Application Field 0.
 377 * @app1:         MM2S/S2MM User Application Field 1.
 378 * @app2:         MM2S/S2MM User Application Field 2.
 379 * @app3:         MM2S/S2MM User Application Field 3.
 380 * @app4:         MM2S/S2MM User Application Field 4.
 381 * @sw_id_offset: MM2S/S2MM Sw ID
 382 * @ptp_tx_skb:   If timestamping is enabled used for timestamping skb
 383 *                Otherwise reserved.
 384 * @ptp_tx_ts_tag: Tag value of 2 step timestamping if timestamping is enabled
 385 *                 Otherwise reserved.
 386 * @tx_skb:       Transmit skb address
 387 */
 388struct axidma_bd {
 389        u32 next;       /* Physical address of next buffer descriptor */
 390        u32 reserved1;
 391        u32 phys;
 392        u32 reserved2;
 393        u32 reserved3;
 394        u32 reserved4;
 395        u32 cntrl;
 396        u32 status;
 397        u32 app0;
 398        u32 app1;       /* TX start << 16 | insert */
 399        u32 app2;       /* TX csum seed */
 400        u32 app3;
 401        u32 app4;
 402        phys_addr_t sw_id_offset; /* first unused field by h/w */
 403        phys_addr_t ptp_tx_skb;
 404        u32 ptp_tx_ts_tag;
 405        phys_addr_t tx_skb;
 406        u32 tx_desc_mapping;
 407} __aligned(128);
 408
 409#define DESC_DMA_MAP_SINGLE 0
 410#define DESC_DMA_MAP_PAGE 1
 411
 412/**
 413 * struct axienet_local - axienet private per device data
 414 * @ndev:       Pointer for net_device to which it will be attached.
 415 * @dev:        Pointer to device structure
 416 * @phy_dev:    Pointer to PHY device structure attached to the axienet_local
 417 * @phy_node:   Pointer to device node structure
 418 * @mii_bus:    Pointer to MII bus structure
 419 * @regs:       Base address for the axienet_local device address space
 420 * @dma_regs:   Base address for the axidma device address space
 421 * @dma_err_tasklet: Tasklet structure to process Axi DMA errors
 422 * @tx_lock:    Spin lock for tx path
 423 * @tx_irq:     Axidma TX IRQ number
 424 * @rx_irq:     Axidma RX IRQ number
 425 * @eth_irq:    Axi Ethernet IRQ number
 426 * @phy_type:   Phy type to identify between MII/GMII/RGMII/SGMII/1000 Base-X
 427 * @options:    AxiEthernet option word
 428 * @last_link:  Phy link state in which the PHY was negotiated earlier
 429 * @features:   Stores the extended features supported by the axienet hw
 430 * @tx_bd_v:    Virtual address of the TX buffer descriptor ring
 431 * @tx_bd_p:    Physical address(start address) of the TX buffer descr. ring
 432 * @rx_bd_v:    Virtual address of the RX buffer descriptor ring
 433 * @rx_bd_p:    Physical address(start address) of the RX buffer descr. ring
 434 * @tx_bd_ci:   Stores the index of the Tx buffer descriptor in the ring being
 435 *              accessed currently. Used while alloc. BDs before a TX starts
 436 * @tx_bd_tail: Stores the index of the Tx buffer descriptor in the ring being
 437 *              accessed currently. Used while processing BDs after the TX
 438 *              completed.
 439 * @rx_bd_ci:   Stores the index of the Rx buffer descriptor in the ring being
 440 *              accessed currently.
 441 * @max_frm_size: Stores the maximum size of the frame that can be that
 442 *                Txed/Rxed in the existing hardware. If jumbo option is
 443 *                supported, the maximum frame size would be 9k. Else it is
 444 *                1522 bytes (assuming support for basic VLAN)
 445 * @rxmem:      Stores rx memory size for jumbo frame handling.
 446 * @csum_offload_on_tx_path:    Stores the checksum selection on TX side.
 447 * @csum_offload_on_rx_path:    Stores the checksum selection on RX side.
 448 * @coalesce_count_rx:  Store the irq coalesce on RX side.
 449 * @coalesce_count_tx:  Store the irq coalesce on TX side.
 450 * @is_10Gmac:    Check for 10g mac.
 451 * @phy_interface: Phy interface type.
 452 * @phy_flags:  Phy interface flags.
 453 * @eth_hasnobuf: Ethernet is configured in Non buf mode.
 454 * @tx_ts_regs:   Base address for the axififo device address space.
 455 * @tstamp_config: Hardware timestamp config structure.
 456 */
 457struct axienet_local {
 458        struct net_device *ndev;
 459        struct device *dev;
 460
 461        /* Connection to PHY device */
 462        struct phy_device *phy_dev;     /* Pointer to PHY device */
 463        struct device_node *phy_node;
 464
 465        /* MDIO bus data */
 466        struct mii_bus *mii_bus;        /* MII bus reference */
 467
 468        /* IO registers, dma functions and IRQs */
 469        void __iomem *regs;
 470        void __iomem *dma_regs;
 471
 472        struct tasklet_struct dma_err_tasklet;
 473        spinlock_t tx_lock;
 474        spinlock_t rx_lock;             /* Spin lock */
 475        struct napi_struct napi;        /* NAPI Structure */
 476
 477        int tx_irq;
 478        int rx_irq;
 479        int eth_irq;
 480        u32 phy_type;
 481
 482        u32 options;                    /* Current options word */
 483        u32 last_link;
 484        u32 features;
 485
 486        /* Buffer descriptors */
 487        struct axidma_bd *tx_bd_v;
 488        dma_addr_t tx_bd_p;
 489        struct axidma_bd *rx_bd_v;
 490        dma_addr_t rx_bd_p;
 491        u32 tx_bd_ci;
 492        u32 tx_bd_tail;
 493        u32 rx_bd_ci;
 494
 495        u32 max_frm_size;
 496        u32 rxmem;
 497
 498        int csum_offload_on_tx_path;
 499        int csum_offload_on_rx_path;
 500
 501        u32 coalesce_count_rx;
 502        u32 coalesce_count_tx;
 503        u32 is_10Gmac;
 504        u32 phy_interface;
 505        u32 phy_flags;
 506        bool eth_hasnobuf;
 507
 508#ifdef CONFIG_XILINX_AXI_EMAC_HWTSTAMP
 509        void __iomem *tx_ts_regs;
 510        struct hwtstamp_config tstamp_config;
 511#endif
 512};
 513
 514/**
 515 * struct axiethernet_option - Used to set axi ethernet hardware options
 516 * @opt:        Option to be set.
 517 * @reg:        Register offset to be written for setting the option
 518 * @m_or:       Mask to be ORed for setting the option in the register
 519 */
 520struct axienet_option {
 521        u32 opt;
 522        u32 reg;
 523        u32 m_or;
 524};
 525
 526/**
 527 * axienet_ior - Memory mapped Axi Ethernet register read
 528 * @lp:         Pointer to axienet local structure
 529 * @offset:     Address offset from the base address of Axi Ethernet core
 530 *
 531 * Return: The contents of the Axi Ethernet register
 532 *
 533 * This function returns the contents of the corresponding register.
 534 */
 535static inline u32 axienet_ior(struct axienet_local *lp, off_t offset)
 536{
 537        return in_be32(lp->regs + offset);
 538}
 539
 540/**
 541 * axienet_iow - Memory mapped Axi Ethernet register write
 542 * @lp:         Pointer to axienet local structure
 543 * @offset:     Address offset from the base address of Axi Ethernet core
 544 * @value:      Value to be written into the Axi Ethernet register
 545 *
 546 * This function writes the desired value into the corresponding Axi Ethernet
 547 * register.
 548 */
 549static inline void axienet_iow(struct axienet_local *lp, off_t offset,
 550                               u32 value)
 551{
 552        out_be32((lp->regs + offset), value);
 553}
 554
 555#ifdef CONFIG_XILINX_AXI_EMAC_HWTSTAMP
 556/**
 557 * axienet_txts_ior - Memory mapped AXI FIFO MM S register read
 558 * @lp:         Pointer to axienet_local structure
 559 * @reg:     Address offset from the base address of AXI FIFO MM S
 560 *              core
 561 *
 562 * Return: the contents of the AXI FIFO MM S register
 563 */
 564
 565static inline u32 axienet_txts_ior(struct axienet_local *lp, off_t reg)
 566{
 567        return in_be32(lp->tx_ts_regs + reg);
 568}
 569
 570/**
 571 * axienet_txts_iow - Memory mapper AXI FIFO MM S register write
 572 * @lp:         Pointer to axienet_local structure
 573 * @reg:     Address offset from the base address of AXI FIFO MM S
 574 *              core.
 575 * @value:      Value to be written into the AXI FIFO MM S register
 576 */
 577static inline void axienet_txts_iow(struct  axienet_local *lp, off_t reg,
 578                                    u32 value)
 579{
 580        out_be32((lp->tx_ts_regs + reg), value);
 581}
 582#endif
 583
 584/* Function prototypes visible in xilinx_axienet_mdio.c for other files */
 585int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np);
 586int axienet_mdio_wait_until_ready(struct axienet_local *lp);
 587void axienet_mdio_teardown(struct axienet_local *lp);
 588
 589#endif /* XILINX_AXI_ENET_H */
 590