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17#include <linux/types.h>
18#include "core.h"
19#include "hw.h"
20
21const struct ath10k_hw_regs qca988x_regs = {
22 .rtc_state_cold_reset_mask = 0x00000400,
23 .rtc_soc_base_address = 0x00004000,
24 .rtc_wmac_base_address = 0x00005000,
25 .soc_core_base_address = 0x00009000,
26 .ce_wrapper_base_address = 0x00057000,
27 .ce0_base_address = 0x00057400,
28 .ce1_base_address = 0x00057800,
29 .ce2_base_address = 0x00057c00,
30 .ce3_base_address = 0x00058000,
31 .ce4_base_address = 0x00058400,
32 .ce5_base_address = 0x00058800,
33 .ce6_base_address = 0x00058c00,
34 .ce7_base_address = 0x00059000,
35 .soc_reset_control_si0_rst_mask = 0x00000001,
36 .soc_reset_control_ce_rst_mask = 0x00040000,
37 .soc_chip_id_address = 0x000000ec,
38 .scratch_3_address = 0x00000030,
39 .fw_indicator_address = 0x00009030,
40 .pcie_local_base_address = 0x00080000,
41 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
42 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
43 .pcie_intr_fw_mask = 0x00000400,
44 .pcie_intr_ce_mask_all = 0x0007f800,
45 .pcie_intr_clr_address = 0x00000014,
46};
47
48const struct ath10k_hw_regs qca6174_regs = {
49 .rtc_state_cold_reset_mask = 0x00002000,
50 .rtc_soc_base_address = 0x00000800,
51 .rtc_wmac_base_address = 0x00001000,
52 .soc_core_base_address = 0x0003a000,
53 .ce_wrapper_base_address = 0x00034000,
54 .ce0_base_address = 0x00034400,
55 .ce1_base_address = 0x00034800,
56 .ce2_base_address = 0x00034c00,
57 .ce3_base_address = 0x00035000,
58 .ce4_base_address = 0x00035400,
59 .ce5_base_address = 0x00035800,
60 .ce6_base_address = 0x00035c00,
61 .ce7_base_address = 0x00036000,
62 .soc_reset_control_si0_rst_mask = 0x00000000,
63 .soc_reset_control_ce_rst_mask = 0x00000001,
64 .soc_chip_id_address = 0x000000f0,
65 .scratch_3_address = 0x00000028,
66 .fw_indicator_address = 0x0003a028,
67 .pcie_local_base_address = 0x00080000,
68 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
69 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
70 .pcie_intr_fw_mask = 0x00000400,
71 .pcie_intr_ce_mask_all = 0x0007f800,
72 .pcie_intr_clr_address = 0x00000014,
73};
74
75const struct ath10k_hw_regs qca99x0_regs = {
76 .rtc_state_cold_reset_mask = 0x00000400,
77 .rtc_soc_base_address = 0x00080000,
78 .rtc_wmac_base_address = 0x00000000,
79 .soc_core_base_address = 0x00082000,
80 .ce_wrapper_base_address = 0x0004d000,
81 .ce0_base_address = 0x0004a000,
82 .ce1_base_address = 0x0004a400,
83 .ce2_base_address = 0x0004a800,
84 .ce3_base_address = 0x0004ac00,
85 .ce4_base_address = 0x0004b000,
86 .ce5_base_address = 0x0004b400,
87 .ce6_base_address = 0x0004b800,
88 .ce7_base_address = 0x0004bc00,
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99 .soc_reset_control_si0_rst_mask = 0x00000001,
100 .soc_reset_control_ce_rst_mask = 0x00000100,
101 .soc_chip_id_address = 0x000000ec,
102 .scratch_3_address = 0x00040050,
103 .fw_indicator_address = 0x00040050,
104 .pcie_local_base_address = 0x00000000,
105 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
106 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
107 .pcie_intr_fw_mask = 0x00100000,
108 .pcie_intr_ce_mask_all = 0x000fff00,
109 .pcie_intr_clr_address = 0x00000010,
110};
111
112const struct ath10k_hw_regs qca4019_regs = {
113 .rtc_soc_base_address = 0x00080000,
114 .soc_core_base_address = 0x00082000,
115 .ce_wrapper_base_address = 0x0004d000,
116 .ce0_base_address = 0x0004a000,
117 .ce1_base_address = 0x0004a400,
118 .ce2_base_address = 0x0004a800,
119 .ce3_base_address = 0x0004ac00,
120 .ce4_base_address = 0x0004b000,
121 .ce5_base_address = 0x0004b400,
122 .ce6_base_address = 0x0004b800,
123 .ce7_base_address = 0x0004bc00,
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133 .soc_reset_control_si0_rst_mask = 0x00000001,
134 .soc_reset_control_ce_rst_mask = 0x00000100,
135 .soc_chip_id_address = 0x000000ec,
136 .fw_indicator_address = 0x0004f00c,
137 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
138 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
139 .pcie_intr_fw_mask = 0x00100000,
140 .pcie_intr_ce_mask_all = 0x000fff00,
141 .pcie_intr_clr_address = 0x00000010,
142};
143
144const struct ath10k_hw_values qca988x_values = {
145 .rtc_state_val_on = 3,
146 .ce_count = 8,
147 .msi_assign_ce_max = 7,
148 .num_target_ce_config_wlan = 7,
149 .ce_desc_meta_data_mask = 0xFFFC,
150 .ce_desc_meta_data_lsb = 2,
151};
152
153const struct ath10k_hw_values qca6174_values = {
154 .rtc_state_val_on = 3,
155 .ce_count = 8,
156 .msi_assign_ce_max = 7,
157 .num_target_ce_config_wlan = 7,
158 .ce_desc_meta_data_mask = 0xFFFC,
159 .ce_desc_meta_data_lsb = 2,
160};
161
162const struct ath10k_hw_values qca99x0_values = {
163 .rtc_state_val_on = 5,
164 .ce_count = 12,
165 .msi_assign_ce_max = 12,
166 .num_target_ce_config_wlan = 10,
167 .ce_desc_meta_data_mask = 0xFFF0,
168 .ce_desc_meta_data_lsb = 4,
169};
170
171const struct ath10k_hw_values qca4019_values = {
172 .ce_count = 12,
173 .num_target_ce_config_wlan = 10,
174 .ce_desc_meta_data_mask = 0xFFF0,
175 .ce_desc_meta_data_lsb = 4,
176};
177
178void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
179 u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
180{
181 u32 cc_fix = 0;
182
183 survey->filled |= SURVEY_INFO_TIME |
184 SURVEY_INFO_TIME_BUSY;
185
186 if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) {
187 cc_fix = 0x7fffffff;
188 survey->filled &= ~SURVEY_INFO_TIME_BUSY;
189 }
190
191 cc -= cc_prev - cc_fix;
192 rcc -= rcc_prev;
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194 survey->time = CCNT_TO_MSEC(ar, cc);
195 survey->time_busy = CCNT_TO_MSEC(ar, rcc);
196}
197
