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17#ifndef _HAL_H_
18#define _HAL_H_
19
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32
33
34#define WCN36XX_HAL_VER_MAJOR 1
35#define WCN36XX_HAL_VER_MINOR 4
36#define WCN36XX_HAL_VER_VERSION 1
37#define WCN36XX_HAL_VER_REVISION 2
38
39
40#define WCN36XX_HAL_MAX_ENUM_SIZE 0x7FFFFFFF
41#define WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE 0x7FFF
42
43
44#define STACFG_MAX_TC 8
45
46
47#define WCN36XX_HAL_MAX_AC 4
48
49#define WCN36XX_HAL_IPV4_ADDR_LEN 4
50
51#define WALN_HAL_STA_INVALID_IDX 0xFF
52#define WCN36XX_HAL_BSS_INVALID_IDX 0xFF
53
54
55#define BEACON_TEMPLATE_SIZE 0x180
56
57
58#define PARAM_BCN_INTERVAL_CHANGED (1 << 0)
59#define PARAM_SHORT_PREAMBLE_CHANGED (1 << 1)
60#define PARAM_SHORT_SLOT_TIME_CHANGED (1 << 2)
61#define PARAM_llACOEXIST_CHANGED (1 << 3)
62#define PARAM_llBCOEXIST_CHANGED (1 << 4)
63#define PARAM_llGCOEXIST_CHANGED (1 << 5)
64#define PARAM_HT20MHZCOEXIST_CHANGED (1<<6)
65#define PARAM_NON_GF_DEVICES_PRESENT_CHANGED (1<<7)
66#define PARAM_RIFS_MODE_CHANGED (1<<8)
67#define PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED (1<<9)
68#define PARAM_OBSS_MODE_CHANGED (1<<10)
69#define PARAM_BEACON_UPDATE_MASK \
70 (PARAM_BCN_INTERVAL_CHANGED | \
71 PARAM_SHORT_PREAMBLE_CHANGED | \
72 PARAM_SHORT_SLOT_TIME_CHANGED | \
73 PARAM_llACOEXIST_CHANGED | \
74 PARAM_llBCOEXIST_CHANGED | \
75 PARAM_llGCOEXIST_CHANGED | \
76 PARAM_HT20MHZCOEXIST_CHANGED | \
77 PARAM_NON_GF_DEVICES_PRESENT_CHANGED | \
78 PARAM_RIFS_MODE_CHANGED | \
79 PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED | \
80 PARAM_OBSS_MODE_CHANGED)
81
82
83#define DUMPCMD_RSP_BUFFER 100
84
85
86#define WCN36XX_HAL_VERSION_LENGTH 64
87
88
89enum wcn36xx_hal_host_msg_type {
90
91 WCN36XX_HAL_START_REQ = 0,
92 WCN36XX_HAL_START_RSP = 1,
93 WCN36XX_HAL_STOP_REQ = 2,
94 WCN36XX_HAL_STOP_RSP = 3,
95
96
97 WCN36XX_HAL_INIT_SCAN_REQ = 4,
98 WCN36XX_HAL_INIT_SCAN_RSP = 5,
99 WCN36XX_HAL_START_SCAN_REQ = 6,
100 WCN36XX_HAL_START_SCAN_RSP = 7,
101 WCN36XX_HAL_END_SCAN_REQ = 8,
102 WCN36XX_HAL_END_SCAN_RSP = 9,
103 WCN36XX_HAL_FINISH_SCAN_REQ = 10,
104 WCN36XX_HAL_FINISH_SCAN_RSP = 11,
105
106
107 WCN36XX_HAL_CONFIG_STA_REQ = 12,
108 WCN36XX_HAL_CONFIG_STA_RSP = 13,
109 WCN36XX_HAL_DELETE_STA_REQ = 14,
110 WCN36XX_HAL_DELETE_STA_RSP = 15,
111 WCN36XX_HAL_CONFIG_BSS_REQ = 16,
112 WCN36XX_HAL_CONFIG_BSS_RSP = 17,
113 WCN36XX_HAL_DELETE_BSS_REQ = 18,
114 WCN36XX_HAL_DELETE_BSS_RSP = 19,
115
116
117 WCN36XX_HAL_JOIN_REQ = 20,
118 WCN36XX_HAL_JOIN_RSP = 21,
119 WCN36XX_HAL_POST_ASSOC_REQ = 22,
120 WCN36XX_HAL_POST_ASSOC_RSP = 23,
121
122
123 WCN36XX_HAL_SET_BSSKEY_REQ = 24,
124 WCN36XX_HAL_SET_BSSKEY_RSP = 25,
125 WCN36XX_HAL_SET_STAKEY_REQ = 26,
126 WCN36XX_HAL_SET_STAKEY_RSP = 27,
127 WCN36XX_HAL_RMV_BSSKEY_REQ = 28,
128 WCN36XX_HAL_RMV_BSSKEY_RSP = 29,
129 WCN36XX_HAL_RMV_STAKEY_REQ = 30,
130 WCN36XX_HAL_RMV_STAKEY_RSP = 31,
131
132
133 WCN36XX_HAL_ADD_TS_REQ = 32,
134 WCN36XX_HAL_ADD_TS_RSP = 33,
135 WCN36XX_HAL_DEL_TS_REQ = 34,
136 WCN36XX_HAL_DEL_TS_RSP = 35,
137 WCN36XX_HAL_UPD_EDCA_PARAMS_REQ = 36,
138 WCN36XX_HAL_UPD_EDCA_PARAMS_RSP = 37,
139 WCN36XX_HAL_ADD_BA_REQ = 38,
140 WCN36XX_HAL_ADD_BA_RSP = 39,
141 WCN36XX_HAL_DEL_BA_REQ = 40,
142 WCN36XX_HAL_DEL_BA_RSP = 41,
143
144 WCN36XX_HAL_CH_SWITCH_REQ = 42,
145 WCN36XX_HAL_CH_SWITCH_RSP = 43,
146 WCN36XX_HAL_SET_LINK_ST_REQ = 44,
147 WCN36XX_HAL_SET_LINK_ST_RSP = 45,
148 WCN36XX_HAL_GET_STATS_REQ = 46,
149 WCN36XX_HAL_GET_STATS_RSP = 47,
150 WCN36XX_HAL_UPDATE_CFG_REQ = 48,
151 WCN36XX_HAL_UPDATE_CFG_RSP = 49,
152
153 WCN36XX_HAL_MISSED_BEACON_IND = 50,
154 WCN36XX_HAL_UNKNOWN_ADDR2_FRAME_RX_IND = 51,
155 WCN36XX_HAL_MIC_FAILURE_IND = 52,
156 WCN36XX_HAL_FATAL_ERROR_IND = 53,
157 WCN36XX_HAL_SET_KEYDONE_MSG = 54,
158
159
160 WCN36XX_HAL_DOWNLOAD_NV_REQ = 55,
161 WCN36XX_HAL_DOWNLOAD_NV_RSP = 56,
162
163 WCN36XX_HAL_ADD_BA_SESSION_REQ = 57,
164 WCN36XX_HAL_ADD_BA_SESSION_RSP = 58,
165 WCN36XX_HAL_TRIGGER_BA_REQ = 59,
166 WCN36XX_HAL_TRIGGER_BA_RSP = 60,
167 WCN36XX_HAL_UPDATE_BEACON_REQ = 61,
168 WCN36XX_HAL_UPDATE_BEACON_RSP = 62,
169 WCN36XX_HAL_SEND_BEACON_REQ = 63,
170 WCN36XX_HAL_SEND_BEACON_RSP = 64,
171
172 WCN36XX_HAL_SET_BCASTKEY_REQ = 65,
173 WCN36XX_HAL_SET_BCASTKEY_RSP = 66,
174 WCN36XX_HAL_DELETE_STA_CONTEXT_IND = 67,
175 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_REQ = 68,
176 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_RSP = 69,
177
178
179 WCN36XX_HAL_PROCESS_PTT_REQ = 70,
180 WCN36XX_HAL_PROCESS_PTT_RSP = 71,
181
182
183 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_REQ = 72,
184 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_RSP = 73,
185 WCN36XX_HAL_TL_HAL_FLUSH_AC_REQ = 74,
186 WCN36XX_HAL_TL_HAL_FLUSH_AC_RSP = 75,
187
188 WCN36XX_HAL_ENTER_IMPS_REQ = 76,
189 WCN36XX_HAL_EXIT_IMPS_REQ = 77,
190 WCN36XX_HAL_ENTER_BMPS_REQ = 78,
191 WCN36XX_HAL_EXIT_BMPS_REQ = 79,
192 WCN36XX_HAL_ENTER_UAPSD_REQ = 80,
193 WCN36XX_HAL_EXIT_UAPSD_REQ = 81,
194 WCN36XX_HAL_UPDATE_UAPSD_PARAM_REQ = 82,
195 WCN36XX_HAL_CONFIGURE_RXP_FILTER_REQ = 83,
196 WCN36XX_HAL_ADD_BCN_FILTER_REQ = 84,
197 WCN36XX_HAL_REM_BCN_FILTER_REQ = 85,
198 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN = 86,
199 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN = 87,
200 WCN36XX_HAL_ENTER_WOWL_REQ = 88,
201 WCN36XX_HAL_EXIT_WOWL_REQ = 89,
202 WCN36XX_HAL_HOST_OFFLOAD_REQ = 90,
203 WCN36XX_HAL_SET_RSSI_THRESH_REQ = 91,
204 WCN36XX_HAL_GET_RSSI_REQ = 92,
205 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_REQ = 93,
206 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_REQ = 94,
207
208 WCN36XX_HAL_ENTER_IMPS_RSP = 95,
209 WCN36XX_HAL_EXIT_IMPS_RSP = 96,
210 WCN36XX_HAL_ENTER_BMPS_RSP = 97,
211 WCN36XX_HAL_EXIT_BMPS_RSP = 98,
212 WCN36XX_HAL_ENTER_UAPSD_RSP = 99,
213 WCN36XX_HAL_EXIT_UAPSD_RSP = 100,
214 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_RSP = 101,
215 WCN36XX_HAL_UPDATE_UAPSD_PARAM_RSP = 102,
216 WCN36XX_HAL_CONFIGURE_RXP_FILTER_RSP = 103,
217 WCN36XX_HAL_ADD_BCN_FILTER_RSP = 104,
218 WCN36XX_HAL_REM_BCN_FILTER_RSP = 105,
219 WCN36XX_HAL_SET_RSSI_THRESH_RSP = 106,
220 WCN36XX_HAL_HOST_OFFLOAD_RSP = 107,
221 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN_RSP = 108,
222 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN_RSP = 109,
223 WCN36XX_HAL_ENTER_WOWL_RSP = 110,
224 WCN36XX_HAL_EXIT_WOWL_RSP = 111,
225 WCN36XX_HAL_RSSI_NOTIFICATION_IND = 112,
226 WCN36XX_HAL_GET_RSSI_RSP = 113,
227 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_RSP = 114,
228
229
230 WCN36XX_HAL_SET_MAX_TX_POWER_REQ = 115,
231 WCN36XX_HAL_SET_MAX_TX_POWER_RSP = 116,
232
233
234 WCN36XX_HAL_AGGR_ADD_TS_REQ = 117,
235 WCN36XX_HAL_AGGR_ADD_TS_RSP = 118,
236
237
238 WCN36XX_HAL_SET_P2P_GONOA_REQ = 119,
239 WCN36XX_HAL_SET_P2P_GONOA_RSP = 120,
240
241
242 WCN36XX_HAL_DUMP_COMMAND_REQ = 121,
243 WCN36XX_HAL_DUMP_COMMAND_RSP = 122,
244
245
246 WCN36XX_HAL_START_OEM_DATA_REQ = 123,
247 WCN36XX_HAL_START_OEM_DATA_RSP = 124,
248
249
250 WCN36XX_HAL_ADD_STA_SELF_REQ = 125,
251 WCN36XX_HAL_ADD_STA_SELF_RSP = 126,
252
253
254 WCN36XX_HAL_DEL_STA_SELF_REQ = 127,
255 WCN36XX_HAL_DEL_STA_SELF_RSP = 128,
256
257
258 WCN36XX_HAL_COEX_IND = 129,
259
260
261 WCN36XX_HAL_OTA_TX_COMPL_IND = 130,
262
263
264 WCN36XX_HAL_HOST_SUSPEND_IND = 131,
265 WCN36XX_HAL_HOST_RESUME_REQ = 132,
266 WCN36XX_HAL_HOST_RESUME_RSP = 133,
267
268 WCN36XX_HAL_SET_TX_POWER_REQ = 134,
269 WCN36XX_HAL_SET_TX_POWER_RSP = 135,
270 WCN36XX_HAL_GET_TX_POWER_REQ = 136,
271 WCN36XX_HAL_GET_TX_POWER_RSP = 137,
272
273 WCN36XX_HAL_P2P_NOA_ATTR_IND = 138,
274
275 WCN36XX_HAL_ENABLE_RADAR_DETECT_REQ = 139,
276 WCN36XX_HAL_ENABLE_RADAR_DETECT_RSP = 140,
277 WCN36XX_HAL_GET_TPC_REPORT_REQ = 141,
278 WCN36XX_HAL_GET_TPC_REPORT_RSP = 142,
279 WCN36XX_HAL_RADAR_DETECT_IND = 143,
280 WCN36XX_HAL_RADAR_DETECT_INTR_IND = 144,
281 WCN36XX_HAL_KEEP_ALIVE_REQ = 145,
282 WCN36XX_HAL_KEEP_ALIVE_RSP = 146,
283
284
285 WCN36XX_HAL_SET_PREF_NETWORK_REQ = 147,
286 WCN36XX_HAL_SET_PREF_NETWORK_RSP = 148,
287 WCN36XX_HAL_SET_RSSI_FILTER_REQ = 149,
288 WCN36XX_HAL_SET_RSSI_FILTER_RSP = 150,
289 WCN36XX_HAL_UPDATE_SCAN_PARAM_REQ = 151,
290 WCN36XX_HAL_UPDATE_SCAN_PARAM_RSP = 152,
291 WCN36XX_HAL_PREF_NETW_FOUND_IND = 153,
292
293 WCN36XX_HAL_SET_TX_PER_TRACKING_REQ = 154,
294 WCN36XX_HAL_SET_TX_PER_TRACKING_RSP = 155,
295 WCN36XX_HAL_TX_PER_HIT_IND = 156,
296
297 WCN36XX_HAL_8023_MULTICAST_LIST_REQ = 157,
298 WCN36XX_HAL_8023_MULTICAST_LIST_RSP = 158,
299
300 WCN36XX_HAL_SET_PACKET_FILTER_REQ = 159,
301 WCN36XX_HAL_SET_PACKET_FILTER_RSP = 160,
302 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_REQ = 161,
303 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_RSP = 162,
304 WCN36XX_HAL_CLEAR_PACKET_FILTER_REQ = 163,
305 WCN36XX_HAL_CLEAR_PACKET_FILTER_RSP = 164,
306
307
308
309
310
311 WCN36XX_HAL_INIT_SCAN_CON_REQ = 165,
312
313 WCN36XX_HAL_SET_POWER_PARAMS_REQ = 166,
314 WCN36XX_HAL_SET_POWER_PARAMS_RSP = 167,
315
316 WCN36XX_HAL_TSM_STATS_REQ = 168,
317 WCN36XX_HAL_TSM_STATS_RSP = 169,
318
319
320 WCN36XX_HAL_WAKE_REASON_IND = 170,
321
322
323 WCN36XX_HAL_GTK_OFFLOAD_REQ = 171,
324 WCN36XX_HAL_GTK_OFFLOAD_RSP = 172,
325 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_REQ = 173,
326 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_RSP = 174,
327
328 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_REQ = 175,
329 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_RSP = 176,
330 WCN36XX_HAL_EXCLUDE_UNENCRYPTED_IND = 177,
331
332 WCN36XX_HAL_SET_THERMAL_MITIGATION_REQ = 178,
333 WCN36XX_HAL_SET_THERMAL_MITIGATION_RSP = 179,
334
335 WCN36XX_HAL_UPDATE_VHT_OP_MODE_REQ = 182,
336 WCN36XX_HAL_UPDATE_VHT_OP_MODE_RSP = 183,
337
338 WCN36XX_HAL_P2P_NOA_START_IND = 184,
339
340 WCN36XX_HAL_GET_ROAM_RSSI_REQ = 185,
341 WCN36XX_HAL_GET_ROAM_RSSI_RSP = 186,
342
343 WCN36XX_HAL_CLASS_B_STATS_IND = 187,
344 WCN36XX_HAL_DEL_BA_IND = 188,
345 WCN36XX_HAL_DHCP_START_IND = 189,
346 WCN36XX_HAL_DHCP_STOP_IND = 190,
347
348 WCN36XX_HAL_AVOID_FREQ_RANGE_IND = 233,
349
350 WCN36XX_HAL_MSG_MAX = WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE
351};
352
353
354enum wcn36xx_hal_host_msg_version {
355 WCN36XX_HAL_MSG_VERSION0 = 0,
356 WCN36XX_HAL_MSG_VERSION1 = 1,
357
358 WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION = 0x7FFF,
359 WCN36XX_HAL_MSG_VERSION_MAX_FIELD = WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION
360};
361
362enum driver_type {
363 DRIVER_TYPE_PRODUCTION = 0,
364 DRIVER_TYPE_MFG = 1,
365 DRIVER_TYPE_DVT = 2,
366 DRIVER_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
367};
368
369enum wcn36xx_hal_stop_type {
370 HAL_STOP_TYPE_SYS_RESET,
371 HAL_STOP_TYPE_SYS_DEEP_SLEEP,
372 HAL_STOP_TYPE_RF_KILL,
373 HAL_STOP_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
374};
375
376enum wcn36xx_hal_sys_mode {
377 HAL_SYS_MODE_NORMAL,
378 HAL_SYS_MODE_LEARN,
379 HAL_SYS_MODE_SCAN,
380 HAL_SYS_MODE_PROMISC,
381 HAL_SYS_MODE_SUSPEND_LINK,
382 HAL_SYS_MODE_ROAM_SCAN,
383 HAL_SYS_MODE_ROAM_SUSPEND_LINK,
384 HAL_SYS_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
385};
386
387enum phy_chan_bond_state {
388
389 PHY_SINGLE_CHANNEL_CENTERED = 0,
390
391
392 PHY_DOUBLE_CHANNEL_LOW_PRIMARY = 1,
393
394
395 PHY_DOUBLE_CHANNEL_CENTERED = 2,
396
397
398 PHY_DOUBLE_CHANNEL_HIGH_PRIMARY = 3,
399
400
401 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_CENTERED = 4,
402
403
404 PHY_QUADRUPLE_CHANNEL_20MHZ_CENTERED_40MHZ_CENTERED = 5,
405
406
407 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_CENTERED = 6,
408
409
410 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW = 7,
411
412
413 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW = 8,
414
415
416 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH = 9,
417
418
419 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH = 10,
420
421 PHY_CHANNEL_BONDING_STATE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
422};
423
424
425enum wcn36xx_hal_ht_mimo_state {
426
427 WCN36XX_HAL_HT_MIMO_PS_STATIC = 0,
428
429
430 WCN36XX_HAL_HT_MIMO_PS_DYNAMIC = 1,
431
432
433 WCN36XX_HAL_HT_MIMO_PS_NA = 2,
434
435
436 WCN36XX_HAL_HT_MIMO_PS_NO_LIMIT = 3,
437
438 WCN36XX_HAL_HT_MIMO_PS_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
439};
440
441
442enum sta_rate_mode {
443 STA_TAURUS = 0,
444 STA_TITAN,
445 STA_POLARIS,
446 STA_11b,
447 STA_11bg,
448 STA_11a,
449 STA_11n,
450 STA_11ac,
451 STA_INVALID_RATE_MODE = WCN36XX_HAL_MAX_ENUM_SIZE
452};
453
454
455#define WCN36XX_HAL_NUM_DSSS_RATES 4
456
457
458#define WCN36XX_HAL_NUM_OFDM_RATES 8
459
460
461#define WCN36XX_HAL_NUM_POLARIS_RATES 3
462
463#define WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET 16
464
465enum wcn36xx_hal_bss_type {
466 WCN36XX_HAL_INFRASTRUCTURE_MODE,
467
468
469 WCN36XX_HAL_INFRA_AP_MODE,
470
471 WCN36XX_HAL_IBSS_MODE,
472
473
474 WCN36XX_HAL_BTAMP_STA_MODE,
475
476
477 WCN36XX_HAL_BTAMP_AP_MODE,
478
479 WCN36XX_HAL_AUTO_MODE,
480
481 WCN36XX_HAL_DONOT_USE_BSS_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
482};
483
484enum wcn36xx_hal_nw_type {
485 WCN36XX_HAL_11A_NW_TYPE,
486 WCN36XX_HAL_11B_NW_TYPE,
487 WCN36XX_HAL_11G_NW_TYPE,
488 WCN36XX_HAL_11N_NW_TYPE,
489 WCN36XX_HAL_DONOT_USE_NW_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
490};
491
492#define WCN36XX_HAL_MAC_RATESET_EID_MAX 12
493
494enum wcn36xx_hal_ht_operating_mode {
495
496 WCN36XX_HAL_HT_OP_MODE_PURE,
497
498
499 WCN36XX_HAL_HT_OP_MODE_OVERLAP_LEGACY,
500
501
502 WCN36XX_HAL_HT_OP_MODE_NO_LEGACY_20MHZ_HT,
503
504
505 WCN36XX_HAL_HT_OP_MODE_MIXED,
506
507 WCN36XX_HAL_HT_OP_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
508};
509
510
511enum ani_ed_type {
512 WCN36XX_HAL_ED_NONE,
513 WCN36XX_HAL_ED_WEP40,
514 WCN36XX_HAL_ED_WEP104,
515 WCN36XX_HAL_ED_TKIP,
516 WCN36XX_HAL_ED_CCMP,
517 WCN36XX_HAL_ED_WPI,
518 WCN36XX_HAL_ED_AES_128_CMAC,
519 WCN36XX_HAL_ED_NOT_IMPLEMENTED = WCN36XX_HAL_MAX_ENUM_SIZE
520};
521
522#define WLAN_MAX_KEY_RSC_LEN 16
523#define WLAN_WAPI_KEY_RSC_LEN 16
524
525
526#define WCN36XX_HAL_MAC_MAX_KEY_LENGTH 32
527#define WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS 4
528
529
530
531
532enum ani_key_direction {
533 WCN36XX_HAL_TX_ONLY,
534 WCN36XX_HAL_RX_ONLY,
535 WCN36XX_HAL_TX_RX,
536 WCN36XX_HAL_TX_DEFAULT,
537 WCN36XX_HAL_DONOT_USE_KEY_DIRECTION = WCN36XX_HAL_MAX_ENUM_SIZE
538};
539
540enum ani_wep_type {
541 WCN36XX_HAL_WEP_STATIC,
542 WCN36XX_HAL_WEP_DYNAMIC,
543 WCN36XX_HAL_WEP_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
544};
545
546enum wcn36xx_hal_link_state {
547
548 WCN36XX_HAL_LINK_IDLE_STATE = 0,
549 WCN36XX_HAL_LINK_PREASSOC_STATE = 1,
550 WCN36XX_HAL_LINK_POSTASSOC_STATE = 2,
551 WCN36XX_HAL_LINK_AP_STATE = 3,
552 WCN36XX_HAL_LINK_IBSS_STATE = 4,
553
554
555 WCN36XX_HAL_LINK_BTAMP_PREASSOC_STATE = 5,
556 WCN36XX_HAL_LINK_BTAMP_POSTASSOC_STATE = 6,
557 WCN36XX_HAL_LINK_BTAMP_AP_STATE = 7,
558 WCN36XX_HAL_LINK_BTAMP_STA_STATE = 8,
559
560
561 WCN36XX_HAL_LINK_LEARN_STATE = 9,
562 WCN36XX_HAL_LINK_SCAN_STATE = 10,
563 WCN36XX_HAL_LINK_FINISH_SCAN_STATE = 11,
564 WCN36XX_HAL_LINK_INIT_CAL_STATE = 12,
565 WCN36XX_HAL_LINK_FINISH_CAL_STATE = 13,
566 WCN36XX_HAL_LINK_LISTEN_STATE = 14,
567
568 WCN36XX_HAL_LINK_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
569};
570
571enum wcn36xx_hal_stats_mask {
572 HAL_SUMMARY_STATS_INFO = 0x00000001,
573 HAL_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
574 HAL_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
575 HAL_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
576 HAL_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
577 HAL_PER_STA_STATS_INFO = 0x00000020
578};
579
580
581enum bt_amp_event_type {
582 BTAMP_EVENT_CONNECTION_START,
583 BTAMP_EVENT_CONNECTION_STOP,
584 BTAMP_EVENT_CONNECTION_TERMINATED,
585
586
587 BTAMP_EVENT_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
588};
589
590
591enum pe_stats_mask {
592 PE_SUMMARY_STATS_INFO = 0x00000001,
593 PE_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
594 PE_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
595 PE_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
596 PE_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
597 PE_PER_STA_STATS_INFO = 0x00000020,
598
599
600 PE_STATS_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
601};
602
603
604
605
606#define WCN36XX_HAL_CFG_STA_ID 0
607#define WCN36XX_HAL_CFG_CURRENT_TX_ANTENNA 1
608#define WCN36XX_HAL_CFG_CURRENT_RX_ANTENNA 2
609#define WCN36XX_HAL_CFG_LOW_GAIN_OVERRIDE 3
610#define WCN36XX_HAL_CFG_POWER_STATE_PER_CHAIN 4
611#define WCN36XX_HAL_CFG_CAL_PERIOD 5
612#define WCN36XX_HAL_CFG_CAL_CONTROL 6
613#define WCN36XX_HAL_CFG_PROXIMITY 7
614#define WCN36XX_HAL_CFG_NETWORK_DENSITY 8
615#define WCN36XX_HAL_CFG_MAX_MEDIUM_TIME 9
616#define WCN36XX_HAL_CFG_MAX_MPDUS_IN_AMPDU 10
617#define WCN36XX_HAL_CFG_RTS_THRESHOLD 11
618#define WCN36XX_HAL_CFG_SHORT_RETRY_LIMIT 12
619#define WCN36XX_HAL_CFG_LONG_RETRY_LIMIT 13
620#define WCN36XX_HAL_CFG_FRAGMENTATION_THRESHOLD 14
621#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ZERO 15
622#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ONE 16
623#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_TWO 17
624#define WCN36XX_HAL_CFG_FIXED_RATE 18
625#define WCN36XX_HAL_CFG_RETRYRATE_POLICY 19
626#define WCN36XX_HAL_CFG_RETRYRATE_SECONDARY 20
627#define WCN36XX_HAL_CFG_RETRYRATE_TERTIARY 21
628#define WCN36XX_HAL_CFG_FORCE_POLICY_PROTECTION 22
629#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_24GHZ 23
630#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_5GHZ 24
631#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_24GHZ 25
632#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_5GHZ 26
633#define WCN36XX_HAL_CFG_MAX_BA_SESSIONS 27
634#define WCN36XX_HAL_CFG_PS_DATA_INACTIVITY_TIMEOUT 28
635#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_FILTER 29
636#define WCN36XX_HAL_CFG_PS_ENABLE_RSSI_MONITOR 30
637#define WCN36XX_HAL_CFG_NUM_BEACON_PER_RSSI_AVERAGE 31
638#define WCN36XX_HAL_CFG_STATS_PERIOD 32
639#define WCN36XX_HAL_CFG_CFP_MAX_DURATION 33
640#define WCN36XX_HAL_CFG_FRAME_TRANS_ENABLED 34
641#define WCN36XX_HAL_CFG_DTIM_PERIOD 35
642#define WCN36XX_HAL_CFG_EDCA_WMM_ACBK 36
643#define WCN36XX_HAL_CFG_EDCA_WMM_ACBE 37
644#define WCN36XX_HAL_CFG_EDCA_WMM_ACVO 38
645#define WCN36XX_HAL_CFG_EDCA_WMM_ACVI 39
646#define WCN36XX_HAL_CFG_BA_THRESHOLD_HIGH 40
647#define WCN36XX_HAL_CFG_MAX_BA_BUFFERS 41
648#define WCN36XX_HAL_CFG_RPE_POLLING_THRESHOLD 42
649#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC0_REG 43
650#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC1_REG 44
651#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC2_REG 45
652#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC3_REG 46
653#define WCN36XX_HAL_CFG_NO_OF_ONCHIP_REORDER_SESSIONS 47
654#define WCN36XX_HAL_CFG_PS_LISTEN_INTERVAL 48
655#define WCN36XX_HAL_CFG_PS_HEART_BEAT_THRESHOLD 49
656#define WCN36XX_HAL_CFG_PS_NTH_BEACON_FILTER 50
657#define WCN36XX_HAL_CFG_PS_MAX_PS_POLL 51
658#define WCN36XX_HAL_CFG_PS_MIN_RSSI_THRESHOLD 52
659#define WCN36XX_HAL_CFG_PS_RSSI_FILTER_PERIOD 53
660#define WCN36XX_HAL_CFG_PS_BROADCAST_FRAME_FILTER_ENABLE 54
661#define WCN36XX_HAL_CFG_PS_IGNORE_DTIM 55
662#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_EARLY_TERM 56
663#define WCN36XX_HAL_CFG_DYNAMIC_PS_POLL_VALUE 57
664#define WCN36XX_HAL_CFG_PS_NULLDATA_AP_RESP_TIMEOUT 58
665#define WCN36XX_HAL_CFG_TELE_BCN_WAKEUP_EN 59
666#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI 60
667#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS 61
668#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI 62
669#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI_IDLE_BCNS 63
670#define WCN36XX_HAL_CFG_TX_PWR_CTRL_ENABLE 64
671#define WCN36XX_HAL_CFG_VALID_RADAR_CHANNEL_LIST 65
672#define WCN36XX_HAL_CFG_TX_POWER_24_20 66
673#define WCN36XX_HAL_CFG_TX_POWER_24_40 67
674#define WCN36XX_HAL_CFG_TX_POWER_50_20 68
675#define WCN36XX_HAL_CFG_TX_POWER_50_40 69
676#define WCN36XX_HAL_CFG_MCAST_BCAST_FILTER_SETTING 70
677#define WCN36XX_HAL_CFG_BCN_EARLY_TERM_WAKEUP_INTERVAL 71
678#define WCN36XX_HAL_CFG_MAX_TX_POWER_2_4 72
679#define WCN36XX_HAL_CFG_MAX_TX_POWER_5 73
680#define WCN36XX_HAL_CFG_INFRA_STA_KEEP_ALIVE_PERIOD 74
681#define WCN36XX_HAL_CFG_ENABLE_CLOSE_LOOP 75
682#define WCN36XX_HAL_CFG_BTC_EXECUTION_MODE 76
683#define WCN36XX_HAL_CFG_BTC_DHCP_BT_SLOTS_TO_BLOCK 77
684#define WCN36XX_HAL_CFG_BTC_A2DP_DHCP_BT_SUB_INTERVALS 78
685#define WCN36XX_HAL_CFG_PS_TX_INACTIVITY_TIMEOUT 79
686#define WCN36XX_HAL_CFG_WCNSS_API_VERSION 80
687#define WCN36XX_HAL_CFG_AP_KEEPALIVE_TIMEOUT 81
688#define WCN36XX_HAL_CFG_GO_KEEPALIVE_TIMEOUT 82
689#define WCN36XX_HAL_CFG_ENABLE_MC_ADDR_LIST 83
690#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_BT 84
691#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_BT 85
692#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_BT 86
693#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_BT 87
694#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_WLAN 88
695#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_WLAN 89
696#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_WLAN 90
697#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_WLAN 91
698#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_BT 92
699#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_WLAN 93
700#define WCN36XX_HAL_CFG_BTC_MAX_SCO_BLOCK_PERC 94
701#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_A2DP 95
702#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_SCO 96
703#define WCN36XX_HAL_CFG_ENABLE_UNICAST_FILTER 97
704#define WCN36XX_HAL_CFG_MAX_ASSOC_LIMIT 98
705#define WCN36XX_HAL_CFG_ENABLE_LPWR_IMG_TRANSITION 99
706#define WCN36XX_HAL_CFG_ENABLE_MCC_ADAPTIVE_SCHEDULER 100
707#define WCN36XX_HAL_CFG_ENABLE_DETECT_PS_SUPPORT 101
708#define WCN36XX_HAL_CFG_AP_LINK_MONITOR_TIMEOUT 102
709#define WCN36XX_HAL_CFG_BTC_DWELL_TIME_MULTIPLIER 103
710#define WCN36XX_HAL_CFG_ENABLE_TDLS_OXYGEN_MODE 104
711#define WCN36XX_HAL_CFG_MAX_PARAMS 105
712
713
714
715
716struct wcnss_wlan_version {
717 u8 revision;
718 u8 version;
719 u8 minor;
720 u8 major;
721} __packed;
722
723
724struct wcn36xx_hal_keys {
725 u8 id;
726
727
728 u8 unicast;
729
730 enum ani_key_direction direction;
731
732
733 u8 rsc[WLAN_MAX_KEY_RSC_LEN];
734
735
736 u8 pae_role;
737
738 u16 length;
739 u8 key[WCN36XX_HAL_MAC_MAX_KEY_LENGTH];
740} __packed;
741
742
743
744
745
746struct wcn36xx_hal_set_sta_key_params {
747
748 u16 sta_index;
749
750
751 enum ani_ed_type enc_type;
752
753
754 enum ani_wep_type wep_type;
755
756
757 u8 def_wep_idx;
758
759
760 struct wcn36xx_hal_keys key[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
761
762
763
764
765
766 u8 single_tid_rc;
767
768} __packed;
769
770
771struct wcn36xx_hal_msg_header {
772 enum wcn36xx_hal_host_msg_type msg_type:16;
773 enum wcn36xx_hal_host_msg_version msg_version:16;
774 u32 len;
775} __packed;
776
777
778struct wcn36xx_hal_cfg {
779
780
781 u16 id;
782
783
784
785 u16 len;
786
787
788 u16 pad_bytes;
789
790
791 u16 reserve;
792
793
794
795} __packed;
796
797struct wcn36xx_hal_mac_start_parameters {
798
799 enum driver_type type;
800
801
802 u32 len;
803
804
805
806
807
808
809
810} __packed;
811
812struct wcn36xx_hal_mac_start_req_msg {
813
814 struct wcn36xx_hal_msg_header header;
815 struct wcn36xx_hal_mac_start_parameters params;
816} __packed;
817
818struct wcn36xx_hal_mac_start_rsp_params {
819
820 u16 status;
821
822
823 u8 stations;
824
825
826 u8 bssids;
827
828
829 struct wcnss_wlan_version version;
830
831
832 u8 crm_version[WCN36XX_HAL_VERSION_LENGTH];
833
834
835 u8 wlan_version[WCN36XX_HAL_VERSION_LENGTH];
836
837} __packed;
838
839struct wcn36xx_hal_mac_start_rsp_msg {
840 struct wcn36xx_hal_msg_header header;
841 struct wcn36xx_hal_mac_start_rsp_params start_rsp_params;
842} __packed;
843
844struct wcn36xx_hal_mac_stop_req_params {
845
846 enum wcn36xx_hal_stop_type reason;
847
848} __packed;
849
850struct wcn36xx_hal_mac_stop_req_msg {
851 struct wcn36xx_hal_msg_header header;
852 struct wcn36xx_hal_mac_stop_req_params stop_req_params;
853} __packed;
854
855struct wcn36xx_hal_mac_stop_rsp_msg {
856 struct wcn36xx_hal_msg_header header;
857
858
859 u32 status;
860} __packed;
861
862struct wcn36xx_hal_update_cfg_req_msg {
863
864
865
866
867 struct wcn36xx_hal_msg_header header;
868
869
870 u32 len;
871
872
873
874
875
876
877
878
879
880} __packed;
881
882struct wcn36xx_hal_update_cfg_rsp_msg {
883 struct wcn36xx_hal_msg_header header;
884
885
886 u32 status;
887
888} __packed;
889
890
891struct wcn36xx_hal_mac_frame_ctl {
892
893#ifndef ANI_LITTLE_BIT_ENDIAN
894
895 u8 subType:4;
896 u8 type:2;
897 u8 protVer:2;
898
899 u8 order:1;
900 u8 wep:1;
901 u8 moreData:1;
902 u8 powerMgmt:1;
903 u8 retry:1;
904 u8 moreFrag:1;
905 u8 fromDS:1;
906 u8 toDS:1;
907
908#else
909
910 u8 protVer:2;
911 u8 type:2;
912 u8 subType:4;
913
914 u8 toDS:1;
915 u8 fromDS:1;
916 u8 moreFrag:1;
917 u8 retry:1;
918 u8 powerMgmt:1;
919 u8 moreData:1;
920 u8 wep:1;
921 u8 order:1;
922
923#endif
924
925};
926
927
928struct wcn36xx_hal_mac_seq_ctl {
929 u8 fragNum:4;
930 u8 seqNumLo:4;
931 u8 seqNumHi:8;
932};
933
934
935struct wcn36xx_hal_mac_mgmt_hdr {
936 struct wcn36xx_hal_mac_frame_ctl fc;
937 u8 durationLo;
938 u8 durationHi;
939 u8 da[6];
940 u8 sa[6];
941 u8 bssId[6];
942 struct wcn36xx_hal_mac_seq_ctl seqControl;
943};
944
945
946#define WCN36XX_HAL_NUM_BSSID 2
947
948
949struct wcn36xx_hal_scan_entry {
950 u8 bss_index[WCN36XX_HAL_NUM_BSSID];
951 u8 active_bss_count;
952};
953
954struct wcn36xx_hal_init_scan_req_msg {
955 struct wcn36xx_hal_msg_header header;
956
957
958
959 enum wcn36xx_hal_sys_mode mode;
960
961
962 u8 bssid[ETH_ALEN];
963
964
965 u8 notify;
966
967
968
969 u8 frame_type;
970
971
972
973
974
975 u8 frame_len;
976
977
978
979 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
980
981
982 struct wcn36xx_hal_scan_entry scan_entry;
983};
984
985struct wcn36xx_hal_init_scan_con_req_msg {
986 struct wcn36xx_hal_msg_header header;
987
988
989
990 enum wcn36xx_hal_sys_mode mode;
991
992
993 u8 bssid[ETH_ALEN];
994
995
996 u8 notify;
997
998
999
1000 u8 frame_type;
1001
1002
1003
1004
1005
1006 u8 frame_length;
1007
1008
1009
1010 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1011
1012
1013 struct wcn36xx_hal_scan_entry scan_entry;
1014
1015
1016 u8 use_noa;
1017
1018
1019 u16 scan_duration;
1020
1021};
1022
1023struct wcn36xx_hal_init_scan_rsp_msg {
1024 struct wcn36xx_hal_msg_header header;
1025
1026
1027 u32 status;
1028
1029} __packed;
1030
1031struct wcn36xx_hal_start_scan_req_msg {
1032 struct wcn36xx_hal_msg_header header;
1033
1034
1035 u8 scan_channel;
1036} __packed;
1037
1038struct wcn36xx_hal_start_rsp_msg {
1039 struct wcn36xx_hal_msg_header header;
1040
1041
1042 u32 status;
1043
1044 u32 start_tsf[2];
1045 u8 tx_mgmt_power;
1046
1047} __packed;
1048
1049struct wcn36xx_hal_end_scan_req_msg {
1050 struct wcn36xx_hal_msg_header header;
1051
1052
1053
1054
1055 u8 scan_channel;
1056} __packed;
1057
1058struct wcn36xx_hal_end_scan_rsp_msg {
1059 struct wcn36xx_hal_msg_header header;
1060
1061
1062 u32 status;
1063} __packed;
1064
1065struct wcn36xx_hal_finish_scan_req_msg {
1066 struct wcn36xx_hal_msg_header header;
1067
1068
1069
1070 enum wcn36xx_hal_sys_mode mode;
1071
1072
1073 u8 oper_channel;
1074
1075
1076
1077
1078 enum phy_chan_bond_state cb_state;
1079
1080
1081 u8 bssid[ETH_ALEN];
1082
1083
1084 u8 notify;
1085
1086
1087
1088 u8 frame_type;
1089
1090
1091
1092
1093
1094 u8 frame_length;
1095
1096
1097
1098 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1099
1100
1101 struct wcn36xx_hal_scan_entry scan_entry;
1102
1103} __packed;
1104
1105struct wcn36xx_hal_finish_scan_rsp_msg {
1106 struct wcn36xx_hal_msg_header header;
1107
1108
1109 u32 status;
1110
1111} __packed;
1112
1113enum wcn36xx_hal_rate_index {
1114 HW_RATE_INDEX_1MBPS = 0x82,
1115 HW_RATE_INDEX_2MBPS = 0x84,
1116 HW_RATE_INDEX_5_5MBPS = 0x8B,
1117 HW_RATE_INDEX_6MBPS = 0x0C,
1118 HW_RATE_INDEX_9MBPS = 0x12,
1119 HW_RATE_INDEX_11MBPS = 0x96,
1120 HW_RATE_INDEX_12MBPS = 0x18,
1121 HW_RATE_INDEX_18MBPS = 0x24,
1122 HW_RATE_INDEX_24MBPS = 0x30,
1123 HW_RATE_INDEX_36MBPS = 0x48,
1124 HW_RATE_INDEX_48MBPS = 0x60,
1125 HW_RATE_INDEX_54MBPS = 0x6C
1126};
1127
1128struct wcn36xx_hal_supported_rates {
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148 enum sta_rate_mode op_rate_mode;
1149
1150
1151
1152 u16 dsss_rates[WCN36XX_HAL_NUM_DSSS_RATES];
1153 u16 ofdm_rates[WCN36XX_HAL_NUM_OFDM_RATES];
1154 u16 legacy_rates[WCN36XX_HAL_NUM_POLARIS_RATES];
1155 u16 reserved;
1156
1157
1158
1159
1160
1161
1162 u32 enhanced_rate_bitmap;
1163
1164
1165
1166
1167
1168 u8 supported_mcs_set[WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET];
1169
1170
1171
1172
1173
1174
1175
1176 u16 rx_highest_data_rate;
1177
1178} __packed;
1179
1180struct wcn36xx_hal_config_sta_params {
1181
1182 u8 bssid[ETH_ALEN];
1183
1184
1185 u16 aid;
1186
1187
1188 u8 type;
1189
1190
1191 u8 short_preamble_supported;
1192
1193
1194 u8 mac[ETH_ALEN];
1195
1196
1197 u16 listen_interval;
1198
1199
1200 u8 wmm_enabled;
1201
1202
1203 u8 ht_capable;
1204
1205
1206 u8 tx_channel_width_set;
1207
1208
1209 u8 rifs_mode;
1210
1211
1212
1213
1214 u8 lsig_txop_protection;
1215
1216
1217
1218 u8 max_ampdu_size;
1219
1220
1221 u8 max_ampdu_density;
1222
1223
1224 u8 max_amsdu_size;
1225
1226
1227 u8 sgi_40mhz;
1228
1229
1230 u8 sgi_20Mhz;
1231
1232
1233
1234 struct wcn36xx_hal_supported_rates supported_rates;
1235
1236
1237 u8 rmf;
1238
1239
1240 u32 encrypt_type;
1241
1242
1243
1244
1245 u8 action;
1246
1247
1248
1249
1250 u8 uapsd;
1251
1252
1253 u8 max_sp_len;
1254
1255
1256
1257 u8 green_field_capable;
1258
1259
1260 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1261
1262
1263 u8 delayed_ba_support;
1264
1265
1266 u8 max_ampdu_duration;
1267
1268
1269
1270
1271
1272 u8 dsss_cck_mode_40mhz;
1273
1274
1275
1276 u8 sta_index;
1277
1278
1279
1280
1281 u8 bssid_index;
1282
1283 u8 p2p;
1284
1285
1286
1287
1288} __packed;
1289
1290struct wcn36xx_hal_config_sta_req_msg {
1291 struct wcn36xx_hal_msg_header header;
1292 struct wcn36xx_hal_config_sta_params sta_params;
1293} __packed;
1294
1295struct wcn36xx_hal_config_sta_params_v1 {
1296
1297 u8 bssid[ETH_ALEN];
1298
1299
1300 u16 aid;
1301
1302
1303 u8 type;
1304
1305
1306 u8 short_preamble_supported;
1307
1308
1309 u8 mac[ETH_ALEN];
1310
1311
1312 u16 listen_interval;
1313
1314
1315 u8 wmm_enabled;
1316
1317
1318 u8 ht_capable;
1319
1320
1321 u8 tx_channel_width_set;
1322
1323
1324 u8 rifs_mode;
1325
1326
1327
1328
1329 u8 lsig_txop_protection;
1330
1331
1332
1333 u8 max_ampdu_size;
1334
1335
1336 u8 max_ampdu_density;
1337
1338
1339 u8 max_amsdu_size;
1340
1341
1342 u8 sgi_40mhz;
1343
1344
1345 u8 sgi_20Mhz;
1346
1347
1348 u8 rmf;
1349
1350
1351 u32 encrypt_type;
1352
1353
1354
1355
1356 u8 action;
1357
1358
1359
1360
1361 u8 uapsd;
1362
1363
1364 u8 max_sp_len;
1365
1366
1367
1368 u8 green_field_capable;
1369
1370
1371 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1372
1373
1374 u8 delayed_ba_support;
1375
1376
1377 u8 max_ampdu_duration;
1378
1379
1380
1381
1382
1383 u8 dsss_cck_mode_40mhz;
1384
1385
1386
1387 u8 sta_index;
1388
1389
1390
1391
1392 u8 bssid_index;
1393
1394 u8 p2p;
1395
1396
1397 u8 reserved;
1398
1399
1400 struct wcn36xx_hal_supported_rates supported_rates;
1401} __packed;
1402
1403struct wcn36xx_hal_config_sta_req_msg_v1 {
1404 struct wcn36xx_hal_msg_header header;
1405 struct wcn36xx_hal_config_sta_params_v1 sta_params;
1406} __packed;
1407
1408struct config_sta_rsp_params {
1409
1410 u32 status;
1411
1412
1413 u8 sta_index;
1414
1415
1416 u8 bssid_index;
1417
1418
1419 u8 dpu_index;
1420
1421
1422 u8 bcast_dpu_index;
1423
1424
1425 u8 bcast_mgmt_dpu_idx;
1426
1427
1428 u8 uc_ucast_sig;
1429
1430
1431 u8 uc_bcast_sig;
1432
1433
1434 u8 uc_mgmt_sig;
1435
1436 u8 p2p;
1437
1438} __packed;
1439
1440struct wcn36xx_hal_config_sta_rsp_msg {
1441 struct wcn36xx_hal_msg_header header;
1442
1443 struct config_sta_rsp_params params;
1444} __packed;
1445
1446
1447struct wcn36xx_hal_delete_sta_req_msg {
1448 struct wcn36xx_hal_msg_header header;
1449
1450
1451 u8 sta_index;
1452
1453} __packed;
1454
1455
1456struct wcn36xx_hal_delete_sta_rsp_msg {
1457 struct wcn36xx_hal_msg_header header;
1458
1459
1460 u32 status;
1461
1462
1463 u8 sta_id;
1464} __packed;
1465
1466
1467
1468struct wcn36xx_hal_rate_set {
1469 u8 num_rates;
1470 u8 rate[WCN36XX_HAL_MAC_RATESET_EID_MAX];
1471} __packed;
1472
1473
1474struct wcn36xx_hal_aci_aifsn {
1475#ifndef ANI_LITTLE_BIT_ENDIAN
1476 u8 rsvd:1;
1477 u8 aci:2;
1478 u8 acm:1;
1479 u8 aifsn:4;
1480#else
1481 u8 aifsn:4;
1482 u8 acm:1;
1483 u8 aci:2;
1484 u8 rsvd:1;
1485#endif
1486} __packed;
1487
1488
1489struct wcn36xx_hal_mac_cw {
1490#ifndef ANI_LITTLE_BIT_ENDIAN
1491 u8 max:4;
1492 u8 min:4;
1493#else
1494 u8 min:4;
1495 u8 max:4;
1496#endif
1497} __packed;
1498
1499struct wcn36xx_hal_edca_param_record {
1500 struct wcn36xx_hal_aci_aifsn aci;
1501 struct wcn36xx_hal_mac_cw cw;
1502 u16 txop_limit;
1503} __packed;
1504
1505struct wcn36xx_hal_mac_ssid {
1506 u8 length;
1507 u8 ssid[32];
1508} __packed;
1509
1510
1511
1512enum wcn36xx_hal_con_mode {
1513 WCN36XX_HAL_STA_MODE = 0,
1514
1515
1516
1517 WCN36XX_HAL_STA_SAP_MODE = 1,
1518
1519 WCN36XX_HAL_P2P_CLIENT_MODE,
1520 WCN36XX_HAL_P2P_GO_MODE,
1521 WCN36XX_HAL_MONITOR_MODE,
1522};
1523
1524
1525
1526
1527
1528
1529enum wcn36xx_hal_concurrency_mode {
1530 HAL_STA = 1,
1531 HAL_SAP = 2,
1532
1533
1534 HAL_STA_SAP = 3,
1535
1536 HAL_P2P_CLIENT = 4,
1537 HAL_P2P_GO = 8,
1538 HAL_MAX_CONCURRENCY_PERSONA = 4
1539};
1540
1541struct wcn36xx_hal_config_bss_params {
1542
1543 u8 bssid[ETH_ALEN];
1544
1545
1546 u8 self_mac_addr[ETH_ALEN];
1547
1548
1549 enum wcn36xx_hal_bss_type bss_type;
1550
1551
1552 u8 oper_mode;
1553
1554
1555 enum wcn36xx_hal_nw_type nw_type;
1556
1557
1558 u8 short_slot_time_supported;
1559
1560
1561 u8 lla_coexist;
1562
1563
1564 u8 llb_coexist;
1565
1566
1567 u8 llg_coexist;
1568
1569
1570 u8 ht20_coexist;
1571
1572
1573 u8 lln_non_gf_coexist;
1574
1575
1576 u8 lsig_tx_op_protection_full_support;
1577
1578
1579 u8 rifs_mode;
1580
1581
1582 u16 beacon_interval;
1583
1584
1585 u8 dtim_period;
1586
1587
1588 u8 tx_channel_width_set;
1589
1590
1591 u8 oper_channel;
1592
1593
1594 u8 ext_channel;
1595
1596
1597 u8 reserved;
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608 struct wcn36xx_hal_config_sta_params sta;
1609
1610 struct wcn36xx_hal_mac_ssid ssid;
1611
1612
1613
1614
1615
1616 u8 action;
1617
1618
1619 struct wcn36xx_hal_rate_set rateset;
1620
1621
1622 u8 ht;
1623
1624
1625 u8 obss_prot_enabled;
1626
1627
1628 u8 rmf;
1629
1630
1631 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
1632
1633
1634 u8 dual_cts_protection;
1635
1636
1637 u8 max_probe_resp_retry_limit;
1638
1639
1640 u8 hidden_ssid;
1641
1642
1643 u8 proxy_probe_resp;
1644
1645
1646
1647
1648
1649 u8 edca_params_valid;
1650
1651
1652 struct wcn36xx_hal_edca_param_record acbe;
1653
1654
1655 struct wcn36xx_hal_edca_param_record acbk;
1656
1657
1658 struct wcn36xx_hal_edca_param_record acvi;
1659
1660
1661 struct wcn36xx_hal_edca_param_record acvo;
1662
1663
1664 u8 ext_set_sta_key_param_valid;
1665
1666
1667 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
1668
1669
1670
1671 u8 wcn36xx_hal_persona;
1672
1673 u8 spectrum_mgt_enable;
1674
1675
1676 s8 tx_mgmt_power;
1677
1678
1679
1680 s8 max_tx_power;
1681} __packed;
1682
1683struct wcn36xx_hal_config_bss_req_msg {
1684 struct wcn36xx_hal_msg_header header;
1685 struct wcn36xx_hal_config_bss_params bss_params;
1686} __packed;
1687
1688struct wcn36xx_hal_config_bss_params_v1 {
1689
1690 u8 bssid[ETH_ALEN];
1691
1692
1693 u8 self_mac_addr[ETH_ALEN];
1694
1695
1696 enum wcn36xx_hal_bss_type bss_type;
1697
1698
1699 u8 oper_mode;
1700
1701
1702 enum wcn36xx_hal_nw_type nw_type;
1703
1704
1705 u8 short_slot_time_supported;
1706
1707
1708 u8 lla_coexist;
1709
1710
1711 u8 llb_coexist;
1712
1713
1714 u8 llg_coexist;
1715
1716
1717 u8 ht20_coexist;
1718
1719
1720 u8 lln_non_gf_coexist;
1721
1722
1723 u8 lsig_tx_op_protection_full_support;
1724
1725
1726 u8 rifs_mode;
1727
1728
1729 u16 beacon_interval;
1730
1731
1732 u8 dtim_period;
1733
1734
1735 u8 tx_channel_width_set;
1736
1737
1738 u8 oper_channel;
1739
1740
1741 u8 ext_channel;
1742
1743
1744 u8 reserved;
1745
1746
1747 struct wcn36xx_hal_mac_ssid ssid;
1748
1749
1750
1751
1752
1753 u8 action;
1754
1755
1756 struct wcn36xx_hal_rate_set rateset;
1757
1758
1759 u8 ht;
1760
1761
1762 u8 obss_prot_enabled;
1763
1764
1765 u8 rmf;
1766
1767
1768 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
1769
1770
1771 u8 dual_cts_protection;
1772
1773
1774 u8 max_probe_resp_retry_limit;
1775
1776
1777 u8 hidden_ssid;
1778
1779
1780 u8 proxy_probe_resp;
1781
1782
1783
1784
1785
1786 u8 edca_params_valid;
1787
1788
1789 struct wcn36xx_hal_edca_param_record acbe;
1790
1791
1792 struct wcn36xx_hal_edca_param_record acbk;
1793
1794
1795 struct wcn36xx_hal_edca_param_record acvi;
1796
1797
1798 struct wcn36xx_hal_edca_param_record acvo;
1799
1800
1801 u8 ext_set_sta_key_param_valid;
1802
1803
1804 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
1805
1806
1807
1808 u8 wcn36xx_hal_persona;
1809
1810 u8 spectrum_mgt_enable;
1811
1812
1813 s8 tx_mgmt_power;
1814
1815
1816
1817 s8 max_tx_power;
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827 struct wcn36xx_hal_config_sta_params_v1 sta;
1828} __packed;
1829
1830struct wcn36xx_hal_config_bss_req_msg_v1 {
1831 struct wcn36xx_hal_msg_header header;
1832 struct wcn36xx_hal_config_bss_params_v1 bss_params;
1833} __packed;
1834
1835struct wcn36xx_hal_config_bss_rsp_params {
1836
1837 u32 status;
1838
1839
1840 u8 bss_index;
1841
1842
1843 u8 dpu_desc_index;
1844
1845
1846 u8 ucast_dpu_signature;
1847
1848
1849 u8 bcast_dpu_desc_indx;
1850
1851
1852 u8 bcast_dpu_signature;
1853
1854
1855 u8 mgmt_dpu_desc_index;
1856
1857
1858 u8 mgmt_dpu_signature;
1859
1860
1861 u8 bss_sta_index;
1862
1863
1864 u8 bss_self_sta_index;
1865
1866
1867 u8 bss_bcast_sta_idx;
1868
1869
1870 u8 mac[ETH_ALEN];
1871
1872
1873 s8 tx_mgmt_power;
1874
1875} __packed;
1876
1877struct wcn36xx_hal_config_bss_rsp_msg {
1878 struct wcn36xx_hal_msg_header header;
1879 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
1880} __packed;
1881
1882struct wcn36xx_hal_delete_bss_req_msg {
1883 struct wcn36xx_hal_msg_header header;
1884
1885
1886 u8 bss_index;
1887
1888} __packed;
1889
1890struct wcn36xx_hal_delete_bss_rsp_msg {
1891 struct wcn36xx_hal_msg_header header;
1892
1893
1894 u32 status;
1895
1896
1897 u8 bss_index;
1898
1899} __packed;
1900
1901struct wcn36xx_hal_join_req_msg {
1902 struct wcn36xx_hal_msg_header header;
1903
1904
1905 u8 bssid[ETH_ALEN];
1906
1907
1908 u8 channel;
1909
1910
1911 u8 self_sta_mac_addr[ETH_ALEN];
1912
1913
1914 u8 local_power_constraint;
1915
1916
1917 enum phy_chan_bond_state secondary_channel_offset;
1918
1919
1920 enum wcn36xx_hal_link_state link_state;
1921
1922
1923 s8 max_tx_power;
1924} __packed;
1925
1926struct wcn36xx_hal_join_rsp_msg {
1927 struct wcn36xx_hal_msg_header header;
1928
1929
1930 u32 status;
1931
1932
1933 u8 tx_mgmt_power;
1934} __packed;
1935
1936struct post_assoc_req_msg {
1937 struct wcn36xx_hal_msg_header header;
1938
1939 struct wcn36xx_hal_config_sta_params sta_params;
1940 struct wcn36xx_hal_config_bss_params bss_params;
1941};
1942
1943struct post_assoc_rsp_msg {
1944 struct wcn36xx_hal_msg_header header;
1945 struct config_sta_rsp_params sta_rsp_params;
1946 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
1947};
1948
1949
1950struct wcn36xx_hal_set_bss_key_req_msg {
1951 struct wcn36xx_hal_msg_header header;
1952
1953
1954 u8 bss_idx;
1955
1956
1957 enum ani_ed_type enc_type;
1958
1959
1960 u8 num_keys;
1961
1962
1963 struct wcn36xx_hal_keys keys[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
1964
1965
1966
1967 u8 single_tid_rc;
1968} __packed;
1969
1970
1971struct wcn36xx_hal_set_bss_key_req_msg_tagged {
1972 struct wcn36xx_hal_set_bss_key_req_msg Msg;
1973 u32 tag;
1974} __packed;
1975
1976struct wcn36xx_hal_set_bss_key_rsp_msg {
1977 struct wcn36xx_hal_msg_header header;
1978
1979
1980 u32 status;
1981} __packed;
1982
1983
1984
1985
1986
1987
1988
1989struct wcn36xx_hal_set_sta_key_req_msg {
1990 struct wcn36xx_hal_msg_header header;
1991 struct wcn36xx_hal_set_sta_key_params set_sta_key_params;
1992} __packed;
1993
1994struct wcn36xx_hal_set_sta_key_rsp_msg {
1995 struct wcn36xx_hal_msg_header header;
1996
1997
1998 u32 status;
1999} __packed;
2000
2001struct wcn36xx_hal_remove_bss_key_req_msg {
2002 struct wcn36xx_hal_msg_header header;
2003
2004
2005 u8 bss_idx;
2006
2007
2008 enum ani_ed_type enc_type;
2009
2010
2011 u8 key_id;
2012
2013
2014
2015 enum ani_wep_type wep_type;
2016} __packed;
2017
2018struct wcn36xx_hal_remove_bss_key_rsp_msg {
2019 struct wcn36xx_hal_msg_header header;
2020
2021
2022 u32 status;
2023} __packed;
2024
2025
2026
2027
2028struct wcn36xx_hal_remove_sta_key_req_msg {
2029 struct wcn36xx_hal_msg_header header;
2030
2031
2032 u16 sta_idx;
2033
2034
2035 enum ani_ed_type enc_type;
2036
2037
2038 u8 key_id;
2039
2040
2041
2042 u8 unicast;
2043
2044} __packed;
2045
2046struct wcn36xx_hal_remove_sta_key_rsp_msg {
2047 struct wcn36xx_hal_msg_header header;
2048
2049
2050 u32 status;
2051
2052} __packed;
2053
2054#ifdef FEATURE_OEM_DATA_SUPPORT
2055
2056#ifndef OEM_DATA_REQ_SIZE
2057#define OEM_DATA_REQ_SIZE 134
2058#endif
2059
2060#ifndef OEM_DATA_RSP_SIZE
2061#define OEM_DATA_RSP_SIZE 1968
2062#endif
2063
2064struct start_oem_data_req_msg {
2065 struct wcn36xx_hal_msg_header header;
2066
2067 u32 status;
2068 tSirMacAddr self_mac_addr;
2069 u8 oem_data_req[OEM_DATA_REQ_SIZE];
2070
2071};
2072
2073struct start_oem_data_rsp_msg {
2074 struct wcn36xx_hal_msg_header header;
2075
2076 u8 oem_data_rsp[OEM_DATA_RSP_SIZE];
2077};
2078
2079#endif
2080
2081struct wcn36xx_hal_switch_channel_req_msg {
2082 struct wcn36xx_hal_msg_header header;
2083
2084
2085 u8 channel_number;
2086
2087
2088 u8 local_power_constraint;
2089
2090
2091 enum phy_chan_bond_state secondary_channel_offset;
2092
2093
2094 u8 tx_mgmt_power;
2095
2096
2097 u8 max_tx_power;
2098
2099
2100 u8 self_sta_mac_addr[ETH_ALEN];
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111 u8 bssid[ETH_ALEN];
2112} __packed;
2113
2114struct wcn36xx_hal_switch_channel_rsp_msg {
2115 struct wcn36xx_hal_msg_header header;
2116
2117
2118 u32 status;
2119
2120
2121 u8 channel_number;
2122
2123
2124 u8 tx_mgmt_power;
2125
2126
2127 u8 bssid[ETH_ALEN];
2128
2129} __packed;
2130
2131struct update_edca_params_req_msg {
2132 struct wcn36xx_hal_msg_header header;
2133
2134
2135 u16 bss_index;
2136
2137
2138 struct wcn36xx_hal_edca_param_record acbe;
2139
2140
2141 struct wcn36xx_hal_edca_param_record acbk;
2142
2143
2144 struct wcn36xx_hal_edca_param_record acvi;
2145
2146
2147 struct wcn36xx_hal_edca_param_record acvo;
2148};
2149
2150struct update_edca_params_rsp_msg {
2151 struct wcn36xx_hal_msg_header header;
2152
2153
2154 u32 status;
2155};
2156
2157struct dpu_stats_params {
2158
2159 u16 sta_index;
2160
2161
2162 u8 enc_mode;
2163
2164
2165 u32 status;
2166
2167
2168 u32 send_blocks;
2169 u32 recv_blocks;
2170 u32 replays;
2171 u8 mic_error_cnt;
2172 u32 prot_excl_cnt;
2173 u16 format_err_cnt;
2174 u16 un_decryptable_cnt;
2175 u32 decrypt_err_cnt;
2176 u32 decrypt_ok_cnt;
2177};
2178
2179struct wcn36xx_hal_stats_req_msg {
2180 struct wcn36xx_hal_msg_header header;
2181
2182
2183 u32 sta_id;
2184
2185
2186 u32 stats_mask;
2187};
2188
2189struct ani_summary_stats_info {
2190
2191
2192 u32 retry_cnt[4];
2193
2194
2195
2196
2197 u32 multiple_retry_cnt[4];
2198
2199
2200
2201
2202 u32 tx_frm_cnt[4];
2203
2204
2205
2206 u32 rx_frm_cnt;
2207
2208
2209 u32 frm_dup_cnt;
2210
2211
2212 u32 fail_cnt[4];
2213
2214
2215
2216 u32 rts_fail_cnt;
2217
2218
2219
2220 u32 ack_fail_cnt;
2221
2222
2223
2224 u32 rts_succ_cnt;
2225
2226
2227
2228
2229 u32 rx_discard_cnt;
2230
2231
2232
2233
2234 u32 rx_error_cnt;
2235
2236
2237
2238
2239 u32 tx_byte_cnt;
2240};
2241
2242
2243enum tx_rate_info {
2244
2245 HAL_TX_RATE_LEGACY = 0x1,
2246
2247
2248 HAL_TX_RATE_HT20 = 0x2,
2249
2250
2251 HAL_TX_RATE_HT40 = 0x4,
2252
2253
2254 HAL_TX_RATE_SGI = 0x8,
2255
2256
2257 HAL_TX_RATE_LGI = 0x10
2258};
2259
2260struct ani_global_class_a_stats_info {
2261
2262
2263 u32 rx_frag_cnt;
2264
2265
2266
2267
2268 u32 promiscuous_rx_frag_cnt;
2269
2270
2271
2272
2273
2274 u32 rx_input_sensitivity;
2275
2276
2277
2278 u32 max_pwr;
2279
2280
2281
2282
2283 u32 sync_fail_cnt;
2284
2285
2286
2287 u32 tx_rate;
2288
2289
2290 u32 mcs_index;
2291
2292
2293
2294 u32 tx_rate_flags;
2295};
2296
2297struct ani_global_security_stats {
2298
2299
2300
2301 u32 rx_wep_unencrypted_frm_cnt;
2302
2303
2304
2305 u32 rx_mic_fail_cnt;
2306
2307
2308
2309 u32 tkip_icv_err;
2310
2311
2312
2313 u32 aes_ccmp_format_err;
2314
2315
2316
2317 u32 aes_ccmp_replay_cnt;
2318
2319
2320
2321
2322 u32 aes_ccmp_decrpt_err;
2323
2324
2325
2326 u32 wep_undecryptable_cnt;
2327
2328
2329
2330 u32 wep_icv_err;
2331
2332
2333
2334 u32 rx_decrypt_succ_cnt;
2335
2336
2337
2338 u32 rx_decrypt_fail_cnt;
2339};
2340
2341struct ani_global_class_b_stats_info {
2342 struct ani_global_security_stats uc_stats;
2343 struct ani_global_security_stats mc_bc_stats;
2344};
2345
2346struct ani_global_class_c_stats_info {
2347
2348
2349
2350 u32 rx_amsdu_cnt;
2351
2352
2353
2354 u32 rx_ampdu_cnt;
2355
2356
2357
2358 u32 tx_20_frm_cnt;
2359
2360
2361
2362 u32 rx_20_frm_cnt;
2363
2364
2365
2366 u32 rx_mpdu_in_ampdu_cnt;
2367
2368
2369
2370
2371 u32 ampdu_delimiter_crc_err;
2372};
2373
2374struct ani_per_sta_stats_info {
2375
2376
2377 u32 tx_frag_cnt[4];
2378
2379
2380 u32 tx_ampdu_cnt;
2381
2382
2383
2384 u32 tx_mpdu_in_ampdu_cnt;
2385};
2386
2387struct wcn36xx_hal_stats_rsp_msg {
2388 struct wcn36xx_hal_msg_header header;
2389
2390
2391 u32 status;
2392
2393
2394 u32 sta_index;
2395
2396
2397 u32 stats_mask;
2398
2399
2400 u16 msg_type;
2401
2402
2403 u16 msg_len;
2404};
2405
2406struct wcn36xx_hal_set_link_state_req_msg {
2407 struct wcn36xx_hal_msg_header header;
2408
2409 u8 bssid[ETH_ALEN];
2410 enum wcn36xx_hal_link_state state;
2411 u8 self_mac_addr[ETH_ALEN];
2412
2413} __packed;
2414
2415struct set_link_state_rsp_msg {
2416 struct wcn36xx_hal_msg_header header;
2417
2418
2419 u32 status;
2420};
2421
2422
2423struct wcn36xx_hal_ts_info_tfc {
2424#ifndef ANI_LITTLE_BIT_ENDIAN
2425 u16 ackPolicy:2;
2426 u16 userPrio:3;
2427 u16 psb:1;
2428 u16 aggregation:1;
2429 u16 accessPolicy:2;
2430 u16 direction:2;
2431 u16 tsid:4;
2432 u16 trafficType:1;
2433#else
2434 u16 trafficType:1;
2435 u16 tsid:4;
2436 u16 direction:2;
2437 u16 accessPolicy:2;
2438 u16 aggregation:1;
2439 u16 psb:1;
2440 u16 userPrio:3;
2441 u16 ackPolicy:2;
2442#endif
2443};
2444
2445
2446struct wcn36xx_hal_ts_info_sch {
2447#ifndef ANI_LITTLE_BIT_ENDIAN
2448 u8 rsvd:7;
2449 u8 schedule:1;
2450#else
2451 u8 schedule:1;
2452 u8 rsvd:7;
2453#endif
2454};
2455
2456
2457struct wcn36xx_hal_ts_info {
2458 struct wcn36xx_hal_ts_info_tfc traffic;
2459 struct wcn36xx_hal_ts_info_sch schedule;
2460};
2461
2462
2463struct wcn36xx_hal_tspec_ie {
2464 u8 type;
2465 u8 length;
2466 struct wcn36xx_hal_ts_info ts_info;
2467 u16 nom_msdu_size;
2468 u16 max_msdu_size;
2469 u32 min_svc_interval;
2470 u32 max_svc_interval;
2471 u32 inact_interval;
2472 u32 suspend_interval;
2473 u32 svc_start_time;
2474 u32 min_data_rate;
2475 u32 mean_data_rate;
2476 u32 peak_data_rate;
2477 u32 max_burst_sz;
2478 u32 delay_bound;
2479 u32 min_phy_rate;
2480 u16 surplus_bw;
2481 u16 medium_time;
2482};
2483
2484struct add_ts_req_msg {
2485 struct wcn36xx_hal_msg_header header;
2486
2487
2488 u16 sta_index;
2489
2490
2491 u16 tspec_index;
2492
2493
2494 struct wcn36xx_hal_tspec_ie tspec;
2495
2496
2497
2498
2499 u8 uapsd;
2500
2501
2502
2503
2504 u32 service_interval[WCN36XX_HAL_MAX_AC];
2505
2506
2507 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
2508
2509
2510 u32 delay_interval[WCN36XX_HAL_MAX_AC];
2511};
2512
2513struct add_rs_rsp_msg {
2514 struct wcn36xx_hal_msg_header header;
2515
2516
2517 u32 status;
2518};
2519
2520struct del_ts_req_msg {
2521 struct wcn36xx_hal_msg_header header;
2522
2523
2524 u16 sta_index;
2525
2526
2527 u16 tspec_index;
2528
2529
2530 u8 bssid[ETH_ALEN];
2531};
2532
2533struct del_ts_rsp_msg {
2534 struct wcn36xx_hal_msg_header header;
2535
2536
2537 u32 status;
2538};
2539
2540
2541
2542
2543
2544struct wcn36xx_hal_add_ba_session_req_msg {
2545 struct wcn36xx_hal_msg_header header;
2546
2547
2548 u16 sta_index;
2549
2550
2551 u8 mac_addr[ETH_ALEN];
2552
2553
2554
2555 u8 dialog_token;
2556
2557
2558
2559 u8 tid;
2560
2561
2562
2563 u8 policy;
2564
2565
2566
2567
2568
2569
2570
2571 u16 buffer_size;
2572
2573
2574 u16 timeout;
2575
2576
2577
2578
2579 u16 ssn;
2580
2581
2582
2583
2584 u8 direction;
2585} __packed;
2586
2587struct wcn36xx_hal_add_ba_session_rsp_msg {
2588 struct wcn36xx_hal_msg_header header;
2589
2590
2591 u32 status;
2592
2593
2594 u8 dialog_token;
2595
2596
2597 u8 ba_tid;
2598
2599
2600 u8 ba_buffer_size;
2601
2602 u8 ba_session_id;
2603
2604
2605 u8 win_size;
2606
2607
2608 u8 sta_index;
2609
2610
2611 u16 ssn;
2612} __packed;
2613
2614struct wcn36xx_hal_add_ba_req_msg {
2615 struct wcn36xx_hal_msg_header header;
2616
2617
2618 u8 session_id;
2619
2620
2621 u8 win_size;
2622
2623#ifdef FEATURE_ON_CHIP_REORDERING
2624 u8 reordering_done_on_chip;
2625#endif
2626} __packed;
2627
2628struct wcn36xx_hal_add_ba_rsp_msg {
2629 struct wcn36xx_hal_msg_header header;
2630
2631
2632 u32 status;
2633
2634
2635 u8 dialog_token;
2636} __packed;
2637
2638struct add_ba_info {
2639 u16 ba_enable:1;
2640 u16 starting_seq_num:12;
2641 u16 reserved:3;
2642};
2643
2644struct wcn36xx_hal_trigger_ba_rsp_candidate {
2645 u8 sta_addr[ETH_ALEN];
2646 struct add_ba_info ba_info[STACFG_MAX_TC];
2647} __packed;
2648
2649struct wcn36xx_hal_trigger_ba_req_candidate {
2650 u8 sta_index;
2651 u8 tid_bitmap;
2652} __packed;
2653
2654struct wcn36xx_hal_trigger_ba_req_msg {
2655 struct wcn36xx_hal_msg_header header;
2656
2657
2658 u8 session_id;
2659
2660
2661
2662
2663 u16 candidate_cnt;
2664
2665} __packed;
2666
2667struct wcn36xx_hal_trigger_ba_rsp_msg {
2668 struct wcn36xx_hal_msg_header header;
2669
2670
2671 u8 bssid[ETH_ALEN];
2672
2673
2674 u32 status;
2675
2676
2677
2678
2679 u16 candidate_cnt;
2680} __packed;
2681
2682struct wcn36xx_hal_del_ba_req_msg {
2683 struct wcn36xx_hal_msg_header header;
2684
2685
2686 u16 sta_index;
2687
2688
2689 u8 tid;
2690
2691
2692
2693
2694 u8 direction;
2695} __packed;
2696
2697struct wcn36xx_hal_del_ba_rsp_msg {
2698 struct wcn36xx_hal_msg_header header;
2699
2700
2701 u32 status;
2702} __packed;
2703
2704struct tsm_stats_req_msg {
2705 struct wcn36xx_hal_msg_header header;
2706
2707
2708 u8 tid;
2709
2710 u8 bssid[ETH_ALEN];
2711};
2712
2713struct tsm_stats_rsp_msg {
2714 struct wcn36xx_hal_msg_header header;
2715
2716
2717 u32 status;
2718
2719
2720 u16 uplink_pkt_queue_delay;
2721
2722
2723 u16 uplink_pkt_queue_delay_hist[4];
2724
2725
2726 u32 uplink_pkt_tx_delay;
2727
2728
2729 u16 uplink_pkt_loss;
2730
2731
2732 u16 uplink_pkt_count;
2733
2734
2735 u8 roaming_count;
2736
2737
2738 u16 roaming_delay;
2739};
2740
2741struct set_key_done_msg {
2742 struct wcn36xx_hal_msg_header header;
2743
2744
2745 u8 bssidx;
2746 u8 enc_type;
2747};
2748
2749struct wcn36xx_hal_nv_img_download_req_msg {
2750
2751
2752
2753
2754 struct wcn36xx_hal_msg_header header;
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764 u16 frag_number;
2765
2766
2767
2768
2769
2770
2771 u16 last_fragment;
2772
2773
2774 u32 nv_img_buffer_size;
2775
2776
2777
2778
2779} __packed;
2780
2781struct wcn36xx_hal_nv_img_download_rsp_msg {
2782 struct wcn36xx_hal_msg_header header;
2783
2784
2785
2786 u32 status;
2787} __packed;
2788
2789struct wcn36xx_hal_nv_store_ind {
2790
2791
2792 struct wcn36xx_hal_msg_header header;
2793
2794
2795 u32 table_id;
2796
2797
2798 u32 nv_blob_size;
2799
2800
2801
2802};
2803
2804
2805
2806#define WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE 6
2807
2808
2809
2810
2811struct mic_failure_ind_msg {
2812 struct wcn36xx_hal_msg_header header;
2813
2814 u8 bssid[ETH_ALEN];
2815
2816
2817 u8 src_addr[ETH_ALEN];
2818
2819
2820 u8 ta_addr[ETH_ALEN];
2821
2822 u8 dst_addr[ETH_ALEN];
2823
2824 u8 multicast;
2825
2826
2827 u8 iv1;
2828
2829
2830 u8 key_id;
2831
2832
2833 u8 tsc[WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE];
2834
2835
2836 u8 rx_addr[ETH_ALEN];
2837};
2838
2839struct update_vht_op_mode_req_msg {
2840 struct wcn36xx_hal_msg_header header;
2841
2842 u16 op_mode;
2843 u16 sta_id;
2844};
2845
2846struct update_vht_op_mode_params_rsp_msg {
2847 struct wcn36xx_hal_msg_header header;
2848
2849 u32 status;
2850};
2851
2852struct update_beacon_req_msg {
2853 struct wcn36xx_hal_msg_header header;
2854
2855 u8 bss_index;
2856
2857
2858
2859 u8 short_preamble;
2860
2861
2862 u8 short_slot_time;
2863
2864
2865 u16 beacon_interval;
2866
2867
2868 u8 lla_coexist;
2869 u8 llb_coexist;
2870 u8 llg_coexist;
2871 u8 ht20_coexist;
2872 u8 lln_non_gf_coexist;
2873 u8 lsig_tx_op_protection_full_support;
2874 u8 rifs_mode;
2875
2876 u16 param_change_bitmap;
2877};
2878
2879struct update_beacon_rsp_msg {
2880 struct wcn36xx_hal_msg_header header;
2881 u32 status;
2882};
2883
2884struct wcn36xx_hal_send_beacon_req_msg {
2885 struct wcn36xx_hal_msg_header header;
2886
2887
2888 u32 beacon_length;
2889
2890
2891 u8 beacon[BEACON_TEMPLATE_SIZE];
2892
2893 u8 bssid[ETH_ALEN];
2894
2895
2896 u32 tim_ie_offset;
2897
2898
2899 u16 p2p_ie_offset;
2900} __packed;
2901
2902struct send_beacon_rsp_msg {
2903 struct wcn36xx_hal_msg_header header;
2904 u32 status;
2905} __packed;
2906
2907struct enable_radar_req_msg {
2908 struct wcn36xx_hal_msg_header header;
2909
2910 u8 bssid[ETH_ALEN];
2911 u8 channel;
2912};
2913
2914struct enable_radar_rsp_msg {
2915 struct wcn36xx_hal_msg_header header;
2916
2917
2918 u8 bssid[ETH_ALEN];
2919
2920
2921 u32 status;
2922};
2923
2924struct radar_detect_intr_ind_msg {
2925 struct wcn36xx_hal_msg_header header;
2926
2927 u8 radar_det_channel;
2928};
2929
2930struct radar_detect_ind_msg {
2931 struct wcn36xx_hal_msg_header header;
2932
2933
2934 u8 channel_number;
2935
2936
2937 u16 radar_pulse_width;
2938
2939
2940 u16 num_radar_pulse;
2941};
2942
2943struct wcn36xx_hal_get_tpc_report_req_msg {
2944 struct wcn36xx_hal_msg_header header;
2945
2946 u8 sta[ETH_ALEN];
2947 u8 dialog_token;
2948 u8 txpower;
2949};
2950
2951struct wcn36xx_hal_get_tpc_report_rsp_msg {
2952 struct wcn36xx_hal_msg_header header;
2953
2954
2955 u32 status;
2956};
2957
2958struct wcn36xx_hal_send_probe_resp_req_msg {
2959 struct wcn36xx_hal_msg_header header;
2960
2961 u8 probe_resp_template[BEACON_TEMPLATE_SIZE];
2962 u32 probe_resp_template_len;
2963 u32 proxy_probe_req_valid_ie_bmap[8];
2964 u8 bssid[ETH_ALEN];
2965};
2966
2967struct send_probe_resp_rsp_msg {
2968 struct wcn36xx_hal_msg_header header;
2969
2970
2971 u32 status;
2972};
2973
2974struct send_unknown_frame_rx_ind_msg {
2975 struct wcn36xx_hal_msg_header header;
2976
2977
2978 u32 status;
2979};
2980
2981struct wcn36xx_hal_delete_sta_context_ind_msg {
2982 struct wcn36xx_hal_msg_header header;
2983
2984 u16 aid;
2985 u16 sta_id;
2986
2987
2988 u8 bssid[ETH_ALEN];
2989
2990
2991 u8 addr2[ETH_ALEN];
2992
2993
2994 u16 reason_code;
2995} __packed;
2996
2997struct indicate_del_sta {
2998 struct wcn36xx_hal_msg_header header;
2999 u8 aid;
3000 u8 sta_index;
3001 u8 bss_index;
3002 u8 reason_code;
3003 u32 status;
3004};
3005
3006struct bt_amp_event_msg {
3007 struct wcn36xx_hal_msg_header header;
3008
3009 enum bt_amp_event_type btAmpEventType;
3010};
3011
3012struct bt_amp_event_rsp {
3013 struct wcn36xx_hal_msg_header header;
3014
3015
3016 u32 status;
3017};
3018
3019struct tl_hal_flush_ac_req_msg {
3020 struct wcn36xx_hal_msg_header header;
3021
3022
3023 u8 sta_id;
3024
3025
3026 u8 tid;
3027};
3028
3029struct tl_hal_flush_ac_rsp_msg {
3030 struct wcn36xx_hal_msg_header header;
3031
3032
3033 u8 sta_id;
3034
3035
3036 u8 tid;
3037
3038
3039 u32 status;
3040};
3041
3042struct wcn36xx_hal_enter_imps_req_msg {
3043 struct wcn36xx_hal_msg_header header;
3044};
3045
3046struct wcn36xx_hal_exit_imps_req {
3047 struct wcn36xx_hal_msg_header header;
3048};
3049
3050struct wcn36xx_hal_enter_bmps_req_msg {
3051 struct wcn36xx_hal_msg_header header;
3052
3053 u8 bss_index;
3054
3055
3056#ifndef BUILD_QWPTTSTATIC
3057 u64 tbtt;
3058#endif
3059 u8 dtim_count;
3060
3061
3062
3063 u8 dtim_period;
3064
3065
3066 u32 rssi_filter_period;
3067
3068 u32 num_beacon_per_rssi_average;
3069 u8 rssi_filter_enable;
3070} __packed;
3071
3072struct wcn36xx_hal_exit_bmps_req_msg {
3073 struct wcn36xx_hal_msg_header header;
3074
3075 u8 send_data_null;
3076 u8 bss_index;
3077} __packed;
3078
3079struct wcn36xx_hal_missed_beacon_ind_msg {
3080 struct wcn36xx_hal_msg_header header;
3081
3082 u8 bss_index;
3083} __packed;
3084
3085
3086
3087
3088
3089
3090struct beacon_filter_ie {
3091 u8 element_id;
3092 u8 check_ie_presence;
3093 u8 offset;
3094 u8 value;
3095 u8 bitmask;
3096 u8 ref;
3097};
3098
3099struct wcn36xx_hal_add_bcn_filter_req_msg {
3100 struct wcn36xx_hal_msg_header header;
3101
3102 u16 capability_info;
3103 u16 capability_mask;
3104 u16 beacon_interval;
3105 u16 ie_num;
3106 u8 bss_index;
3107 u8 reserved;
3108};
3109
3110struct wcn36xx_hal_rem_bcn_filter_req {
3111 struct wcn36xx_hal_msg_header header;
3112
3113 u8 ie_Count;
3114 u8 rem_ie_id[1];
3115};
3116
3117#define WCN36XX_HAL_IPV4_ARP_REPLY_OFFLOAD 0
3118#define WCN36XX_HAL_IPV6_NEIGHBOR_DISCOVERY_OFFLOAD 1
3119#define WCN36XX_HAL_IPV6_NS_OFFLOAD 2
3120#define WCN36XX_HAL_IPV6_ADDR_LEN 16
3121#define WCN36XX_HAL_OFFLOAD_DISABLE 0
3122#define WCN36XX_HAL_OFFLOAD_ENABLE 1
3123#define WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE 0x2
3124#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE \
3125 (HAL_OFFLOAD_ENABLE|HAL_OFFLOAD_BCAST_FILTER_ENABLE)
3126
3127struct wcn36xx_hal_ns_offload_params {
3128 u8 src_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3129 u8 self_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3130
3131
3132 u8 target_ipv6_addr1[WCN36XX_HAL_IPV6_ADDR_LEN];
3133 u8 target_ipv6_addr2[WCN36XX_HAL_IPV6_ADDR_LEN];
3134
3135 u8 self_addr[ETH_ALEN];
3136 u8 src_ipv6_addr_valid:1;
3137 u8 target_ipv6_addr1_valid:1;
3138 u8 target_ipv6_addr2_valid:1;
3139 u8 reserved1:5;
3140
3141
3142 u8 reserved2;
3143
3144
3145 u32 slot_index;
3146 u8 bss_index;
3147};
3148
3149struct wcn36xx_hal_host_offload_req {
3150 u8 offload_Type;
3151
3152
3153 u8 enable;
3154
3155 union {
3156 u8 host_ipv4_addr[4];
3157 u8 host_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3158 } u;
3159};
3160
3161struct wcn36xx_hal_host_offload_req_msg {
3162 struct wcn36xx_hal_msg_header header;
3163 struct wcn36xx_hal_host_offload_req host_offload_params;
3164 struct wcn36xx_hal_ns_offload_params ns_offload_params;
3165};
3166
3167
3168#define WCN36XX_HAL_KEEP_ALIVE_NULL_PKT 1
3169#define WCN36XX_HAL_KEEP_ALIVE_UNSOLICIT_ARP_RSP 2
3170
3171
3172#define WCN36XX_HAL_KEEP_ALIVE_DISABLE 0
3173#define WCN36XX_HAL_KEEP_ALIVE_ENABLE 1
3174#define WCN36XX_KEEP_ALIVE_TIME_PERIOD 30
3175
3176
3177struct wcn36xx_hal_keep_alive_req_msg {
3178 struct wcn36xx_hal_msg_header header;
3179
3180 u8 packet_type;
3181 u32 time_period;
3182 u8 host_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3183 u8 dest_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3184 u8 dest_addr[ETH_ALEN];
3185 u8 bss_index;
3186} __packed;
3187
3188struct wcn36xx_hal_rssi_threshold_req_msg {
3189 struct wcn36xx_hal_msg_header header;
3190
3191 s8 threshold1:8;
3192 s8 threshold2:8;
3193 s8 threshold3:8;
3194 u8 thres1_pos_notify:1;
3195 u8 thres1_neg_notify:1;
3196 u8 thres2_pos_notify:1;
3197 u8 thres2_neg_notify:1;
3198 u8 thres3_pos_notify:1;
3199 u8 thres3_neg_notify:1;
3200 u8 reserved10:2;
3201};
3202
3203struct wcn36xx_hal_enter_uapsd_req_msg {
3204 struct wcn36xx_hal_msg_header header;
3205
3206 u8 bk_delivery:1;
3207 u8 be_delivery:1;
3208 u8 vi_delivery:1;
3209 u8 vo_delivery:1;
3210 u8 bk_trigger:1;
3211 u8 be_trigger:1;
3212 u8 vi_trigger:1;
3213 u8 vo_trigger:1;
3214 u8 bss_index;
3215};
3216
3217struct wcn36xx_hal_exit_uapsd_req_msg {
3218 struct wcn36xx_hal_msg_header header;
3219 u8 bss_index;
3220};
3221
3222#define WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE 128
3223#define WCN36XX_HAL_WOWL_BCAST_MAX_NUM_PATTERNS 16
3224
3225struct wcn36xx_hal_wowl_add_bcast_ptrn_req_msg {
3226 struct wcn36xx_hal_msg_header header;
3227
3228
3229 u8 id;
3230
3231
3232
3233 u8 byte_Offset;
3234
3235
3236 u8 size;
3237
3238
3239 u8 pattern[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3240
3241
3242 u8 mask_size;
3243
3244
3245 u8 mask[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3246
3247
3248 u8 extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3249
3250
3251 u8 mask_extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3252
3253 u8 bss_index;
3254};
3255
3256struct wcn36xx_hal_wow_del_bcast_ptrn_req_msg {
3257 struct wcn36xx_hal_msg_header header;
3258
3259
3260 u8 id;
3261 u8 bss_index;
3262};
3263
3264struct wcn36xx_hal_wowl_enter_req_msg {
3265 struct wcn36xx_hal_msg_header header;
3266
3267
3268 u8 magic_packet_enable;
3269
3270
3271 u8 magic_pattern[ETH_ALEN];
3272
3273
3274
3275
3276
3277
3278 u8 pattern_filtering_enable;
3279
3280
3281
3282
3283
3284
3285
3286 u8 ucast_pattern_filtering_enable;
3287
3288
3289
3290
3291
3292 u8 wow_channel_switch_receive;
3293
3294
3295
3296
3297
3298 u8 wow_deauth_receive;
3299
3300
3301
3302
3303
3304 u8 wow_disassoc_receive;
3305
3306
3307
3308
3309
3310
3311 u8 wow_max_missed_beacons;
3312
3313
3314
3315
3316
3317
3318 u8 wow_max_sleep;
3319
3320
3321
3322
3323
3324 u8 wow_eap_id_request_enable;
3325
3326
3327
3328
3329 u8 wow_eapol_4way_enable;
3330
3331
3332
3333
3334 u8 wow_net_scan_offload_match;
3335
3336
3337
3338
3339 u8 wow_gtk_rekey_error;
3340
3341
3342
3343 u8 wow_bss_connection_loss;
3344
3345 u8 bss_index;
3346};
3347
3348struct wcn36xx_hal_wowl_exit_req_msg {
3349 struct wcn36xx_hal_msg_header header;
3350
3351 u8 bss_index;
3352};
3353
3354struct wcn36xx_hal_get_rssi_req_msg {
3355 struct wcn36xx_hal_msg_header header;
3356};
3357
3358struct wcn36xx_hal_get_roam_rssi_req_msg {
3359 struct wcn36xx_hal_msg_header header;
3360
3361
3362 u32 sta_id;
3363};
3364
3365struct wcn36xx_hal_set_uapsd_ac_params_req_msg {
3366 struct wcn36xx_hal_msg_header header;
3367
3368
3369 u8 sta_idx;
3370
3371
3372 u8 ac;
3373
3374
3375 u8 up;
3376
3377
3378 u32 service_interval;
3379
3380
3381 u32 suspend_interval;
3382
3383
3384 u32 delay_interval;
3385};
3386
3387struct wcn36xx_hal_configure_rxp_filter_req_msg {
3388 struct wcn36xx_hal_msg_header header;
3389
3390 u8 set_mcst_bcst_filter_setting;
3391 u8 set_mcst_bcst_filter;
3392};
3393
3394struct wcn36xx_hal_enter_imps_rsp_msg {
3395 struct wcn36xx_hal_msg_header header;
3396
3397
3398 u32 status;
3399};
3400
3401struct wcn36xx_hal_exit_imps_rsp_msg {
3402 struct wcn36xx_hal_msg_header header;
3403
3404
3405 u32 status;
3406};
3407
3408struct wcn36xx_hal_enter_bmps_rsp_msg {
3409 struct wcn36xx_hal_msg_header header;
3410
3411
3412 u32 status;
3413
3414 u8 bss_index;
3415} __packed;
3416
3417struct wcn36xx_hal_exit_bmps_rsp_msg {
3418 struct wcn36xx_hal_msg_header header;
3419
3420
3421 u32 status;
3422
3423 u8 bss_index;
3424} __packed;
3425
3426struct wcn36xx_hal_enter_uapsd_rsp_msg {
3427 struct wcn36xx_hal_msg_header header;
3428
3429
3430 u32 status;
3431
3432 u8 bss_index;
3433};
3434
3435struct wcn36xx_hal_exit_uapsd_rsp_msg {
3436 struct wcn36xx_hal_msg_header header;
3437
3438
3439 u32 status;
3440
3441 u8 bss_index;
3442};
3443
3444struct wcn36xx_hal_rssi_notification_ind_msg {
3445 struct wcn36xx_hal_msg_header header;
3446
3447 u32 rssi_thres1_pos_cross:1;
3448 u32 rssi_thres1_neg_cross:1;
3449 u32 rssi_thres2_pos_cross:1;
3450 u32 rssi_thres2_neg_cross:1;
3451 u32 rssi_thres3_pos_cross:1;
3452 u32 rssi_thres3_neg_cross:1;
3453 u32 avg_rssi:8;
3454 u32 reserved:18;
3455
3456};
3457
3458struct wcn36xx_hal_get_rssio_rsp_msg {
3459 struct wcn36xx_hal_msg_header header;
3460
3461
3462 u32 status;
3463 s8 rssi;
3464
3465};
3466
3467struct wcn36xx_hal_get_roam_rssi_rsp_msg {
3468 struct wcn36xx_hal_msg_header header;
3469
3470
3471 u32 status;
3472
3473 u8 sta_id;
3474 s8 rssi;
3475};
3476
3477struct wcn36xx_hal_wowl_enter_rsp_msg {
3478 struct wcn36xx_hal_msg_header header;
3479
3480
3481 u32 status;
3482 u8 bss_index;
3483};
3484
3485struct wcn36xx_hal_wowl_exit_rsp_msg {
3486 struct wcn36xx_hal_msg_header header;
3487
3488
3489 u32 status;
3490 u8 bss_index;
3491};
3492
3493struct wcn36xx_hal_add_bcn_filter_rsp_msg {
3494 struct wcn36xx_hal_msg_header header;
3495
3496
3497 u32 status;
3498};
3499
3500struct wcn36xx_hal_rem_bcn_filter_rsp_msg {
3501 struct wcn36xx_hal_msg_header header;
3502
3503
3504 u32 status;
3505};
3506
3507struct wcn36xx_hal_add_wowl_bcast_ptrn_rsp_msg {
3508 struct wcn36xx_hal_msg_header header;
3509
3510
3511 u32 status;
3512 u8 bss_index;
3513};
3514
3515struct wcn36xx_hal_del_wowl_bcast_ptrn_rsp_msg {
3516 struct wcn36xx_hal_msg_header header;
3517
3518
3519 u32 status;
3520 u8 bss_index;
3521};
3522
3523struct wcn36xx_hal_host_offload_rsp_msg {
3524 struct wcn36xx_hal_msg_header header;
3525
3526
3527 u32 status;
3528};
3529
3530struct wcn36xx_hal_keep_alive_rsp_msg {
3531 struct wcn36xx_hal_msg_header header;
3532
3533
3534 u32 status;
3535};
3536
3537struct wcn36xx_hal_set_rssi_thresh_rsp_msg {
3538 struct wcn36xx_hal_msg_header header;
3539
3540
3541 u32 status;
3542};
3543
3544struct wcn36xx_hal_set_uapsd_ac_params_rsp_msg {
3545 struct wcn36xx_hal_msg_header header;
3546
3547
3548 u32 status;
3549};
3550
3551struct wcn36xx_hal_configure_rxp_filter_rsp_msg {
3552 struct wcn36xx_hal_msg_header header;
3553
3554
3555 u32 status;
3556};
3557
3558struct set_max_tx_pwr_req {
3559 struct wcn36xx_hal_msg_header header;
3560
3561
3562
3563
3564 u8 bssid[ETH_ALEN];
3565
3566 u8 self_addr[ETH_ALEN];
3567
3568
3569 u8 power;
3570};
3571
3572struct set_max_tx_pwr_rsp_msg {
3573 struct wcn36xx_hal_msg_header header;
3574
3575
3576 u8 power;
3577
3578
3579 u32 status;
3580};
3581
3582struct set_tx_pwr_req_msg {
3583 struct wcn36xx_hal_msg_header header;
3584
3585
3586 u32 tx_power;
3587
3588 u8 bss_index;
3589};
3590
3591struct set_tx_pwr_rsp_msg {
3592 struct wcn36xx_hal_msg_header header;
3593
3594
3595 u32 status;
3596};
3597
3598struct get_tx_pwr_req_msg {
3599 struct wcn36xx_hal_msg_header header;
3600
3601 u8 sta_id;
3602};
3603
3604struct get_tx_pwr_rsp_msg {
3605 struct wcn36xx_hal_msg_header header;
3606
3607
3608 u32 status;
3609
3610
3611 u32 tx_power;
3612};
3613
3614struct set_p2p_gonoa_req_msg {
3615 struct wcn36xx_hal_msg_header header;
3616
3617 u8 opp_ps;
3618 u32 ct_window;
3619 u8 count;
3620 u32 duration;
3621 u32 interval;
3622 u32 single_noa_duration;
3623 u8 ps_selection;
3624};
3625
3626struct set_p2p_gonoa_rsp_msg {
3627 struct wcn36xx_hal_msg_header header;
3628
3629
3630 u32 status;
3631};
3632
3633struct wcn36xx_hal_add_sta_self_req {
3634 struct wcn36xx_hal_msg_header header;
3635
3636 u8 self_addr[ETH_ALEN];
3637 u32 status;
3638} __packed;
3639
3640struct wcn36xx_hal_add_sta_self_rsp_msg {
3641 struct wcn36xx_hal_msg_header header;
3642
3643
3644 u32 status;
3645
3646
3647 u8 self_sta_index;
3648
3649
3650 u8 dpu_index;
3651
3652
3653 u8 dpu_signature;
3654} __packed;
3655
3656struct wcn36xx_hal_del_sta_self_req_msg {
3657 struct wcn36xx_hal_msg_header header;
3658
3659 u8 self_addr[ETH_ALEN];
3660} __packed;
3661
3662struct wcn36xx_hal_del_sta_self_rsp_msg {
3663 struct wcn36xx_hal_msg_header header;
3664
3665
3666 u32 status;
3667
3668 u8 self_addr[ETH_ALEN];
3669} __packed;
3670
3671struct aggr_add_ts_req {
3672 struct wcn36xx_hal_msg_header header;
3673
3674
3675 u16 sta_idx;
3676
3677
3678
3679
3680 u16 tspec_index;
3681
3682
3683 struct wcn36xx_hal_tspec_ie tspec[WCN36XX_HAL_MAX_AC];
3684
3685
3686
3687
3688 u8 uapsd;
3689
3690
3691
3692
3693 u32 service_interval[WCN36XX_HAL_MAX_AC];
3694
3695
3696 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
3697
3698
3699 u32 delay_interval[WCN36XX_HAL_MAX_AC];
3700};
3701
3702struct aggr_add_ts_rsp_msg {
3703 struct wcn36xx_hal_msg_header header;
3704
3705
3706 u32 status0;
3707
3708
3709 u32 status1;
3710};
3711
3712struct wcn36xx_hal_configure_apps_cpu_wakeup_state_req_msg {
3713 struct wcn36xx_hal_msg_header header;
3714
3715 u8 is_apps_cpu_awake;
3716};
3717
3718struct wcn36xx_hal_configure_apps_cpu_wakeup_state_rsp_msg {
3719 struct wcn36xx_hal_msg_header header;
3720
3721
3722 u32 status;
3723};
3724
3725struct wcn36xx_hal_dump_cmd_req_msg {
3726 struct wcn36xx_hal_msg_header header;
3727
3728 u32 arg1;
3729 u32 arg2;
3730 u32 arg3;
3731 u32 arg4;
3732 u32 arg5;
3733} __packed;
3734
3735struct wcn36xx_hal_dump_cmd_rsp_msg {
3736 struct wcn36xx_hal_msg_header header;
3737
3738
3739 u32 status;
3740
3741
3742 u32 rsp_length;
3743
3744
3745
3746 u8 rsp_buffer[DUMPCMD_RSP_BUFFER];
3747} __packed;
3748
3749#define WLAN_COEX_IND_DATA_SIZE (4)
3750#define WLAN_COEX_IND_TYPE_DISABLE_HB_MONITOR (0)
3751#define WLAN_COEX_IND_TYPE_ENABLE_HB_MONITOR (1)
3752
3753struct coex_ind_msg {
3754 struct wcn36xx_hal_msg_header header;
3755
3756
3757 u32 type;
3758
3759
3760 u32 data[WLAN_COEX_IND_DATA_SIZE];
3761};
3762
3763struct wcn36xx_hal_tx_compl_ind_msg {
3764 struct wcn36xx_hal_msg_header header;
3765
3766
3767 u32 status;
3768};
3769
3770struct wcn36xx_hal_wlan_host_suspend_ind_msg {
3771 struct wcn36xx_hal_msg_header header;
3772
3773 u32 configured_mcst_bcst_filter_setting;
3774 u32 active_session_count;
3775};
3776
3777struct wcn36xx_hal_wlan_exclude_unencrpted_ind_msg {
3778 struct wcn36xx_hal_msg_header header;
3779
3780 u8 dot11_exclude_unencrypted;
3781 u8 bssid[ETH_ALEN];
3782};
3783
3784struct noa_attr_ind_msg {
3785 struct wcn36xx_hal_msg_header header;
3786
3787 u8 index;
3788 u8 opp_ps_flag;
3789 u16 ctwin;
3790
3791 u16 noa1_interval_count;
3792 u16 bss_index;
3793 u32 noa1_duration;
3794 u32 noa1_interval;
3795 u32 noa1_starttime;
3796
3797 u16 noa2_interval_count;
3798 u16 reserved2;
3799 u32 noa2_duration;
3800 u32 noa2_interval;
3801 u32 noa2_start_time;
3802
3803 u32 status;
3804};
3805
3806struct noa_start_ind_msg {
3807 struct wcn36xx_hal_msg_header header;
3808
3809 u32 status;
3810 u32 bss_index;
3811};
3812
3813struct wcn36xx_hal_wlan_host_resume_req_msg {
3814 struct wcn36xx_hal_msg_header header;
3815
3816 u8 configured_mcst_bcst_filter_setting;
3817};
3818
3819struct wcn36xx_hal_host_resume_rsp_msg {
3820 struct wcn36xx_hal_msg_header header;
3821
3822
3823 u32 status;
3824};
3825
3826struct wcn36xx_hal_del_ba_ind_msg {
3827 struct wcn36xx_hal_msg_header header;
3828
3829 u16 sta_idx;
3830
3831
3832 u8 peer_addr[ETH_ALEN];
3833
3834
3835 u8 ba_tid;
3836
3837
3838
3839
3840
3841 u8 direction;
3842
3843 u32 reason_code;
3844
3845
3846 u8 bssid[ETH_ALEN];
3847};
3848
3849
3850
3851
3852#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS 26
3853
3854
3855#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX 60
3856
3857
3858#define WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS 16
3859
3860
3861#define WCN36XX_HAL_PNO_MAX_SCAN_TIMERS 10
3862
3863
3864#define WCN36XX_HAL_PNO_MAX_PROBE_SIZE 450
3865
3866
3867
3868
3869
3870
3871
3872
3873
3874
3875enum pno_mode {
3876 PNO_MODE_IMMEDIATE,
3877 PNO_MODE_ON_SUSPEND,
3878 PNO_MODE_ON_RESUME,
3879 PNO_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3880};
3881
3882
3883enum auth_type {
3884 AUTH_TYPE_ANY = 0,
3885 AUTH_TYPE_OPEN_SYSTEM = 1,
3886
3887
3888 AUTH_TYPE_WPA = 2,
3889 AUTH_TYPE_WPA_PSK = 3,
3890
3891 AUTH_TYPE_RSN = 4,
3892 AUTH_TYPE_RSN_PSK = 5,
3893 AUTH_TYPE_FT_RSN = 6,
3894 AUTH_TYPE_FT_RSN_PSK = 7,
3895 AUTH_TYPE_WAPI_WAI_CERTIFICATE = 8,
3896 AUTH_TYPE_WAPI_WAI_PSK = 9,
3897
3898 AUTH_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3899};
3900
3901
3902enum ed_type {
3903 ED_ANY = 0,
3904 ED_NONE = 1,
3905 ED_WEP = 2,
3906 ED_TKIP = 3,
3907 ED_CCMP = 4,
3908 ED_WPI = 5,
3909
3910 ED_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3911};
3912
3913
3914enum ssid_bcast_type {
3915 BCAST_UNKNOWN = 0,
3916 BCAST_NORMAL = 1,
3917 BCAST_HIDDEN = 2,
3918
3919 BCAST_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
3920};
3921
3922
3923struct network_type {
3924
3925 struct wcn36xx_hal_mac_ssid ssid;
3926
3927
3928 enum auth_type authentication;
3929
3930
3931 enum ed_type encryption;
3932
3933
3934
3935 u8 channel_count;
3936 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
3937
3938
3939 u8 rssi_threshold;
3940};
3941
3942struct scan_timer {
3943
3944 u32 value;
3945
3946
3947
3948 u32 repeat;
3949
3950
3951
3952
3953};
3954
3955
3956struct scan_timers_type {
3957
3958 u8 count;
3959
3960
3961
3962
3963
3964
3965
3966
3967 struct scan_timer values[WCN36XX_HAL_PNO_MAX_SCAN_TIMERS];
3968};
3969
3970
3971struct set_pref_netw_list_req {
3972 struct wcn36xx_hal_msg_header header;
3973
3974
3975 u32 enable;
3976
3977
3978 enum pno_mode mode;
3979
3980
3981 u32 networks_count;
3982
3983
3984 struct network_type networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
3985
3986
3987 struct scan_timers_type scan_timers;
3988
3989
3990 u16 band_24g_probe_size;
3991 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
3992
3993
3994 u16 band_5g_probe_size;
3995 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
3996};
3997
3998
3999struct network_type_new {
4000
4001 struct wcn36xx_hal_mac_ssid ssid;
4002
4003
4004 enum auth_type authentication;
4005
4006
4007 enum ed_type encryption;
4008
4009
4010 enum ssid_bcast_type bcast_network_type;
4011
4012
4013
4014 u8 channel_count;
4015 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4016
4017
4018 u8 rssi_threshold;
4019};
4020
4021
4022struct set_pref_netw_list_req_new {
4023 struct wcn36xx_hal_msg_header header;
4024
4025
4026 u32 enable;
4027
4028
4029 enum pno_mode mode;
4030
4031
4032 u32 networks_count;
4033
4034
4035 struct network_type_new networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
4036
4037
4038 struct scan_timers_type scan_timers;
4039
4040
4041 u16 band_24g_probe_size;
4042 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4043
4044
4045 u16 band_5g_probe_size;
4046 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4047};
4048
4049
4050struct set_pref_netw_list_resp {
4051 struct wcn36xx_hal_msg_header header;
4052
4053
4054
4055 u32 status;
4056};
4057
4058
4059struct pref_netw_found_ind {
4060
4061 struct wcn36xx_hal_msg_header header;
4062
4063
4064 struct wcn36xx_hal_mac_ssid ssid;
4065
4066
4067 u8 rssi;
4068};
4069
4070
4071struct set_rssi_filter_req {
4072 struct wcn36xx_hal_msg_header header;
4073
4074
4075 u8 rssi_threshold;
4076};
4077
4078
4079struct set_rssi_filter_resp {
4080 struct wcn36xx_hal_msg_header header;
4081
4082
4083 u32 status;
4084};
4085
4086
4087
4088struct wcn36xx_hal_update_scan_params_req {
4089
4090 struct wcn36xx_hal_msg_header header;
4091
4092
4093 u8 dot11d_enabled;
4094
4095
4096 u8 dot11d_resolved;
4097
4098
4099 u8 channel_count;
4100 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4101
4102
4103 u16 active_min_ch_time;
4104
4105
4106 u16 active_max_ch_time;
4107
4108
4109 u16 passive_min_ch_time;
4110
4111
4112 u16 passive_max_ch_time;
4113
4114
4115 enum phy_chan_bond_state state;
4116} __packed;
4117
4118
4119
4120struct update_scan_params_req_ex {
4121
4122 struct wcn36xx_hal_msg_header header;
4123
4124
4125 u8 dot11d_enabled;
4126
4127
4128 u8 dot11d_resolved;
4129
4130
4131 u8 channel_count;
4132 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX];
4133
4134
4135 u16 active_min_ch_time;
4136
4137
4138 u16 active_max_ch_time;
4139
4140
4141 u16 passive_min_ch_time;
4142
4143
4144 u16 passive_max_ch_time;
4145
4146
4147 enum phy_chan_bond_state state;
4148};
4149
4150
4151
4152struct wcn36xx_hal_update_scan_params_resp {
4153
4154 struct wcn36xx_hal_msg_header header;
4155
4156
4157 u32 status;
4158} __packed;
4159
4160struct wcn36xx_hal_set_tx_per_tracking_req_msg {
4161 struct wcn36xx_hal_msg_header header;
4162
4163
4164 u8 tx_per_tracking_enable;
4165
4166
4167 u8 tx_per_tracking_period;
4168
4169
4170 u8 tx_per_tracking_ratio;
4171
4172
4173
4174 u32 tx_per_tracking_watermark;
4175};
4176
4177struct wcn36xx_hal_set_tx_per_tracking_rsp_msg {
4178 struct wcn36xx_hal_msg_header header;
4179
4180
4181 u32 status;
4182
4183};
4184
4185struct tx_per_hit_ind_msg {
4186 struct wcn36xx_hal_msg_header header;
4187};
4188
4189
4190#define WCN36XX_HAL_PROTOCOL_DATA_LEN 8
4191#define WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS 240
4192#define WCN36XX_HAL_MAX_NUM_FILTERS 20
4193#define WCN36XX_HAL_MAX_CMP_PER_FILTER 10
4194
4195enum wcn36xx_hal_receive_packet_filter_type {
4196 HAL_RCV_FILTER_TYPE_INVALID,
4197 HAL_RCV_FILTER_TYPE_FILTER_PKT,
4198 HAL_RCV_FILTER_TYPE_BUFFER_PKT,
4199 HAL_RCV_FILTER_TYPE_MAX_ENUM_SIZE
4200};
4201
4202enum wcn36xx_hal_rcv_pkt_flt_protocol_type {
4203 HAL_FILTER_PROTO_TYPE_INVALID,
4204 HAL_FILTER_PROTO_TYPE_MAC,
4205 HAL_FILTER_PROTO_TYPE_ARP,
4206 HAL_FILTER_PROTO_TYPE_IPV4,
4207 HAL_FILTER_PROTO_TYPE_IPV6,
4208 HAL_FILTER_PROTO_TYPE_UDP,
4209 HAL_FILTER_PROTO_TYPE_MAX
4210};
4211
4212enum wcn36xx_hal_rcv_pkt_flt_cmp_flag_type {
4213 HAL_FILTER_CMP_TYPE_INVALID,
4214 HAL_FILTER_CMP_TYPE_EQUAL,
4215 HAL_FILTER_CMP_TYPE_MASK_EQUAL,
4216 HAL_FILTER_CMP_TYPE_NOT_EQUAL,
4217 HAL_FILTER_CMP_TYPE_MAX
4218};
4219
4220struct wcn36xx_hal_rcv_pkt_filter_params {
4221 u8 protocol_layer;
4222 u8 cmp_flag;
4223
4224
4225 u16 data_length;
4226
4227
4228 u8 data_offset;
4229
4230
4231 u8 reserved;
4232
4233
4234 u8 compare_data[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4235
4236
4237 u8 data_mask[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4238};
4239
4240struct wcn36xx_hal_sessionized_rcv_pkt_filter_cfg_type {
4241 u8 id;
4242 u8 type;
4243 u8 params_count;
4244 u32 coleasce_time;
4245 u8 bss_index;
4246 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4247};
4248
4249struct wcn36xx_hal_set_rcv_pkt_filter_req_msg {
4250 struct wcn36xx_hal_msg_header header;
4251
4252 u8 id;
4253 u8 type;
4254 u8 params_count;
4255 u32 coalesce_time;
4256 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4257};
4258
4259struct wcn36xx_hal_rcv_flt_mc_addr_list_type {
4260
4261 u8 data_offset;
4262
4263 u32 mc_addr_count;
4264 u8 mc_addr[ETH_ALEN][WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS];
4265 u8 bss_index;
4266};
4267
4268struct wcn36xx_hal_set_pkt_filter_rsp_msg {
4269 struct wcn36xx_hal_msg_header header;
4270
4271
4272 u32 status;
4273
4274 u8 bss_index;
4275};
4276
4277struct wcn36xx_hal_rcv_flt_pkt_match_cnt_req_msg {
4278 struct wcn36xx_hal_msg_header header;
4279
4280 u8 bss_index;
4281};
4282
4283struct wcn36xx_hal_rcv_flt_pkt_match_cnt {
4284 u8 id;
4285 u32 match_cnt;
4286};
4287
4288struct wcn36xx_hal_rcv_flt_pkt_match_cnt_rsp_msg {
4289 struct wcn36xx_hal_msg_header header;
4290
4291
4292 u32 status;
4293
4294 u32 match_count;
4295 struct wcn36xx_hal_rcv_flt_pkt_match_cnt
4296 matches[WCN36XX_HAL_MAX_NUM_FILTERS];
4297 u8 bss_index;
4298};
4299
4300struct wcn36xx_hal_rcv_flt_pkt_clear_param {
4301
4302 u32 status;
4303 u8 id;
4304 u8 bss_index;
4305};
4306
4307struct wcn36xx_hal_rcv_flt_pkt_clear_req_msg {
4308 struct wcn36xx_hal_msg_header header;
4309 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4310};
4311
4312struct wcn36xx_hal_rcv_flt_pkt_clear_rsp_msg {
4313 struct wcn36xx_hal_msg_header header;
4314 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4315};
4316
4317struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_req_msg {
4318 struct wcn36xx_hal_msg_header header;
4319 struct wcn36xx_hal_rcv_flt_mc_addr_list_type mc_addr_list;
4320};
4321
4322struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_rsp_msg {
4323 struct wcn36xx_hal_msg_header header;
4324 u32 status;
4325 u8 bss_index;
4326};
4327
4328
4329
4330struct wcn36xx_hal_set_power_params_req_msg {
4331 struct wcn36xx_hal_msg_header header;
4332
4333
4334 u32 ignore_dtim;
4335
4336
4337 u32 dtim_period;
4338
4339
4340 u32 listen_interval;
4341
4342
4343 u32 bcast_mcast_filter;
4344
4345
4346 u32 enable_bet;
4347
4348
4349 u32 bet_interval;
4350} __packed;
4351
4352struct wcn36xx_hal_set_power_params_resp {
4353
4354 struct wcn36xx_hal_msg_header header;
4355
4356
4357 u32 status;
4358} __packed;
4359
4360
4361
4362enum place_holder_in_cap_bitmap {
4363 MCC = 0,
4364 P2P = 1,
4365 DOT11AC = 2,
4366 SLM_SESSIONIZATION = 3,
4367 DOT11AC_OPMODE = 4,
4368 SAP32STA = 5,
4369 TDLS = 6,
4370 P2P_GO_NOA_DECOUPLE_INIT_SCAN = 7,
4371 WLANACTIVE_OFFLOAD = 8,
4372 BEACON_OFFLOAD = 9,
4373 SCAN_OFFLOAD = 10,
4374 ROAM_OFFLOAD = 11,
4375 BCN_MISS_OFFLOAD = 12,
4376 STA_POWERSAVE = 13,
4377 STA_ADVANCED_PWRSAVE = 14,
4378 AP_UAPSD = 15,
4379 AP_DFS = 16,
4380 BLOCKACK = 17,
4381 PHY_ERR = 18,
4382 BCN_FILTER = 19,
4383 RTT = 20,
4384 RATECTRL = 21,
4385 WOW = 22,
4386 MAX_FEATURE_SUPPORTED = 128,
4387};
4388
4389#define WCN36XX_HAL_CAPS_SIZE 4
4390
4391struct wcn36xx_hal_feat_caps_msg {
4392
4393 struct wcn36xx_hal_msg_header header;
4394
4395 u32 feat_caps[WCN36XX_HAL_CAPS_SIZE];
4396} __packed;
4397
4398
4399enum gtk_rekey_status {
4400 WCN36XX_HAL_GTK_REKEY_STATUS_SUCCESS = 0,
4401
4402
4403 WCN36XX_HAL_GTK_REKEY_STATUS_NOT_HANDLED = 1,
4404
4405
4406 WCN36XX_HAL_GTK_REKEY_STATUS_MIC_ERROR = 2,
4407
4408
4409 WCN36XX_HAL_GTK_REKEY_STATUS_DECRYPT_ERROR = 3,
4410
4411
4412 WCN36XX_HAL_GTK_REKEY_STATUS_REPLAY_ERROR = 4,
4413
4414
4415 WCN36XX_HAL_GTK_REKEY_STATUS_MISSING_KDE = 5,
4416
4417
4418 WCN36XX_HAL_GTK_REKEY_STATUS_MISSING_IGTK_KDE = 6,
4419
4420
4421 WCN36XX_HAL_GTK_REKEY_STATUS_INSTALL_ERROR = 7,
4422
4423
4424 WCN36XX_HAL_GTK_REKEY_STATUS_IGTK_INSTALL_ERROR = 8,
4425
4426
4427 WCN36XX_HAL_GTK_REKEY_STATUS_RESP_TX_ERROR = 9,
4428
4429
4430 WCN36XX_HAL_GTK_REKEY_STATUS_GEN_ERROR = 255
4431};
4432
4433
4434enum wake_reason_type {
4435 WCN36XX_HAL_WAKE_REASON_NONE = 0,
4436
4437
4438 WCN36XX_HAL_WAKE_REASON_MAGIC_PACKET = 1,
4439
4440
4441 WCN36XX_HAL_WAKE_REASON_PATTERN_MATCH = 2,
4442
4443
4444 WCN36XX_HAL_WAKE_REASON_EAPID_PACKET = 3,
4445
4446
4447 WCN36XX_HAL_WAKE_REASON_EAPOL4WAY_PACKET = 4,
4448
4449
4450 WCN36XX_HAL_WAKE_REASON_NETSCAN_OFFL_MATCH = 5,
4451
4452
4453 WCN36XX_HAL_WAKE_REASON_GTK_REKEY_STATUS = 6,
4454
4455
4456 WCN36XX_HAL_WAKE_REASON_BSS_CONN_LOST = 7,
4457};
4458
4459
4460
4461
4462
4463
4464
4465
4466
4467
4468
4469
4470
4471
4472
4473
4474struct wcn36xx_hal_wake_reason_ind {
4475 struct wcn36xx_hal_msg_header header;
4476
4477
4478 u32 reason;
4479
4480
4481 u32 reason_arg;
4482
4483
4484
4485
4486 u32 stored_data_len;
4487
4488
4489 u32 actual_data_len;
4490
4491
4492
4493 u8 data_start[1];
4494
4495 u32 bss_index:8;
4496 u32 reserved:24;
4497};
4498
4499#define WCN36XX_HAL_GTK_KEK_BYTES 16
4500#define WCN36XX_HAL_GTK_KCK_BYTES 16
4501
4502#define WCN36XX_HAL_GTK_OFFLOAD_FLAGS_DISABLE (1 << 0)
4503
4504#define GTK_SET_BSS_KEY_TAG 0x1234AA55
4505
4506struct wcn36xx_hal_gtk_offload_req_msg {
4507 struct wcn36xx_hal_msg_header header;
4508
4509
4510 u32 flags;
4511
4512
4513 u8 kck[WCN36XX_HAL_GTK_KCK_BYTES];
4514
4515
4516 u8 kek[WCN36XX_HAL_GTK_KEK_BYTES];
4517
4518
4519 u64 key_replay_counter;
4520
4521 u8 bss_index;
4522};
4523
4524struct wcn36xx_hal_gtk_offload_rsp_msg {
4525 struct wcn36xx_hal_msg_header header;
4526
4527
4528 u32 status;
4529
4530 u8 bss_index;
4531};
4532
4533struct wcn36xx_hal_gtk_offload_get_info_req_msg {
4534 struct wcn36xx_hal_msg_header header;
4535 u8 bss_index;
4536};
4537
4538struct wcn36xx_hal_gtk_offload_get_info_rsp_msg {
4539 struct wcn36xx_hal_msg_header header;
4540
4541
4542 u32 status;
4543
4544
4545 u32 last_rekey_status;
4546
4547
4548 u64 key_replay_counter;
4549
4550
4551 u32 total_rekey_count;
4552
4553
4554 u32 gtk_rekey_count;
4555
4556
4557 u32 igtk_rekey_count;
4558
4559 u8 bss_index;
4560};
4561
4562struct dhcp_info {
4563
4564 u8 device_mode;
4565
4566 u8 addr[ETH_ALEN];
4567};
4568
4569struct dhcp_ind_status {
4570 struct wcn36xx_hal_msg_header header;
4571
4572
4573 u32 status;
4574};
4575
4576
4577
4578
4579
4580
4581
4582
4583
4584
4585enum wcn36xx_hal_thermal_mitigation_mode_type {
4586 HAL_THERMAL_MITIGATION_MODE_INVALID = -1,
4587 HAL_THERMAL_MITIGATION_MODE_0,
4588 HAL_THERMAL_MITIGATION_MODE_1,
4589 HAL_THERMAL_MITIGATION_MODE_2,
4590 HAL_THERMAL_MITIGATION_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
4591};
4592
4593
4594
4595
4596
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611enum wcn36xx_hal_thermal_mitigation_level_type {
4612 HAL_THERMAL_MITIGATION_LEVEL_INVALID = -1,
4613 HAL_THERMAL_MITIGATION_LEVEL_0,
4614 HAL_THERMAL_MITIGATION_LEVEL_1,
4615 HAL_THERMAL_MITIGATION_LEVEL_2,
4616 HAL_THERMAL_MITIGATION_LEVEL_3,
4617 HAL_THERMAL_MITIGATION_LEVEL_4,
4618 HAL_THERMAL_MITIGATION_LEVEL_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
4619};
4620
4621
4622
4623struct set_thermal_mitigation_req_msg {
4624 struct wcn36xx_hal_msg_header header;
4625
4626
4627 enum wcn36xx_hal_thermal_mitigation_mode_type mode;
4628
4629
4630 enum wcn36xx_hal_thermal_mitigation_level_type level;
4631};
4632
4633struct set_thermal_mitigation_resp {
4634
4635 struct wcn36xx_hal_msg_header header;
4636
4637
4638 u32 status;
4639};
4640
4641
4642
4643struct stats_class_b_ind {
4644 struct wcn36xx_hal_msg_header header;
4645
4646
4647 u32 duration;
4648
4649
4650
4651
4652 u32 tx_bytes_pushed;
4653 u32 tx_packets_pushed;
4654
4655
4656 u32 rx_bytes_rcvd;
4657 u32 rx_packets_rcvd;
4658 u32 rx_time_total;
4659};
4660
4661#endif
4662