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69#ifndef __iwl_commands_h__
70#define __iwl_commands_h__
71
72#include <linux/ieee80211.h>
73#include <linux/types.h>
74
75
76enum {
77 REPLY_ALIVE = 0x1,
78 REPLY_ERROR = 0x2,
79 REPLY_ECHO = 0x3,
80
81
82 REPLY_RXON = 0x10,
83 REPLY_RXON_ASSOC = 0x11,
84 REPLY_QOS_PARAM = 0x13,
85 REPLY_RXON_TIMING = 0x14,
86
87
88 REPLY_ADD_STA = 0x18,
89 REPLY_REMOVE_STA = 0x19,
90 REPLY_REMOVE_ALL_STA = 0x1a,
91 REPLY_TXFIFO_FLUSH = 0x1e,
92
93
94 REPLY_WEPKEY = 0x20,
95
96
97 REPLY_TX = 0x1c,
98 REPLY_LEDS_CMD = 0x48,
99 REPLY_TX_LINK_QUALITY_CMD = 0x4e,
100
101
102 COEX_PRIORITY_TABLE_CMD = 0x5a,
103 COEX_MEDIUM_NOTIFICATION = 0x5b,
104 COEX_EVENT_CMD = 0x5c,
105
106
107 TEMPERATURE_NOTIFICATION = 0x62,
108 CALIBRATION_CFG_CMD = 0x65,
109 CALIBRATION_RES_NOTIFICATION = 0x66,
110 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
111
112
113 REPLY_QUIET_CMD = 0x71,
114 REPLY_CHANNEL_SWITCH = 0x72,
115 CHANNEL_SWITCH_NOTIFICATION = 0x73,
116 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74,
117 SPECTRUM_MEASURE_NOTIFICATION = 0x75,
118
119
120 POWER_TABLE_CMD = 0x77,
121 PM_SLEEP_NOTIFICATION = 0x7A,
122 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B,
123
124
125 REPLY_SCAN_CMD = 0x80,
126 REPLY_SCAN_ABORT_CMD = 0x81,
127 SCAN_START_NOTIFICATION = 0x82,
128 SCAN_RESULTS_NOTIFICATION = 0x83,
129 SCAN_COMPLETE_NOTIFICATION = 0x84,
130
131
132 BEACON_NOTIFICATION = 0x90,
133 REPLY_TX_BEACON = 0x91,
134 WHO_IS_AWAKE_NOTIFICATION = 0x94,
135
136
137 REPLY_TX_POWER_DBM_CMD = 0x95,
138 QUIET_NOTIFICATION = 0x96,
139 REPLY_TX_PWR_TABLE_CMD = 0x97,
140 REPLY_TX_POWER_DBM_CMD_V1 = 0x98,
141 TX_ANT_CONFIGURATION_CMD = 0x98,
142 MEASURE_ABORT_NOTIFICATION = 0x99,
143
144
145 REPLY_BT_CONFIG = 0x9b,
146
147
148 REPLY_STATISTICS_CMD = 0x9c,
149 STATISTICS_NOTIFICATION = 0x9d,
150
151
152 REPLY_CARD_STATE_CMD = 0xa0,
153 CARD_STATE_NOTIFICATION = 0xa1,
154
155
156 MISSED_BEACONS_NOTIFICATION = 0xa2,
157
158 REPLY_CT_KILL_CONFIG_CMD = 0xa4,
159 SENSITIVITY_CMD = 0xa8,
160 REPLY_PHY_CALIBRATION_CMD = 0xb0,
161 REPLY_RX_PHY_CMD = 0xc0,
162 REPLY_RX_MPDU_CMD = 0xc1,
163 REPLY_RX = 0xc3,
164 REPLY_COMPRESSED_BA = 0xc5,
165
166
167 REPLY_BT_COEX_PRIO_TABLE = 0xcc,
168 REPLY_BT_COEX_PROT_ENV = 0xcd,
169 REPLY_BT_COEX_PROFILE_NOTIF = 0xce,
170
171
172 REPLY_WIPAN_PARAMS = 0xb2,
173 REPLY_WIPAN_RXON = 0xb3,
174 REPLY_WIPAN_RXON_TIMING = 0xb4,
175 REPLY_WIPAN_RXON_ASSOC = 0xb6,
176 REPLY_WIPAN_QOS_PARAM = 0xb7,
177 REPLY_WIPAN_WEPKEY = 0xb8,
178 REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9,
179 REPLY_WIPAN_NOA_NOTIFICATION = 0xbc,
180 REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd,
181
182 REPLY_WOWLAN_PATTERNS = 0xe0,
183 REPLY_WOWLAN_WAKEUP_FILTER = 0xe1,
184 REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2,
185 REPLY_WOWLAN_TKIP_PARAMS = 0xe3,
186 REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
187 REPLY_WOWLAN_GET_STATUS = 0xe5,
188 REPLY_D3_CONFIG = 0xd3,
189
190 REPLY_MAX = 0xff
191};
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200
201
202#define IWL_MIN_NUM_QUEUES 11
203
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206
207#define IWL_DEFAULT_CMD_QUEUE_NUM 4
208#define IWL_IPAN_CMD_QUEUE_NUM 9
209
210#define IWL_TX_FIFO_BK 0
211#define IWL_TX_FIFO_BE 1
212#define IWL_TX_FIFO_VI 2
213#define IWL_TX_FIFO_VO 3
214#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
215#define IWL_TX_FIFO_BE_IPAN 4
216#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
217#define IWL_TX_FIFO_VO_IPAN 5
218
219#define IWL_TX_FIFO_AUX 5
220#define IWL_TX_FIFO_UNUSED 255
221
222#define IWLAGN_CMD_FIFO_NUM 7
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228
229#define IWL_IPAN_MCAST_QUEUE 8
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279#define RATE_MCS_CODE_MSK 0x7
280#define RATE_MCS_SPATIAL_POS 3
281#define RATE_MCS_SPATIAL_MSK 0x18
282#define RATE_MCS_HT_DUP_POS 5
283#define RATE_MCS_HT_DUP_MSK 0x20
284
285#define RATE_MCS_RATE_MSK 0xff
286
287
288#define RATE_MCS_FLAGS_POS 8
289#define RATE_MCS_HT_POS 8
290#define RATE_MCS_HT_MSK 0x100
291
292
293#define RATE_MCS_CCK_POS 9
294#define RATE_MCS_CCK_MSK 0x200
295
296
297#define RATE_MCS_GF_POS 10
298#define RATE_MCS_GF_MSK 0x400
299
300
301#define RATE_MCS_HT40_POS 11
302#define RATE_MCS_HT40_MSK 0x800
303
304
305#define RATE_MCS_DUP_POS 12
306#define RATE_MCS_DUP_MSK 0x1000
307
308
309#define RATE_MCS_SGI_POS 13
310#define RATE_MCS_SGI_MSK 0x2000
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321#define RATE_MCS_ANT_POS 14
322#define RATE_MCS_ANT_A_MSK 0x04000
323#define RATE_MCS_ANT_B_MSK 0x08000
324#define RATE_MCS_ANT_C_MSK 0x10000
325#define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
326#define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
327#define RATE_ANT_NUM 3
328
329#define POWER_TABLE_NUM_ENTRIES 33
330#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
331#define POWER_TABLE_CCK_ENTRY 32
332
333#define IWL_PWR_NUM_HT_OFDM_ENTRIES 24
334#define IWL_PWR_CCK_ENTRIES 2
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342
343struct tx_power_dual_stream {
344 __le32 dw;
345} __packed;
346
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349
350
351#define IWLAGN_TX_POWER_AUTO 0x7f
352#define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6)
353
354struct iwlagn_tx_power_dbm_cmd {
355 s8 global_lmt;
356 u8 flags;
357 s8 srv_chan_lmt;
358 u8 reserved;
359} __packed;
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367struct iwl_tx_ant_config_cmd {
368 __le32 valid;
369} __packed;
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376
377#define UCODE_VALID_OK cpu_to_le32(0x1)
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425struct iwl_error_event_table {
426 u32 valid;
427 u32 error_id;
428 u32 pc;
429 u32 blink1;
430 u32 blink2;
431 u32 ilink1;
432 u32 ilink2;
433 u32 data1;
434 u32 data2;
435 u32 line;
436 u32 bcon_time;
437 u32 tsf_low;
438 u32 tsf_hi;
439 u32 gp1;
440 u32 gp2;
441 u32 gp3;
442 u32 ucode_ver;
443 u32 hw_ver;
444 u32 brd_ver;
445 u32 log_pc;
446 u32 frame_ptr;
447 u32 stack_ptr;
448 u32 hcmd;
449 u32 isr0;
450
451 u32 isr1;
452
453 u32 isr2;
454
455 u32 isr3;
456
457 u32 isr4;
458
459 u32 isr_pref;
460 u32 wait_event;
461 u32 l2p_control;
462 u32 l2p_duration;
463 u32 l2p_mhvalid;
464 u32 l2p_addr_match;
465 u32 lmpm_pmg_sel;
466
467 u32 u_timestamp;
468
469 u32 flow_handler;
470} __packed;
471
472struct iwl_alive_resp {
473 u8 ucode_minor;
474 u8 ucode_major;
475 __le16 reserved1;
476 u8 sw_rev[8];
477 u8 ver_type;
478 u8 ver_subtype;
479 __le16 reserved2;
480 __le32 log_event_table_ptr;
481 __le32 error_event_table_ptr;
482 __le32 timestamp;
483 __le32 is_valid;
484} __packed;
485
486
487
488
489struct iwl_error_resp {
490 __le32 error_type;
491 u8 cmd_id;
492 u8 reserved1;
493 __le16 bad_cmd_seq_num;
494 __le32 error_info;
495 __le64 timestamp;
496} __packed;
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507
508enum {
509 RXON_DEV_TYPE_AP = 1,
510 RXON_DEV_TYPE_ESS = 3,
511 RXON_DEV_TYPE_IBSS = 4,
512 RXON_DEV_TYPE_SNIFFER = 6,
513 RXON_DEV_TYPE_CP = 7,
514 RXON_DEV_TYPE_2STA = 8,
515 RXON_DEV_TYPE_P2P = 9,
516};
517
518
519#define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
520#define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
521#define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
522#define RXON_RX_CHAIN_VALID_POS (1)
523#define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
524#define RXON_RX_CHAIN_FORCE_SEL_POS (4)
525#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
526#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
527#define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
528#define RXON_RX_CHAIN_CNT_POS (10)
529#define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
530#define RXON_RX_CHAIN_MIMO_CNT_POS (12)
531#define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
532#define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
533
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535
536#define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
537#define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
538
539#define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
540
541#define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
542
543#define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
544#define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
545
546#define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
547#define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
548#define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
549#define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
550
551#define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
552#define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
553
554
555#define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
556
557
558
559#define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
560#define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
561
562#define RXON_FLG_HT_OPERATING_MODE_POS (23)
563
564#define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
565#define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
566
567#define RXON_FLG_CHANNEL_MODE_POS (25)
568#define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
569
570
571enum {
572 CHANNEL_MODE_LEGACY = 0,
573 CHANNEL_MODE_PURE_40 = 1,
574 CHANNEL_MODE_MIXED = 2,
575 CHANNEL_MODE_RESERVED = 3,
576};
577#define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
578#define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
579#define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
580
581
582#define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
583
584
585
586#define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
587
588#define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
589
590#define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
591
592#define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
593
594#define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
595
596#define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
597
598#define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
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618struct iwl_rxon_cmd {
619 u8 node_addr[6];
620 __le16 reserved1;
621 u8 bssid_addr[6];
622 __le16 reserved2;
623 u8 wlap_bssid_addr[6];
624 __le16 reserved3;
625 u8 dev_type;
626 u8 air_propagation;
627 __le16 rx_chain;
628 u8 ofdm_basic_rates;
629 u8 cck_basic_rates;
630 __le16 assoc_id;
631 __le32 flags;
632 __le32 filter_flags;
633 __le16 channel;
634 u8 ofdm_ht_single_stream_basic_rates;
635 u8 ofdm_ht_dual_stream_basic_rates;
636 u8 ofdm_ht_triple_stream_basic_rates;
637 u8 reserved5;
638 __le16 acquisition_data;
639 __le16 reserved6;
640} __packed;
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644
645struct iwl_rxon_assoc_cmd {
646 __le32 flags;
647 __le32 filter_flags;
648 u8 ofdm_basic_rates;
649 u8 cck_basic_rates;
650 __le16 reserved1;
651 u8 ofdm_ht_single_stream_basic_rates;
652 u8 ofdm_ht_dual_stream_basic_rates;
653 u8 ofdm_ht_triple_stream_basic_rates;
654 u8 reserved2;
655 __le16 rx_chain_select_flags;
656 __le16 acquisition_data;
657 __le32 reserved3;
658} __packed;
659
660#define IWL_CONN_MAX_LISTEN_INTERVAL 10
661#define IWL_MAX_UCODE_BEACON_INTERVAL 4
662
663
664
665
666struct iwl_rxon_time_cmd {
667 __le64 timestamp;
668 __le16 beacon_interval;
669 __le16 atim_window;
670 __le32 beacon_init_val;
671 __le16 listen_interval;
672 u8 dtim_period;
673 u8 delta_cp_bss_tbtts;
674} __packed;
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690struct iwl5000_channel_switch_cmd {
691 u8 band;
692 u8 expect_beacon;
693 __le16 channel;
694 __le32 rxon_flags;
695 __le32 rxon_filter_flags;
696 __le32 switch_time;
697 __le32 reserved[2][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
698} __packed;
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711struct iwl6000_channel_switch_cmd {
712 u8 band;
713 u8 expect_beacon;
714 __le16 channel;
715 __le32 rxon_flags;
716 __le32 rxon_filter_flags;
717 __le32 switch_time;
718 __le32 reserved[3][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
719} __packed;
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724struct iwl_csa_notification {
725 __le16 band;
726 __le16 channel;
727 __le32 status;
728} __packed;
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752struct iwl_ac_qos {
753 __le16 cw_min;
754 __le16 cw_max;
755 u8 aifsn;
756 u8 reserved1;
757 __le16 edca_txop;
758} __packed;
759
760
761#define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
762#define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
763#define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
764
765
766#define AC_NUM 4
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774struct iwl_qosparam_cmd {
775 __le32 qos_flags;
776 struct iwl_ac_qos ac[AC_NUM];
777} __packed;
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789#define IWL_AP_ID 0
790#define IWL_AP_ID_PAN 1
791#define IWL_STA_ID 2
792#define IWLAGN_PAN_BCAST_ID 14
793#define IWLAGN_BROADCAST_ID 15
794#define IWLAGN_STATION_COUNT 16
795
796#define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
797
798#define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
799#define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
800#define STA_FLG_PAN_STATION cpu_to_le32(1 << 13)
801#define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
802#define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
803#define STA_FLG_MAX_AGG_SIZE_POS (19)
804#define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
805#define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
806#define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
807#define STA_FLG_AGG_MPDU_DENSITY_POS (23)
808#define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
809
810
811#define STA_CONTROL_MODIFY_MSK 0x01
812
813
814#define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
815#define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
816#define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
817#define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
818#define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
819
820#define STA_KEY_FLG_KEYID_POS 8
821#define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
822
823#define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
824
825
826#define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
827#define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
828#define STA_KEY_MAX_NUM 8
829#define STA_KEY_MAX_NUM_PAN 16
830
831#define IWLAGN_HW_KEY_DEFAULT 0xfe
832
833
834#define STA_MODIFY_KEY_MASK 0x01
835#define STA_MODIFY_TID_DISABLE_TX 0x02
836#define STA_MODIFY_TX_RATE_MSK 0x04
837#define STA_MODIFY_ADDBA_TID_MSK 0x08
838#define STA_MODIFY_DELBA_TID_MSK 0x10
839#define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
840
841
842struct iwl_keyinfo {
843 __le16 key_flags;
844 u8 tkip_rx_tsc_byte2;
845 u8 reserved1;
846 __le16 tkip_rx_ttak[5];
847 u8 key_offset;
848 u8 reserved2;
849 u8 key[16];
850 __le64 tx_secur_seq_cnt;
851 __le64 hw_tkip_mic_rx_key;
852 __le64 hw_tkip_mic_tx_key;
853} __packed;
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867struct sta_id_modify {
868 u8 addr[ETH_ALEN];
869 __le16 reserved1;
870 u8 sta_id;
871 u8 modify_mask;
872 __le16 reserved2;
873} __packed;
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901struct iwl_addsta_cmd {
902 u8 mode;
903 u8 reserved[3];
904 struct sta_id_modify sta;
905 struct iwl_keyinfo key;
906 __le32 station_flags;
907 __le32 station_flags_msk;
908
909
910
911
912 __le16 tid_disable_tx;
913 __le16 legacy_reserved;
914
915
916
917 u8 add_immediate_ba_tid;
918
919
920
921 u8 remove_immediate_ba_tid;
922
923
924
925 __le16 add_immediate_ba_ssn;
926
927
928
929
930
931
932 __le16 sleep_tx_count;
933
934 __le16 reserved2;
935} __packed;
936
937
938#define ADD_STA_SUCCESS_MSK 0x1
939#define ADD_STA_NO_ROOM_IN_TABLE 0x2
940#define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
941#define ADD_STA_MODIFY_NON_EXIST_STA 0x8
942
943
944
945struct iwl_add_sta_resp {
946 u8 status;
947} __packed;
948
949#define REM_STA_SUCCESS_MSK 0x1
950
951
952
953struct iwl_rem_sta_resp {
954 u8 status;
955} __packed;
956
957
958
959
960struct iwl_rem_sta_cmd {
961 u8 num_sta;
962 u8 reserved[3];
963 u8 addr[ETH_ALEN];
964 u8 reserved2[2];
965} __packed;
966
967
968
969#define IWL_SCD_BK_MSK BIT(0)
970#define IWL_SCD_BE_MSK BIT(1)
971#define IWL_SCD_VI_MSK BIT(2)
972#define IWL_SCD_VO_MSK BIT(3)
973#define IWL_SCD_MGMT_MSK BIT(3)
974
975
976#define IWL_PAN_SCD_BK_MSK BIT(4)
977#define IWL_PAN_SCD_BE_MSK BIT(5)
978#define IWL_PAN_SCD_VI_MSK BIT(6)
979#define IWL_PAN_SCD_VO_MSK BIT(7)
980#define IWL_PAN_SCD_MGMT_MSK BIT(7)
981#define IWL_PAN_SCD_MULTICAST_MSK BIT(8)
982
983#define IWL_AGG_TX_QUEUE_MSK 0xffc00
984
985#define IWL_DROP_ALL BIT(1)
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008struct iwl_txfifo_flush_cmd_v3 {
1009 __le32 queue_control;
1010 __le16 flush_control;
1011 __le16 reserved;
1012} __packed;
1013
1014struct iwl_txfifo_flush_cmd_v2 {
1015 __le16 queue_control;
1016 __le16 flush_control;
1017} __packed;
1018
1019
1020
1021
1022struct iwl_wep_key {
1023 u8 key_index;
1024 u8 key_offset;
1025 u8 reserved1[2];
1026 u8 key_size;
1027 u8 reserved2[3];
1028 u8 key[16];
1029} __packed;
1030
1031struct iwl_wep_cmd {
1032 u8 num_keys;
1033 u8 global_key_type;
1034 u8 flags;
1035 u8 reserved;
1036 struct iwl_wep_key key[0];
1037} __packed;
1038
1039#define WEP_KEY_WEP_TYPE 1
1040#define WEP_KEYS_MAX 4
1041#define WEP_INVALID_OFFSET 0xff
1042#define WEP_KEY_LEN_64 5
1043#define WEP_KEY_LEN_128 13
1044
1045
1046
1047
1048
1049
1050
1051#define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1052#define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1053
1054#define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1055#define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
1056#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
1057#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
1058#define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70
1059#define RX_RES_PHY_FLAGS_ANTENNA_POS 4
1060#define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7)
1061
1062#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1063#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1064#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1065#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1066#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1067#define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1068
1069#define RX_RES_STATUS_STATION_FOUND (1<<6)
1070#define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7)
1071
1072#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1073#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1074#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1075#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1076#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1077
1078#define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1079#define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1080#define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
1081#define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1082
1083
1084#define IWLAGN_RX_RES_PHY_CNT 8
1085#define IWLAGN_RX_RES_AGC_IDX 1
1086#define IWLAGN_RX_RES_RSSI_AB_IDX 2
1087#define IWLAGN_RX_RES_RSSI_C_IDX 3
1088#define IWLAGN_OFDM_AGC_MSK 0xfe00
1089#define IWLAGN_OFDM_AGC_BIT_POS 9
1090#define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff
1091#define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00
1092#define IWLAGN_OFDM_RSSI_A_BIT_POS 0
1093#define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000
1094#define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000
1095#define IWLAGN_OFDM_RSSI_B_BIT_POS 16
1096#define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff
1097#define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00
1098#define IWLAGN_OFDM_RSSI_C_BIT_POS 0
1099
1100struct iwlagn_non_cfg_phy {
1101 __le32 non_cfg_phy[IWLAGN_RX_RES_PHY_CNT];
1102} __packed;
1103
1104
1105
1106
1107
1108
1109struct iwl_rx_phy_res {
1110 u8 non_cfg_phy_cnt;
1111 u8 cfg_phy_cnt;
1112 u8 stat_id;
1113 u8 reserved1;
1114 __le64 timestamp;
1115 __le32 beacon_time_stamp;
1116 __le16 phy_flags;
1117 __le16 channel;
1118 u8 non_cfg_phy_buf[32];
1119 __le32 rate_n_flags;
1120 __le16 byte_count;
1121 __le16 frame_time;
1122} __packed;
1123
1124struct iwl_rx_mpdu_res_start {
1125 __le16 byte_count;
1126 __le16 reserved;
1127} __packed;
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
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1150
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1152
1153
1154
1155
1156
1157
1158
1159
1160
1161#define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1162
1163
1164
1165
1166#define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1167
1168
1169
1170
1171
1172
1173
1174#define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1175
1176
1177
1178#define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1179
1180
1181#define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1182
1183
1184
1185#define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1186
1187
1188
1189
1190
1191#define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1192
1193
1194
1195#define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1196
1197
1198
1199
1200#define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1201
1202
1203
1204
1205
1206
1207
1208#define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1209
1210
1211
1212#define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1213
1214
1215#define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1216
1217
1218
1219
1220
1221#define TX_CMD_SEC_WEP 0x01
1222#define TX_CMD_SEC_CCM 0x02
1223#define TX_CMD_SEC_TKIP 0x03
1224#define TX_CMD_SEC_MSK 0x03
1225#define TX_CMD_SEC_SHIFT 6
1226#define TX_CMD_SEC_KEY128 0x08
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237struct iwl_dram_scratch {
1238 u8 try_cnt;
1239 u8 bt_kill_cnt;
1240 __le16 reserved;
1241} __packed;
1242
1243struct iwl_tx_cmd {
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254 __le16 len;
1255
1256
1257
1258
1259
1260
1261 __le16 next_frame_len;
1262
1263 __le32 tx_flags;
1264
1265
1266
1267 struct iwl_dram_scratch scratch;
1268
1269
1270 __le32 rate_n_flags;
1271
1272
1273 u8 sta_id;
1274
1275
1276 u8 sec_ctl;
1277
1278
1279
1280
1281
1282
1283
1284
1285 u8 initial_rate_index;
1286 u8 reserved;
1287 u8 key[16];
1288 __le16 next_frame_flags;
1289 __le16 reserved2;
1290 union {
1291 __le32 life_time;
1292 __le32 attempt;
1293 } stop_time;
1294
1295
1296
1297 __le32 dram_lsb_ptr;
1298 u8 dram_msb_ptr;
1299
1300 u8 rts_retry_limit;
1301 u8 data_retry_limit;
1302 u8 tid_tspec;
1303 union {
1304 __le16 pm_frame_timeout;
1305 __le16 attempt_duration;
1306 } timeout;
1307
1308
1309
1310
1311
1312 __le16 driver_txop;
1313
1314
1315
1316
1317
1318 u8 payload[0];
1319 struct ieee80211_hdr hdr[0];
1320} __packed;
1321
1322
1323
1324
1325
1326
1327
1328
1329enum {
1330 TX_STATUS_SUCCESS = 0x01,
1331 TX_STATUS_DIRECT_DONE = 0x02,
1332
1333 TX_STATUS_POSTPONE_DELAY = 0x40,
1334 TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
1335 TX_STATUS_POSTPONE_BT_PRIO = 0x42,
1336 TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
1337 TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
1338
1339 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
1340 TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
1341 TX_STATUS_FAIL_LONG_LIMIT = 0x83,
1342 TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1343 TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
1344 TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
1345 TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1346 TX_STATUS_FAIL_DEST_PS = 0x88,
1347 TX_STATUS_FAIL_HOST_ABORTED = 0x89,
1348 TX_STATUS_FAIL_BT_RETRY = 0x8a,
1349 TX_STATUS_FAIL_STA_INVALID = 0x8b,
1350 TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1351 TX_STATUS_FAIL_TID_DISABLE = 0x8d,
1352 TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
1353 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1354 TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
1355 TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1356};
1357
1358#define TX_PACKET_MODE_REGULAR 0x0000
1359#define TX_PACKET_MODE_BURST_SEQ 0x0100
1360#define TX_PACKET_MODE_BURST_FIRST 0x0200
1361
1362enum {
1363 TX_POWER_PA_NOT_ACTIVE = 0x0,
1364};
1365
1366enum {
1367 TX_STATUS_MSK = 0x000000ff,
1368 TX_STATUS_DELAY_MSK = 0x00000040,
1369 TX_STATUS_ABORT_MSK = 0x00000080,
1370 TX_PACKET_MODE_MSK = 0x0000ff00,
1371 TX_FIFO_NUMBER_MSK = 0x00070000,
1372 TX_RESERVED = 0x00780000,
1373 TX_POWER_PA_DETECT_MSK = 0x7f800000,
1374 TX_ABORT_REQUIRED_MSK = 0x80000000,
1375};
1376
1377
1378
1379
1380
1381enum {
1382 AGG_TX_STATE_TRANSMITTED = 0x00,
1383 AGG_TX_STATE_UNDERRUN_MSK = 0x01,
1384 AGG_TX_STATE_BT_PRIO_MSK = 0x02,
1385 AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
1386 AGG_TX_STATE_ABORT_MSK = 0x08,
1387 AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
1388 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
1389 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40,
1390 AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
1391 AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
1392 AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
1393 AGG_TX_STATE_DUMP_TX_MSK = 0x200,
1394 AGG_TX_STATE_DELAY_TX_MSK = 0x400
1395};
1396
1397#define AGG_TX_STATUS_MSK 0x00000fff
1398#define AGG_TX_TRY_MSK 0x0000f000
1399#define AGG_TX_TRY_POS 12
1400
1401#define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1402 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
1403 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
1404
1405
1406#define AGG_TX_STATE_TRY_CNT_POS 12
1407#define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1408
1409
1410#define AGG_TX_STATE_SEQ_NUM_POS 16
1411#define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1412
1413
1414
1415
1416
1417
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1433
1434
1435struct agg_tx_status {
1436 __le16 status;
1437 __le16 sequence;
1438} __packed;
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450#define IWL50_TX_RES_INIT_RATE_INDEX_POS 0
1451#define IWL50_TX_RES_INIT_RATE_INDEX_MSK 0x0f
1452#define IWL50_TX_RES_RATE_TABLE_COLOR_POS 4
1453#define IWL50_TX_RES_RATE_TABLE_COLOR_MSK 0x70
1454#define IWL50_TX_RES_INV_RATE_INDEX_MSK 0x80
1455
1456
1457#define IWLAGN_TX_RES_TID_POS 0
1458#define IWLAGN_TX_RES_TID_MSK 0x0f
1459#define IWLAGN_TX_RES_RA_POS 4
1460#define IWLAGN_TX_RES_RA_MSK 0xf0
1461
1462struct iwlagn_tx_resp {
1463 u8 frame_count;
1464 u8 bt_kill_count;
1465 u8 failure_rts;
1466 u8 failure_frame;
1467
1468
1469
1470 __le32 rate_n_flags;
1471
1472
1473
1474 __le16 wireless_media_time;
1475
1476 u8 pa_status;
1477 u8 pa_integ_res_a[3];
1478 u8 pa_integ_res_b[3];
1479 u8 pa_integ_res_C[3];
1480
1481 __le32 tfd_info;
1482 __le16 seq_ctl;
1483 __le16 byte_cnt;
1484 u8 tlc_info;
1485 u8 ra_tid;
1486 __le16 frame_ctrl;
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500 struct agg_tx_status status;
1501
1502} __packed;
1503
1504
1505
1506
1507
1508struct iwl_compressed_ba_resp {
1509 __le32 sta_addr_lo32;
1510 __le16 sta_addr_hi16;
1511 __le16 reserved;
1512
1513
1514 u8 sta_id;
1515 u8 tid;
1516 __le16 seq_ctl;
1517 __le64 bitmap;
1518 __le16 scd_flow;
1519 __le16 scd_ssn;
1520 u8 txed;
1521 u8 txed_2_done;
1522 __le16 reserved1;
1523} __packed;
1524
1525
1526
1527
1528
1529
1530
1531#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1532
1533
1534#define LINK_QUAL_AC_NUM AC_NUM
1535
1536
1537#define LINK_QUAL_MAX_RETRY_NUM 16
1538
1539
1540#define LINK_QUAL_ANT_A_MSK (1 << 0)
1541#define LINK_QUAL_ANT_B_MSK (1 << 1)
1542#define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1543
1544
1545
1546
1547
1548
1549
1550struct iwl_link_qual_general_params {
1551 u8 flags;
1552
1553
1554 u8 mimo_delimiter;
1555
1556
1557 u8 single_stream_ant_msk;
1558
1559
1560 u8 dual_stream_ant_msk;
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573 u8 start_rate_index[LINK_QUAL_AC_NUM];
1574} __packed;
1575
1576#define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000)
1577#define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
1578#define LINK_QUAL_AGG_TIME_LIMIT_MIN (100)
1579
1580#define LINK_QUAL_AGG_DISABLE_START_DEF (3)
1581#define LINK_QUAL_AGG_DISABLE_START_MAX (255)
1582#define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1583
1584#define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63)
1585#define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
1586#define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
1587
1588
1589
1590
1591
1592
1593struct iwl_link_qual_agg_params {
1594
1595
1596
1597
1598
1599 __le16 agg_time_limit;
1600
1601
1602
1603
1604
1605
1606
1607 u8 agg_dis_start_th;
1608
1609
1610
1611
1612
1613
1614 u8 agg_frame_cnt_limit;
1615
1616 __le32 reserved;
1617} __packed;
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1805
1806
1807struct iwl_link_quality_cmd {
1808
1809
1810 u8 sta_id;
1811 u8 reserved1;
1812 __le16 control;
1813 struct iwl_link_qual_general_params general_params;
1814 struct iwl_link_qual_agg_params agg_params;
1815
1816
1817
1818
1819
1820
1821 struct {
1822 __le32 rate_n_flags;
1823 } rs_table[LINK_QUAL_MAX_RETRY_NUM];
1824 __le32 reserved2;
1825} __packed;
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836#define BT_COEX_DISABLE (0x0)
1837#define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
1838#define BT_ENABLE_PRIORITY BIT(1)
1839#define BT_ENABLE_2_WIRE BIT(2)
1840
1841#define BT_COEX_DISABLE (0x0)
1842#define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
1843
1844#define BT_LEAD_TIME_MIN (0x0)
1845#define BT_LEAD_TIME_DEF (0x1E)
1846#define BT_LEAD_TIME_MAX (0xFF)
1847
1848#define BT_MAX_KILL_MIN (0x1)
1849#define BT_MAX_KILL_DEF (0x5)
1850#define BT_MAX_KILL_MAX (0xFF)
1851
1852#define BT_DURATION_LIMIT_DEF 625
1853#define BT_DURATION_LIMIT_MAX 1250
1854#define BT_DURATION_LIMIT_MIN 625
1855
1856#define BT_ON_THRESHOLD_DEF 4
1857#define BT_ON_THRESHOLD_MAX 1000
1858#define BT_ON_THRESHOLD_MIN 1
1859
1860#define BT_FRAG_THRESHOLD_DEF 0
1861#define BT_FRAG_THRESHOLD_MAX 0
1862#define BT_FRAG_THRESHOLD_MIN 0
1863
1864#define BT_AGG_THRESHOLD_DEF 1200
1865#define BT_AGG_THRESHOLD_MAX 8000
1866#define BT_AGG_THRESHOLD_MIN 400
1867
1868
1869
1870
1871
1872
1873
1874
1875struct iwl_bt_cmd {
1876 u8 flags;
1877 u8 lead_time;
1878 u8 max_kill;
1879 u8 reserved;
1880 __le32 kill_ack_mask;
1881 __le32 kill_cts_mask;
1882} __packed;
1883
1884#define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0)
1885
1886#define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5))
1887#define IWLAGN_BT_FLAG_COEX_MODE_SHIFT 3
1888#define IWLAGN_BT_FLAG_COEX_MODE_DISABLED 0
1889#define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W 1
1890#define IWLAGN_BT_FLAG_COEX_MODE_3W 2
1891#define IWLAGN_BT_FLAG_COEX_MODE_4W 3
1892
1893#define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6)
1894
1895#define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7)
1896
1897#define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75
1898#define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65
1899
1900#define IWLAGN_BT_PRIO_BOOST_MAX 0xFF
1901#define IWLAGN_BT_PRIO_BOOST_MIN 0x00
1902#define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0
1903#define IWLAGN_BT_PRIO_BOOST_DEFAULT32 0xF0F0F0F0
1904
1905#define IWLAGN_BT_MAX_KILL_DEFAULT 5
1906
1907#define IWLAGN_BT3_T7_DEFAULT 1
1908
1909enum iwl_bt_kill_idx {
1910 IWL_BT_KILL_DEFAULT = 0,
1911 IWL_BT_KILL_OVERRIDE = 1,
1912 IWL_BT_KILL_REDUCE = 2,
1913};
1914
1915#define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
1916#define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
1917#define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
1918#define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0)
1919
1920#define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT 2
1921
1922#define IWLAGN_BT3_T2_DEFAULT 0xc
1923
1924#define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0))
1925#define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1))
1926#define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2))
1927#define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3))
1928#define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4))
1929#define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5))
1930#define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6))
1931#define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7))
1932
1933#define IWLAGN_BT_ALL_VALID_MSK (IWLAGN_BT_VALID_ENABLE_FLAGS | \
1934 IWLAGN_BT_VALID_BOOST | \
1935 IWLAGN_BT_VALID_MAX_KILL | \
1936 IWLAGN_BT_VALID_3W_TIMERS | \
1937 IWLAGN_BT_VALID_KILL_ACK_MASK | \
1938 IWLAGN_BT_VALID_KILL_CTS_MASK | \
1939 IWLAGN_BT_VALID_REDUCED_TX_PWR | \
1940 IWLAGN_BT_VALID_3W_LUT)
1941
1942#define IWLAGN_BT_REDUCED_TX_PWR BIT(0)
1943
1944#define IWLAGN_BT_DECISION_LUT_SIZE 12
1945
1946struct iwl_basic_bt_cmd {
1947 u8 flags;
1948 u8 ledtime;
1949 u8 max_kill;
1950 u8 bt3_timer_t7_value;
1951 __le32 kill_ack_mask;
1952 __le32 kill_cts_mask;
1953 u8 bt3_prio_sample_time;
1954 u8 bt3_timer_t2_value;
1955 __le16 bt4_reaction_time;
1956 __le32 bt3_lookup_table[IWLAGN_BT_DECISION_LUT_SIZE];
1957
1958
1959
1960
1961 u8 reduce_txpower;
1962 u8 reserved;
1963 __le16 valid;
1964};
1965
1966struct iwl_bt_cmd_v1 {
1967 struct iwl_basic_bt_cmd basic;
1968 u8 prio_boost;
1969
1970
1971
1972
1973 u8 tx_prio_boost;
1974 __le16 rx_prio_boost;
1975};
1976
1977struct iwl_bt_cmd_v2 {
1978 struct iwl_basic_bt_cmd basic;
1979 __le32 prio_boost;
1980
1981
1982
1983
1984 u8 reserved;
1985 u8 tx_prio_boost;
1986 __le16 rx_prio_boost;
1987};
1988
1989#define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0))
1990
1991struct iwlagn_bt_sco_cmd {
1992 __le32 flags;
1993};
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004#define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
2005 RXON_FILTER_CTL2HOST_MSK | \
2006 RXON_FILTER_ACCEPT_GRP_MSK | \
2007 RXON_FILTER_DIS_DECRYPT_MSK | \
2008 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
2009 RXON_FILTER_ASSOC_MSK | \
2010 RXON_FILTER_BCON_AWARE_MSK)
2011
2012struct iwl_measure_channel {
2013 __le32 duration;
2014
2015 u8 channel;
2016 u8 type;
2017 __le16 reserved;
2018} __packed;
2019
2020
2021
2022
2023struct iwl_spectrum_cmd {
2024 __le16 len;
2025 u8 token;
2026 u8 id;
2027 u8 origin;
2028 u8 periodic;
2029 __le16 path_loss_timeout;
2030 __le32 start_time;
2031 __le32 reserved2;
2032 __le32 flags;
2033 __le32 filter_flags;
2034 __le16 channel_count;
2035 __le16 reserved3;
2036 struct iwl_measure_channel channels[10];
2037} __packed;
2038
2039
2040
2041
2042struct iwl_spectrum_resp {
2043 u8 token;
2044 u8 id;
2045 __le16 status;
2046
2047
2048} __packed;
2049
2050enum iwl_measurement_state {
2051 IWL_MEASUREMENT_START = 0,
2052 IWL_MEASUREMENT_STOP = 1,
2053};
2054
2055enum iwl_measurement_status {
2056 IWL_MEASUREMENT_OK = 0,
2057 IWL_MEASUREMENT_CONCURRENT = 1,
2058 IWL_MEASUREMENT_CSA_CONFLICT = 2,
2059 IWL_MEASUREMENT_TGH_CONFLICT = 3,
2060
2061 IWL_MEASUREMENT_STOPPED = 6,
2062 IWL_MEASUREMENT_TIMEOUT = 7,
2063 IWL_MEASUREMENT_PERIODIC_FAILED = 8,
2064};
2065
2066#define NUM_ELEMENTS_IN_HISTOGRAM 8
2067
2068struct iwl_measurement_histogram {
2069 __le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM];
2070 __le32 cck[NUM_ELEMENTS_IN_HISTOGRAM];
2071} __packed;
2072
2073
2074struct iwl_measurement_cca_counters {
2075 __le32 ofdm;
2076 __le32 cck;
2077} __packed;
2078
2079enum iwl_measure_type {
2080 IWL_MEASURE_BASIC = (1 << 0),
2081 IWL_MEASURE_CHANNEL_LOAD = (1 << 1),
2082 IWL_MEASURE_HISTOGRAM_RPI = (1 << 2),
2083 IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
2084 IWL_MEASURE_FRAME = (1 << 4),
2085
2086 IWL_MEASURE_IDLE = (1 << 7),
2087};
2088
2089
2090
2091
2092struct iwl_spectrum_notification {
2093 u8 id;
2094 u8 token;
2095 u8 channel_index;
2096 u8 state;
2097 __le32 start_time;
2098 u8 band;
2099 u8 channel;
2100 u8 type;
2101 u8 reserved1;
2102
2103
2104 __le32 cca_ofdm;
2105 __le32 cca_cck;
2106 __le32 cca_time;
2107 u8 basic_type;
2108
2109 u8 reserved2[3];
2110 struct iwl_measurement_histogram histogram;
2111 __le32 stop_time;
2112 __le32 status;
2113} __packed;
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155
2156#define IWL_POWER_VEC_SIZE 5
2157
2158#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2159#define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2160#define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2161#define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2162#define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2163#define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2164#define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2165#define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2166#define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2167#define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
2168#define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
2169
2170struct iwl_powertable_cmd {
2171 __le16 flags;
2172 u8 keep_alive_seconds;
2173 u8 debug_flags;
2174 __le32 rx_data_timeout;
2175 __le32 tx_data_timeout;
2176 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
2177 __le32 keep_alive_beacons;
2178} __packed;
2179
2180
2181
2182
2183
2184struct iwl_sleep_notification {
2185 u8 pm_sleep_mode;
2186 u8 pm_wakeup_src;
2187 __le16 reserved;
2188 __le32 sleep_time;
2189 __le32 tsf_low;
2190 __le32 bcon_timer;
2191} __packed;
2192
2193
2194enum {
2195 IWL_PM_NO_SLEEP = 0,
2196 IWL_PM_SLP_MAC = 1,
2197 IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
2198 IWL_PM_SLP_FULL_MAC_CARD_STATE = 3,
2199 IWL_PM_SLP_PHY = 4,
2200 IWL_PM_SLP_REPENT = 5,
2201 IWL_PM_WAKEUP_BY_TIMER = 6,
2202 IWL_PM_WAKEUP_BY_DRIVER = 7,
2203 IWL_PM_WAKEUP_BY_RFKILL = 8,
2204
2205 IWL_PM_NUM_OF_MODES = 12,
2206};
2207
2208
2209
2210
2211#define CARD_STATE_CMD_DISABLE 0x00
2212#define CARD_STATE_CMD_ENABLE 0x01
2213#define CARD_STATE_CMD_HALT 0x02
2214struct iwl_card_state_cmd {
2215 __le32 status;
2216} __packed;
2217
2218
2219
2220
2221struct iwl_card_state_notif {
2222 __le32 flags;
2223} __packed;
2224
2225#define HW_CARD_DISABLED 0x01
2226#define SW_CARD_DISABLED 0x02
2227#define CT_CARD_DISABLED 0x04
2228#define RXON_CARD_DISABLED 0x10
2229
2230struct iwl_ct_kill_config {
2231 __le32 reserved;
2232 __le32 critical_temperature_M;
2233 __le32 critical_temperature_R;
2234} __packed;
2235
2236
2237struct iwl_ct_kill_throttling_config {
2238 __le32 critical_temperature_exit;
2239 __le32 reserved;
2240 __le32 critical_temperature_enter;
2241} __packed;
2242
2243
2244
2245
2246
2247
2248
2249#define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2250#define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2251
2252
2253
2254
2255
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270
2271
2272struct iwl_scan_channel {
2273
2274
2275
2276
2277
2278
2279
2280 __le32 type;
2281 __le16 channel;
2282 u8 tx_gain;
2283 u8 dsp_atten;
2284 __le16 active_dwell;
2285 __le16 passive_dwell;
2286} __packed;
2287
2288
2289#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299struct iwl_ssid_ie {
2300 u8 id;
2301 u8 len;
2302 u8 ssid[32];
2303} __packed;
2304
2305#define PROBE_OPTION_MAX 20
2306#define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2307#define IWL_GOOD_CRC_TH_DISABLED 0
2308#define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2309#define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2310#define IWL_MAX_CMD_SIZE 4096
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363
2364
2365enum iwl_scan_flags {
2366
2367 IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1),
2368
2369};
2370
2371struct iwl_scan_cmd {
2372 __le16 len;
2373 u8 scan_flags;
2374 u8 channel_count;
2375 __le16 quiet_time;
2376
2377 __le16 quiet_plcp_th;
2378 __le16 good_CRC_th;
2379 __le16 rx_chain;
2380 __le32 max_out_time;
2381
2382 __le32 suspend_time;
2383
2384
2385 __le32 flags;
2386 __le32 filter_flags;
2387
2388
2389
2390 struct iwl_tx_cmd tx_cmd;
2391
2392
2393 struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410 u8 data[0];
2411} __packed;
2412
2413
2414#define CAN_ABORT_STATUS cpu_to_le32(0x1)
2415
2416#define ABORT_STATUS 0x2
2417
2418
2419
2420
2421struct iwl_scanreq_notification {
2422 __le32 status;
2423} __packed;
2424
2425
2426
2427
2428struct iwl_scanstart_notification {
2429 __le32 tsf_low;
2430 __le32 tsf_high;
2431 __le32 beacon_timer;
2432 u8 channel;
2433 u8 band;
2434 u8 reserved[2];
2435 __le32 status;
2436} __packed;
2437
2438#define SCAN_OWNER_STATUS 0x1
2439#define MEASURE_OWNER_STATUS 0x2
2440
2441#define IWL_PROBE_STATUS_OK 0
2442#define IWL_PROBE_STATUS_TX_FAILED BIT(0)
2443
2444#define IWL_PROBE_STATUS_FAIL_TTL BIT(1)
2445#define IWL_PROBE_STATUS_FAIL_BT BIT(2)
2446
2447#define NUMBER_OF_STATISTICS 1
2448
2449
2450
2451struct iwl_scanresults_notification {
2452 u8 channel;
2453 u8 band;
2454 u8 probe_status;
2455 u8 num_probe_not_sent;
2456 __le32 tsf_low;
2457 __le32 tsf_high;
2458 __le32 statistics[NUMBER_OF_STATISTICS];
2459} __packed;
2460
2461
2462
2463
2464struct iwl_scancomplete_notification {
2465 u8 scanned_channels;
2466 u8 status;
2467 u8 bt_status;
2468 u8 last_channel;
2469 __le32 tsf_low;
2470 __le32 tsf_high;
2471} __packed;
2472
2473
2474
2475
2476
2477
2478
2479
2480enum iwl_ibss_manager {
2481 IWL_NOT_IBSS_MANAGER = 0,
2482 IWL_IBSS_MANAGER = 1,
2483};
2484
2485
2486
2487
2488
2489struct iwlagn_beacon_notif {
2490 struct iwlagn_tx_resp beacon_notify_hdr;
2491 __le32 low_tsf;
2492 __le32 high_tsf;
2493 __le32 ibss_mgr_status;
2494} __packed;
2495
2496
2497
2498
2499
2500struct iwl_tx_beacon_cmd {
2501 struct iwl_tx_cmd tx;
2502 __le16 tim_idx;
2503 u8 tim_size;
2504 u8 reserved1;
2505 struct ieee80211_hdr frame[0];
2506} __packed;
2507
2508
2509
2510
2511
2512
2513
2514#define IWL_TEMP_CONVERT 260
2515
2516#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
2517#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
2518#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
2519
2520
2521struct rate_histogram {
2522 union {
2523 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2524 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2525 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2526 } success;
2527 union {
2528 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2529 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2530 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2531 } failed;
2532} __packed;
2533
2534
2535
2536struct statistics_dbg {
2537 __le32 burst_check;
2538 __le32 burst_count;
2539 __le32 wait_for_silence_timeout_cnt;
2540 __le32 reserved[3];
2541} __packed;
2542
2543struct statistics_rx_phy {
2544 __le32 ina_cnt;
2545 __le32 fina_cnt;
2546 __le32 plcp_err;
2547 __le32 crc32_err;
2548 __le32 overrun_err;
2549 __le32 early_overrun_err;
2550 __le32 crc32_good;
2551 __le32 false_alarm_cnt;
2552 __le32 fina_sync_err_cnt;
2553 __le32 sfd_timeout;
2554 __le32 fina_timeout;
2555 __le32 unresponded_rts;
2556 __le32 rxe_frame_limit_overrun;
2557 __le32 sent_ack_cnt;
2558 __le32 sent_cts_cnt;
2559 __le32 sent_ba_rsp_cnt;
2560 __le32 dsp_self_kill;
2561 __le32 mh_format_err;
2562 __le32 re_acq_main_rssi_sum;
2563 __le32 reserved3;
2564} __packed;
2565
2566struct statistics_rx_ht_phy {
2567 __le32 plcp_err;
2568 __le32 overrun_err;
2569 __le32 early_overrun_err;
2570 __le32 crc32_good;
2571 __le32 crc32_err;
2572 __le32 mh_format_err;
2573 __le32 agg_crc32_good;
2574 __le32 agg_mpdu_cnt;
2575 __le32 agg_cnt;
2576 __le32 unsupport_mcs;
2577} __packed;
2578
2579#define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2580
2581struct statistics_rx_non_phy {
2582 __le32 bogus_cts;
2583 __le32 bogus_ack;
2584 __le32 non_bssid_frames;
2585
2586 __le32 filtered_frames;
2587
2588 __le32 non_channel_beacons;
2589
2590 __le32 channel_beacons;
2591
2592 __le32 num_missed_bcon;
2593 __le32 adc_rx_saturation_time;
2594
2595 __le32 ina_detection_search_time;
2596
2597 __le32 beacon_silence_rssi_a;
2598 __le32 beacon_silence_rssi_b;
2599 __le32 beacon_silence_rssi_c;
2600 __le32 interference_data_flag;
2601
2602
2603 __le32 channel_load;
2604 __le32 dsp_false_alarms;
2605
2606 __le32 beacon_rssi_a;
2607 __le32 beacon_rssi_b;
2608 __le32 beacon_rssi_c;
2609 __le32 beacon_energy_a;
2610 __le32 beacon_energy_b;
2611 __le32 beacon_energy_c;
2612} __packed;
2613
2614struct statistics_rx_non_phy_bt {
2615 struct statistics_rx_non_phy common;
2616
2617 __le32 num_bt_kills;
2618 __le32 reserved[2];
2619} __packed;
2620
2621struct statistics_rx {
2622 struct statistics_rx_phy ofdm;
2623 struct statistics_rx_phy cck;
2624 struct statistics_rx_non_phy general;
2625 struct statistics_rx_ht_phy ofdm_ht;
2626} __packed;
2627
2628struct statistics_rx_bt {
2629 struct statistics_rx_phy ofdm;
2630 struct statistics_rx_phy cck;
2631 struct statistics_rx_non_phy_bt general;
2632 struct statistics_rx_ht_phy ofdm_ht;
2633} __packed;
2634
2635
2636
2637
2638
2639
2640
2641
2642struct statistics_tx_power {
2643 u8 ant_a;
2644 u8 ant_b;
2645 u8 ant_c;
2646 u8 reserved;
2647} __packed;
2648
2649struct statistics_tx_non_phy_agg {
2650 __le32 ba_timeout;
2651 __le32 ba_reschedule_frames;
2652 __le32 scd_query_agg_frame_cnt;
2653 __le32 scd_query_no_agg;
2654 __le32 scd_query_agg;
2655 __le32 scd_query_mismatch;
2656 __le32 frame_not_ready;
2657 __le32 underrun;
2658 __le32 bt_prio_kill;
2659 __le32 rx_ba_rsp_cnt;
2660} __packed;
2661
2662struct statistics_tx {
2663 __le32 preamble_cnt;
2664 __le32 rx_detected_cnt;
2665 __le32 bt_prio_defer_cnt;
2666 __le32 bt_prio_kill_cnt;
2667 __le32 few_bytes_cnt;
2668 __le32 cts_timeout;
2669 __le32 ack_timeout;
2670 __le32 expected_ack_cnt;
2671 __le32 actual_ack_cnt;
2672 __le32 dump_msdu_cnt;
2673 __le32 burst_abort_next_frame_mismatch_cnt;
2674 __le32 burst_abort_missing_next_frame_cnt;
2675 __le32 cts_timeout_collision;
2676 __le32 ack_or_ba_timeout_collision;
2677 struct statistics_tx_non_phy_agg agg;
2678
2679
2680
2681
2682
2683 struct statistics_tx_power tx_power;
2684 __le32 reserved1;
2685} __packed;
2686
2687
2688struct statistics_div {
2689 __le32 tx_on_a;
2690 __le32 tx_on_b;
2691 __le32 exec_time;
2692 __le32 probe_time;
2693 __le32 reserved1;
2694 __le32 reserved2;
2695} __packed;
2696
2697struct statistics_general_common {
2698 __le32 temperature;
2699 __le32 temperature_m;
2700 struct statistics_dbg dbg;
2701 __le32 sleep_time;
2702 __le32 slots_out;
2703 __le32 slots_idle;
2704 __le32 ttl_timestamp;
2705 struct statistics_div div;
2706 __le32 rx_enable_counter;
2707
2708
2709
2710
2711
2712 __le32 num_of_sos_states;
2713} __packed;
2714
2715struct statistics_bt_activity {
2716
2717 __le32 hi_priority_tx_req_cnt;
2718 __le32 hi_priority_tx_denied_cnt;
2719 __le32 lo_priority_tx_req_cnt;
2720 __le32 lo_priority_tx_denied_cnt;
2721
2722 __le32 hi_priority_rx_req_cnt;
2723 __le32 hi_priority_rx_denied_cnt;
2724 __le32 lo_priority_rx_req_cnt;
2725 __le32 lo_priority_rx_denied_cnt;
2726} __packed;
2727
2728struct statistics_general {
2729 struct statistics_general_common common;
2730 __le32 reserved2;
2731 __le32 reserved3;
2732} __packed;
2733
2734struct statistics_general_bt {
2735 struct statistics_general_common common;
2736 struct statistics_bt_activity activity;
2737 __le32 reserved2;
2738 __le32 reserved3;
2739} __packed;
2740
2741#define UCODE_STATISTICS_CLEAR_MSK (0x1 << 0)
2742#define UCODE_STATISTICS_FREQUENCY_MSK (0x1 << 1)
2743#define UCODE_STATISTICS_NARROW_BAND_MSK (0x1 << 2)
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760#define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)
2761#define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)
2762struct iwl_statistics_cmd {
2763 __le32 configuration_flags;
2764} __packed;
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781#define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2782#define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
2783
2784struct iwl_notif_statistics {
2785 __le32 flag;
2786 struct statistics_rx rx;
2787 struct statistics_tx tx;
2788 struct statistics_general general;
2789} __packed;
2790
2791struct iwl_bt_notif_statistics {
2792 __le32 flag;
2793 struct statistics_rx_bt rx;
2794 struct statistics_tx tx;
2795 struct statistics_general_bt general;
2796} __packed;
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818#define IWL_MISSED_BEACON_THRESHOLD_MIN (1)
2819#define IWL_MISSED_BEACON_THRESHOLD_DEF (5)
2820#define IWL_MISSED_BEACON_THRESHOLD_MAX IWL_MISSED_BEACON_THRESHOLD_DEF
2821
2822struct iwl_missed_beacon_notif {
2823 __le32 consecutive_missed_beacons;
2824 __le32 total_missed_becons;
2825 __le32 num_expected_beacons;
2826 __le32 num_recvd_beacons;
2827} __packed;
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002#define HD_TABLE_SIZE (11)
3003#define HD_MIN_ENERGY_CCK_DET_INDEX (0)
3004#define HD_MIN_ENERGY_OFDM_DET_INDEX (1)
3005#define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2)
3006#define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3)
3007#define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4)
3008#define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5)
3009#define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6)
3010#define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7)
3011#define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8)
3012#define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9)
3013#define HD_OFDM_ENERGY_TH_IN_INDEX (10)
3014
3015
3016
3017
3018#define HD_INA_NON_SQUARE_DET_OFDM_INDEX (11)
3019#define HD_INA_NON_SQUARE_DET_CCK_INDEX (12)
3020#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX (13)
3021#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX (14)
3022#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (15)
3023#define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX (16)
3024#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX (17)
3025#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX (18)
3026#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (19)
3027#define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX (20)
3028#define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX (21)
3029#define HD_RESERVED (22)
3030
3031
3032#define ENHANCE_HD_TABLE_SIZE (23)
3033
3034
3035#define ENHANCE_HD_TABLE_ENTRIES (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE)
3036
3037#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0)
3038#define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0)
3039#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0)
3040#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668)
3041#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3042#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486)
3043#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37)
3044#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853)
3045#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3046#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476)
3047#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99)
3048
3049#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1)
3050#define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1)
3051#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1)
3052#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600)
3053#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40)
3054#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486)
3055#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45)
3056#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853)
3057#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60)
3058#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476)
3059#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99)
3060
3061
3062
3063#define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0)
3064#define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1)
3065
3066
3067
3068
3069
3070
3071
3072
3073struct iwl_sensitivity_cmd {
3074 __le16 control;
3075 __le16 table[HD_TABLE_SIZE];
3076} __packed;
3077
3078
3079
3080
3081struct iwl_enhance_sensitivity_cmd {
3082 __le16 control;
3083 __le16 enhance_table[ENHANCE_HD_TABLE_SIZE];
3084} __packed;
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143enum {
3144 IWL_PHY_CALIBRATE_DC_CMD = 8,
3145 IWL_PHY_CALIBRATE_LO_CMD = 9,
3146 IWL_PHY_CALIBRATE_TX_IQ_CMD = 11,
3147 IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15,
3148 IWL_PHY_CALIBRATE_BASE_BAND_CMD = 16,
3149 IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD = 17,
3150 IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD = 18,
3151};
3152
3153
3154
3155
3156enum iwl_ucode_calib_cfg {
3157 IWL_CALIB_CFG_RX_BB_IDX = BIT(0),
3158 IWL_CALIB_CFG_DC_IDX = BIT(1),
3159 IWL_CALIB_CFG_LO_IDX = BIT(2),
3160 IWL_CALIB_CFG_TX_IQ_IDX = BIT(3),
3161 IWL_CALIB_CFG_RX_IQ_IDX = BIT(4),
3162 IWL_CALIB_CFG_NOISE_IDX = BIT(5),
3163 IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6),
3164 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7),
3165 IWL_CALIB_CFG_PAPD_IDX = BIT(8),
3166 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9),
3167 IWL_CALIB_CFG_TX_PWR_IDX = BIT(10),
3168};
3169
3170#define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3171 IWL_CALIB_CFG_DC_IDX | \
3172 IWL_CALIB_CFG_LO_IDX | \
3173 IWL_CALIB_CFG_TX_IQ_IDX | \
3174 IWL_CALIB_CFG_RX_IQ_IDX | \
3175 IWL_CALIB_CFG_CRYSTAL_IDX)
3176
3177#define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3178 IWL_CALIB_CFG_DC_IDX | \
3179 IWL_CALIB_CFG_LO_IDX | \
3180 IWL_CALIB_CFG_TX_IQ_IDX | \
3181 IWL_CALIB_CFG_RX_IQ_IDX | \
3182 IWL_CALIB_CFG_TEMPERATURE_IDX | \
3183 IWL_CALIB_CFG_PAPD_IDX | \
3184 IWL_CALIB_CFG_TX_PWR_IDX | \
3185 IWL_CALIB_CFG_CRYSTAL_IDX)
3186
3187#define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))
3188
3189struct iwl_calib_cfg_elmnt_s {
3190 __le32 is_enable;
3191 __le32 start;
3192 __le32 send_res;
3193 __le32 apply_res;
3194 __le32 reserved;
3195} __packed;
3196
3197struct iwl_calib_cfg_status_s {
3198 struct iwl_calib_cfg_elmnt_s once;
3199 struct iwl_calib_cfg_elmnt_s perd;
3200 __le32 flags;
3201} __packed;
3202
3203struct iwl_calib_cfg_cmd {
3204 struct iwl_calib_cfg_status_s ucd_calib_cfg;
3205 struct iwl_calib_cfg_status_s drv_calib_cfg;
3206 __le32 reserved1;
3207} __packed;
3208
3209struct iwl_calib_hdr {
3210 u8 op_code;
3211 u8 first_group;
3212 u8 groups_num;
3213 u8 data_valid;
3214} __packed;
3215
3216struct iwl_calib_cmd {
3217 struct iwl_calib_hdr hdr;
3218 u8 data[0];
3219} __packed;
3220
3221struct iwl_calib_xtal_freq_cmd {
3222 struct iwl_calib_hdr hdr;
3223 u8 cap_pin1;
3224 u8 cap_pin2;
3225 u8 pad[2];
3226} __packed;
3227
3228#define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)
3229struct iwl_calib_temperature_offset_cmd {
3230 struct iwl_calib_hdr hdr;
3231 __le16 radio_sensor_offset;
3232 __le16 reserved;
3233} __packed;
3234
3235struct iwl_calib_temperature_offset_v2_cmd {
3236 struct iwl_calib_hdr hdr;
3237 __le16 radio_sensor_offset_high;
3238 __le16 radio_sensor_offset_low;
3239 __le16 burntVoltageRef;
3240 __le16 reserved;
3241} __packed;
3242
3243
3244struct iwl_calib_chain_noise_reset_cmd {
3245 struct iwl_calib_hdr hdr;
3246 u8 data[0];
3247};
3248
3249
3250struct iwl_calib_chain_noise_gain_cmd {
3251 struct iwl_calib_hdr hdr;
3252 u8 delta_gain_1;
3253 u8 delta_gain_2;
3254 u8 pad[2];
3255} __packed;
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270struct iwl_led_cmd {
3271 __le32 interval;
3272 u8 id;
3273 u8 off;
3274
3275 u8 on;
3276
3277 u8 reserved;
3278} __packed;
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291#define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1)
3292#define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2)
3293#define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4)
3294
3295#define COEX_CU_UNASSOC_IDLE_RP 4
3296#define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4
3297#define COEX_CU_UNASSOC_AUTO_SCAN_RP 4
3298#define COEX_CU_CALIBRATION_RP 4
3299#define COEX_CU_PERIODIC_CALIBRATION_RP 4
3300#define COEX_CU_CONNECTION_ESTAB_RP 4
3301#define COEX_CU_ASSOCIATED_IDLE_RP 4
3302#define COEX_CU_ASSOC_MANUAL_SCAN_RP 4
3303#define COEX_CU_ASSOC_AUTO_SCAN_RP 4
3304#define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4
3305#define COEX_CU_RF_ON_RP 6
3306#define COEX_CU_RF_OFF_RP 4
3307#define COEX_CU_STAND_ALONE_DEBUG_RP 6
3308#define COEX_CU_IPAN_ASSOC_LEVEL_RP 4
3309#define COEX_CU_RSRVD1_RP 4
3310#define COEX_CU_RSRVD2_RP 4
3311
3312#define COEX_CU_UNASSOC_IDLE_WP 3
3313#define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3
3314#define COEX_CU_UNASSOC_AUTO_SCAN_WP 3
3315#define COEX_CU_CALIBRATION_WP 3
3316#define COEX_CU_PERIODIC_CALIBRATION_WP 3
3317#define COEX_CU_CONNECTION_ESTAB_WP 3
3318#define COEX_CU_ASSOCIATED_IDLE_WP 3
3319#define COEX_CU_ASSOC_MANUAL_SCAN_WP 3
3320#define COEX_CU_ASSOC_AUTO_SCAN_WP 3
3321#define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3
3322#define COEX_CU_RF_ON_WP 3
3323#define COEX_CU_RF_OFF_WP 3
3324#define COEX_CU_STAND_ALONE_DEBUG_WP 6
3325#define COEX_CU_IPAN_ASSOC_LEVEL_WP 3
3326#define COEX_CU_RSRVD1_WP 3
3327#define COEX_CU_RSRVD2_WP 3
3328
3329#define COEX_UNASSOC_IDLE_FLAGS 0
3330#define COEX_UNASSOC_MANUAL_SCAN_FLAGS \
3331 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3332 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3333#define COEX_UNASSOC_AUTO_SCAN_FLAGS \
3334 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3335 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3336#define COEX_CALIBRATION_FLAGS \
3337 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3338 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3339#define COEX_PERIODIC_CALIBRATION_FLAGS 0
3340
3341
3342
3343
3344#define COEX_CONNECTION_ESTAB_FLAGS \
3345 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3346 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3347 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3348#define COEX_ASSOCIATED_IDLE_FLAGS 0
3349#define COEX_ASSOC_MANUAL_SCAN_FLAGS \
3350 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3351 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3352#define COEX_ASSOC_AUTO_SCAN_FLAGS \
3353 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3354 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3355#define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
3356#define COEX_RF_ON_FLAGS 0
3357#define COEX_RF_OFF_FLAGS 0
3358#define COEX_STAND_ALONE_DEBUG_FLAGS \
3359 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3360 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3361#define COEX_IPAN_ASSOC_LEVEL_FLAGS \
3362 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3363 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3364 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3365#define COEX_RSRVD1_FLAGS 0
3366#define COEX_RSRVD2_FLAGS 0
3367
3368
3369
3370
3371#define COEX_CU_RF_ON_FLAGS \
3372 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3373 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3374 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3375
3376
3377enum {
3378
3379 COEX_UNASSOC_IDLE = 0,
3380 COEX_UNASSOC_MANUAL_SCAN = 1,
3381 COEX_UNASSOC_AUTO_SCAN = 2,
3382
3383 COEX_CALIBRATION = 3,
3384 COEX_PERIODIC_CALIBRATION = 4,
3385
3386 COEX_CONNECTION_ESTAB = 5,
3387
3388 COEX_ASSOCIATED_IDLE = 6,
3389 COEX_ASSOC_MANUAL_SCAN = 7,
3390 COEX_ASSOC_AUTO_SCAN = 8,
3391 COEX_ASSOC_ACTIVE_LEVEL = 9,
3392
3393 COEX_RF_ON = 10,
3394 COEX_RF_OFF = 11,
3395 COEX_STAND_ALONE_DEBUG = 12,
3396
3397 COEX_IPAN_ASSOC_LEVEL = 13,
3398
3399 COEX_RSRVD1 = 14,
3400 COEX_RSRVD2 = 15,
3401 COEX_NUM_OF_EVENTS = 16
3402};
3403
3404
3405
3406
3407
3408
3409struct iwl_wimax_coex_event_entry {
3410 u8 request_prio;
3411 u8 win_medium_prio;
3412 u8 reserved;
3413 u8 flags;
3414} __packed;
3415
3416
3417
3418
3419#define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1)
3420
3421#define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4)
3422
3423#define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8)
3424
3425#define COEX_FLAGS_COEX_ENABLE_MSK (0x80)
3426
3427struct iwl_wimax_coex_cmd {
3428 u8 flags;
3429 u8 reserved[3];
3430 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
3431} __packed;
3432
3433
3434
3435
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445
3446
3447#define COEX_MEDIUM_BUSY (0x0)
3448#define COEX_MEDIUM_ACTIVE (0x1)
3449#define COEX_MEDIUM_PRE_RELEASE (0x2)
3450#define COEX_MEDIUM_MSK (0x7)
3451
3452
3453#define COEX_MEDIUM_CHANGED (0x8)
3454#define COEX_MEDIUM_CHANGED_MSK (0x8)
3455#define COEX_MEDIUM_SHIFT (3)
3456
3457struct iwl_coex_medium_notification {
3458 __le32 status;
3459 __le32 events;
3460} __packed;
3461
3462
3463
3464
3465
3466
3467
3468
3469#define COEX_EVENT_REQUEST_MSK (0x1)
3470
3471struct iwl_coex_event_cmd {
3472 u8 flags;
3473 u8 event;
3474 __le16 reserved;
3475} __packed;
3476
3477struct iwl_coex_event_resp {
3478 __le32 status;
3479} __packed;
3480
3481
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491enum iwl_bt_coex_profile_traffic_load {
3492 IWL_BT_COEX_TRAFFIC_LOAD_NONE = 0,
3493 IWL_BT_COEX_TRAFFIC_LOAD_LOW = 1,
3494 IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 2,
3495 IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS = 3,
3496
3497
3498
3499
3500};
3501
3502#define BT_SESSION_ACTIVITY_1_UART_MSG 0x1
3503#define BT_SESSION_ACTIVITY_2_UART_MSG 0x2
3504
3505
3506#define BT_UART_MSG_FRAME1MSGTYPE_POS (0)
3507#define BT_UART_MSG_FRAME1MSGTYPE_MSK \
3508 (0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS)
3509#define BT_UART_MSG_FRAME1SSN_POS (3)
3510#define BT_UART_MSG_FRAME1SSN_MSK \
3511 (0x3 << BT_UART_MSG_FRAME1SSN_POS)
3512#define BT_UART_MSG_FRAME1UPDATEREQ_POS (5)
3513#define BT_UART_MSG_FRAME1UPDATEREQ_MSK \
3514 (0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS)
3515#define BT_UART_MSG_FRAME1RESERVED_POS (6)
3516#define BT_UART_MSG_FRAME1RESERVED_MSK \
3517 (0x3 << BT_UART_MSG_FRAME1RESERVED_POS)
3518
3519#define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS (0)
3520#define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK \
3521 (0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS)
3522#define BT_UART_MSG_FRAME2TRAFFICLOAD_POS (2)
3523#define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK \
3524 (0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS)
3525#define BT_UART_MSG_FRAME2CHLSEQN_POS (4)
3526#define BT_UART_MSG_FRAME2CHLSEQN_MSK \
3527 (0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS)
3528#define BT_UART_MSG_FRAME2INBAND_POS (5)
3529#define BT_UART_MSG_FRAME2INBAND_MSK \
3530 (0x1 << BT_UART_MSG_FRAME2INBAND_POS)
3531#define BT_UART_MSG_FRAME2RESERVED_POS (6)
3532#define BT_UART_MSG_FRAME2RESERVED_MSK \
3533 (0x3 << BT_UART_MSG_FRAME2RESERVED_POS)
3534
3535#define BT_UART_MSG_FRAME3SCOESCO_POS (0)
3536#define BT_UART_MSG_FRAME3SCOESCO_MSK \
3537 (0x1 << BT_UART_MSG_FRAME3SCOESCO_POS)
3538#define BT_UART_MSG_FRAME3SNIFF_POS (1)
3539#define BT_UART_MSG_FRAME3SNIFF_MSK \
3540 (0x1 << BT_UART_MSG_FRAME3SNIFF_POS)
3541#define BT_UART_MSG_FRAME3A2DP_POS (2)
3542#define BT_UART_MSG_FRAME3A2DP_MSK \
3543 (0x1 << BT_UART_MSG_FRAME3A2DP_POS)
3544#define BT_UART_MSG_FRAME3ACL_POS (3)
3545#define BT_UART_MSG_FRAME3ACL_MSK \
3546 (0x1 << BT_UART_MSG_FRAME3ACL_POS)
3547#define BT_UART_MSG_FRAME3MASTER_POS (4)
3548#define BT_UART_MSG_FRAME3MASTER_MSK \
3549 (0x1 << BT_UART_MSG_FRAME3MASTER_POS)
3550#define BT_UART_MSG_FRAME3OBEX_POS (5)
3551#define BT_UART_MSG_FRAME3OBEX_MSK \
3552 (0x1 << BT_UART_MSG_FRAME3OBEX_POS)
3553#define BT_UART_MSG_FRAME3RESERVED_POS (6)
3554#define BT_UART_MSG_FRAME3RESERVED_MSK \
3555 (0x3 << BT_UART_MSG_FRAME3RESERVED_POS)
3556
3557#define BT_UART_MSG_FRAME4IDLEDURATION_POS (0)
3558#define BT_UART_MSG_FRAME4IDLEDURATION_MSK \
3559 (0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS)
3560#define BT_UART_MSG_FRAME4RESERVED_POS (6)
3561#define BT_UART_MSG_FRAME4RESERVED_MSK \
3562 (0x3 << BT_UART_MSG_FRAME4RESERVED_POS)
3563
3564#define BT_UART_MSG_FRAME5TXACTIVITY_POS (0)
3565#define BT_UART_MSG_FRAME5TXACTIVITY_MSK \
3566 (0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS)
3567#define BT_UART_MSG_FRAME5RXACTIVITY_POS (2)
3568#define BT_UART_MSG_FRAME5RXACTIVITY_MSK \
3569 (0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS)
3570#define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS (4)
3571#define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK \
3572 (0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS)
3573#define BT_UART_MSG_FRAME5RESERVED_POS (6)
3574#define BT_UART_MSG_FRAME5RESERVED_MSK \
3575 (0x3 << BT_UART_MSG_FRAME5RESERVED_POS)
3576
3577#define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS (0)
3578#define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK \
3579 (0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS)
3580#define BT_UART_MSG_FRAME6DISCOVERABLE_POS (5)
3581#define BT_UART_MSG_FRAME6DISCOVERABLE_MSK \
3582 (0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS)
3583#define BT_UART_MSG_FRAME6RESERVED_POS (6)
3584#define BT_UART_MSG_FRAME6RESERVED_MSK \
3585 (0x3 << BT_UART_MSG_FRAME6RESERVED_POS)
3586
3587#define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS (0)
3588#define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK \
3589 (0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS)
3590#define BT_UART_MSG_FRAME7PAGE_POS (3)
3591#define BT_UART_MSG_FRAME7PAGE_MSK \
3592 (0x1 << BT_UART_MSG_FRAME7PAGE_POS)
3593#define BT_UART_MSG_FRAME7INQUIRY_POS (4)
3594#define BT_UART_MSG_FRAME7INQUIRY_MSK \
3595 (0x1 << BT_UART_MSG_FRAME7INQUIRY_POS)
3596#define BT_UART_MSG_FRAME7CONNECTABLE_POS (5)
3597#define BT_UART_MSG_FRAME7CONNECTABLE_MSK \
3598 (0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS)
3599#define BT_UART_MSG_FRAME7RESERVED_POS (6)
3600#define BT_UART_MSG_FRAME7RESERVED_MSK \
3601 (0x3 << BT_UART_MSG_FRAME7RESERVED_POS)
3602
3603
3604#define BT_UART_MSG_2_FRAME1RESERVED1_POS (5)
3605#define BT_UART_MSG_2_FRAME1RESERVED1_MSK \
3606 (0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS)
3607#define BT_UART_MSG_2_FRAME1RESERVED2_POS (6)
3608#define BT_UART_MSG_2_FRAME1RESERVED2_MSK \
3609 (0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS)
3610
3611#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS (0)
3612#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK \
3613 (0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS)
3614#define BT_UART_MSG_2_FRAME2RESERVED_POS (6)
3615#define BT_UART_MSG_2_FRAME2RESERVED_MSK \
3616 (0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS)
3617
3618#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS (0)
3619#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK \
3620 (0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS)
3621#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS (4)
3622#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK \
3623 (0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS)
3624#define BT_UART_MSG_2_FRAME3LEMASTER_POS (5)
3625#define BT_UART_MSG_2_FRAME3LEMASTER_MSK \
3626 (0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS)
3627#define BT_UART_MSG_2_FRAME3RESERVED_POS (6)
3628#define BT_UART_MSG_2_FRAME3RESERVED_MSK \
3629 (0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS)
3630
3631#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS (0)
3632#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK \
3633 (0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS)
3634#define BT_UART_MSG_2_FRAME4NUMLECONN_POS (4)
3635#define BT_UART_MSG_2_FRAME4NUMLECONN_MSK \
3636 (0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS)
3637#define BT_UART_MSG_2_FRAME4RESERVED_POS (6)
3638#define BT_UART_MSG_2_FRAME4RESERVED_MSK \
3639 (0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS)
3640
3641#define BT_UART_MSG_2_FRAME5BTMINRSSI_POS (0)
3642#define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK \
3643 (0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS)
3644#define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS (4)
3645#define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK \
3646 (0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS)
3647#define BT_UART_MSG_2_FRAME5LEADVERMODE_POS (5)
3648#define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK \
3649 (0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS)
3650#define BT_UART_MSG_2_FRAME5RESERVED_POS (6)
3651#define BT_UART_MSG_2_FRAME5RESERVED_MSK \
3652 (0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS)
3653
3654#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS (0)
3655#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK \
3656 (0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS)
3657#define BT_UART_MSG_2_FRAME6RFU_POS (5)
3658#define BT_UART_MSG_2_FRAME6RFU_MSK \
3659 (0x1<<BT_UART_MSG_2_FRAME6RFU_POS)
3660#define BT_UART_MSG_2_FRAME6RESERVED_POS (6)
3661#define BT_UART_MSG_2_FRAME6RESERVED_MSK \
3662 (0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS)
3663
3664#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS (0)
3665#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK \
3666 (0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS)
3667#define BT_UART_MSG_2_FRAME7LEPROFILE1_POS (3)
3668#define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK \
3669 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS)
3670#define BT_UART_MSG_2_FRAME7LEPROFILE2_POS (4)
3671#define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK \
3672 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS)
3673#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS (5)
3674#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK \
3675 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS)
3676#define BT_UART_MSG_2_FRAME7RESERVED_POS (6)
3677#define BT_UART_MSG_2_FRAME7RESERVED_MSK \
3678 (0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS)
3679
3680
3681#define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD (-62)
3682#define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD (-65)
3683
3684struct iwl_bt_uart_msg {
3685 u8 header;
3686 u8 frame1;
3687 u8 frame2;
3688 u8 frame3;
3689 u8 frame4;
3690 u8 frame5;
3691 u8 frame6;
3692 u8 frame7;
3693} __packed;
3694
3695struct iwl_bt_coex_profile_notif {
3696 struct iwl_bt_uart_msg last_bt_uart_msg;
3697 u8 bt_status;
3698 u8 bt_traffic_load;
3699 u8 bt_ci_compliance;
3700 u8 reserved;
3701} __packed;
3702
3703#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS 0
3704#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK 0x1
3705#define IWL_BT_COEX_PRIO_TBL_PRIO_POS 1
3706#define IWL_BT_COEX_PRIO_TBL_PRIO_MASK 0x0e
3707#define IWL_BT_COEX_PRIO_TBL_RESERVED_POS 4
3708#define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK 0xf0
3709#define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT 1
3710
3711
3712
3713
3714
3715enum bt_coex_prio_table_events {
3716 BT_COEX_PRIO_TBL_EVT_INIT_CALIB1 = 0,
3717 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2 = 1,
3718 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1 = 2,
3719 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2 = 3,
3720 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1 = 4,
3721 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2 = 5,
3722 BT_COEX_PRIO_TBL_EVT_DTIM = 6,
3723 BT_COEX_PRIO_TBL_EVT_SCAN52 = 7,
3724 BT_COEX_PRIO_TBL_EVT_SCAN24 = 8,
3725 BT_COEX_PRIO_TBL_EVT_RESERVED0 = 9,
3726 BT_COEX_PRIO_TBL_EVT_RESERVED1 = 10,
3727 BT_COEX_PRIO_TBL_EVT_RESERVED2 = 11,
3728 BT_COEX_PRIO_TBL_EVT_RESERVED3 = 12,
3729 BT_COEX_PRIO_TBL_EVT_RESERVED4 = 13,
3730 BT_COEX_PRIO_TBL_EVT_RESERVED5 = 14,
3731 BT_COEX_PRIO_TBL_EVT_RESERVED6 = 15,
3732
3733 BT_COEX_PRIO_TBL_EVT_MAX,
3734};
3735
3736enum bt_coex_prio_table_priorities {
3737 BT_COEX_PRIO_TBL_DISABLED = 0,
3738 BT_COEX_PRIO_TBL_PRIO_LOW = 1,
3739 BT_COEX_PRIO_TBL_PRIO_HIGH = 2,
3740 BT_COEX_PRIO_TBL_PRIO_BYPASS = 3,
3741 BT_COEX_PRIO_TBL_PRIO_COEX_OFF = 4,
3742 BT_COEX_PRIO_TBL_PRIO_COEX_ON = 5,
3743 BT_COEX_PRIO_TBL_PRIO_RSRVD1 = 6,
3744 BT_COEX_PRIO_TBL_PRIO_RSRVD2 = 7,
3745 BT_COEX_PRIO_TBL_MAX,
3746};
3747
3748struct iwl_bt_coex_prio_table_cmd {
3749 u8 prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX];
3750} __packed;
3751
3752#define IWL_BT_COEX_ENV_CLOSE 0
3753#define IWL_BT_COEX_ENV_OPEN 1
3754
3755
3756
3757
3758struct iwl_bt_coex_prot_env_cmd {
3759 u8 action;
3760 u8 type;
3761 u8 reserved[2];
3762} __packed;
3763
3764
3765
3766
3767enum iwlagn_d3_wakeup_filters {
3768 IWLAGN_D3_WAKEUP_RFKILL = BIT(0),
3769 IWLAGN_D3_WAKEUP_SYSASSERT = BIT(1),
3770};
3771
3772struct iwlagn_d3_config_cmd {
3773 __le32 min_sleep_time;
3774 __le32 wakeup_flags;
3775} __packed;
3776
3777
3778
3779
3780#define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16
3781#define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128
3782
3783struct iwlagn_wowlan_pattern {
3784 u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8];
3785 u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN];
3786 u8 mask_size;
3787 u8 pattern_size;
3788 __le16 reserved;
3789} __packed;
3790
3791#define IWLAGN_WOWLAN_MAX_PATTERNS 20
3792
3793struct iwlagn_wowlan_patterns_cmd {
3794 __le32 n_patterns;
3795 struct iwlagn_wowlan_pattern patterns[];
3796} __packed;
3797
3798
3799
3800
3801enum iwlagn_wowlan_wakeup_filters {
3802 IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0),
3803 IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1),
3804 IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2),
3805 IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3),
3806 IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4),
3807 IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5),
3808 IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6),
3809 IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(7),
3810 IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(8),
3811};
3812
3813struct iwlagn_wowlan_wakeup_filter_cmd {
3814 __le32 enabled;
3815 __le16 non_qos_seq;
3816 __le16 reserved;
3817 __le16 qos_seq[8];
3818};
3819
3820
3821
3822
3823#define IWLAGN_NUM_RSC 16
3824
3825struct tkip_sc {
3826 __le16 iv16;
3827 __le16 pad;
3828 __le32 iv32;
3829} __packed;
3830
3831struct iwlagn_tkip_rsc_tsc {
3832 struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC];
3833 struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC];
3834 struct tkip_sc tsc;
3835} __packed;
3836
3837struct aes_sc {
3838 __le64 pn;
3839} __packed;
3840
3841struct iwlagn_aes_rsc_tsc {
3842 struct aes_sc unicast_rsc[IWLAGN_NUM_RSC];
3843 struct aes_sc multicast_rsc[IWLAGN_NUM_RSC];
3844 struct aes_sc tsc;
3845} __packed;
3846
3847union iwlagn_all_tsc_rsc {
3848 struct iwlagn_tkip_rsc_tsc tkip;
3849 struct iwlagn_aes_rsc_tsc aes;
3850};
3851
3852struct iwlagn_wowlan_rsc_tsc_params_cmd {
3853 union iwlagn_all_tsc_rsc all_tsc_rsc;
3854} __packed;
3855
3856
3857
3858
3859#define IWLAGN_MIC_KEY_SIZE 8
3860#define IWLAGN_P1K_SIZE 5
3861struct iwlagn_mic_keys {
3862 u8 tx[IWLAGN_MIC_KEY_SIZE];
3863 u8 rx_unicast[IWLAGN_MIC_KEY_SIZE];
3864 u8 rx_mcast[IWLAGN_MIC_KEY_SIZE];
3865} __packed;
3866
3867struct iwlagn_p1k_cache {
3868 __le16 p1k[IWLAGN_P1K_SIZE];
3869} __packed;
3870
3871#define IWLAGN_NUM_RX_P1K_CACHE 2
3872
3873struct iwlagn_wowlan_tkip_params_cmd {
3874 struct iwlagn_mic_keys mic_keys;
3875 struct iwlagn_p1k_cache tx;
3876 struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE];
3877 struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE];
3878} __packed;
3879
3880
3881
3882
3883
3884#define IWLAGN_KCK_MAX_SIZE 32
3885#define IWLAGN_KEK_MAX_SIZE 32
3886
3887struct iwlagn_wowlan_kek_kck_material_cmd {
3888 u8 kck[IWLAGN_KCK_MAX_SIZE];
3889 u8 kek[IWLAGN_KEK_MAX_SIZE];
3890 __le16 kck_len;
3891 __le16 kek_len;
3892 __le64 replay_ctr;
3893} __packed;
3894
3895#define RF_KILL_INDICATOR_FOR_WOWLAN 0x87
3896
3897
3898
3899
3900struct iwlagn_wowlan_status {
3901 __le64 replay_ctr;
3902 __le32 rekey_status;
3903 __le32 wakeup_reason;
3904 u8 pattern_number;
3905 u8 reserved1;
3906 __le16 qos_seq_ctr[8];
3907 __le16 non_qos_seq_ctr;
3908 __le16 reserved2;
3909 union iwlagn_all_tsc_rsc tsc_rsc;
3910 __le16 reserved3;
3911} __packed;
3912
3913
3914
3915
3916
3917
3918
3919
3920#define IWL_MIN_SLOT_TIME 20
3921
3922
3923
3924
3925
3926
3927
3928
3929struct iwl_wipan_slot {
3930 __le16 width;
3931 u8 type;
3932 u8 reserved;
3933} __packed;
3934
3935#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1)
3936#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2)
3937#define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3)
3938#define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4)
3939#define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5)
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949
3950
3951
3952
3953
3954
3955
3956struct iwl_wipan_params_cmd {
3957 __le16 flags;
3958 u8 reserved;
3959 u8 num_slots;
3960 struct iwl_wipan_slot slots[10];
3961} __packed;
3962
3963
3964
3965
3966
3967
3968
3969
3970
3971struct iwl_wipan_p2p_channel_switch_cmd {
3972 __le16 channel;
3973 __le16 reserved;
3974};
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987struct iwl_wipan_noa_descriptor {
3988 u8 count;
3989 __le32 duration;
3990 __le32 interval;
3991 __le32 starttime;
3992} __packed;
3993
3994struct iwl_wipan_noa_attribute {
3995 u8 id;
3996 __le16 length;
3997 u8 index;
3998 u8 ct_window;
3999 struct iwl_wipan_noa_descriptor descr0, descr1;
4000 u8 reserved;
4001} __packed;
4002
4003struct iwl_wipan_noa_notification {
4004 u32 noa_active;
4005 struct iwl_wipan_noa_attribute noa_attribute;
4006} __packed;
4007
4008#endif
4009