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15#ifndef __MT7601U_DMA_H
16#define __MT7601U_DMA_H
17
18#include <asm/unaligned.h>
19#include <linux/skbuff.h>
20
21#include "util.h"
22
23#define MT_DMA_HDR_LEN 4
24#define MT_RX_INFO_LEN 4
25#define MT_FCE_INFO_LEN 4
26#define MT_DMA_HDRS (MT_DMA_HDR_LEN + MT_RX_INFO_LEN)
27
28
29#define MT_TXD_INFO_LEN GENMASK(15, 0)
30#define MT_TXD_INFO_D_PORT GENMASK(29, 27)
31#define MT_TXD_INFO_TYPE GENMASK(31, 30)
32
33enum mt76_msg_port {
34 WLAN_PORT,
35 CPU_RX_PORT,
36 CPU_TX_PORT,
37 HOST_PORT,
38 VIRTUAL_CPU_RX_PORT,
39 VIRTUAL_CPU_TX_PORT,
40 DISCARD,
41};
42
43enum mt76_info_type {
44 DMA_PACKET,
45 DMA_COMMAND,
46};
47
48
49#define MT_TXD_PKT_INFO_NEXT_VLD BIT(16)
50#define MT_TXD_PKT_INFO_TX_BURST BIT(17)
51#define MT_TXD_PKT_INFO_80211 BIT(19)
52#define MT_TXD_PKT_INFO_TSO BIT(20)
53#define MT_TXD_PKT_INFO_CSO BIT(21)
54#define MT_TXD_PKT_INFO_WIV BIT(24)
55#define MT_TXD_PKT_INFO_QSEL GENMASK(26, 25)
56
57enum mt76_qsel {
58 MT_QSEL_MGMT,
59 MT_QSEL_HCCA,
60 MT_QSEL_EDCA,
61 MT_QSEL_EDCA_2,
62};
63
64
65#define MT_TXD_CMD_INFO_SEQ GENMASK(19, 16)
66#define MT_TXD_CMD_INFO_TYPE GENMASK(26, 20)
67
68static inline int mt7601u_dma_skb_wrap(struct sk_buff *skb,
69 enum mt76_msg_port d_port,
70 enum mt76_info_type type, u32 flags)
71{
72 u32 info;
73
74
75
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80
81 info = flags |
82 MT76_SET(MT_TXD_INFO_LEN, round_up(skb->len, 4)) |
83 MT76_SET(MT_TXD_INFO_D_PORT, d_port) |
84 MT76_SET(MT_TXD_INFO_TYPE, type);
85
86 put_unaligned_le32(info, skb_push(skb, sizeof(info)));
87 return skb_put_padto(skb, round_up(skb->len, 4) + 4);
88}
89
90static inline int
91mt7601u_dma_skb_wrap_pkt(struct sk_buff *skb, enum mt76_qsel qsel, u32 flags)
92{
93 flags |= MT76_SET(MT_TXD_PKT_INFO_QSEL, qsel);
94 return mt7601u_dma_skb_wrap(skb, WLAN_PORT, DMA_PACKET, flags);
95}
96
97
98#define MT_RXD_INFO_LEN GENMASK(13, 0)
99#define MT_RXD_INFO_PCIE_INTR BIT(24)
100#define MT_RXD_INFO_QSEL GENMASK(26, 25)
101#define MT_RXD_INFO_PORT GENMASK(29, 27)
102#define MT_RXD_INFO_TYPE GENMASK(31, 30)
103
104
105#define MT_RXD_PKT_INFO_UDP_ERR BIT(16)
106#define MT_RXD_PKT_INFO_TCP_ERR BIT(17)
107#define MT_RXD_PKT_INFO_IP_ERR BIT(18)
108#define MT_RXD_PKT_INFO_PKT_80211 BIT(19)
109#define MT_RXD_PKT_INFO_L3L4_DONE BIT(20)
110#define MT_RXD_PKT_INFO_MAC_LEN GENMASK(23, 21)
111
112
113#define MT_RXD_CMD_INFO_SELF_GEN BIT(15)
114#define MT_RXD_CMD_INFO_CMD_SEQ GENMASK(19, 16)
115#define MT_RXD_CMD_INFO_EVT_TYPE GENMASK(23, 20)
116
117enum mt76_evt_type {
118 CMD_DONE,
119 CMD_ERROR,
120 CMD_RETRY,
121 EVENT_PWR_RSP,
122 EVENT_WOW_RSP,
123 EVENT_CARRIER_DETECT_RSP,
124 EVENT_DFS_DETECT_RSP,
125};
126
127#endif
128