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17#include <linux/vmalloc.h>
18#include <linux/sched.h>
19#include <linux/firmware.h>
20
21#include "cw1200.h"
22#include "fwio.h"
23#include "hwio.h"
24#include "hwbus.h"
25#include "bh.h"
26
27static int cw1200_get_hw_type(u32 config_reg_val, int *major_revision)
28{
29 int hw_type = -1;
30 u32 silicon_type = (config_reg_val >> 24) & 0x7;
31 u32 silicon_vers = (config_reg_val >> 31) & 0x1;
32
33 switch (silicon_type) {
34 case 0x00:
35 *major_revision = 1;
36 hw_type = HIF_9000_SILICON_VERSATILE;
37 break;
38 case 0x01:
39 case 0x02:
40 case 0x04:
41 *major_revision = silicon_type;
42 if (silicon_vers)
43 hw_type = HIF_8601_VERSATILE;
44 else
45 hw_type = HIF_8601_SILICON;
46 break;
47 default:
48 break;
49 }
50
51 return hw_type;
52}
53
54static int cw1200_load_firmware_cw1200(struct cw1200_common *priv)
55{
56 int ret, block, num_blocks;
57 unsigned i;
58 u32 val32;
59 u32 put = 0, get = 0;
60 u8 *buf = NULL;
61 const char *fw_path;
62 const struct firmware *firmware = NULL;
63
64
65#define APB_WRITE(reg, val) \
66 do { \
67 ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
68 if (ret < 0) \
69 goto exit; \
70 } while (0)
71#define APB_WRITE2(reg, val) \
72 do { \
73 ret = cw1200_apb_write_32(priv, CW1200_APB(reg), (val)); \
74 if (ret < 0) \
75 goto free_buffer; \
76 } while (0)
77#define APB_READ(reg, val) \
78 do { \
79 ret = cw1200_apb_read_32(priv, CW1200_APB(reg), &(val)); \
80 if (ret < 0) \
81 goto free_buffer; \
82 } while (0)
83#define REG_WRITE(reg, val) \
84 do { \
85 ret = cw1200_reg_write_32(priv, (reg), (val)); \
86 if (ret < 0) \
87 goto exit; \
88 } while (0)
89#define REG_READ(reg, val) \
90 do { \
91 ret = cw1200_reg_read_32(priv, (reg), &(val)); \
92 if (ret < 0) \
93 goto exit; \
94 } while (0)
95
96 switch (priv->hw_revision) {
97 case CW1200_HW_REV_CUT10:
98 fw_path = FIRMWARE_CUT10;
99 if (!priv->sdd_path)
100 priv->sdd_path = SDD_FILE_10;
101 break;
102 case CW1200_HW_REV_CUT11:
103 fw_path = FIRMWARE_CUT11;
104 if (!priv->sdd_path)
105 priv->sdd_path = SDD_FILE_11;
106 break;
107 case CW1200_HW_REV_CUT20:
108 fw_path = FIRMWARE_CUT20;
109 if (!priv->sdd_path)
110 priv->sdd_path = SDD_FILE_20;
111 break;
112 case CW1200_HW_REV_CUT22:
113 fw_path = FIRMWARE_CUT22;
114 if (!priv->sdd_path)
115 priv->sdd_path = SDD_FILE_22;
116 break;
117 case CW1X60_HW_REV:
118 fw_path = FIRMWARE_CW1X60;
119 if (!priv->sdd_path)
120 priv->sdd_path = SDD_FILE_CW1X60;
121 break;
122 default:
123 pr_err("Invalid silicon revision %d.\n", priv->hw_revision);
124 return -EINVAL;
125 }
126
127
128 APB_WRITE(DOWNLOAD_IMAGE_SIZE_REG, DOWNLOAD_ARE_YOU_HERE);
129 APB_WRITE(DOWNLOAD_PUT_REG, 0);
130 APB_WRITE(DOWNLOAD_GET_REG, 0);
131 APB_WRITE(DOWNLOAD_STATUS_REG, DOWNLOAD_PENDING);
132 APB_WRITE(DOWNLOAD_FLAGS_REG, 0);
133
134
135 REG_WRITE(ST90TDS_SRAM_BASE_ADDR_REG_ID, 0xFFF20000);
136 REG_WRITE(ST90TDS_AHB_DPORT_REG_ID, 0xEAFFFFFE);
137
138
139 REG_READ(ST90TDS_CONFIG_REG_ID, val32);
140 val32 &= ~ST90TDS_CONFIG_CPU_RESET_BIT;
141 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
142
143
144 val32 &= ~ST90TDS_CONFIG_CPU_CLK_DIS_BIT;
145 REG_WRITE(ST90TDS_CONFIG_REG_ID, val32);
146
147
148 ret = request_firmware(&firmware, fw_path, priv->pdev);
149 if (ret) {
150 pr_err("Can't load firmware file %s.\n", fw_path);
151 goto exit;
152 }
153
154 buf = kmalloc(DOWNLOAD_BLOCK_SIZE, GFP_KERNEL | GFP_DMA);
155 if (!buf) {
156 pr_err("Can't allocate firmware load buffer.\n");
157 ret = -ENOMEM;
158 goto firmware_release;
159 }
160
161
162 for (i = 0; i < 100; i += 1 + i / 2) {
163 APB_READ(DOWNLOAD_IMAGE_SIZE_REG, val32);
164 if (val32 == DOWNLOAD_I_AM_HERE)
165 break;
166 mdelay(i);
167 }
168
169 if (val32 != DOWNLOAD_I_AM_HERE) {
170 pr_err("Bootloader is not ready.\n");
171 ret = -ETIMEDOUT;
172 goto free_buffer;
173 }
174
175
176 num_blocks = (firmware->size - 1) / DOWNLOAD_BLOCK_SIZE + 1;
177
178
179 val32 = firmware->size;
180 APB_WRITE2(DOWNLOAD_IMAGE_SIZE_REG, val32);
181
182
183 for (block = 0; block < num_blocks; block++) {
184 size_t tx_size;
185 size_t block_size;
186
187
188 APB_READ(DOWNLOAD_STATUS_REG, val32);
189 if (val32 != DOWNLOAD_PENDING) {
190 pr_err("Bootloader reported error %d.\n", val32);
191 ret = -EIO;
192 goto free_buffer;
193 }
194
195
196 for (i = 0; i < 100; i++) {
197 APB_READ(DOWNLOAD_GET_REG, get);
198 if ((put - get) <=
199 (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE))
200 break;
201 mdelay(i);
202 }
203
204 if ((put - get) > (DOWNLOAD_FIFO_SIZE - DOWNLOAD_BLOCK_SIZE)) {
205 pr_err("Timeout waiting for FIFO.\n");
206 ret = -ETIMEDOUT;
207 goto free_buffer;
208 }
209
210
211 tx_size = block_size = min_t(size_t, firmware->size - put,
212 DOWNLOAD_BLOCK_SIZE);
213
214 memcpy(buf, &firmware->data[put], block_size);
215 if (block_size < DOWNLOAD_BLOCK_SIZE) {
216 memset(&buf[block_size], 0,
217 DOWNLOAD_BLOCK_SIZE - block_size);
218 tx_size = DOWNLOAD_BLOCK_SIZE;
219 }
220
221
222 ret = cw1200_apb_write(priv,
223 CW1200_APB(DOWNLOAD_FIFO_OFFSET +
224 (put & (DOWNLOAD_FIFO_SIZE - 1))),
225 buf, tx_size);
226 if (ret < 0) {
227 pr_err("Can't write firmware block @ %d!\n",
228 put & (DOWNLOAD_FIFO_SIZE - 1));
229 goto free_buffer;
230 }
231
232
233 put += block_size;
234 APB_WRITE2(DOWNLOAD_PUT_REG, put);
235 }
236
237
238 for (i = 0; i < 300; i += 1 + i / 2) {
239 APB_READ(DOWNLOAD_STATUS_REG, val32);
240 if (val32 != DOWNLOAD_PENDING)
241 break;
242 mdelay(i);
243 }
244 if (val32 != DOWNLOAD_SUCCESS) {
245 pr_err("Wait for download completion failed: 0x%.8X\n", val32);
246 ret = -ETIMEDOUT;
247 goto free_buffer;
248 } else {
249 pr_info("Firmware download completed.\n");
250 ret = 0;
251 }
252
253free_buffer:
254 kfree(buf);
255firmware_release:
256 release_firmware(firmware);
257exit:
258 return ret;
259
260#undef APB_WRITE
261#undef APB_WRITE2
262#undef APB_READ
263#undef REG_WRITE
264#undef REG_READ
265}
266
267
268static int config_reg_read(struct cw1200_common *priv, u32 *val)
269{
270 switch (priv->hw_type) {
271 case HIF_9000_SILICON_VERSATILE: {
272 u16 val16;
273 int ret = cw1200_reg_read_16(priv,
274 ST90TDS_CONFIG_REG_ID,
275 &val16);
276 if (ret < 0)
277 return ret;
278 *val = val16;
279 return 0;
280 }
281 case HIF_8601_VERSATILE:
282 case HIF_8601_SILICON:
283 default:
284 cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, val);
285 break;
286 }
287 return 0;
288}
289
290static int config_reg_write(struct cw1200_common *priv, u32 val)
291{
292 switch (priv->hw_type) {
293 case HIF_9000_SILICON_VERSATILE:
294 return cw1200_reg_write_16(priv,
295 ST90TDS_CONFIG_REG_ID,
296 (u16)val);
297 case HIF_8601_VERSATILE:
298 case HIF_8601_SILICON:
299 default:
300 return cw1200_reg_write_32(priv, ST90TDS_CONFIG_REG_ID, val);
301 }
302 return 0;
303}
304
305int cw1200_load_firmware(struct cw1200_common *priv)
306{
307 int ret;
308 int i;
309 u32 val32;
310 u16 val16;
311 int major_revision = -1;
312
313
314 ret = cw1200_reg_read_32(priv, ST90TDS_CONFIG_REG_ID, &val32);
315 if (ret < 0) {
316 pr_err("Can't read config register.\n");
317 goto out;
318 }
319
320 if (val32 == 0 || val32 == 0xffffffff) {
321 pr_err("Bad config register value (0x%08x)\n", val32);
322 ret = -EIO;
323 goto out;
324 }
325
326 priv->hw_type = cw1200_get_hw_type(val32, &major_revision);
327 if (priv->hw_type < 0) {
328 pr_err("Can't deduce hardware type.\n");
329 ret = -ENOTSUPP;
330 goto out;
331 }
332
333
334 ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
335 cw1200_dpll_from_clk(priv->hw_refclk));
336 if (ret < 0) {
337 pr_err("Can't write DPLL register.\n");
338 goto out;
339 }
340
341 msleep(20);
342
343 ret = cw1200_reg_read_32(priv,
344 ST90TDS_TSET_GEN_R_W_REG_ID, &val32);
345 if (ret < 0) {
346 pr_err("Can't read DPLL register.\n");
347 goto out;
348 }
349
350 if (val32 != cw1200_dpll_from_clk(priv->hw_refclk)) {
351 pr_err("Unable to initialise DPLL register. Wrote 0x%.8X, Read 0x%.8X.\n",
352 cw1200_dpll_from_clk(priv->hw_refclk), val32);
353 ret = -EIO;
354 goto out;
355 }
356
357
358 ret = cw1200_reg_read_16(priv, ST90TDS_CONTROL_REG_ID, &val16);
359 if (ret < 0) {
360 pr_err("set_wakeup: can't read control register.\n");
361 goto out;
362 }
363
364 ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
365 val16 | ST90TDS_CONT_WUP_BIT);
366 if (ret < 0) {
367 pr_err("set_wakeup: can't write control register.\n");
368 goto out;
369 }
370
371
372 for (i = 0; i < 300; i += (1 + i / 2)) {
373 ret = cw1200_reg_read_16(priv,
374 ST90TDS_CONTROL_REG_ID, &val16);
375 if (ret < 0) {
376 pr_err("wait_for_wakeup: can't read control register.\n");
377 goto out;
378 }
379
380 if (val16 & ST90TDS_CONT_RDY_BIT)
381 break;
382
383 msleep(i);
384 }
385
386 if ((val16 & ST90TDS_CONT_RDY_BIT) == 0) {
387 pr_err("wait_for_wakeup: device is not responding.\n");
388 ret = -ETIMEDOUT;
389 goto out;
390 }
391
392 switch (major_revision) {
393 case 1:
394
395 ret = cw1200_ahb_read_32(priv, CW1200_CUT_ID_ADDR, &val32);
396 if (ret) {
397 pr_err("HW detection: can't read CUT ID.\n");
398 goto out;
399 }
400
401 switch (val32) {
402 case CW1200_CUT_11_ID_STR:
403 pr_info("CW1x00 Cut 1.1 silicon detected.\n");
404 priv->hw_revision = CW1200_HW_REV_CUT11;
405 break;
406 default:
407 pr_info("CW1x00 Cut 1.0 silicon detected.\n");
408 priv->hw_revision = CW1200_HW_REV_CUT10;
409 break;
410 }
411
412
413
414
415 priv->ba_rx_tid_mask = 0;
416 priv->ba_tx_tid_mask = 0;
417 break;
418 case 2: {
419 u32 ar1, ar2, ar3;
420 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR, &ar1);
421 if (ret) {
422 pr_err("(1) HW detection: can't read CUT ID\n");
423 goto out;
424 }
425 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 4, &ar2);
426 if (ret) {
427 pr_err("(2) HW detection: can't read CUT ID.\n");
428 goto out;
429 }
430
431 ret = cw1200_ahb_read_32(priv, CW1200_CUT2_ID_ADDR + 8, &ar3);
432 if (ret) {
433 pr_err("(3) HW detection: can't read CUT ID.\n");
434 goto out;
435 }
436
437 if (ar1 == CW1200_CUT_22_ID_STR1 &&
438 ar2 == CW1200_CUT_22_ID_STR2 &&
439 ar3 == CW1200_CUT_22_ID_STR3) {
440 pr_info("CW1x00 Cut 2.2 silicon detected.\n");
441 priv->hw_revision = CW1200_HW_REV_CUT22;
442 } else {
443 pr_info("CW1x00 Cut 2.0 silicon detected.\n");
444 priv->hw_revision = CW1200_HW_REV_CUT20;
445 }
446 break;
447 }
448 case 4:
449 pr_info("CW1x60 silicon detected.\n");
450 priv->hw_revision = CW1X60_HW_REV;
451 break;
452 default:
453 pr_err("Unsupported silicon major revision %d.\n",
454 major_revision);
455 ret = -ENOTSUPP;
456 goto out;
457 }
458
459
460 ret = config_reg_read(priv, &val32);
461 if (ret < 0) {
462 pr_err("Can't read config register.\n");
463 goto out;
464 }
465
466 if (!(val32 & ST90TDS_CONFIG_ACCESS_MODE_BIT)) {
467 pr_err("Device is already in QUEUE mode!\n");
468 ret = -EINVAL;
469 goto out;
470 }
471
472 switch (priv->hw_type) {
473 case HIF_8601_SILICON:
474 if (priv->hw_revision == CW1X60_HW_REV) {
475 pr_err("Can't handle CW1160/1260 firmware load yet.\n");
476 ret = -ENOTSUPP;
477 goto out;
478 }
479 ret = cw1200_load_firmware_cw1200(priv);
480 break;
481 default:
482 pr_err("Can't perform firmware load for hw type %d.\n",
483 priv->hw_type);
484 ret = -ENOTSUPP;
485 goto out;
486 }
487 if (ret < 0) {
488 pr_err("Firmware load error.\n");
489 goto out;
490 }
491
492
493 priv->hwbus_ops->lock(priv->hwbus_priv);
494 ret = __cw1200_irq_enable(priv, 1);
495 priv->hwbus_ops->unlock(priv->hwbus_priv);
496 if (ret < 0)
497 goto unsubscribe;
498
499
500 ret = config_reg_read(priv, &val32);
501 if (ret < 0) {
502 pr_err("Can't read config register.\n");
503 goto unsubscribe;
504 }
505 ret = config_reg_write(priv, val32 & ~ST90TDS_CONFIG_ACCESS_MODE_BIT);
506 if (ret < 0) {
507 pr_err("Can't write config register.\n");
508 goto unsubscribe;
509 }
510
511
512
513
514 mdelay(10);
515 config_reg_read(priv, &val32);
516
517out:
518 return ret;
519
520unsubscribe:
521
522 priv->hwbus_ops->lock(priv->hwbus_priv);
523 ret = __cw1200_irq_enable(priv, 0);
524 priv->hwbus_ops->unlock(priv->hwbus_priv);
525 return ret;
526}
527
