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22#include <linux/types.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/slab.h>
26#include <linux/init.h>
27
28#include <linux/mm.h>
29#include <linux/string.h>
30#include <linux/pci.h>
31#include <linux/scatterlist.h>
32#include <linux/iommu-helper.h>
33
34#include <asm/byteorder.h>
35#include <asm/io.h>
36#include <asm/dma.h>
37
38#include <asm/hardware.h>
39
40#include <linux/proc_fs.h>
41#include <linux/seq_file.h>
42#include <linux/module.h>
43
44#include <asm/ropes.h>
45#include <asm/mckinley.h>
46#include <asm/runway.h>
47#include <asm/page.h>
48#include <asm/pdc.h>
49#include <asm/pdcpat.h>
50#include <asm/parisc-device.h>
51
52#define MODULE_NAME "SBA"
53
54
55
56
57
58
59#undef DEBUG_SBA_INIT
60#undef DEBUG_SBA_RUN
61#undef DEBUG_SBA_RUN_SG
62#undef DEBUG_SBA_RESOURCE
63#undef ASSERT_PDIR_SANITY
64#undef DEBUG_LARGE_SG_ENTRIES
65#undef DEBUG_DMB_TRAP
66
67#ifdef DEBUG_SBA_INIT
68#define DBG_INIT(x...) printk(x)
69#else
70#define DBG_INIT(x...)
71#endif
72
73#ifdef DEBUG_SBA_RUN
74#define DBG_RUN(x...) printk(x)
75#else
76#define DBG_RUN(x...)
77#endif
78
79#ifdef DEBUG_SBA_RUN_SG
80#define DBG_RUN_SG(x...) printk(x)
81#else
82#define DBG_RUN_SG(x...)
83#endif
84
85
86#ifdef DEBUG_SBA_RESOURCE
87#define DBG_RES(x...) printk(x)
88#else
89#define DBG_RES(x...)
90#endif
91
92#define SBA_INLINE __inline__
93
94#define DEFAULT_DMA_HINT_REG 0
95
96struct sba_device *sba_list;
97EXPORT_SYMBOL_GPL(sba_list);
98
99static unsigned long ioc_needs_fdc = 0;
100
101
102static unsigned int global_ioc_cnt = 0;
103
104
105static unsigned long piranha_bad_128k = 0;
106
107
108#define SBA_DEV(d) ((struct sba_device *) (d))
109
110#ifdef CONFIG_AGP_PARISC
111#define SBA_AGP_SUPPORT
112#endif
113
114#ifdef SBA_AGP_SUPPORT
115static int sba_reserve_agpgart = 1;
116module_param(sba_reserve_agpgart, int, 0444);
117MODULE_PARM_DESC(sba_reserve_agpgart, "Reserve half of IO pdir as AGPGART");
118#endif
119
120
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123
124
125
126
127
128
129#define READ_REG32(addr) readl(addr)
130#define READ_REG64(addr) readq(addr)
131#define WRITE_REG32(val, addr) writel((val), (addr))
132#define WRITE_REG64(val, addr) writeq((val), (addr))
133
134#ifdef CONFIG_64BIT
135#define READ_REG(addr) READ_REG64(addr)
136#define WRITE_REG(value, addr) WRITE_REG64(value, addr)
137#else
138#define READ_REG(addr) READ_REG32(addr)
139#define WRITE_REG(value, addr) WRITE_REG32(value, addr)
140#endif
141
142#ifdef DEBUG_SBA_INIT
143
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151
152
153static void
154sba_dump_ranges(void __iomem *hpa)
155{
156 DBG_INIT("SBA at 0x%p\n", hpa);
157 DBG_INIT("IOS_DIST_BASE : %Lx\n", READ_REG64(hpa+IOS_DIST_BASE));
158 DBG_INIT("IOS_DIST_MASK : %Lx\n", READ_REG64(hpa+IOS_DIST_MASK));
159 DBG_INIT("IOS_DIST_ROUTE : %Lx\n", READ_REG64(hpa+IOS_DIST_ROUTE));
160 DBG_INIT("\n");
161 DBG_INIT("IOS_DIRECT_BASE : %Lx\n", READ_REG64(hpa+IOS_DIRECT_BASE));
162 DBG_INIT("IOS_DIRECT_MASK : %Lx\n", READ_REG64(hpa+IOS_DIRECT_MASK));
163 DBG_INIT("IOS_DIRECT_ROUTE: %Lx\n", READ_REG64(hpa+IOS_DIRECT_ROUTE));
164}
165
166
167
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169
170
171
172static void sba_dump_tlb(void __iomem *hpa)
173{
174 DBG_INIT("IO TLB at 0x%p\n", hpa);
175 DBG_INIT("IOC_IBASE : 0x%Lx\n", READ_REG64(hpa+IOC_IBASE));
176 DBG_INIT("IOC_IMASK : 0x%Lx\n", READ_REG64(hpa+IOC_IMASK));
177 DBG_INIT("IOC_TCNFG : 0x%Lx\n", READ_REG64(hpa+IOC_TCNFG));
178 DBG_INIT("IOC_PDIR_BASE: 0x%Lx\n", READ_REG64(hpa+IOC_PDIR_BASE));
179 DBG_INIT("\n");
180}
181#else
182#define sba_dump_ranges(x)
183#define sba_dump_tlb(x)
184#endif
185
186
187#ifdef ASSERT_PDIR_SANITY
188
189
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194
195
196
197static void
198sba_dump_pdir_entry(struct ioc *ioc, char *msg, uint pide)
199{
200
201 u64 *ptr = &(ioc->pdir_base[pide & (~0U * BITS_PER_LONG)]);
202 unsigned long *rptr = (unsigned long *) &(ioc->res_map[(pide >>3) & ~(sizeof(unsigned long) - 1)]);
203 uint rcnt;
204
205 printk(KERN_DEBUG "SBA: %s rp %p bit %d rval 0x%lx\n",
206 msg,
207 rptr, pide & (BITS_PER_LONG - 1), *rptr);
208
209 rcnt = 0;
210 while (rcnt < BITS_PER_LONG) {
211 printk(KERN_DEBUG "%s %2d %p %016Lx\n",
212 (rcnt == (pide & (BITS_PER_LONG - 1)))
213 ? " -->" : " ",
214 rcnt, ptr, *ptr );
215 rcnt++;
216 ptr++;
217 }
218 printk(KERN_DEBUG "%s", msg);
219}
220
221
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226
227
228
229static int
230sba_check_pdir(struct ioc *ioc, char *msg)
231{
232 u32 *rptr_end = (u32 *) &(ioc->res_map[ioc->res_size]);
233 u32 *rptr = (u32 *) ioc->res_map;
234 u64 *pptr = ioc->pdir_base;
235 uint pide = 0;
236
237 while (rptr < rptr_end) {
238 u32 rval = *rptr;
239 int rcnt = 32;
240
241 while (rcnt) {
242
243 u32 pde = ((u32) (((char *)pptr)[7])) << 24;
244 if ((rval ^ pde) & 0x80000000)
245 {
246
247
248
249
250 sba_dump_pdir_entry(ioc, msg, pide);
251 return(1);
252 }
253 rcnt--;
254 rval <<= 1;
255 pptr++;
256 pide++;
257 }
258 rptr++;
259 }
260
261 return 0;
262}
263
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271
272
273static void
274sba_dump_sg( struct ioc *ioc, struct scatterlist *startsg, int nents)
275{
276 while (nents-- > 0) {
277 printk(KERN_DEBUG " %d : %08lx/%05x %p/%05x\n",
278 nents,
279 (unsigned long) sg_dma_address(startsg),
280 sg_dma_len(startsg),
281 sg_virt(startsg), startsg->length);
282 startsg++;
283 }
284}
285
286#endif
287
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298
299
300#define PAGES_PER_RANGE 1
301
302
303
304#ifdef ZX1_SUPPORT
305
306#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((ioc->ibase) | (iovp) | (offset))
307#define SBA_IOVP(ioc,iova) ((iova) & (ioc)->iovp_mask)
308#else
309
310#define SBA_IOVA(ioc,iovp,offset,hint_reg) ((iovp) | (offset))
311#define SBA_IOVP(ioc,iova) (iova)
312#endif
313
314#define PDIR_INDEX(iovp) ((iovp)>>IOVP_SHIFT)
315
316#define RESMAP_MASK(n) (~0UL << (BITS_PER_LONG - (n)))
317#define RESMAP_IDX_MASK (sizeof(unsigned long) - 1)
318
319static unsigned long ptr_to_pide(struct ioc *ioc, unsigned long *res_ptr,
320 unsigned int bitshiftcnt)
321{
322 return (((unsigned long)res_ptr - (unsigned long)ioc->res_map) << 3)
323 + bitshiftcnt;
324}
325
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332
333
334
335static SBA_INLINE unsigned long
336sba_search_bitmap(struct ioc *ioc, struct device *dev,
337 unsigned long bits_wanted)
338{
339 unsigned long *res_ptr = ioc->res_hint;
340 unsigned long *res_end = (unsigned long *) &(ioc->res_map[ioc->res_size]);
341 unsigned long pide = ~0UL, tpide;
342 unsigned long boundary_size;
343 unsigned long shift;
344 int ret;
345
346 boundary_size = ALIGN((unsigned long long)dma_get_seg_boundary(dev) + 1,
347 1ULL << IOVP_SHIFT) >> IOVP_SHIFT;
348
349#if defined(ZX1_SUPPORT)
350 BUG_ON(ioc->ibase & ~IOVP_MASK);
351 shift = ioc->ibase >> IOVP_SHIFT;
352#else
353 shift = 0;
354#endif
355
356 if (bits_wanted > (BITS_PER_LONG/2)) {
357
358 for(; res_ptr < res_end; ++res_ptr) {
359 tpide = ptr_to_pide(ioc, res_ptr, 0);
360 ret = iommu_is_span_boundary(tpide, bits_wanted,
361 shift,
362 boundary_size);
363 if ((*res_ptr == 0) && !ret) {
364 *res_ptr = RESMAP_MASK(bits_wanted);
365 pide = tpide;
366 break;
367 }
368 }
369
370 res_ptr++;
371 ioc->res_bitshift = 0;
372 } else {
373
374
375
376
377
378
379 unsigned long o = 1 << get_order(bits_wanted << PAGE_SHIFT);
380 uint bitshiftcnt = ALIGN(ioc->res_bitshift, o);
381 unsigned long mask;
382
383 if (bitshiftcnt >= BITS_PER_LONG) {
384 bitshiftcnt = 0;
385 res_ptr++;
386 }
387 mask = RESMAP_MASK(bits_wanted) >> bitshiftcnt;
388
389 DBG_RES("%s() o %ld %p", __func__, o, res_ptr);
390 while(res_ptr < res_end)
391 {
392 DBG_RES(" %p %lx %lx\n", res_ptr, mask, *res_ptr);
393 WARN_ON(mask == 0);
394 tpide = ptr_to_pide(ioc, res_ptr, bitshiftcnt);
395 ret = iommu_is_span_boundary(tpide, bits_wanted,
396 shift,
397 boundary_size);
398 if ((((*res_ptr) & mask) == 0) && !ret) {
399 *res_ptr |= mask;
400 pide = tpide;
401 break;
402 }
403 mask >>= o;
404 bitshiftcnt += o;
405 if (mask == 0) {
406 mask = RESMAP_MASK(bits_wanted);
407 bitshiftcnt=0;
408 res_ptr++;
409 }
410 }
411
412 ioc->res_bitshift = bitshiftcnt + bits_wanted;
413 }
414
415
416 if (res_end <= res_ptr) {
417 ioc->res_hint = (unsigned long *) ioc->res_map;
418 ioc->res_bitshift = 0;
419 } else {
420 ioc->res_hint = res_ptr;
421 }
422 return (pide);
423}
424
425
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429
430
431
432
433
434static int
435sba_alloc_range(struct ioc *ioc, struct device *dev, size_t size)
436{
437 unsigned int pages_needed = size >> IOVP_SHIFT;
438#ifdef SBA_COLLECT_STATS
439 unsigned long cr_start = mfctl(16);
440#endif
441 unsigned long pide;
442
443 pide = sba_search_bitmap(ioc, dev, pages_needed);
444 if (pide >= (ioc->res_size << 3)) {
445 pide = sba_search_bitmap(ioc, dev, pages_needed);
446 if (pide >= (ioc->res_size << 3))
447 panic("%s: I/O MMU @ %p is out of mapping resources\n",
448 __FILE__, ioc->ioc_hpa);
449 }
450
451#ifdef ASSERT_PDIR_SANITY
452
453 if(0x00 != ((u8 *) ioc->pdir_base)[pide*sizeof(u64) + 7]) {
454 sba_dump_pdir_entry(ioc, "sba_search_bitmap() botched it?", pide);
455 }
456#endif
457
458 DBG_RES("%s(%x) %d -> %lx hint %x/%x\n",
459 __func__, size, pages_needed, pide,
460 (uint) ((unsigned long) ioc->res_hint - (unsigned long) ioc->res_map),
461 ioc->res_bitshift );
462
463#ifdef SBA_COLLECT_STATS
464 {
465 unsigned long cr_end = mfctl(16);
466 unsigned long tmp = cr_end - cr_start;
467
468 cr_start = (cr_end < cr_start) ? -(tmp) : (tmp);
469 }
470 ioc->avg_search[ioc->avg_idx++] = cr_start;
471 ioc->avg_idx &= SBA_SEARCH_SAMPLE - 1;
472
473 ioc->used_pages += pages_needed;
474#endif
475
476 return (pide);
477}
478
479
480
481
482
483
484
485
486
487
488static SBA_INLINE void
489sba_free_range(struct ioc *ioc, dma_addr_t iova, size_t size)
490{
491 unsigned long iovp = SBA_IOVP(ioc, iova);
492 unsigned int pide = PDIR_INDEX(iovp);
493 unsigned int ridx = pide >> 3;
494 unsigned long *res_ptr = (unsigned long *) &((ioc)->res_map[ridx & ~RESMAP_IDX_MASK]);
495
496 int bits_not_wanted = size >> IOVP_SHIFT;
497
498
499 unsigned long m = RESMAP_MASK(bits_not_wanted) >> (pide & (BITS_PER_LONG - 1));
500
501 DBG_RES("%s( ,%x,%x) %x/%lx %x %p %lx\n",
502 __func__, (uint) iova, size,
503 bits_not_wanted, m, pide, res_ptr, *res_ptr);
504
505#ifdef SBA_COLLECT_STATS
506 ioc->used_pages -= bits_not_wanted;
507#endif
508
509 *res_ptr &= ~m;
510}
511
512
513
514
515
516
517
518
519#ifdef SBA_HINT_SUPPORT
520#define SBA_DMA_HINT(ioc, val) ((val) << (ioc)->hint_shift_pdir)
521#endif
522
523typedef unsigned long space_t;
524#define KERNEL_SPACE 0
525
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566static void SBA_INLINE
567sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
568 unsigned long hint)
569{
570 u64 pa;
571 register unsigned ci;
572
573 pa = virt_to_phys(vba);
574 pa &= IOVP_MASK;
575
576 mtsp(sid,1);
577 asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
578 pa |= (ci >> PAGE_SHIFT) & 0xff;
579
580 pa |= SBA_PDIR_VALID_BIT;
581 *pdir_ptr = cpu_to_le64(pa);
582
583
584
585
586
587
588 if (ioc_needs_fdc)
589 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
590}
591
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608
609static SBA_INLINE void
610sba_mark_invalid(struct ioc *ioc, dma_addr_t iova, size_t byte_cnt)
611{
612 u32 iovp = (u32) SBA_IOVP(ioc,iova);
613 u64 *pdir_ptr = &ioc->pdir_base[PDIR_INDEX(iovp)];
614
615#ifdef ASSERT_PDIR_SANITY
616
617
618
619
620
621
622 if (0x80 != (((u8 *) pdir_ptr)[7])) {
623 sba_dump_pdir_entry(ioc,"sba_mark_invalid()", PDIR_INDEX(iovp));
624 }
625#endif
626
627 if (byte_cnt > IOVP_SIZE)
628 {
629#if 0
630 unsigned long entries_per_cacheline = ioc_needs_fdc ?
631 L1_CACHE_ALIGN(((unsigned long) pdir_ptr))
632 - (unsigned long) pdir_ptr;
633 : 262144;
634#endif
635
636
637 iovp |= get_order(byte_cnt) + PAGE_SHIFT;
638
639 do {
640
641 ((u8 *) pdir_ptr)[7] = 0;
642 if (ioc_needs_fdc) {
643 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
644#if 0
645 entries_per_cacheline = L1_CACHE_SHIFT - 3;
646#endif
647 }
648 pdir_ptr++;
649 byte_cnt -= IOVP_SIZE;
650 } while (byte_cnt > IOVP_SIZE);
651 } else
652 iovp |= IOVP_SHIFT;
653
654
655
656
657
658
659
660
661 ((u8 *) pdir_ptr)[7] = 0;
662 if (ioc_needs_fdc)
663 asm volatile("fdc %%r0(%0)" : : "r" (pdir_ptr));
664
665 WRITE_REG( SBA_IOVA(ioc, iovp, 0, 0), ioc->ioc_hpa+IOC_PCOM);
666}
667
668
669
670
671
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673
674
675static int sba_dma_supported( struct device *dev, u64 mask)
676{
677 struct ioc *ioc;
678
679 if (dev == NULL) {
680 printk(KERN_ERR MODULE_NAME ": EISA/ISA/et al not supported\n");
681 BUG();
682 return(0);
683 }
684
685
686
687
688
689
690 if (mask > ~0U)
691 return 0;
692
693 ioc = GET_IOC(dev);
694
695
696
697
698
699 return((int)(mask >= (ioc->ibase - 1 +
700 (ioc->pdir_size / sizeof(u64) * IOVP_SIZE) )));
701}
702
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711
712
713static dma_addr_t
714sba_map_single(struct device *dev, void *addr, size_t size,
715 enum dma_data_direction direction)
716{
717 struct ioc *ioc;
718 unsigned long flags;
719 dma_addr_t iovp;
720 dma_addr_t offset;
721 u64 *pdir_start;
722 int pide;
723
724 ioc = GET_IOC(dev);
725
726
727 offset = ((dma_addr_t) (long) addr) & ~IOVP_MASK;
728
729
730 size = (size + offset + ~IOVP_MASK) & IOVP_MASK;
731
732 spin_lock_irqsave(&ioc->res_lock, flags);
733#ifdef ASSERT_PDIR_SANITY
734 sba_check_pdir(ioc,"Check before sba_map_single()");
735#endif
736
737#ifdef SBA_COLLECT_STATS
738 ioc->msingle_calls++;
739 ioc->msingle_pages += size >> IOVP_SHIFT;
740#endif
741 pide = sba_alloc_range(ioc, dev, size);
742 iovp = (dma_addr_t) pide << IOVP_SHIFT;
743
744 DBG_RUN("%s() 0x%p -> 0x%lx\n",
745 __func__, addr, (long) iovp | offset);
746
747 pdir_start = &(ioc->pdir_base[pide]);
748
749 while (size > 0) {
750 sba_io_pdir_entry(pdir_start, KERNEL_SPACE, (unsigned long) addr, 0);
751
752 DBG_RUN(" pdir 0x%p %02x%02x%02x%02x%02x%02x%02x%02x\n",
753 pdir_start,
754 (u8) (((u8 *) pdir_start)[7]),
755 (u8) (((u8 *) pdir_start)[6]),
756 (u8) (((u8 *) pdir_start)[5]),
757 (u8) (((u8 *) pdir_start)[4]),
758 (u8) (((u8 *) pdir_start)[3]),
759 (u8) (((u8 *) pdir_start)[2]),
760 (u8) (((u8 *) pdir_start)[1]),
761 (u8) (((u8 *) pdir_start)[0])
762 );
763
764 addr += IOVP_SIZE;
765 size -= IOVP_SIZE;
766 pdir_start++;
767 }
768
769
770 if (ioc_needs_fdc)
771 asm volatile("sync" : : );
772
773#ifdef ASSERT_PDIR_SANITY
774 sba_check_pdir(ioc,"Check after sba_map_single()");
775#endif
776 spin_unlock_irqrestore(&ioc->res_lock, flags);
777
778
779 return SBA_IOVA(ioc, iovp, offset, DEFAULT_DMA_HINT_REG);
780}
781
782
783static dma_addr_t
784sba_map_page(struct device *dev, struct page *page, unsigned long offset,
785 size_t size, enum dma_data_direction direction,
786 struct dma_attrs *attrs)
787{
788 return sba_map_single(dev, page_address(page) + offset, size,
789 direction);
790}
791
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799
800
801
802static void
803sba_unmap_page(struct device *dev, dma_addr_t iova, size_t size,
804 enum dma_data_direction direction, struct dma_attrs *attrs)
805{
806 struct ioc *ioc;
807#if DELAYED_RESOURCE_CNT > 0
808 struct sba_dma_pair *d;
809#endif
810 unsigned long flags;
811 dma_addr_t offset;
812
813 DBG_RUN("%s() iovp 0x%lx/%x\n", __func__, (long) iova, size);
814
815 ioc = GET_IOC(dev);
816 offset = iova & ~IOVP_MASK;
817 iova ^= offset;
818 size += offset;
819 size = ALIGN(size, IOVP_SIZE);
820
821 spin_lock_irqsave(&ioc->res_lock, flags);
822
823#ifdef SBA_COLLECT_STATS
824 ioc->usingle_calls++;
825 ioc->usingle_pages += size >> IOVP_SHIFT;
826#endif
827
828 sba_mark_invalid(ioc, iova, size);
829
830#if DELAYED_RESOURCE_CNT > 0
831
832
833
834 d = &(ioc->saved[ioc->saved_cnt]);
835 d->iova = iova;
836 d->size = size;
837 if (++(ioc->saved_cnt) >= DELAYED_RESOURCE_CNT) {
838 int cnt = ioc->saved_cnt;
839 while (cnt--) {
840 sba_free_range(ioc, d->iova, d->size);
841 d--;
842 }
843 ioc->saved_cnt = 0;
844
845 READ_REG(ioc->ioc_hpa+IOC_PCOM);
846 }
847#else
848 sba_free_range(ioc, iova, size);
849
850
851 if (ioc_needs_fdc)
852 asm volatile("sync" : : );
853
854 READ_REG(ioc->ioc_hpa+IOC_PCOM);
855#endif
856
857 spin_unlock_irqrestore(&ioc->res_lock, flags);
858
859
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861
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865
866
867}
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877
878static void *sba_alloc(struct device *hwdev, size_t size, dma_addr_t *dma_handle,
879 gfp_t gfp, struct dma_attrs *attrs)
880{
881 void *ret;
882
883 if (!hwdev) {
884
885 *dma_handle = 0;
886 return NULL;
887 }
888
889 ret = (void *) __get_free_pages(gfp, get_order(size));
890
891 if (ret) {
892 memset(ret, 0, size);
893 *dma_handle = sba_map_single(hwdev, ret, size, 0);
894 }
895
896 return ret;
897}
898
899
900
901
902
903
904
905
906
907
908
909static void
910sba_free(struct device *hwdev, size_t size, void *vaddr,
911 dma_addr_t dma_handle, struct dma_attrs *attrs)
912{
913 sba_unmap_page(hwdev, dma_handle, size, 0, NULL);
914 free_pages((unsigned long) vaddr, get_order(size));
915}
916
917
918
919
920
921
922
923#define PIDE_FLAG 0x80000000UL
924
925#ifdef SBA_COLLECT_STATS
926#define IOMMU_MAP_STATS
927#endif
928#include "iommu-helpers.h"
929
930#ifdef DEBUG_LARGE_SG_ENTRIES
931int dump_run_sg = 0;
932#endif
933
934
935
936
937
938
939
940
941
942
943
944static int
945sba_map_sg(struct device *dev, struct scatterlist *sglist, int nents,
946 enum dma_data_direction direction, struct dma_attrs *attrs)
947{
948 struct ioc *ioc;
949 int coalesced, filled = 0;
950 unsigned long flags;
951
952 DBG_RUN_SG("%s() START %d entries\n", __func__, nents);
953
954 ioc = GET_IOC(dev);
955
956
957 if (nents == 1) {
958 sg_dma_address(sglist) = sba_map_single(dev, sg_virt(sglist),
959 sglist->length, direction);
960 sg_dma_len(sglist) = sglist->length;
961 return 1;
962 }
963
964 spin_lock_irqsave(&ioc->res_lock, flags);
965
966#ifdef ASSERT_PDIR_SANITY
967 if (sba_check_pdir(ioc,"Check before sba_map_sg()"))
968 {
969 sba_dump_sg(ioc, sglist, nents);
970 panic("Check before sba_map_sg()");
971 }
972#endif
973
974#ifdef SBA_COLLECT_STATS
975 ioc->msg_calls++;
976#endif
977
978
979
980
981
982
983
984
985
986 coalesced = iommu_coalesce_chunks(ioc, dev, sglist, nents, sba_alloc_range);
987
988
989
990
991
992
993
994
995
996 filled = iommu_fill_pdir(ioc, sglist, nents, 0, sba_io_pdir_entry);
997
998
999 if (ioc_needs_fdc)
1000 asm volatile("sync" : : );
1001
1002#ifdef ASSERT_PDIR_SANITY
1003 if (sba_check_pdir(ioc,"Check after sba_map_sg()"))
1004 {
1005 sba_dump_sg(ioc, sglist, nents);
1006 panic("Check after sba_map_sg()\n");
1007 }
1008#endif
1009
1010 spin_unlock_irqrestore(&ioc->res_lock, flags);
1011
1012 DBG_RUN_SG("%s() DONE %d mappings\n", __func__, filled);
1013
1014 return filled;
1015}
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027static void
1028sba_unmap_sg(struct device *dev, struct scatterlist *sglist, int nents,
1029 enum dma_data_direction direction, struct dma_attrs *attrs)
1030{
1031 struct ioc *ioc;
1032#ifdef ASSERT_PDIR_SANITY
1033 unsigned long flags;
1034#endif
1035
1036 DBG_RUN_SG("%s() START %d entries, %p,%x\n",
1037 __func__, nents, sg_virt(sglist), sglist->length);
1038
1039 ioc = GET_IOC(dev);
1040
1041#ifdef SBA_COLLECT_STATS
1042 ioc->usg_calls++;
1043#endif
1044
1045#ifdef ASSERT_PDIR_SANITY
1046 spin_lock_irqsave(&ioc->res_lock, flags);
1047 sba_check_pdir(ioc,"Check before sba_unmap_sg()");
1048 spin_unlock_irqrestore(&ioc->res_lock, flags);
1049#endif
1050
1051 while (sg_dma_len(sglist) && nents--) {
1052
1053 sba_unmap_page(dev, sg_dma_address(sglist), sg_dma_len(sglist),
1054 direction, NULL);
1055#ifdef SBA_COLLECT_STATS
1056 ioc->usg_pages += ((sg_dma_address(sglist) & ~IOVP_MASK) + sg_dma_len(sglist) + IOVP_SIZE - 1) >> PAGE_SHIFT;
1057 ioc->usingle_calls--;
1058#endif
1059 ++sglist;
1060 }
1061
1062 DBG_RUN_SG("%s() DONE (nents %d)\n", __func__, nents);
1063
1064#ifdef ASSERT_PDIR_SANITY
1065 spin_lock_irqsave(&ioc->res_lock, flags);
1066 sba_check_pdir(ioc,"Check after sba_unmap_sg()");
1067 spin_unlock_irqrestore(&ioc->res_lock, flags);
1068#endif
1069
1070}
1071
1072static struct dma_map_ops sba_ops = {
1073 .dma_supported = sba_dma_supported,
1074 .alloc = sba_alloc,
1075 .free = sba_free,
1076 .map_page = sba_map_page,
1077 .unmap_page = sba_unmap_page,
1078 .map_sg = sba_map_sg,
1079 .unmap_sg = sba_unmap_sg,
1080};
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092static void
1093sba_get_pat_resources(struct sba_device *sba_dev)
1094{
1095#if 0
1096
1097
1098
1099
1100
1101
1102PAT_MOD(mod)->mod_info.mod_pages = PAT_GET_MOD_PAGES(temp);
1103 FIXME : ???
1104PAT_MOD(mod)->mod_info.dvi = PAT_GET_DVI(temp);
1105 Tells where the dvi bits are located in the address.
1106PAT_MOD(mod)->mod_info.ioc = PAT_GET_IOC(temp);
1107 FIXME : ???
1108#endif
1109}
1110
1111
1112
1113
1114
1115
1116
1117#define PIRANHA_ADDR_MASK 0x00160000UL
1118#define PIRANHA_ADDR_VAL 0x00060000UL
1119static void *
1120sba_alloc_pdir(unsigned int pdir_size)
1121{
1122 unsigned long pdir_base;
1123 unsigned long pdir_order = get_order(pdir_size);
1124
1125 pdir_base = __get_free_pages(GFP_KERNEL, pdir_order);
1126 if (NULL == (void *) pdir_base) {
1127 panic("%s() could not allocate I/O Page Table\n",
1128 __func__);
1129 }
1130
1131
1132
1133
1134
1135
1136
1137 if ( ((boot_cpu_data.pdc.cpuid >> 5) & 0x7f) != 0x13
1138 || (boot_cpu_data.pdc.versions > 0x202)
1139 || (boot_cpu_data.pdc.capabilities & 0x08L) )
1140 return (void *) pdir_base;
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160 if (pdir_order <= (19-12)) {
1161 if (((virt_to_phys(pdir_base)+pdir_size-1) & PIRANHA_ADDR_MASK) == PIRANHA_ADDR_VAL) {
1162
1163 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, (19-12));
1164
1165 free_pages(pdir_base, pdir_order);
1166
1167 pdir_base = new_pdir;
1168
1169
1170 while (pdir_order < (19-12)) {
1171 new_pdir += pdir_size;
1172 free_pages(new_pdir, pdir_order);
1173 pdir_order +=1;
1174 pdir_size <<=1;
1175 }
1176 }
1177 } else {
1178
1179
1180
1181
1182 unsigned long new_pdir = __get_free_pages(GFP_KERNEL, pdir_order+1);
1183
1184
1185 free_pages( pdir_base, pdir_order);
1186
1187
1188 free_pages(new_pdir, 20-12);
1189
1190 pdir_base = new_pdir + 1024*1024;
1191
1192 if (pdir_order > (20-12)) {
1193
1194
1195
1196
1197
1198
1199 piranha_bad_128k = 1;
1200
1201 new_pdir += 3*1024*1024;
1202
1203 free_pages(new_pdir, 20-12);
1204
1205
1206 free_pages(new_pdir - 128*1024 , 17-12);
1207
1208 pdir_size -= 128*1024;
1209 }
1210 }
1211
1212 memset((void *) pdir_base, 0, pdir_size);
1213 return (void *) pdir_base;
1214}
1215
1216struct ibase_data_struct {
1217 struct ioc *ioc;
1218 int ioc_num;
1219};
1220
1221static int setup_ibase_imask_callback(struct device *dev, void *data)
1222{
1223
1224 extern void lba_set_iregs(struct parisc_device *, u32, u32);
1225 struct parisc_device *lba = to_parisc_device(dev);
1226 struct ibase_data_struct *ibd = data;
1227 int rope_num = (lba->hpa.start >> 13) & 0xf;
1228 if (rope_num >> 3 == ibd->ioc_num)
1229 lba_set_iregs(lba, ibd->ioc->ibase, ibd->ioc->imask);
1230 return 0;
1231}
1232
1233
1234static void
1235setup_ibase_imask(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1236{
1237 struct ibase_data_struct ibase_data = {
1238 .ioc = ioc,
1239 .ioc_num = ioc_num,
1240 };
1241
1242 device_for_each_child(&sba->dev, &ibase_data,
1243 setup_ibase_imask_callback);
1244}
1245
1246#ifdef SBA_AGP_SUPPORT
1247static int
1248sba_ioc_find_quicksilver(struct device *dev, void *data)
1249{
1250 int *agp_found = data;
1251 struct parisc_device *lba = to_parisc_device(dev);
1252
1253 if (IS_QUICKSILVER(lba))
1254 *agp_found = 1;
1255 return 0;
1256}
1257#endif
1258
1259static void
1260sba_ioc_init_pluto(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1261{
1262 u32 iova_space_mask;
1263 u32 iova_space_size;
1264 int iov_order, tcnfg;
1265#ifdef SBA_AGP_SUPPORT
1266 int agp_found = 0;
1267#endif
1268
1269
1270
1271
1272
1273 ioc->ibase = READ_REG(ioc->ioc_hpa + IOC_IBASE);
1274 iova_space_size = ~(READ_REG(ioc->ioc_hpa + IOC_IMASK) & 0xFFFFFFFFUL) + 1;
1275
1276 if ((ioc->ibase < 0xfed00000UL) && ((ioc->ibase + iova_space_size) > 0xfee00000UL)) {
1277 printk("WARNING: IOV space overlaps local config and interrupt message, truncating\n");
1278 iova_space_size /= 2;
1279 }
1280
1281
1282
1283
1284
1285 iov_order = get_order(iova_space_size >> (IOVP_SHIFT - PAGE_SHIFT));
1286 ioc->pdir_size = (iova_space_size / IOVP_SIZE) * sizeof(u64);
1287
1288 DBG_INIT("%s() hpa 0x%p IOV %dMB (%d bits)\n",
1289 __func__, ioc->ioc_hpa, iova_space_size >> 20,
1290 iov_order + PAGE_SHIFT);
1291
1292 ioc->pdir_base = (void *) __get_free_pages(GFP_KERNEL,
1293 get_order(ioc->pdir_size));
1294 if (!ioc->pdir_base)
1295 panic("Couldn't allocate I/O Page Table\n");
1296
1297 memset(ioc->pdir_base, 0, ioc->pdir_size);
1298
1299 DBG_INIT("%s() pdir %p size %x\n",
1300 __func__, ioc->pdir_base, ioc->pdir_size);
1301
1302#ifdef SBA_HINT_SUPPORT
1303 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1304 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1305
1306 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1307 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1308#endif
1309
1310 WARN_ON((((unsigned long) ioc->pdir_base) & PAGE_MASK) != (unsigned long) ioc->pdir_base);
1311 WRITE_REG(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1312
1313
1314 iova_space_mask = 0xffffffff;
1315 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1316 ioc->imask = iova_space_mask;
1317#ifdef ZX1_SUPPORT
1318 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1319#endif
1320 sba_dump_tlb(ioc->ioc_hpa);
1321
1322 setup_ibase_imask(sba, ioc, ioc_num);
1323
1324 WRITE_REG(ioc->imask, ioc->ioc_hpa + IOC_IMASK);
1325
1326#ifdef CONFIG_64BIT
1327
1328
1329
1330
1331 ioc->imask |= 0xFFFFFFFF00000000UL;
1332#endif
1333
1334
1335 switch (PAGE_SHIFT) {
1336 case 12: tcnfg = 0; break;
1337 case 13: tcnfg = 1; break;
1338 case 14: tcnfg = 2; break;
1339 case 16: tcnfg = 3; break;
1340 default:
1341 panic(__FILE__ "Unsupported system page size %d",
1342 1 << PAGE_SHIFT);
1343 break;
1344 }
1345 WRITE_REG(tcnfg, ioc->ioc_hpa + IOC_TCNFG);
1346
1347
1348
1349
1350
1351 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa + IOC_IBASE);
1352
1353
1354
1355
1356
1357 WRITE_REG(ioc->ibase | 31, ioc->ioc_hpa + IOC_PCOM);
1358
1359#ifdef SBA_AGP_SUPPORT
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369 device_for_each_child(&sba->dev, &agp_found, sba_ioc_find_quicksilver);
1370
1371 if (agp_found && sba_reserve_agpgart) {
1372 printk(KERN_INFO "%s: reserving %dMb of IOVA space for agpgart\n",
1373 __func__, (iova_space_size/2) >> 20);
1374 ioc->pdir_size /= 2;
1375 ioc->pdir_base[PDIR_INDEX(iova_space_size/2)] = SBA_AGPGART_COOKIE;
1376 }
1377#endif
1378}
1379
1380static void
1381sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
1382{
1383 u32 iova_space_size, iova_space_mask;
1384 unsigned int pdir_size, iov_order, tcnfg;
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400 iova_space_size = (u32) (totalram_pages/global_ioc_cnt);
1401
1402
1403 if (iova_space_size < (1 << (20 - PAGE_SHIFT))) {
1404 iova_space_size = 1 << (20 - PAGE_SHIFT);
1405 }
1406 else if (iova_space_size > (1 << (30 - PAGE_SHIFT))) {
1407 iova_space_size = 1 << (30 - PAGE_SHIFT);
1408 }
1409
1410
1411
1412
1413
1414
1415 iov_order = get_order(iova_space_size << PAGE_SHIFT);
1416
1417
1418 iova_space_size = 1 << (iov_order + PAGE_SHIFT);
1419
1420 ioc->pdir_size = pdir_size = (iova_space_size/IOVP_SIZE) * sizeof(u64);
1421
1422 DBG_INIT("%s() hpa 0x%lx mem %ldMB IOV %dMB (%d bits)\n",
1423 __func__,
1424 ioc->ioc_hpa,
1425 (unsigned long) totalram_pages >> (20 - PAGE_SHIFT),
1426 iova_space_size>>20,
1427 iov_order + PAGE_SHIFT);
1428
1429 ioc->pdir_base = sba_alloc_pdir(pdir_size);
1430
1431 DBG_INIT("%s() pdir %p size %x\n",
1432 __func__, ioc->pdir_base, pdir_size);
1433
1434#ifdef SBA_HINT_SUPPORT
1435
1436 ioc->hint_shift_pdir = iov_order + PAGE_SHIFT;
1437 ioc->hint_mask_pdir = ~(0x3 << (iov_order + PAGE_SHIFT));
1438
1439 DBG_INIT(" hint_shift_pdir %x hint_mask_pdir %lx\n",
1440 ioc->hint_shift_pdir, ioc->hint_mask_pdir);
1441#endif
1442
1443 WRITE_REG64(virt_to_phys(ioc->pdir_base), ioc->ioc_hpa + IOC_PDIR_BASE);
1444
1445
1446 iova_space_mask = 0xffffffff;
1447 iova_space_mask <<= (iov_order + PAGE_SHIFT);
1448
1449
1450
1451
1452
1453 ioc->ibase = 0;
1454 ioc->imask = iova_space_mask;
1455#ifdef ZX1_SUPPORT
1456 ioc->iovp_mask = ~(iova_space_mask + PAGE_SIZE - 1);
1457#endif
1458
1459 DBG_INIT("%s() IOV base 0x%lx mask 0x%0lx\n",
1460 __func__, ioc->ibase, ioc->imask);
1461
1462
1463
1464
1465
1466
1467
1468 setup_ibase_imask(sba, ioc, ioc_num);
1469
1470
1471
1472
1473 WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
1474 WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
1475
1476
1477 switch (PAGE_SHIFT) {
1478 case 12: tcnfg = 0; break;
1479 case 13: tcnfg = 1; break;
1480 case 14: tcnfg = 2; break;
1481 case 16: tcnfg = 3; break;
1482 default:
1483 panic(__FILE__ "Unsupported system page size %d",
1484 1 << PAGE_SHIFT);
1485 break;
1486 }
1487
1488 WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
1489
1490
1491
1492
1493
1494 WRITE_REG(0 | 31, ioc->ioc_hpa+IOC_PCOM);
1495
1496 ioc->ibase = 0;
1497
1498 DBG_INIT("%s() DONE\n", __func__);
1499}
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514static void __iomem *ioc_remap(struct sba_device *sba_dev, unsigned int offset)
1515{
1516 return ioremap_nocache(sba_dev->dev->hpa.start + offset, SBA_FUNC_SIZE);
1517}
1518
1519static void sba_hw_init(struct sba_device *sba_dev)
1520{
1521 int i;
1522 int num_ioc;
1523 u64 ioc_ctl;
1524
1525 if (!is_pdc_pat()) {
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543 if (PAGE0->mem_kbd.cl_class == CL_KEYBD) {
1544 pdc_io_reset_devices();
1545 }
1546
1547 }
1548
1549
1550#if 0
1551printk("sba_hw_init(): mem_boot 0x%x 0x%x 0x%x 0x%x\n", PAGE0->mem_boot.hpa,
1552 PAGE0->mem_boot.spa, PAGE0->mem_boot.pad, PAGE0->mem_boot.cl_class);
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563 if ((PAGE0->mem_boot.cl_class != CL_RANDOM)
1564 && (PAGE0->mem_boot.cl_class != CL_SEQU)) {
1565 pdc_io_reset();
1566 }
1567#endif
1568
1569 if (!IS_PLUTO(sba_dev->dev)) {
1570 ioc_ctl = READ_REG(sba_dev->sba_hpa+IOC_CTRL);
1571 DBG_INIT("%s() hpa 0x%lx ioc_ctl 0x%Lx ->",
1572 __func__, sba_dev->sba_hpa, ioc_ctl);
1573 ioc_ctl &= ~(IOC_CTRL_RM | IOC_CTRL_NC | IOC_CTRL_CE);
1574 ioc_ctl |= IOC_CTRL_DD | IOC_CTRL_D4 | IOC_CTRL_TC;
1575
1576
1577
1578 WRITE_REG(ioc_ctl, sba_dev->sba_hpa+IOC_CTRL);
1579
1580#ifdef DEBUG_SBA_INIT
1581 ioc_ctl = READ_REG64(sba_dev->sba_hpa+IOC_CTRL);
1582 DBG_INIT(" 0x%Lx\n", ioc_ctl);
1583#endif
1584 }
1585
1586 if (IS_ASTRO(sba_dev->dev)) {
1587 int err;
1588 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, ASTRO_IOC_OFFSET);
1589 num_ioc = 1;
1590
1591 sba_dev->chip_resv.name = "Astro Intr Ack";
1592 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfef00000UL;
1593 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff000000UL - 1) ;
1594 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1595 BUG_ON(err < 0);
1596
1597 } else if (IS_PLUTO(sba_dev->dev)) {
1598 int err;
1599
1600 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, PLUTO_IOC_OFFSET);
1601 num_ioc = 1;
1602
1603 sba_dev->chip_resv.name = "Pluto Intr/PIOP/VGA";
1604 sba_dev->chip_resv.start = PCI_F_EXTEND | 0xfee00000UL;
1605 sba_dev->chip_resv.end = PCI_F_EXTEND | (0xff200000UL - 1);
1606 err = request_resource(&iomem_resource, &(sba_dev->chip_resv));
1607 WARN_ON(err < 0);
1608
1609 sba_dev->iommu_resv.name = "IOVA Space";
1610 sba_dev->iommu_resv.start = 0x40000000UL;
1611 sba_dev->iommu_resv.end = 0x50000000UL - 1;
1612 err = request_resource(&iomem_resource, &(sba_dev->iommu_resv));
1613 WARN_ON(err < 0);
1614 } else {
1615
1616 sba_dev->ioc[0].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(0));
1617 sba_dev->ioc[1].ioc_hpa = ioc_remap(sba_dev, IKE_IOC_OFFSET(1));
1618 num_ioc = 2;
1619
1620
1621 }
1622
1623
1624 sba_dev->num_ioc = num_ioc;
1625 for (i = 0; i < num_ioc; i++) {
1626 void __iomem *ioc_hpa = sba_dev->ioc[i].ioc_hpa;
1627 unsigned int j;
1628
1629 for (j=0; j < sizeof(u64) * ROPES_PER_IOC; j+=sizeof(u64)) {
1630
1631
1632
1633
1634
1635
1636
1637 if (IS_PLUTO(sba_dev->dev)) {
1638 void __iomem *rope_cfg;
1639 unsigned long cfg_val;
1640
1641 rope_cfg = ioc_hpa + IOC_ROPE0_CFG + j;
1642 cfg_val = READ_REG(rope_cfg);
1643 cfg_val &= ~IOC_ROPE_AO;
1644 WRITE_REG(cfg_val, rope_cfg);
1645 }
1646
1647
1648
1649
1650 WRITE_REG(HF_ENABLE, ioc_hpa + ROPE0_CTL + j);
1651 }
1652
1653
1654 READ_REG(sba_dev->ioc[i].ioc_hpa + ROPE7_CTL);
1655
1656 DBG_INIT(" ioc[%d] ROPE_CFG 0x%Lx ROPE_DBG 0x%Lx\n",
1657 i,
1658 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x40),
1659 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x50)
1660 );
1661 DBG_INIT(" STATUS_CONTROL 0x%Lx FLUSH_CTRL 0x%Lx\n",
1662 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x108),
1663 READ_REG(sba_dev->ioc[i].ioc_hpa + 0x400)
1664 );
1665
1666 if (IS_PLUTO(sba_dev->dev)) {
1667 sba_ioc_init_pluto(sba_dev->dev, &(sba_dev->ioc[i]), i);
1668 } else {
1669 sba_ioc_init(sba_dev->dev, &(sba_dev->ioc[i]), i);
1670 }
1671 }
1672}
1673
1674static void
1675sba_common_init(struct sba_device *sba_dev)
1676{
1677 int i;
1678
1679
1680
1681
1682 sba_dev->next = sba_list;
1683 sba_list = sba_dev;
1684
1685 for(i=0; i< sba_dev->num_ioc; i++) {
1686 int res_size;
1687#ifdef DEBUG_DMB_TRAP
1688 extern void iterate_pages(unsigned long , unsigned long ,
1689 void (*)(pte_t * , unsigned long),
1690 unsigned long );
1691 void set_data_memory_break(pte_t * , unsigned long);
1692#endif
1693
1694 res_size = sba_dev->ioc[i].pdir_size/sizeof(u64);
1695
1696
1697 if (piranha_bad_128k) {
1698 res_size -= (128*1024)/sizeof(u64);
1699 }
1700
1701 res_size >>= 3;
1702 DBG_INIT("%s() res_size 0x%x\n",
1703 __func__, res_size);
1704
1705 sba_dev->ioc[i].res_size = res_size;
1706 sba_dev->ioc[i].res_map = (char *) __get_free_pages(GFP_KERNEL, get_order(res_size));
1707
1708#ifdef DEBUG_DMB_TRAP
1709 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1710 set_data_memory_break, 0);
1711#endif
1712
1713 if (NULL == sba_dev->ioc[i].res_map)
1714 {
1715 panic("%s:%s() could not allocate resource map\n",
1716 __FILE__, __func__ );
1717 }
1718
1719 memset(sba_dev->ioc[i].res_map, 0, res_size);
1720
1721 sba_dev->ioc[i].res_hint = (unsigned long *)
1722 &(sba_dev->ioc[i].res_map[L1_CACHE_BYTES]);
1723
1724#ifdef ASSERT_PDIR_SANITY
1725
1726 sba_dev->ioc[i].res_map[0] = 0x80;
1727 sba_dev->ioc[i].pdir_base[0] = 0xeeffc0addbba0080ULL;
1728#endif
1729
1730
1731 if (piranha_bad_128k) {
1732
1733
1734 int idx_start = (1408*1024/sizeof(u64)) >> 3;
1735 int idx_end = (1536*1024/sizeof(u64)) >> 3;
1736 long *p_start = (long *) &(sba_dev->ioc[i].res_map[idx_start]);
1737 long *p_end = (long *) &(sba_dev->ioc[i].res_map[idx_end]);
1738
1739
1740 while (p_start < p_end)
1741 *p_start++ = -1;
1742
1743 }
1744
1745#ifdef DEBUG_DMB_TRAP
1746 iterate_pages( sba_dev->ioc[i].res_map, res_size,
1747 set_data_memory_break, 0);
1748 iterate_pages( sba_dev->ioc[i].pdir_base, sba_dev->ioc[i].pdir_size,
1749 set_data_memory_break, 0);
1750#endif
1751
1752 DBG_INIT("%s() %d res_map %x %p\n",
1753 __func__, i, res_size, sba_dev->ioc[i].res_map);
1754 }
1755
1756 spin_lock_init(&sba_dev->sba_lock);
1757 ioc_needs_fdc = boot_cpu_data.pdc.capabilities & PDC_MODEL_IOPDIR_FDC;
1758
1759#ifdef DEBUG_SBA_INIT
1760
1761
1762
1763
1764
1765 if (ioc_needs_fdc) {
1766 printk(KERN_INFO MODULE_NAME " FDC/SYNC required.\n");
1767 } else {
1768 printk(KERN_INFO MODULE_NAME " IOC has cache coherent PDIR.\n");
1769 }
1770#endif
1771}
1772
1773#ifdef CONFIG_PROC_FS
1774static int sba_proc_info(struct seq_file *m, void *p)
1775{
1776 struct sba_device *sba_dev = sba_list;
1777 struct ioc *ioc = &sba_dev->ioc[0];
1778 int total_pages = (int) (ioc->res_size << 3);
1779#ifdef SBA_COLLECT_STATS
1780 unsigned long avg = 0, min, max;
1781#endif
1782 int i;
1783
1784 seq_printf(m, "%s rev %d.%d\n",
1785 sba_dev->name,
1786 (sba_dev->hw_rev & 0x7) + 1,
1787 (sba_dev->hw_rev & 0x18) >> 3);
1788 seq_printf(m, "IO PDIR size : %d bytes (%d entries)\n",
1789 (int)((ioc->res_size << 3) * sizeof(u64)),
1790 total_pages);
1791
1792 seq_printf(m, "Resource bitmap : %d bytes (%d pages)\n",
1793 ioc->res_size, ioc->res_size << 3);
1794
1795 seq_printf(m, "LMMIO_BASE/MASK/ROUTE %08x %08x %08x\n",
1796 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_BASE),
1797 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_MASK),
1798 READ_REG32(sba_dev->sba_hpa + LMMIO_DIST_ROUTE));
1799
1800 for (i=0; i<4; i++)
1801 seq_printf(m, "DIR%d_BASE/MASK/ROUTE %08x %08x %08x\n",
1802 i,
1803 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_BASE + i*0x18),
1804 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_MASK + i*0x18),
1805 READ_REG32(sba_dev->sba_hpa + LMMIO_DIRECT0_ROUTE + i*0x18));
1806
1807#ifdef SBA_COLLECT_STATS
1808 seq_printf(m, "IO PDIR entries : %ld free %ld used (%d%%)\n",
1809 total_pages - ioc->used_pages, ioc->used_pages,
1810 (int)(ioc->used_pages * 100 / total_pages));
1811
1812 min = max = ioc->avg_search[0];
1813 for (i = 0; i < SBA_SEARCH_SAMPLE; i++) {
1814 avg += ioc->avg_search[i];
1815 if (ioc->avg_search[i] > max) max = ioc->avg_search[i];
1816 if (ioc->avg_search[i] < min) min = ioc->avg_search[i];
1817 }
1818 avg /= SBA_SEARCH_SAMPLE;
1819 seq_printf(m, " Bitmap search : %ld/%ld/%ld (min/avg/max CPU Cycles)\n",
1820 min, avg, max);
1821
1822 seq_printf(m, "pci_map_single(): %12ld calls %12ld pages (avg %d/1000)\n",
1823 ioc->msingle_calls, ioc->msingle_pages,
1824 (int)((ioc->msingle_pages * 1000)/ioc->msingle_calls));
1825
1826
1827 min = ioc->usingle_calls;
1828 max = ioc->usingle_pages - ioc->usg_pages;
1829 seq_printf(m, "pci_unmap_single: %12ld calls %12ld pages (avg %d/1000)\n",
1830 min, max, (int)((max * 1000)/min));
1831
1832 seq_printf(m, "pci_map_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1833 ioc->msg_calls, ioc->msg_pages,
1834 (int)((ioc->msg_pages * 1000)/ioc->msg_calls));
1835
1836 seq_printf(m, "pci_unmap_sg() : %12ld calls %12ld pages (avg %d/1000)\n",
1837 ioc->usg_calls, ioc->usg_pages,
1838 (int)((ioc->usg_pages * 1000)/ioc->usg_calls));
1839#endif
1840
1841 return 0;
1842}
1843
1844static int
1845sba_proc_open(struct inode *i, struct file *f)
1846{
1847 return single_open(f, &sba_proc_info, NULL);
1848}
1849
1850static const struct file_operations sba_proc_fops = {
1851 .owner = THIS_MODULE,
1852 .open = sba_proc_open,
1853 .read = seq_read,
1854 .llseek = seq_lseek,
1855 .release = single_release,
1856};
1857
1858static int
1859sba_proc_bitmap_info(struct seq_file *m, void *p)
1860{
1861 struct sba_device *sba_dev = sba_list;
1862 struct ioc *ioc = &sba_dev->ioc[0];
1863
1864 seq_hex_dump(m, " ", DUMP_PREFIX_NONE, 32, 4, ioc->res_map,
1865 ioc->res_size, false);
1866 seq_putc(m, '\n');
1867
1868 return 0;
1869}
1870
1871static int
1872sba_proc_bitmap_open(struct inode *i, struct file *f)
1873{
1874 return single_open(f, &sba_proc_bitmap_info, NULL);
1875}
1876
1877static const struct file_operations sba_proc_bitmap_fops = {
1878 .owner = THIS_MODULE,
1879 .open = sba_proc_bitmap_open,
1880 .read = seq_read,
1881 .llseek = seq_lseek,
1882 .release = single_release,
1883};
1884#endif
1885
1886static struct parisc_device_id sba_tbl[] = {
1887 { HPHW_IOA, HVERSION_REV_ANY_ID, ASTRO_RUNWAY_PORT, 0xb },
1888 { HPHW_BCPORT, HVERSION_REV_ANY_ID, IKE_MERCED_PORT, 0xc },
1889 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REO_MERCED_PORT, 0xc },
1890 { HPHW_BCPORT, HVERSION_REV_ANY_ID, REOG_MERCED_PORT, 0xc },
1891 { HPHW_IOA, HVERSION_REV_ANY_ID, PLUTO_MCKINLEY_PORT, 0xc },
1892 { 0, }
1893};
1894
1895static int sba_driver_callback(struct parisc_device *);
1896
1897static struct parisc_driver sba_driver = {
1898 .name = MODULE_NAME,
1899 .id_table = sba_tbl,
1900 .probe = sba_driver_callback,
1901};
1902
1903
1904
1905
1906
1907
1908static int sba_driver_callback(struct parisc_device *dev)
1909{
1910 struct sba_device *sba_dev;
1911 u32 func_class;
1912 int i;
1913 char *version;
1914 void __iomem *sba_addr = ioremap_nocache(dev->hpa.start, SBA_FUNC_SIZE);
1915#ifdef CONFIG_PROC_FS
1916 struct proc_dir_entry *root;
1917#endif
1918
1919 sba_dump_ranges(sba_addr);
1920
1921
1922 func_class = READ_REG(sba_addr + SBA_FCLASS);
1923
1924 if (IS_ASTRO(dev)) {
1925 unsigned long fclass;
1926 static char astro_rev[]="Astro ?.?";
1927
1928
1929 fclass = READ_REG(sba_addr);
1930
1931 astro_rev[6] = '1' + (char) (fclass & 0x7);
1932 astro_rev[8] = '0' + (char) ((fclass & 0x18) >> 3);
1933 version = astro_rev;
1934
1935 } else if (IS_IKE(dev)) {
1936 static char ike_rev[] = "Ike rev ?";
1937 ike_rev[8] = '0' + (char) (func_class & 0xff);
1938 version = ike_rev;
1939 } else if (IS_PLUTO(dev)) {
1940 static char pluto_rev[]="Pluto ?.?";
1941 pluto_rev[6] = '0' + (char) ((func_class & 0xf0) >> 4);
1942 pluto_rev[8] = '0' + (char) (func_class & 0x0f);
1943 version = pluto_rev;
1944 } else {
1945 static char reo_rev[] = "REO rev ?";
1946 reo_rev[8] = '0' + (char) (func_class & 0xff);
1947 version = reo_rev;
1948 }
1949
1950 if (!global_ioc_cnt) {
1951 global_ioc_cnt = count_parisc_driver(&sba_driver);
1952
1953
1954 if ((!IS_ASTRO(dev)) || (!IS_PLUTO(dev)))
1955 global_ioc_cnt *= 2;
1956 }
1957
1958 printk(KERN_INFO "%s found %s at 0x%llx\n",
1959 MODULE_NAME, version, (unsigned long long)dev->hpa.start);
1960
1961 sba_dev = kzalloc(sizeof(struct sba_device), GFP_KERNEL);
1962 if (!sba_dev) {
1963 printk(KERN_ERR MODULE_NAME " - couldn't alloc sba_device\n");
1964 return -ENOMEM;
1965 }
1966
1967 parisc_set_drvdata(dev, sba_dev);
1968
1969 for(i=0; i<MAX_IOC; i++)
1970 spin_lock_init(&(sba_dev->ioc[i].res_lock));
1971
1972 sba_dev->dev = dev;
1973 sba_dev->hw_rev = func_class;
1974 sba_dev->name = dev->name;
1975 sba_dev->sba_hpa = sba_addr;
1976
1977 sba_get_pat_resources(sba_dev);
1978 sba_hw_init(sba_dev);
1979 sba_common_init(sba_dev);
1980
1981 hppa_dma_ops = &sba_ops;
1982
1983#ifdef CONFIG_PROC_FS
1984 switch (dev->id.hversion) {
1985 case PLUTO_MCKINLEY_PORT:
1986 root = proc_mckinley_root;
1987 break;
1988 case ASTRO_RUNWAY_PORT:
1989 case IKE_MERCED_PORT:
1990 default:
1991 root = proc_runway_root;
1992 break;
1993 }
1994
1995 proc_create("sba_iommu", 0, root, &sba_proc_fops);
1996 proc_create("sba_iommu-bitmap", 0, root, &sba_proc_bitmap_fops);
1997#endif
1998
1999 parisc_has_iommu();
2000 return 0;
2001}
2002
2003
2004
2005
2006
2007
2008void __init sba_init(void)
2009{
2010 register_parisc_driver(&sba_driver);
2011}
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021void * sba_get_iommu(struct parisc_device *pci_hba)
2022{
2023 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2024 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2025 char t = sba_dev->id.hw_type;
2026 int iocnum = (pci_hba->hw_path >> 3);
2027
2028 WARN_ON((t != HPHW_IOA) && (t != HPHW_BCPORT));
2029
2030 return &(sba->ioc[iocnum]);
2031}
2032
2033
2034
2035
2036
2037
2038
2039
2040
2041
2042void sba_directed_lmmio(struct parisc_device *pci_hba, struct resource *r)
2043{
2044 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2045 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2046 char t = sba_dev->id.hw_type;
2047 int i;
2048 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1));
2049
2050 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2051
2052 r->start = r->end = 0;
2053
2054
2055 for (i=0; i<4; i++) {
2056 int base, size;
2057 void __iomem *reg = sba->sba_hpa + i*0x18;
2058
2059 base = READ_REG32(reg + LMMIO_DIRECT0_BASE);
2060 if ((base & 1) == 0)
2061 continue;
2062
2063 size = READ_REG32(reg + LMMIO_DIRECT0_ROUTE);
2064
2065 if ((size & (ROPES_PER_IOC-1)) != rope)
2066 continue;
2067
2068 r->start = (base & ~1UL) | PCI_F_EXTEND;
2069 size = ~ READ_REG32(reg + LMMIO_DIRECT0_MASK);
2070 r->end = r->start + size;
2071 r->flags = IORESOURCE_MEM;
2072 }
2073}
2074
2075
2076
2077
2078
2079
2080
2081
2082
2083
2084
2085void sba_distributed_lmmio(struct parisc_device *pci_hba, struct resource *r )
2086{
2087 struct parisc_device *sba_dev = parisc_parent(pci_hba);
2088 struct sba_device *sba = dev_get_drvdata(&sba_dev->dev);
2089 char t = sba_dev->id.hw_type;
2090 int base, size;
2091 int rope = (pci_hba->hw_path & (ROPES_PER_IOC-1));
2092
2093 BUG_ON((t!=HPHW_IOA) && (t!=HPHW_BCPORT));
2094
2095 r->start = r->end = 0;
2096
2097 base = READ_REG32(sba->sba_hpa + LMMIO_DIST_BASE);
2098 if ((base & 1) == 0) {
2099 BUG();
2100 return;
2101 }
2102
2103 r->start = (base & ~1UL) | PCI_F_EXTEND;
2104
2105 size = (~READ_REG32(sba->sba_hpa + LMMIO_DIST_MASK)) / ROPES_PER_IOC;
2106 r->start += rope * (size + 1);
2107 r->end = r->start + size;
2108 r->flags = IORESOURCE_MEM;
2109}
2110