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15#include <linux/clk.h>
16#include <linux/delay.h>
17#include <linux/gpio.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/iopoll.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/of_device.h>
24#include <linux/of_gpio.h>
25#include <linux/pci.h>
26#include <linux/platform_device.h>
27#include <linux/phy/phy.h>
28#include <linux/regulator/consumer.h>
29#include <linux/reset.h>
30#include <linux/slab.h>
31#include <linux/types.h>
32
33#include "pcie-designware.h"
34
35#define PCIE20_PARF_PHY_CTRL 0x40
36#define PCIE20_PARF_PHY_REFCLK 0x4C
37#define PCIE20_PARF_DBI_BASE_ADDR 0x168
38#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
39#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
40
41#define PCIE20_ELBI_SYS_CTRL 0x04
42#define PCIE20_ELBI_SYS_CTRL_LT_ENABLE BIT(0)
43
44#define PCIE20_CAP 0x70
45
46#define PERST_DELAY_US 1000
47
48struct qcom_pcie_resources_v0 {
49 struct clk *iface_clk;
50 struct clk *core_clk;
51 struct clk *phy_clk;
52 struct reset_control *pci_reset;
53 struct reset_control *axi_reset;
54 struct reset_control *ahb_reset;
55 struct reset_control *por_reset;
56 struct reset_control *phy_reset;
57 struct regulator *vdda;
58 struct regulator *vdda_phy;
59 struct regulator *vdda_refclk;
60};
61
62struct qcom_pcie_resources_v1 {
63 struct clk *iface;
64 struct clk *aux;
65 struct clk *master_bus;
66 struct clk *slave_bus;
67 struct reset_control *core;
68 struct regulator *vdda;
69};
70
71union qcom_pcie_resources {
72 struct qcom_pcie_resources_v0 v0;
73 struct qcom_pcie_resources_v1 v1;
74};
75
76struct qcom_pcie;
77
78struct qcom_pcie_ops {
79 int (*get_resources)(struct qcom_pcie *pcie);
80 int (*init)(struct qcom_pcie *pcie);
81 void (*deinit)(struct qcom_pcie *pcie);
82};
83
84struct qcom_pcie {
85 struct pcie_port pp;
86 struct device *dev;
87 union qcom_pcie_resources res;
88 void __iomem *parf;
89 void __iomem *dbi;
90 void __iomem *elbi;
91 struct phy *phy;
92 struct gpio_desc *reset;
93 struct qcom_pcie_ops *ops;
94};
95
96#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
97
98static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
99{
100 gpiod_set_value(pcie->reset, 1);
101 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
102}
103
104static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
105{
106 gpiod_set_value(pcie->reset, 0);
107 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
108}
109
110static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
111{
112 struct pcie_port *pp = arg;
113
114 return dw_handle_msi_irq(pp);
115}
116
117static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
118{
119 u32 val;
120
121 if (dw_pcie_link_up(&pcie->pp))
122 return 0;
123
124
125 val = readl(pcie->elbi + PCIE20_ELBI_SYS_CTRL);
126 val |= PCIE20_ELBI_SYS_CTRL_LT_ENABLE;
127 writel(val, pcie->elbi + PCIE20_ELBI_SYS_CTRL);
128
129 return dw_pcie_wait_for_link(&pcie->pp);
130}
131
132static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
133{
134 struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
135 struct device *dev = pcie->dev;
136
137 res->vdda = devm_regulator_get(dev, "vdda");
138 if (IS_ERR(res->vdda))
139 return PTR_ERR(res->vdda);
140
141 res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
142 if (IS_ERR(res->vdda_phy))
143 return PTR_ERR(res->vdda_phy);
144
145 res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
146 if (IS_ERR(res->vdda_refclk))
147 return PTR_ERR(res->vdda_refclk);
148
149 res->iface_clk = devm_clk_get(dev, "iface");
150 if (IS_ERR(res->iface_clk))
151 return PTR_ERR(res->iface_clk);
152
153 res->core_clk = devm_clk_get(dev, "core");
154 if (IS_ERR(res->core_clk))
155 return PTR_ERR(res->core_clk);
156
157 res->phy_clk = devm_clk_get(dev, "phy");
158 if (IS_ERR(res->phy_clk))
159 return PTR_ERR(res->phy_clk);
160
161 res->pci_reset = devm_reset_control_get(dev, "pci");
162 if (IS_ERR(res->pci_reset))
163 return PTR_ERR(res->pci_reset);
164
165 res->axi_reset = devm_reset_control_get(dev, "axi");
166 if (IS_ERR(res->axi_reset))
167 return PTR_ERR(res->axi_reset);
168
169 res->ahb_reset = devm_reset_control_get(dev, "ahb");
170 if (IS_ERR(res->ahb_reset))
171 return PTR_ERR(res->ahb_reset);
172
173 res->por_reset = devm_reset_control_get(dev, "por");
174 if (IS_ERR(res->por_reset))
175 return PTR_ERR(res->por_reset);
176
177 res->phy_reset = devm_reset_control_get(dev, "phy");
178 if (IS_ERR(res->phy_reset))
179 return PTR_ERR(res->phy_reset);
180
181 return 0;
182}
183
184static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
185{
186 struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
187 struct device *dev = pcie->dev;
188
189 res->vdda = devm_regulator_get(dev, "vdda");
190 if (IS_ERR(res->vdda))
191 return PTR_ERR(res->vdda);
192
193 res->iface = devm_clk_get(dev, "iface");
194 if (IS_ERR(res->iface))
195 return PTR_ERR(res->iface);
196
197 res->aux = devm_clk_get(dev, "aux");
198 if (IS_ERR(res->aux))
199 return PTR_ERR(res->aux);
200
201 res->master_bus = devm_clk_get(dev, "master_bus");
202 if (IS_ERR(res->master_bus))
203 return PTR_ERR(res->master_bus);
204
205 res->slave_bus = devm_clk_get(dev, "slave_bus");
206 if (IS_ERR(res->slave_bus))
207 return PTR_ERR(res->slave_bus);
208
209 res->core = devm_reset_control_get(dev, "core");
210 if (IS_ERR(res->core))
211 return PTR_ERR(res->core);
212
213 return 0;
214}
215
216static void qcom_pcie_deinit_v0(struct qcom_pcie *pcie)
217{
218 struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
219
220 reset_control_assert(res->pci_reset);
221 reset_control_assert(res->axi_reset);
222 reset_control_assert(res->ahb_reset);
223 reset_control_assert(res->por_reset);
224 reset_control_assert(res->pci_reset);
225 clk_disable_unprepare(res->iface_clk);
226 clk_disable_unprepare(res->core_clk);
227 clk_disable_unprepare(res->phy_clk);
228 regulator_disable(res->vdda);
229 regulator_disable(res->vdda_phy);
230 regulator_disable(res->vdda_refclk);
231}
232
233static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
234{
235 struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
236 struct device *dev = pcie->dev;
237 u32 val;
238 int ret;
239
240 ret = regulator_enable(res->vdda);
241 if (ret) {
242 dev_err(dev, "cannot enable vdda regulator\n");
243 return ret;
244 }
245
246 ret = regulator_enable(res->vdda_refclk);
247 if (ret) {
248 dev_err(dev, "cannot enable vdda_refclk regulator\n");
249 goto err_refclk;
250 }
251
252 ret = regulator_enable(res->vdda_phy);
253 if (ret) {
254 dev_err(dev, "cannot enable vdda_phy regulator\n");
255 goto err_vdda_phy;
256 }
257
258 ret = reset_control_assert(res->ahb_reset);
259 if (ret) {
260 dev_err(dev, "cannot assert ahb reset\n");
261 goto err_assert_ahb;
262 }
263
264 ret = clk_prepare_enable(res->iface_clk);
265 if (ret) {
266 dev_err(dev, "cannot prepare/enable iface clock\n");
267 goto err_assert_ahb;
268 }
269
270 ret = clk_prepare_enable(res->phy_clk);
271 if (ret) {
272 dev_err(dev, "cannot prepare/enable phy clock\n");
273 goto err_clk_phy;
274 }
275
276 ret = clk_prepare_enable(res->core_clk);
277 if (ret) {
278 dev_err(dev, "cannot prepare/enable core clock\n");
279 goto err_clk_core;
280 }
281
282 ret = reset_control_deassert(res->ahb_reset);
283 if (ret) {
284 dev_err(dev, "cannot deassert ahb reset\n");
285 goto err_deassert_ahb;
286 }
287
288
289 val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
290 val &= ~BIT(0);
291 writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
292
293
294 val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
295 val |= BIT(16);
296 writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
297
298 ret = reset_control_deassert(res->phy_reset);
299 if (ret) {
300 dev_err(dev, "cannot deassert phy reset\n");
301 return ret;
302 }
303
304 ret = reset_control_deassert(res->pci_reset);
305 if (ret) {
306 dev_err(dev, "cannot deassert pci reset\n");
307 return ret;
308 }
309
310 ret = reset_control_deassert(res->por_reset);
311 if (ret) {
312 dev_err(dev, "cannot deassert por reset\n");
313 return ret;
314 }
315
316 ret = reset_control_deassert(res->axi_reset);
317 if (ret) {
318 dev_err(dev, "cannot deassert axi reset\n");
319 return ret;
320 }
321
322
323 usleep_range(1000, 1500);
324
325 return 0;
326
327err_deassert_ahb:
328 clk_disable_unprepare(res->core_clk);
329err_clk_core:
330 clk_disable_unprepare(res->phy_clk);
331err_clk_phy:
332 clk_disable_unprepare(res->iface_clk);
333err_assert_ahb:
334 regulator_disable(res->vdda_phy);
335err_vdda_phy:
336 regulator_disable(res->vdda_refclk);
337err_refclk:
338 regulator_disable(res->vdda);
339
340 return ret;
341}
342
343static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
344{
345 struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
346
347 reset_control_assert(res->core);
348 clk_disable_unprepare(res->slave_bus);
349 clk_disable_unprepare(res->master_bus);
350 clk_disable_unprepare(res->iface);
351 clk_disable_unprepare(res->aux);
352 regulator_disable(res->vdda);
353}
354
355static int qcom_pcie_init_v1(struct qcom_pcie *pcie)
356{
357 struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
358 struct device *dev = pcie->dev;
359 int ret;
360
361 ret = reset_control_deassert(res->core);
362 if (ret) {
363 dev_err(dev, "cannot deassert core reset\n");
364 return ret;
365 }
366
367 ret = clk_prepare_enable(res->aux);
368 if (ret) {
369 dev_err(dev, "cannot prepare/enable aux clock\n");
370 goto err_res;
371 }
372
373 ret = clk_prepare_enable(res->iface);
374 if (ret) {
375 dev_err(dev, "cannot prepare/enable iface clock\n");
376 goto err_aux;
377 }
378
379 ret = clk_prepare_enable(res->master_bus);
380 if (ret) {
381 dev_err(dev, "cannot prepare/enable master_bus clock\n");
382 goto err_iface;
383 }
384
385 ret = clk_prepare_enable(res->slave_bus);
386 if (ret) {
387 dev_err(dev, "cannot prepare/enable slave_bus clock\n");
388 goto err_master;
389 }
390
391 ret = regulator_enable(res->vdda);
392 if (ret) {
393 dev_err(dev, "cannot enable vdda regulator\n");
394 goto err_slave;
395 }
396
397
398 writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
399
400 if (IS_ENABLED(CONFIG_PCI_MSI)) {
401 u32 val = readl(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
402
403 val |= BIT(31);
404 writel(val, pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);
405 }
406
407 return 0;
408err_slave:
409 clk_disable_unprepare(res->slave_bus);
410err_master:
411 clk_disable_unprepare(res->master_bus);
412err_iface:
413 clk_disable_unprepare(res->iface);
414err_aux:
415 clk_disable_unprepare(res->aux);
416err_res:
417 reset_control_assert(res->core);
418
419 return ret;
420}
421
422static int qcom_pcie_link_up(struct pcie_port *pp)
423{
424 struct qcom_pcie *pcie = to_qcom_pcie(pp);
425 u16 val = readw(pcie->dbi + PCIE20_CAP + PCI_EXP_LNKSTA);
426
427 return !!(val & PCI_EXP_LNKSTA_DLLLA);
428}
429
430static void qcom_pcie_host_init(struct pcie_port *pp)
431{
432 struct qcom_pcie *pcie = to_qcom_pcie(pp);
433 int ret;
434
435 qcom_ep_reset_assert(pcie);
436
437 ret = pcie->ops->init(pcie);
438 if (ret)
439 goto err_deinit;
440
441 ret = phy_power_on(pcie->phy);
442 if (ret)
443 goto err_deinit;
444
445 dw_pcie_setup_rc(pp);
446
447 if (IS_ENABLED(CONFIG_PCI_MSI))
448 dw_pcie_msi_init(pp);
449
450 qcom_ep_reset_deassert(pcie);
451
452 ret = qcom_pcie_establish_link(pcie);
453 if (ret)
454 goto err;
455
456 return;
457err:
458 qcom_ep_reset_assert(pcie);
459 phy_power_off(pcie->phy);
460err_deinit:
461 pcie->ops->deinit(pcie);
462}
463
464static int qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
465 u32 *val)
466{
467
468 if (where == PCI_CLASS_REVISION && size == 4) {
469 *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
470 *val &= 0xff;
471 *val |= PCI_CLASS_BRIDGE_PCI << 16;
472 return PCIBIOS_SUCCESSFUL;
473 }
474
475 return dw_pcie_cfg_read(pp->dbi_base + where, size, val);
476}
477
478static struct pcie_host_ops qcom_pcie_dw_ops = {
479 .link_up = qcom_pcie_link_up,
480 .host_init = qcom_pcie_host_init,
481 .rd_own_conf = qcom_pcie_rd_own_conf,
482};
483
484static const struct qcom_pcie_ops ops_v0 = {
485 .get_resources = qcom_pcie_get_resources_v0,
486 .init = qcom_pcie_init_v0,
487 .deinit = qcom_pcie_deinit_v0,
488};
489
490static const struct qcom_pcie_ops ops_v1 = {
491 .get_resources = qcom_pcie_get_resources_v1,
492 .init = qcom_pcie_init_v1,
493 .deinit = qcom_pcie_deinit_v1,
494};
495
496static int qcom_pcie_probe(struct platform_device *pdev)
497{
498 struct device *dev = &pdev->dev;
499 struct resource *res;
500 struct qcom_pcie *pcie;
501 struct pcie_port *pp;
502 int ret;
503
504 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
505 if (!pcie)
506 return -ENOMEM;
507
508 pcie->ops = (struct qcom_pcie_ops *)of_device_get_match_data(dev);
509 pcie->dev = dev;
510
511 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_LOW);
512 if (IS_ERR(pcie->reset))
513 return PTR_ERR(pcie->reset);
514
515 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
516 pcie->parf = devm_ioremap_resource(dev, res);
517 if (IS_ERR(pcie->parf))
518 return PTR_ERR(pcie->parf);
519
520 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
521 pcie->dbi = devm_ioremap_resource(dev, res);
522 if (IS_ERR(pcie->dbi))
523 return PTR_ERR(pcie->dbi);
524
525 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
526 pcie->elbi = devm_ioremap_resource(dev, res);
527 if (IS_ERR(pcie->elbi))
528 return PTR_ERR(pcie->elbi);
529
530 pcie->phy = devm_phy_optional_get(dev, "pciephy");
531 if (IS_ERR(pcie->phy))
532 return PTR_ERR(pcie->phy);
533
534 ret = pcie->ops->get_resources(pcie);
535 if (ret)
536 return ret;
537
538 pp = &pcie->pp;
539 pp->dev = dev;
540 pp->dbi_base = pcie->dbi;
541 pp->root_bus_nr = -1;
542 pp->ops = &qcom_pcie_dw_ops;
543
544 if (IS_ENABLED(CONFIG_PCI_MSI)) {
545 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
546 if (pp->msi_irq < 0)
547 return pp->msi_irq;
548
549 ret = devm_request_irq(dev, pp->msi_irq,
550 qcom_pcie_msi_irq_handler,
551 IRQF_SHARED, "qcom-pcie-msi", pp);
552 if (ret) {
553 dev_err(dev, "cannot request msi irq\n");
554 return ret;
555 }
556 }
557
558 ret = phy_init(pcie->phy);
559 if (ret)
560 return ret;
561
562 ret = dw_pcie_host_init(pp);
563 if (ret) {
564 dev_err(dev, "cannot initialize host\n");
565 return ret;
566 }
567
568 platform_set_drvdata(pdev, pcie);
569
570 return 0;
571}
572
573static int qcom_pcie_remove(struct platform_device *pdev)
574{
575 struct qcom_pcie *pcie = platform_get_drvdata(pdev);
576
577 qcom_ep_reset_assert(pcie);
578 phy_power_off(pcie->phy);
579 phy_exit(pcie->phy);
580 pcie->ops->deinit(pcie);
581
582 return 0;
583}
584
585static const struct of_device_id qcom_pcie_match[] = {
586 { .compatible = "qcom,pcie-ipq8064", .data = &ops_v0 },
587 { .compatible = "qcom,pcie-apq8064", .data = &ops_v0 },
588 { .compatible = "qcom,pcie-apq8084", .data = &ops_v1 },
589 { }
590};
591MODULE_DEVICE_TABLE(of, qcom_pcie_match);
592
593static struct platform_driver qcom_pcie_driver = {
594 .probe = qcom_pcie_probe,
595 .remove = qcom_pcie_remove,
596 .driver = {
597 .name = "qcom-pcie",
598 .of_match_table = qcom_pcie_match,
599 },
600};
601
602module_platform_driver(qcom_pcie_driver);
603
604MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
605MODULE_DESCRIPTION("Qualcomm PCIe root complex driver");
606MODULE_LICENSE("GPL v2");
607
