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29#ifndef _SHPCHP_H
30#define _SHPCHP_H
31
32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/pci_hotplug.h>
35#include <linux/delay.h>
36#include <linux/sched.h>
37#include <linux/mutex.h>
38#include <linux/workqueue.h>
39
40#if !defined(MODULE)
41 #define MY_NAME "shpchp"
42#else
43 #define MY_NAME THIS_MODULE->name
44#endif
45
46extern bool shpchp_poll_mode;
47extern int shpchp_poll_time;
48extern bool shpchp_debug;
49
50#define dbg(format, arg...) \
51do { \
52 if (shpchp_debug) \
53 printk(KERN_DEBUG "%s: " format, MY_NAME, ## arg); \
54} while (0)
55#define err(format, arg...) \
56 printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
57#define info(format, arg...) \
58 printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
59#define warn(format, arg...) \
60 printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
61
62#define ctrl_dbg(ctrl, format, arg...) \
63 do { \
64 if (shpchp_debug) \
65 dev_printk(KERN_DEBUG, &ctrl->pci_dev->dev, \
66 format, ## arg); \
67 } while (0)
68#define ctrl_err(ctrl, format, arg...) \
69 dev_err(&ctrl->pci_dev->dev, format, ## arg)
70#define ctrl_info(ctrl, format, arg...) \
71 dev_info(&ctrl->pci_dev->dev, format, ## arg)
72#define ctrl_warn(ctrl, format, arg...) \
73 dev_warn(&ctrl->pci_dev->dev, format, ## arg)
74
75
76#define SLOT_NAME_SIZE 10
77struct slot {
78 u8 bus;
79 u8 device;
80 u16 status;
81 u32 number;
82 u8 is_a_board;
83 u8 state;
84 u8 presence_save;
85 u8 pwr_save;
86 struct controller *ctrl;
87 const struct hpc_ops *hpc_ops;
88 struct hotplug_slot *hotplug_slot;
89 struct list_head slot_list;
90 struct delayed_work work;
91 struct mutex lock;
92 struct workqueue_struct *wq;
93 u8 hp_slot;
94};
95
96struct event_info {
97 u32 event_type;
98 struct slot *p_slot;
99 struct work_struct work;
100};
101
102struct controller {
103 struct mutex crit_sect;
104 struct mutex cmd_lock;
105 int num_slots;
106 int slot_num_inc;
107 struct pci_dev *pci_dev;
108 struct list_head slot_list;
109 const struct hpc_ops *hpc_ops;
110 wait_queue_head_t queue;
111 u8 slot_device_offset;
112 u32 pcix_misc2_reg;
113 u32 first_slot;
114 u32 cap_offset;
115 unsigned long mmio_base;
116 unsigned long mmio_size;
117 void __iomem *creg;
118 struct timer_list poll_timer;
119};
120
121
122#define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
123#define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
124
125
126#define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
127#define PCIX_MISCII_OFFSET 0x48
128#define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
129
130
131#define PERRNONFATALENABLE_MASK 0x00040000
132#define PERRFATALENABLE_MASK 0x00080000
133#define PERRFLOODENABLE_MASK 0x00100000
134#define SERRNONFATALENABLE_MASK 0x00200000
135#define SERRFATALENABLE_MASK 0x00400000
136
137
138#define PERR_OBSERVED_MASK 0x00000001
139
140
141#define RSE_MASK 0x40000000
142
143#define INT_BUTTON_IGNORE 0
144#define INT_PRESENCE_ON 1
145#define INT_PRESENCE_OFF 2
146#define INT_SWITCH_CLOSE 3
147#define INT_SWITCH_OPEN 4
148#define INT_POWER_FAULT 5
149#define INT_POWER_FAULT_CLEAR 6
150#define INT_BUTTON_PRESS 7
151#define INT_BUTTON_RELEASE 8
152#define INT_BUTTON_CANCEL 9
153
154#define STATIC_STATE 0
155#define BLINKINGON_STATE 1
156#define BLINKINGOFF_STATE 2
157#define POWERON_STATE 3
158#define POWEROFF_STATE 4
159
160
161#define INTERLOCK_OPEN 0x00000002
162#define ADD_NOT_SUPPORTED 0x00000003
163#define CARD_FUNCTIONING 0x00000005
164#define ADAPTER_NOT_SAME 0x00000006
165#define NO_ADAPTER_PRESENT 0x00000009
166#define NOT_ENOUGH_RESOURCES 0x0000000B
167#define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
168#define WRONG_BUS_FREQUENCY 0x0000000D
169#define POWER_FAILURE 0x0000000E
170
171int __must_check shpchp_create_ctrl_files(struct controller *ctrl);
172void shpchp_remove_ctrl_files(struct controller *ctrl);
173int shpchp_sysfs_enable_slot(struct slot *slot);
174int shpchp_sysfs_disable_slot(struct slot *slot);
175u8 shpchp_handle_attention_button(u8 hp_slot, struct controller *ctrl);
176u8 shpchp_handle_switch_change(u8 hp_slot, struct controller *ctrl);
177u8 shpchp_handle_presence_change(u8 hp_slot, struct controller *ctrl);
178u8 shpchp_handle_power_fault(u8 hp_slot, struct controller *ctrl);
179int shpchp_configure_device(struct slot *p_slot);
180int shpchp_unconfigure_device(struct slot *p_slot);
181void cleanup_slots(struct controller *ctrl);
182void shpchp_queue_pushbutton_work(struct work_struct *work);
183int shpc_init(struct controller *ctrl, struct pci_dev *pdev);
184
185static inline const char *slot_name(struct slot *slot)
186{
187 return hotplug_slot_name(slot->hotplug_slot);
188}
189
190#ifdef CONFIG_ACPI
191#include <linux/pci-acpi.h>
192static inline int get_hp_hw_control_from_firmware(struct pci_dev *dev)
193{
194 u32 flags = OSC_PCI_SHPC_NATIVE_HP_CONTROL;
195 return acpi_get_hp_hw_control_from_firmware(dev, flags);
196}
197#else
198#define get_hp_hw_control_from_firmware(dev) (0)
199#endif
200
201struct ctrl_reg {
202 volatile u32 base_offset;
203 volatile u32 slot_avail1;
204 volatile u32 slot_avail2;
205 volatile u32 slot_config;
206 volatile u16 sec_bus_config;
207 volatile u8 msi_ctrl;
208 volatile u8 prog_interface;
209 volatile u16 cmd;
210 volatile u16 cmd_status;
211 volatile u32 intr_loc;
212 volatile u32 serr_loc;
213 volatile u32 serr_intr_enable;
214 volatile u32 slot1;
215} __attribute__ ((packed));
216
217
218enum ctrl_offsets {
219 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
220 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
221 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
222 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
223 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
224 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
225 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
226 CMD = offsetof(struct ctrl_reg, cmd),
227 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
228 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
229 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
230 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
231 SLOT1 = offsetof(struct ctrl_reg, slot1),
232};
233
234static inline struct slot *get_slot(struct hotplug_slot *hotplug_slot)
235{
236 return hotplug_slot->private;
237}
238
239static inline struct slot *shpchp_find_slot(struct controller *ctrl, u8 device)
240{
241 struct slot *slot;
242
243 list_for_each_entry(slot, &ctrl->slot_list, slot_list) {
244 if (slot->device == device)
245 return slot;
246 }
247
248 ctrl_err(ctrl, "Slot (device=0x%02x) not found\n", device);
249 return NULL;
250}
251
252static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
253{
254 u32 pcix_misc2_temp;
255
256
257 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
258
259 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
260
261
262 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
263 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
264 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
265 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
266 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
267 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
268}
269
270static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
271{
272 u32 pcix_misc2_temp;
273 u32 pcix_bridge_errors_reg;
274 u32 pcix_mem_base_reg;
275 u8 perr_set;
276 u8 rse_set;
277
278
279 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
280 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
281 if (perr_set) {
282 ctrl_dbg(p_slot->ctrl,
283 "Bridge_Errors[ PERR_OBSERVED = %08X] (W1C)\n",
284 perr_set);
285
286 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
287 }
288
289
290 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
291 rse_set = pcix_mem_base_reg & RSE_MASK;
292 if (rse_set) {
293 ctrl_dbg(p_slot->ctrl, "Memory_Base_Limit[ RSE ] (W1C)\n");
294
295 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
296 }
297
298 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
299
300 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
301 pcix_misc2_temp |= SERRFATALENABLE_MASK;
302 else
303 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
304
305 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
306 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
307 else
308 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
309
310 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
311 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
312 else
313 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
314
315 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
316 pcix_misc2_temp |= PERRFATALENABLE_MASK;
317 else
318 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
319
320 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
321 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
322 else
323 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
324 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
325}
326
327struct hpc_ops {
328 int (*power_on_slot)(struct slot *slot);
329 int (*slot_enable)(struct slot *slot);
330 int (*slot_disable)(struct slot *slot);
331 int (*set_bus_speed_mode)(struct slot *slot, enum pci_bus_speed speed);
332 int (*get_power_status)(struct slot *slot, u8 *status);
333 int (*get_attention_status)(struct slot *slot, u8 *status);
334 int (*set_attention_status)(struct slot *slot, u8 status);
335 int (*get_latch_status)(struct slot *slot, u8 *status);
336 int (*get_adapter_status)(struct slot *slot, u8 *status);
337 int (*get_adapter_speed)(struct slot *slot, enum pci_bus_speed *speed);
338 int (*get_mode1_ECC_cap)(struct slot *slot, u8 *mode);
339 int (*get_prog_int)(struct slot *slot, u8 *prog_int);
340 int (*query_power_fault)(struct slot *slot);
341 void (*green_led_on)(struct slot *slot);
342 void (*green_led_off)(struct slot *slot);
343 void (*green_led_blink)(struct slot *slot);
344 void (*release_ctlr)(struct controller *ctrl);
345 int (*check_cmd_status)(struct controller *ctrl);
346};
347
348#endif
349
