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30#ifndef _LINUX_RICOH_H
31#define _LINUX_RICOH_H
32
33
34#define RF5C_MODE_CTL 0x1f
35#define RF5C_PWR_CTL 0x2f
36#define RF5C_CHIP_ID 0x3a
37#define RF5C_MODE_CTL_3 0x3b
38
39
40#define RF5C_IO_OFF(w) (0x36+((w)<<1))
41
42
43#define RF5C_MODE_ATA 0x01
44#define RF5C_MODE_LED_ENA 0x02
45#define RF5C_MODE_CA21 0x04
46#define RF5C_MODE_CA22 0x08
47#define RF5C_MODE_CA23 0x10
48#define RF5C_MODE_CA24 0x20
49#define RF5C_MODE_CA25 0x40
50#define RF5C_MODE_3STATE_BIT7 0x80
51
52
53#define RF5C_PWR_VCC_3V 0x01
54#define RF5C_PWR_IREQ_HIGH 0x02
55#define RF5C_PWR_INPACK_ENA 0x04
56#define RF5C_PWR_5V_DET 0x08
57#define RF5C_PWR_TC_SEL 0x10
58#define RF5C_PWR_DREQ_LOW 0x20
59#define RF5C_PWR_DREQ_OFF 0x00
60#define RF5C_PWR_DREQ_INPACK 0x40
61#define RF5C_PWR_DREQ_SPKR 0x80
62#define RF5C_PWR_DREQ_IOIS16 0xc0
63
64
65#define RF5C_CHIP_RF5C296 0x32
66#define RF5C_CHIP_RF5C396 0xb2
67
68
69#define RF5C_MCTL3_DISABLE 0x01
70#define RF5C_MCTL3_DMA_ENA 0x02
71
72
73
74
75#define RL5C46X_BCR_3E0_ENA 0x0800
76#define RL5C46X_BCR_3E2_ENA 0x1000
77
78
79#define RL5C4XX_CONFIG 0x80
80#define RL5C4XX_CONFIG_IO_1_MODE 0x0200
81#define RL5C4XX_CONFIG_IO_0_MODE 0x0100
82#define RL5C4XX_CONFIG_PREFETCH 0x0001
83
84
85#define RL5C4XX_MISC 0x0082
86#define RL5C4XX_MISC_HW_SUSPEND_ENA 0x0002
87#define RL5C4XX_MISC_VCCEN_POL 0x0100
88#define RL5C4XX_MISC_VPPEN_POL 0x0200
89#define RL5C46X_MISC_SUSPEND 0x0001
90#define RL5C46X_MISC_PWR_SAVE_2 0x0004
91#define RL5C46X_MISC_IFACE_BUSY 0x0008
92#define RL5C46X_MISC_B_LOCK 0x0010
93#define RL5C46X_MISC_A_LOCK 0x0020
94#define RL5C46X_MISC_PCI_LOCK 0x0040
95#define RL5C47X_MISC_IFACE_BUSY 0x0004
96#define RL5C47X_MISC_PCI_INT_MASK 0x0018
97#define RL5C47X_MISC_PCI_INT_DIS 0x0020
98#define RL5C47X_MISC_SUBSYS_WR 0x0040
99#define RL5C47X_MISC_SRIRQ_ENA 0x0080
100#define RL5C47X_MISC_5V_DISABLE 0x0400
101#define RL5C47X_MISC_LED_POL 0x0800
102
103
104#define RL5C4XX_16BIT_CTL 0x0084
105#define RL5C4XX_16CTL_IO_TIMING 0x0100
106#define RL5C4XX_16CTL_MEM_TIMING 0x0200
107#define RL5C46X_16CTL_LEVEL_1 0x0010
108#define RL5C46X_16CTL_LEVEL_2 0x0020
109
110
111#define RL5C4XX_16BIT_IO_0 0x0088
112#define RL5C4XX_16BIT_MEM_0 0x008a
113#define RL5C4XX_SETUP_MASK 0x0007
114#define RL5C4XX_SETUP_SHIFT 0
115#define RL5C4XX_CMD_MASK 0x01f0
116#define RL5C4XX_CMD_SHIFT 4
117#define RL5C4XX_HOLD_MASK 0x1c00
118#define RL5C4XX_HOLD_SHIFT 10
119#define RL5C4XX_MISC_CONTROL 0x2F
120#define RL5C4XX_ZV_ENABLE 0x08
121
122#ifdef __YENTA_H
123
124#define rl_misc(socket) ((socket)->private[0])
125#define rl_ctl(socket) ((socket)->private[1])
126#define rl_io(socket) ((socket)->private[2])
127#define rl_mem(socket) ((socket)->private[3])
128#define rl_config(socket) ((socket)->private[4])
129
130static void ricoh_zoom_video(struct pcmcia_socket *sock, int onoff)
131{
132 u8 reg;
133 struct yenta_socket *socket = container_of(sock, struct yenta_socket, socket);
134
135 reg = config_readb(socket, RL5C4XX_MISC_CONTROL);
136 if (onoff)
137
138 reg |= RL5C4XX_ZV_ENABLE;
139 else
140 reg &= ~RL5C4XX_ZV_ENABLE;
141
142 config_writeb(socket, RL5C4XX_MISC_CONTROL, reg);
143}
144
145static void ricoh_set_zv(struct yenta_socket *socket)
146{
147 if(socket->dev->vendor == PCI_VENDOR_ID_RICOH)
148 {
149 switch(socket->dev->device)
150 {
151
152 case PCI_DEVICE_ID_RICOH_RL5C478:
153 socket->socket.zoom_video = ricoh_zoom_video;
154 break;
155 }
156 }
157}
158
159static void ricoh_save_state(struct yenta_socket *socket)
160{
161 rl_misc(socket) = config_readw(socket, RL5C4XX_MISC);
162 rl_ctl(socket) = config_readw(socket, RL5C4XX_16BIT_CTL);
163 rl_io(socket) = config_readw(socket, RL5C4XX_16BIT_IO_0);
164 rl_mem(socket) = config_readw(socket, RL5C4XX_16BIT_MEM_0);
165 rl_config(socket) = config_readw(socket, RL5C4XX_CONFIG);
166}
167
168static void ricoh_restore_state(struct yenta_socket *socket)
169{
170 config_writew(socket, RL5C4XX_MISC, rl_misc(socket));
171 config_writew(socket, RL5C4XX_16BIT_CTL, rl_ctl(socket));
172 config_writew(socket, RL5C4XX_16BIT_IO_0, rl_io(socket));
173 config_writew(socket, RL5C4XX_16BIT_MEM_0, rl_mem(socket));
174 config_writew(socket, RL5C4XX_CONFIG, rl_config(socket));
175}
176
177
178
179
180
181static int ricoh_override(struct yenta_socket *socket)
182{
183 u16 config, ctl;
184
185 config = config_readw(socket, RL5C4XX_CONFIG);
186
187
188 ctl = RL5C4XX_16CTL_IO_TIMING | RL5C4XX_16CTL_MEM_TIMING;
189
190 if(socket->dev->device < PCI_DEVICE_ID_RICOH_RL5C475) {
191 ctl |= RL5C46X_16CTL_LEVEL_1 | RL5C46X_16CTL_LEVEL_2;
192 } else {
193 config |= RL5C4XX_CONFIG_PREFETCH;
194 }
195
196 config_writew(socket, RL5C4XX_16BIT_CTL, ctl);
197 config_writew(socket, RL5C4XX_CONFIG, config);
198
199 ricoh_set_zv(socket);
200
201 return 0;
202}
203
204#endif
205
206#endif
207