1/* 2 * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's. 3 * 4 * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5 * http://www.samsung.com 6 * Copyright (c) 2012 Linaro Ltd 7 * http://www.linaro.org 8 * 9 * Author: Thomas Abraham <thomas.ab@samsung.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17#ifndef __PINCTRL_SAMSUNG_H 18#define __PINCTRL_SAMSUNG_H 19 20#include <linux/pinctrl/pinctrl.h> 21#include <linux/pinctrl/pinmux.h> 22#include <linux/pinctrl/pinconf.h> 23#include <linux/pinctrl/consumer.h> 24#include <linux/pinctrl/machine.h> 25 26#include <linux/gpio.h> 27 28/* pinmux function number for pin as gpio output line */ 29#define FUNC_INPUT 0x0 30#define FUNC_OUTPUT 0x1 31 32/** 33 * enum pincfg_type - possible pin configuration types supported. 34 * @PINCFG_TYPE_FUNC: Function configuration. 35 * @PINCFG_TYPE_DAT: Pin value configuration. 36 * @PINCFG_TYPE_PUD: Pull up/down configuration. 37 * @PINCFG_TYPE_DRV: Drive strength configuration. 38 * @PINCFG_TYPE_CON_PDN: Pin function in power down mode. 39 * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode. 40 */ 41enum pincfg_type { 42 PINCFG_TYPE_FUNC, 43 PINCFG_TYPE_DAT, 44 PINCFG_TYPE_PUD, 45 PINCFG_TYPE_DRV, 46 PINCFG_TYPE_CON_PDN, 47 PINCFG_TYPE_PUD_PDN, 48 49 PINCFG_TYPE_NUM 50}; 51 52/* 53 * pin configuration (pull up/down and drive strength) type and its value are 54 * packed together into a 16-bits. The upper 8-bits represent the configuration 55 * type and the lower 8-bits hold the value of the configuration type. 56 */ 57#define PINCFG_TYPE_MASK 0xFF 58#define PINCFG_VALUE_SHIFT 8 59#define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT) 60#define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type) 61#define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK) 62#define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \ 63 PINCFG_VALUE_SHIFT) 64/** 65 * enum eint_type - possible external interrupt types. 66 * @EINT_TYPE_NONE: bank does not support external interrupts 67 * @EINT_TYPE_GPIO: bank supportes external gpio interrupts 68 * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts 69 * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts 70 * 71 * Samsung GPIO controller groups all the available pins into banks. The pins 72 * in a pin bank can support external gpio interrupts or external wakeup 73 * interrupts or no interrupts at all. From a software perspective, the only 74 * difference between external gpio and external wakeup interrupts is that 75 * the wakeup interrupts can additionally wakeup the system if it is in 76 * suspended state. 77 */ 78enum eint_type { 79 EINT_TYPE_NONE, 80 EINT_TYPE_GPIO, 81 EINT_TYPE_WKUP, 82 EINT_TYPE_WKUP_MUX, 83}; 84 85/* maximum length of a pin in pin descriptor (example: "gpa0-0") */ 86#define PIN_NAME_LENGTH 10 87 88#define PIN_GROUP(n, p, f) \ 89 { \ 90 .name = n, \ 91 .pins = p, \ 92 .num_pins = ARRAY_SIZE(p), \ 93 .func = f \ 94 } 95 96#define PMX_FUNC(n, g) \ 97 { \ 98 .name = n, \ 99 .groups = g, \ 100 .num_groups = ARRAY_SIZE(g), \ 101 } 102 103struct samsung_pinctrl_drv_data; 104 105/** 106 * struct samsung_pin_bank_type: pin bank type description 107 * @fld_width: widths of configuration bitfields (0 if unavailable) 108 * @reg_offset: offsets of configuration registers (don't care of width is 0) 109 */ 110struct samsung_pin_bank_type { 111 u8 fld_width[PINCFG_TYPE_NUM]; 112 u8 reg_offset[PINCFG_TYPE_NUM]; 113}; 114 115/** 116 * struct samsung_pin_bank_data: represent a controller pin-bank (init data). 117 * @type: type of the bank (register offsets and bitfield widths) 118 * @pctl_offset: starting offset of the pin-bank registers. 119 * @nr_pins: number of pins included in this bank. 120 * @eint_func: function to set in CON register to configure pin as EINT. 121 * @eint_type: type of the external interrupt supported by the bank. 122 * @eint_mask: bit mask of pins which support EINT function. 123 * @eint_offset: SoC-specific EINT register or interrupt offset of bank. 124 * @name: name to be prefixed for each pin in this pin bank. 125 */ 126struct samsung_pin_bank_data { 127 const struct samsung_pin_bank_type *type; 128 u32 pctl_offset; 129 u8 nr_pins; 130 u8 eint_func; 131 enum eint_type eint_type; 132 u32 eint_mask; 133 u32 eint_offset; 134 const char *name; 135}; 136 137/** 138 * struct samsung_pin_bank: represent a controller pin-bank. 139 * @type: type of the bank (register offsets and bitfield widths) 140 * @pctl_offset: starting offset of the pin-bank registers. 141 * @nr_pins: number of pins included in this bank. 142 * @eint_func: function to set in CON register to configure pin as EINT. 143 * @eint_type: type of the external interrupt supported by the bank. 144 * @eint_mask: bit mask of pins which support EINT function. 145 * @eint_offset: SoC-specific EINT register or interrupt offset of bank. 146 * @name: name to be prefixed for each pin in this pin bank. 147 * @pin_base: starting pin number of the bank. 148 * @soc_priv: per-bank private data for SoC-specific code. 149 * @of_node: OF node of the bank. 150 * @drvdata: link to controller driver data 151 * @irq_domain: IRQ domain of the bank. 152 * @gpio_chip: GPIO chip of the bank. 153 * @grange: linux gpio pin range supported by this bank. 154 * @irq_chip: link to irq chip for external gpio and wakeup interrupts. 155 * @slock: spinlock protecting bank registers 156 * @pm_save: saved register values during suspend 157 */ 158struct samsung_pin_bank { 159 const struct samsung_pin_bank_type *type; 160 u32 pctl_offset; 161 u8 nr_pins; 162 u8 eint_func; 163 enum eint_type eint_type; 164 u32 eint_mask; 165 u32 eint_offset; 166 const char *name; 167 168 u32 pin_base; 169 void *soc_priv; 170 struct device_node *of_node; 171 struct samsung_pinctrl_drv_data *drvdata; 172 struct irq_domain *irq_domain; 173 struct gpio_chip gpio_chip; 174 struct pinctrl_gpio_range grange; 175 struct exynos_irq_chip *irq_chip; 176 spinlock_t slock; 177 178 u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/ 179}; 180 181/** 182 * struct samsung_pin_ctrl: represent a pin controller. 183 * @pin_banks: list of pin banks included in this controller. 184 * @nr_banks: number of pin banks. 185 * @eint_gpio_init: platform specific callback to setup the external gpio 186 * interrupts for the controller. 187 * @eint_wkup_init: platform specific callback to setup the external wakeup 188 * interrupts for the controller. 189 */ 190struct samsung_pin_ctrl { 191 const struct samsung_pin_bank_data *pin_banks; 192 u32 nr_banks; 193 194 int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 195 int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); 196 void (*suspend)(struct samsung_pinctrl_drv_data *); 197 void (*resume)(struct samsung_pinctrl_drv_data *); 198}; 199 200/** 201 * struct samsung_pinctrl_drv_data: wrapper for holding driver data together. 202 * @node: global list node 203 * @virt_base: register base address of the controller. 204 * @dev: device instance representing the controller. 205 * @irq: interrpt number used by the controller to notify gpio interrupts. 206 * @ctrl: pin controller instance managed by the driver. 207 * @pctl: pin controller descriptor registered with the pinctrl subsystem. 208 * @pctl_dev: cookie representing pinctrl device instance. 209 * @pin_groups: list of pin groups available to the driver. 210 * @nr_groups: number of such pin groups. 211 * @pmx_functions: list of pin functions available to the driver. 212 * @nr_function: number of such pin functions. 213 * @pin_base: starting system wide pin number. 214 * @nr_pins: number of pins supported by the controller. 215 */ 216struct samsung_pinctrl_drv_data { 217 struct list_head node; 218 void __iomem *virt_base; 219 struct device *dev; 220 int irq; 221 222 struct pinctrl_desc pctl; 223 struct pinctrl_dev *pctl_dev; 224 225 const struct samsung_pin_group *pin_groups; 226 unsigned int nr_groups; 227 const struct samsung_pmx_func *pmx_functions; 228 unsigned int nr_functions; 229 230 struct samsung_pin_bank *pin_banks; 231 u32 nr_banks; 232 unsigned int pin_base; 233 unsigned int nr_pins; 234 235 void (*suspend)(struct samsung_pinctrl_drv_data *); 236 void (*resume)(struct samsung_pinctrl_drv_data *); 237}; 238 239/** 240 * struct samsung_pin_group: represent group of pins of a pinmux function. 241 * @name: name of the pin group, used to lookup the group. 242 * @pins: the pins included in this group. 243 * @num_pins: number of pins included in this group. 244 * @func: the function number to be programmed when selected. 245 */ 246struct samsung_pin_group { 247 const char *name; 248 const unsigned int *pins; 249 u8 num_pins; 250 u8 func; 251}; 252 253/** 254 * struct samsung_pmx_func: represent a pin function. 255 * @name: name of the pin function, used to lookup the function. 256 * @groups: one or more names of pin groups that provide this function. 257 * @num_groups: number of groups included in @groups. 258 */ 259struct samsung_pmx_func { 260 const char *name; 261 const char **groups; 262 u8 num_groups; 263 u32 val; 264}; 265 266/* list of all exported SoC specific data */ 267extern const struct samsung_pin_ctrl exynos3250_pin_ctrl[]; 268extern const struct samsung_pin_ctrl exynos4210_pin_ctrl[]; 269extern const struct samsung_pin_ctrl exynos4x12_pin_ctrl[]; 270extern const struct samsung_pin_ctrl exynos4415_pin_ctrl[]; 271extern const struct samsung_pin_ctrl exynos5250_pin_ctrl[]; 272extern const struct samsung_pin_ctrl exynos5260_pin_ctrl[]; 273extern const struct samsung_pin_ctrl exynos5410_pin_ctrl[]; 274extern const struct samsung_pin_ctrl exynos5420_pin_ctrl[]; 275extern const struct samsung_pin_ctrl exynos5433_pin_ctrl[]; 276extern const struct samsung_pin_ctrl exynos7_pin_ctrl[]; 277extern const struct samsung_pin_ctrl s3c64xx_pin_ctrl[]; 278extern const struct samsung_pin_ctrl s3c2412_pin_ctrl[]; 279extern const struct samsung_pin_ctrl s3c2416_pin_ctrl[]; 280extern const struct samsung_pin_ctrl s3c2440_pin_ctrl[]; 281extern const struct samsung_pin_ctrl s3c2450_pin_ctrl[]; 282extern const struct samsung_pin_ctrl s5pv210_pin_ctrl[]; 283 284#endif /* __PINCTRL_SAMSUNG_H */ 285