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49#include <linux/module.h>
50#include <linux/interrupt.h>
51#include <linux/kernel.h>
52#include <linux/spinlock.h>
53#include <linux/miscdevice.h>
54#include <linux/platform_device.h>
55#include <linux/poll.h>
56#include <linux/sched.h>
57#include <linux/bitops.h>
58#include <linux/slab.h>
59#include <linux/io.h>
60#include <linux/goldfish.h>
61#include <linux/dma-mapping.h>
62#include <linux/mm.h>
63#include <linux/acpi.h>
64
65
66
67
68
69
70
71#define PIPE_REG_COMMAND 0x00
72#define PIPE_REG_STATUS 0x04
73#define PIPE_REG_CHANNEL 0x08
74#define PIPE_REG_CHANNEL_HIGH 0x30
75#define PIPE_REG_SIZE 0x0c
76#define PIPE_REG_ADDRESS 0x10
77#define PIPE_REG_ADDRESS_HIGH 0x34
78#define PIPE_REG_WAKES 0x14
79#define PIPE_REG_PARAMS_ADDR_LOW 0x18
80#define PIPE_REG_PARAMS_ADDR_HIGH 0x1c
81#define PIPE_REG_ACCESS_PARAMS 0x20
82#define PIPE_REG_VERSION 0x24
83
84
85#define CMD_OPEN 1
86#define CMD_CLOSE 2
87#define CMD_POLL 3
88
89
90#define PIPE_POLL_IN (1 << 0)
91#define PIPE_POLL_OUT (1 << 1)
92#define PIPE_POLL_HUP (1 << 2)
93
94
95#define CMD_WRITE_BUFFER 4
96#define CMD_WAKE_ON_WRITE 5
97
98#define CMD_READ_BUFFER 6
99#define CMD_WAKE_ON_READ 7
100
101
102
103#define PIPE_ERROR_INVAL -1
104#define PIPE_ERROR_AGAIN -2
105#define PIPE_ERROR_NOMEM -3
106#define PIPE_ERROR_IO -4
107
108
109#define PIPE_WAKE_CLOSED (1 << 0)
110#define PIPE_WAKE_READ (1 << 1)
111#define PIPE_WAKE_WRITE (1 << 2)
112
113struct access_params {
114 unsigned long channel;
115 u32 size;
116 unsigned long address;
117 u32 cmd;
118 u32 result;
119
120 u32 flags;
121};
122
123
124
125
126
127struct goldfish_pipe_dev {
128 spinlock_t lock;
129 unsigned char __iomem *base;
130 struct access_params *aps;
131 int irq;
132 u32 version;
133};
134
135static struct goldfish_pipe_dev pipe_dev[1];
136
137
138struct goldfish_pipe {
139 struct goldfish_pipe_dev *dev;
140 struct mutex lock;
141 unsigned long flags;
142 wait_queue_head_t wake_queue;
143};
144
145
146
147enum {
148 BIT_CLOSED_ON_HOST = 0,
149 BIT_WAKE_ON_WRITE = 1,
150 BIT_WAKE_ON_READ = 2,
151};
152
153
154static u32 goldfish_cmd_status(struct goldfish_pipe *pipe, u32 cmd)
155{
156 unsigned long flags;
157 u32 status;
158 struct goldfish_pipe_dev *dev = pipe->dev;
159
160 spin_lock_irqsave(&dev->lock, flags);
161 gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
162 dev->base + PIPE_REG_CHANNEL_HIGH);
163 writel(cmd, dev->base + PIPE_REG_COMMAND);
164 status = readl(dev->base + PIPE_REG_STATUS);
165 spin_unlock_irqrestore(&dev->lock, flags);
166 return status;
167}
168
169static void goldfish_cmd(struct goldfish_pipe *pipe, u32 cmd)
170{
171 unsigned long flags;
172 struct goldfish_pipe_dev *dev = pipe->dev;
173
174 spin_lock_irqsave(&dev->lock, flags);
175 gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
176 dev->base + PIPE_REG_CHANNEL_HIGH);
177 writel(cmd, dev->base + PIPE_REG_COMMAND);
178 spin_unlock_irqrestore(&dev->lock, flags);
179}
180
181
182
183
184static int goldfish_pipe_error_convert(int status)
185{
186 switch (status) {
187 case PIPE_ERROR_AGAIN:
188 return -EAGAIN;
189 case PIPE_ERROR_NOMEM:
190 return -ENOMEM;
191 case PIPE_ERROR_IO:
192 return -EIO;
193 default:
194 return -EINVAL;
195 }
196}
197
198
199
200
201
202static int valid_batchbuffer_addr(struct goldfish_pipe_dev *dev,
203 struct access_params *aps)
204{
205 u32 aph, apl;
206 u64 paddr;
207 aph = readl(dev->base + PIPE_REG_PARAMS_ADDR_HIGH);
208 apl = readl(dev->base + PIPE_REG_PARAMS_ADDR_LOW);
209
210 paddr = ((u64)aph << 32) | apl;
211 if (paddr != (__pa(aps)))
212 return 0;
213 return 1;
214}
215
216
217static int setup_access_params_addr(struct platform_device *pdev,
218 struct goldfish_pipe_dev *dev)
219{
220 dma_addr_t dma_handle;
221 struct access_params *aps;
222
223 aps = dmam_alloc_coherent(&pdev->dev, sizeof(struct access_params),
224 &dma_handle, GFP_KERNEL);
225 if (!aps)
226 return -ENOMEM;
227
228 writel(upper_32_bits(dma_handle), dev->base + PIPE_REG_PARAMS_ADDR_HIGH);
229 writel(lower_32_bits(dma_handle), dev->base + PIPE_REG_PARAMS_ADDR_LOW);
230
231 if (valid_batchbuffer_addr(dev, aps)) {
232 dev->aps = aps;
233 return 0;
234 } else
235 return -1;
236}
237
238
239#define INITIAL_BATCH_RESULT (0xdeadbeaf)
240static int access_with_param(struct goldfish_pipe_dev *dev, const int cmd,
241 unsigned long address, unsigned long avail,
242 struct goldfish_pipe *pipe, int *status)
243{
244 struct access_params *aps = dev->aps;
245
246 if (aps == NULL)
247 return -1;
248
249 aps->result = INITIAL_BATCH_RESULT;
250 aps->channel = (unsigned long)pipe;
251 aps->size = avail;
252 aps->address = address;
253 aps->cmd = cmd;
254 writel(cmd, dev->base + PIPE_REG_ACCESS_PARAMS);
255
256
257
258
259 if (aps->result == INITIAL_BATCH_RESULT)
260 return -1;
261 *status = aps->result;
262 return 0;
263}
264
265static ssize_t goldfish_pipe_read_write(struct file *filp, char __user *buffer,
266 size_t bufflen, int is_write)
267{
268 unsigned long irq_flags;
269 struct goldfish_pipe *pipe = filp->private_data;
270 struct goldfish_pipe_dev *dev = pipe->dev;
271 unsigned long address, address_end;
272 int count = 0, ret = -EINVAL;
273
274
275 if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
276 return -EIO;
277
278
279 if (unlikely(bufflen == 0))
280 return 0;
281
282
283 if (!access_ok(is_write ? VERIFY_WRITE : VERIFY_READ,
284 buffer, bufflen))
285 return -EFAULT;
286
287
288 if (mutex_lock_interruptible(&pipe->lock))
289 return -ERESTARTSYS;
290
291 address = (unsigned long)(void *)buffer;
292 address_end = address + bufflen;
293
294 while (address < address_end) {
295 unsigned long page_end = (address & PAGE_MASK) + PAGE_SIZE;
296 unsigned long next = page_end < address_end ? page_end
297 : address_end;
298 unsigned long avail = next - address;
299 int status, wakeBit;
300 struct page *page;
301
302
303 unsigned long xaddr;
304
305
306
307
308
309
310
311 down_read(¤t->mm->mmap_sem);
312 ret = get_user_pages(address, 1, !is_write, 0, &page, NULL);
313 up_read(¤t->mm->mmap_sem);
314 if (ret < 0)
315 break;
316
317 if (dev->version) {
318
319
320
321 xaddr = page_to_phys(page) | (address & ~PAGE_MASK);
322 } else {
323
324
325
326 xaddr = address;
327 }
328
329
330 spin_lock_irqsave(&dev->lock, irq_flags);
331 if (access_with_param(dev,
332 is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER,
333 xaddr, avail, pipe, &status)) {
334 gf_write_ptr(pipe, dev->base + PIPE_REG_CHANNEL,
335 dev->base + PIPE_REG_CHANNEL_HIGH);
336 writel(avail, dev->base + PIPE_REG_SIZE);
337 gf_write_ptr((void *)xaddr,
338 dev->base + PIPE_REG_ADDRESS,
339 dev->base + PIPE_REG_ADDRESS_HIGH);
340 writel(is_write ? CMD_WRITE_BUFFER : CMD_READ_BUFFER,
341 dev->base + PIPE_REG_COMMAND);
342 status = readl(dev->base + PIPE_REG_STATUS);
343 }
344 spin_unlock_irqrestore(&dev->lock, irq_flags);
345
346 if (status > 0 && !is_write)
347 set_page_dirty(page);
348 put_page(page);
349
350 if (status > 0) {
351 count += status;
352 address += status;
353 continue;
354 } else if (status == 0) {
355 ret = 0;
356 break;
357 } else if (status < 0 && count > 0) {
358
359
360
361
362
363
364
365
366
367
368 if (status != PIPE_ERROR_AGAIN)
369 pr_info_ratelimited("goldfish_pipe: backend returned error %d on %s\n",
370 status, is_write ? "write" : "read");
371 ret = 0;
372 break;
373 }
374
375
376
377
378
379 if (status != PIPE_ERROR_AGAIN ||
380 (filp->f_flags & O_NONBLOCK) != 0) {
381 ret = goldfish_pipe_error_convert(status);
382 break;
383 }
384
385
386
387
388
389 wakeBit = is_write ? BIT_WAKE_ON_WRITE : BIT_WAKE_ON_READ;
390 set_bit(wakeBit, &pipe->flags);
391
392
393 goldfish_cmd(pipe,
394 is_write ? CMD_WAKE_ON_WRITE : CMD_WAKE_ON_READ);
395
396
397 mutex_unlock(&pipe->lock);
398
399 while (test_bit(wakeBit, &pipe->flags)) {
400 if (wait_event_interruptible(
401 pipe->wake_queue,
402 !test_bit(wakeBit, &pipe->flags)))
403 return -ERESTARTSYS;
404
405 if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
406 return -EIO;
407 }
408
409
410 if (mutex_lock_interruptible(&pipe->lock))
411 return -ERESTARTSYS;
412 }
413 mutex_unlock(&pipe->lock);
414
415 if (ret < 0)
416 return ret;
417 else
418 return count;
419}
420
421static ssize_t goldfish_pipe_read(struct file *filp, char __user *buffer,
422 size_t bufflen, loff_t *ppos)
423{
424 return goldfish_pipe_read_write(filp, buffer, bufflen, 0);
425}
426
427static ssize_t goldfish_pipe_write(struct file *filp,
428 const char __user *buffer, size_t bufflen,
429 loff_t *ppos)
430{
431 return goldfish_pipe_read_write(filp, (char __user *)buffer,
432 bufflen, 1);
433}
434
435
436static unsigned int goldfish_pipe_poll(struct file *filp, poll_table *wait)
437{
438 struct goldfish_pipe *pipe = filp->private_data;
439 unsigned int mask = 0;
440 int status;
441
442 mutex_lock(&pipe->lock);
443
444 poll_wait(filp, &pipe->wake_queue, wait);
445
446 status = goldfish_cmd_status(pipe, CMD_POLL);
447
448 mutex_unlock(&pipe->lock);
449
450 if (status & PIPE_POLL_IN)
451 mask |= POLLIN | POLLRDNORM;
452
453 if (status & PIPE_POLL_OUT)
454 mask |= POLLOUT | POLLWRNORM;
455
456 if (status & PIPE_POLL_HUP)
457 mask |= POLLHUP;
458
459 if (test_bit(BIT_CLOSED_ON_HOST, &pipe->flags))
460 mask |= POLLERR;
461
462 return mask;
463}
464
465static irqreturn_t goldfish_pipe_interrupt(int irq, void *dev_id)
466{
467 struct goldfish_pipe_dev *dev = dev_id;
468 unsigned long irq_flags;
469 int count = 0;
470
471
472
473
474
475
476 spin_lock_irqsave(&dev->lock, irq_flags);
477 for (;;) {
478
479 struct goldfish_pipe *pipe;
480 unsigned long wakes;
481 unsigned long channel = 0;
482
483#ifdef CONFIG_64BIT
484 channel = (u64)readl(dev->base + PIPE_REG_CHANNEL_HIGH) << 32;
485
486 if (channel == 0)
487 break;
488#endif
489 channel |= readl(dev->base + PIPE_REG_CHANNEL);
490
491 if (channel == 0)
492 break;
493
494
495 wakes = readl(dev->base + PIPE_REG_WAKES);
496 pipe = (struct goldfish_pipe *)(ptrdiff_t)channel;
497
498
499 if (wakes & PIPE_WAKE_CLOSED) {
500 set_bit(BIT_CLOSED_ON_HOST, &pipe->flags);
501 wakes |= PIPE_WAKE_READ | PIPE_WAKE_WRITE;
502 }
503 if (wakes & PIPE_WAKE_READ)
504 clear_bit(BIT_WAKE_ON_READ, &pipe->flags);
505 if (wakes & PIPE_WAKE_WRITE)
506 clear_bit(BIT_WAKE_ON_WRITE, &pipe->flags);
507
508 wake_up_interruptible(&pipe->wake_queue);
509 count++;
510 }
511 spin_unlock_irqrestore(&dev->lock, irq_flags);
512
513 return (count == 0) ? IRQ_NONE : IRQ_HANDLED;
514}
515
516
517
518
519
520
521
522
523
524
525
526
527static int goldfish_pipe_open(struct inode *inode, struct file *file)
528{
529 struct goldfish_pipe *pipe;
530 struct goldfish_pipe_dev *dev = pipe_dev;
531 int32_t status;
532
533
534 pipe = kzalloc(sizeof(*pipe), GFP_KERNEL);
535 if (pipe == NULL)
536 return -ENOMEM;
537
538 pipe->dev = dev;
539 mutex_init(&pipe->lock);
540 init_waitqueue_head(&pipe->wake_queue);
541
542
543
544
545
546
547 status = goldfish_cmd_status(pipe, CMD_OPEN);
548 if (status < 0) {
549 kfree(pipe);
550 return status;
551 }
552
553
554 file->private_data = pipe;
555 return 0;
556}
557
558static int goldfish_pipe_release(struct inode *inode, struct file *filp)
559{
560 struct goldfish_pipe *pipe = filp->private_data;
561
562
563 goldfish_cmd(pipe, CMD_CLOSE);
564 kfree(pipe);
565 filp->private_data = NULL;
566 return 0;
567}
568
569static const struct file_operations goldfish_pipe_fops = {
570 .owner = THIS_MODULE,
571 .read = goldfish_pipe_read,
572 .write = goldfish_pipe_write,
573 .poll = goldfish_pipe_poll,
574 .open = goldfish_pipe_open,
575 .release = goldfish_pipe_release,
576};
577
578static struct miscdevice goldfish_pipe_device = {
579 .minor = MISC_DYNAMIC_MINOR,
580 .name = "goldfish_pipe",
581 .fops = &goldfish_pipe_fops,
582};
583
584static int goldfish_pipe_probe(struct platform_device *pdev)
585{
586 int err;
587 struct resource *r;
588 struct goldfish_pipe_dev *dev = pipe_dev;
589
590
591 WARN_ON(dev->base != NULL);
592
593 spin_lock_init(&dev->lock);
594
595 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
596 if (r == NULL || resource_size(r) < PAGE_SIZE) {
597 dev_err(&pdev->dev, "can't allocate i/o page\n");
598 return -EINVAL;
599 }
600 dev->base = devm_ioremap(&pdev->dev, r->start, PAGE_SIZE);
601 if (dev->base == NULL) {
602 dev_err(&pdev->dev, "ioremap failed\n");
603 return -EINVAL;
604 }
605
606 r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
607 if (r == NULL) {
608 err = -EINVAL;
609 goto error;
610 }
611 dev->irq = r->start;
612
613 err = devm_request_irq(&pdev->dev, dev->irq, goldfish_pipe_interrupt,
614 IRQF_SHARED, "goldfish_pipe", dev);
615 if (err) {
616 dev_err(&pdev->dev, "unable to allocate IRQ\n");
617 goto error;
618 }
619
620 err = misc_register(&goldfish_pipe_device);
621 if (err) {
622 dev_err(&pdev->dev, "unable to register device\n");
623 goto error;
624 }
625 setup_access_params_addr(pdev, dev);
626
627
628
629
630
631 dev->version = readl(dev->base + PIPE_REG_VERSION);
632 return 0;
633
634error:
635 dev->base = NULL;
636 return err;
637}
638
639static int goldfish_pipe_remove(struct platform_device *pdev)
640{
641 struct goldfish_pipe_dev *dev = pipe_dev;
642 misc_deregister(&goldfish_pipe_device);
643 dev->base = NULL;
644 return 0;
645}
646
647static const struct acpi_device_id goldfish_pipe_acpi_match[] = {
648 { "GFSH0003", 0 },
649 { },
650};
651MODULE_DEVICE_TABLE(acpi, goldfish_pipe_acpi_match);
652
653static const struct of_device_id goldfish_pipe_of_match[] = {
654 { .compatible = "google,android-pipe", },
655 {},
656};
657MODULE_DEVICE_TABLE(of, goldfish_pipe_of_match);
658
659static struct platform_driver goldfish_pipe = {
660 .probe = goldfish_pipe_probe,
661 .remove = goldfish_pipe_remove,
662 .driver = {
663 .name = "goldfish_pipe",
664 .owner = THIS_MODULE,
665 .of_match_table = goldfish_pipe_of_match,
666 .acpi_match_table = ACPI_PTR(goldfish_pipe_acpi_match),
667 }
668};
669
670module_platform_driver(goldfish_pipe);
671MODULE_AUTHOR("David Turner <digit@google.com>");
672MODULE_LICENSE("GPL");
673