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11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/bcd.h>
14#include <linux/slab.h>
15#include <linux/rtc.h>
16#include <linux/workqueue.h>
17
18#include <linux/spi/spi.h>
19#include <linux/spi/ds1305.h>
20#include <linux/module.h>
21
22
23
24
25
26
27#define DS1305_WRITE 0x80
28
29
30
31
32
33
34
35#define DS1305_RTC_LEN 7
36
37#define DS1305_SEC 0x00
38#define DS1305_MIN 0x01
39#define DS1305_HOUR 0x02
40# define DS1305_HR_12 0x40
41# define DS1305_HR_PM 0x20
42#define DS1305_WDAY 0x03
43#define DS1305_MDAY 0x04
44#define DS1305_MON 0x05
45#define DS1305_YEAR 0x06
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60#define DS1305_ALM_LEN 4
61#define DS1305_ALM_DISABLE 0x80
62
63#define DS1305_ALM0(r) (0x07 + (r))
64#define DS1305_ALM1(r) (0x0b + (r))
65
66
67
68#define DS1305_CONTROL_LEN 3
69
70#define DS1305_CONTROL 0x0f
71# define DS1305_nEOSC 0x80
72# define DS1305_WP 0x40
73# define DS1305_INTCN 0x04
74# define DS1306_1HZ 0x04
75# define DS1305_AEI1 0x02
76# define DS1305_AEI0 0x01
77#define DS1305_STATUS 0x10
78
79#define DS1305_TRICKLE 0x11
80
81
82
83#define DS1305_NVRAM_LEN 96
84
85#define DS1305_NVRAM 0x20
86
87
88struct ds1305 {
89 struct spi_device *spi;
90 struct rtc_device *rtc;
91
92 struct work_struct work;
93
94 unsigned long flags;
95#define FLAG_EXITING 0
96
97 bool hr12;
98 u8 ctrl[DS1305_CONTROL_LEN];
99};
100
101
102
103
104
105
106
107
108
109static unsigned bcd2hour(u8 bcd)
110{
111 if (bcd & DS1305_HR_12) {
112 unsigned hour = 0;
113
114 bcd &= ~DS1305_HR_12;
115 if (bcd & DS1305_HR_PM) {
116 hour = 12;
117 bcd &= ~DS1305_HR_PM;
118 }
119 hour += bcd2bin(bcd);
120 return hour - 1;
121 }
122 return bcd2bin(bcd);
123}
124
125static u8 hour2bcd(bool hr12, int hour)
126{
127 if (hr12) {
128 hour++;
129 if (hour <= 12)
130 return DS1305_HR_12 | bin2bcd(hour);
131 hour -= 12;
132 return DS1305_HR_12 | DS1305_HR_PM | bin2bcd(hour);
133 }
134 return bin2bcd(hour);
135}
136
137
138
139
140
141
142
143static int ds1305_alarm_irq_enable(struct device *dev, unsigned int enabled)
144{
145 struct ds1305 *ds1305 = dev_get_drvdata(dev);
146 u8 buf[2];
147 long err = -EINVAL;
148
149 buf[0] = DS1305_WRITE | DS1305_CONTROL;
150 buf[1] = ds1305->ctrl[0];
151
152 if (enabled) {
153 if (ds1305->ctrl[0] & DS1305_AEI0)
154 goto done;
155 buf[1] |= DS1305_AEI0;
156 } else {
157 if (!(buf[1] & DS1305_AEI0))
158 goto done;
159 buf[1] &= ~DS1305_AEI0;
160 }
161 err = spi_write_then_read(ds1305->spi, buf, sizeof(buf), NULL, 0);
162 if (err >= 0)
163 ds1305->ctrl[0] = buf[1];
164done:
165 return err;
166
167}
168
169
170
171
172
173
174static int ds1305_get_time(struct device *dev, struct rtc_time *time)
175{
176 struct ds1305 *ds1305 = dev_get_drvdata(dev);
177 u8 addr = DS1305_SEC;
178 u8 buf[DS1305_RTC_LEN];
179 int status;
180
181
182
183
184 status = spi_write_then_read(ds1305->spi, &addr, sizeof(addr),
185 buf, sizeof(buf));
186 if (status < 0)
187 return status;
188
189 dev_vdbg(dev, "%s: %3ph, %4ph\n", "read", &buf[0], &buf[3]);
190
191
192 time->tm_sec = bcd2bin(buf[DS1305_SEC]);
193 time->tm_min = bcd2bin(buf[DS1305_MIN]);
194 time->tm_hour = bcd2hour(buf[DS1305_HOUR]);
195 time->tm_wday = buf[DS1305_WDAY] - 1;
196 time->tm_mday = bcd2bin(buf[DS1305_MDAY]);
197 time->tm_mon = bcd2bin(buf[DS1305_MON]) - 1;
198 time->tm_year = bcd2bin(buf[DS1305_YEAR]) + 100;
199
200 dev_vdbg(dev, "%s secs=%d, mins=%d, "
201 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
202 "read", time->tm_sec, time->tm_min,
203 time->tm_hour, time->tm_mday,
204 time->tm_mon, time->tm_year, time->tm_wday);
205
206
207 return rtc_valid_tm(time);
208}
209
210static int ds1305_set_time(struct device *dev, struct rtc_time *time)
211{
212 struct ds1305 *ds1305 = dev_get_drvdata(dev);
213 u8 buf[1 + DS1305_RTC_LEN];
214 u8 *bp = buf;
215
216 dev_vdbg(dev, "%s secs=%d, mins=%d, "
217 "hours=%d, mday=%d, mon=%d, year=%d, wday=%d\n",
218 "write", time->tm_sec, time->tm_min,
219 time->tm_hour, time->tm_mday,
220 time->tm_mon, time->tm_year, time->tm_wday);
221
222
223 *bp++ = DS1305_WRITE | DS1305_SEC;
224
225 *bp++ = bin2bcd(time->tm_sec);
226 *bp++ = bin2bcd(time->tm_min);
227 *bp++ = hour2bcd(ds1305->hr12, time->tm_hour);
228 *bp++ = (time->tm_wday < 7) ? (time->tm_wday + 1) : 1;
229 *bp++ = bin2bcd(time->tm_mday);
230 *bp++ = bin2bcd(time->tm_mon + 1);
231 *bp++ = bin2bcd(time->tm_year - 100);
232
233 dev_dbg(dev, "%s: %3ph, %4ph\n", "write", &buf[1], &buf[4]);
234
235
236 return spi_write_then_read(ds1305->spi, buf, sizeof(buf),
237 NULL, 0);
238}
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270
271static int ds1305_get_alarm(struct device *dev, struct rtc_wkalrm *alm)
272{
273 struct ds1305 *ds1305 = dev_get_drvdata(dev);
274 struct spi_device *spi = ds1305->spi;
275 u8 addr;
276 int status;
277 u8 buf[DS1305_ALM_LEN];
278
279
280
281
282
283
284 addr = DS1305_CONTROL;
285 status = spi_write_then_read(spi, &addr, sizeof(addr),
286 ds1305->ctrl, sizeof(ds1305->ctrl));
287 if (status < 0)
288 return status;
289
290 alm->enabled = !!(ds1305->ctrl[0] & DS1305_AEI0);
291 alm->pending = !!(ds1305->ctrl[1] & DS1305_AEI0);
292
293
294 addr = DS1305_ALM0(DS1305_SEC);
295 status = spi_write_then_read(spi, &addr, sizeof(addr),
296 buf, sizeof(buf));
297 if (status < 0)
298 return status;
299
300 dev_vdbg(dev, "%s: %02x %02x %02x %02x\n",
301 "alm0 read", buf[DS1305_SEC], buf[DS1305_MIN],
302 buf[DS1305_HOUR], buf[DS1305_WDAY]);
303
304 if ((DS1305_ALM_DISABLE & buf[DS1305_SEC])
305 || (DS1305_ALM_DISABLE & buf[DS1305_MIN])
306 || (DS1305_ALM_DISABLE & buf[DS1305_HOUR]))
307 return -EIO;
308
309
310
311
312
313 alm->time.tm_sec = bcd2bin(buf[DS1305_SEC]);
314 alm->time.tm_min = bcd2bin(buf[DS1305_MIN]);
315 alm->time.tm_hour = bcd2hour(buf[DS1305_HOUR]);
316 alm->time.tm_mday = -1;
317 alm->time.tm_mon = -1;
318 alm->time.tm_year = -1;
319
320 alm->time.tm_wday = -1;
321 alm->time.tm_mday = -1;
322 alm->time.tm_isdst = -1;
323
324 return 0;
325}
326
327
328
329
330static int ds1305_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
331{
332 struct ds1305 *ds1305 = dev_get_drvdata(dev);
333 struct spi_device *spi = ds1305->spi;
334 unsigned long now, later;
335 struct rtc_time tm;
336 int status;
337 u8 buf[1 + DS1305_ALM_LEN];
338
339
340 status = rtc_tm_to_time(&alm->time, &later);
341 if (status < 0)
342 return status;
343
344
345 status = ds1305_get_time(dev, &tm);
346 if (status < 0)
347 return status;
348 status = rtc_tm_to_time(&tm, &now);
349 if (status < 0)
350 return status;
351
352
353 if (later <= now)
354 return -EINVAL;
355 if ((later - now) > 24 * 60 * 60)
356 return -EDOM;
357
358
359 if (ds1305->ctrl[0] & DS1305_AEI0) {
360 ds1305->ctrl[0] &= ~DS1305_AEI0;
361
362 buf[0] = DS1305_WRITE | DS1305_CONTROL;
363 buf[1] = ds1305->ctrl[0];
364 status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
365 if (status < 0)
366 return status;
367 }
368
369
370 buf[0] = DS1305_WRITE | DS1305_ALM0(DS1305_SEC);
371 buf[1 + DS1305_SEC] = bin2bcd(alm->time.tm_sec);
372 buf[1 + DS1305_MIN] = bin2bcd(alm->time.tm_min);
373 buf[1 + DS1305_HOUR] = hour2bcd(ds1305->hr12, alm->time.tm_hour);
374 buf[1 + DS1305_WDAY] = DS1305_ALM_DISABLE;
375
376 dev_dbg(dev, "%s: %02x %02x %02x %02x\n",
377 "alm0 write", buf[1 + DS1305_SEC], buf[1 + DS1305_MIN],
378 buf[1 + DS1305_HOUR], buf[1 + DS1305_WDAY]);
379
380 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
381 if (status < 0)
382 return status;
383
384
385 if (alm->enabled) {
386 ds1305->ctrl[0] |= DS1305_AEI0;
387
388 buf[0] = DS1305_WRITE | DS1305_CONTROL;
389 buf[1] = ds1305->ctrl[0];
390 status = spi_write_then_read(ds1305->spi, buf, 2, NULL, 0);
391 }
392
393 return status;
394}
395
396#ifdef CONFIG_PROC_FS
397
398static int ds1305_proc(struct device *dev, struct seq_file *seq)
399{
400 struct ds1305 *ds1305 = dev_get_drvdata(dev);
401 char *diodes = "no";
402 char *resistors = "";
403
404
405 if ((ds1305->ctrl[2] & 0xf0) == DS1305_TRICKLE_MAGIC) {
406 switch (ds1305->ctrl[2] & 0x0c) {
407 case DS1305_TRICKLE_DS2:
408 diodes = "2 diodes, ";
409 break;
410 case DS1305_TRICKLE_DS1:
411 diodes = "1 diode, ";
412 break;
413 default:
414 goto done;
415 }
416 switch (ds1305->ctrl[2] & 0x03) {
417 case DS1305_TRICKLE_2K:
418 resistors = "2k Ohm";
419 break;
420 case DS1305_TRICKLE_4K:
421 resistors = "4k Ohm";
422 break;
423 case DS1305_TRICKLE_8K:
424 resistors = "8k Ohm";
425 break;
426 default:
427 diodes = "no";
428 break;
429 }
430 }
431
432done:
433 seq_printf(seq, "trickle_charge\t: %s%s\n", diodes, resistors);
434
435 return 0;
436}
437
438#else
439#define ds1305_proc NULL
440#endif
441
442static const struct rtc_class_ops ds1305_ops = {
443 .read_time = ds1305_get_time,
444 .set_time = ds1305_set_time,
445 .read_alarm = ds1305_get_alarm,
446 .set_alarm = ds1305_set_alarm,
447 .proc = ds1305_proc,
448 .alarm_irq_enable = ds1305_alarm_irq_enable,
449};
450
451static void ds1305_work(struct work_struct *work)
452{
453 struct ds1305 *ds1305 = container_of(work, struct ds1305, work);
454 struct mutex *lock = &ds1305->rtc->ops_lock;
455 struct spi_device *spi = ds1305->spi;
456 u8 buf[3];
457 int status;
458
459
460 mutex_lock(lock);
461
462
463
464
465
466 ds1305->ctrl[0] &= ~(DS1305_AEI1 | DS1305_AEI0);
467 ds1305->ctrl[1] = 0;
468
469 buf[0] = DS1305_WRITE | DS1305_CONTROL;
470 buf[1] = ds1305->ctrl[0];
471 buf[2] = 0;
472
473 status = spi_write_then_read(spi, buf, sizeof(buf),
474 NULL, 0);
475 if (status < 0)
476 dev_dbg(&spi->dev, "clear irq --> %d\n", status);
477
478 mutex_unlock(lock);
479
480 if (!test_bit(FLAG_EXITING, &ds1305->flags))
481 enable_irq(spi->irq);
482
483 rtc_update_irq(ds1305->rtc, 1, RTC_AF | RTC_IRQF);
484}
485
486
487
488
489
490
491static irqreturn_t ds1305_irq(int irq, void *p)
492{
493 struct ds1305 *ds1305 = p;
494
495 disable_irq(irq);
496 schedule_work(&ds1305->work);
497 return IRQ_HANDLED;
498}
499
500
501
502
503
504
505
506static void msg_init(struct spi_message *m, struct spi_transfer *x,
507 u8 *addr, size_t count, char *tx, char *rx)
508{
509 spi_message_init(m);
510 memset(x, 0, 2 * sizeof(*x));
511
512 x->tx_buf = addr;
513 x->len = 1;
514 spi_message_add_tail(x, m);
515
516 x++;
517
518 x->tx_buf = tx;
519 x->rx_buf = rx;
520 x->len = count;
521 spi_message_add_tail(x, m);
522}
523
524static ssize_t
525ds1305_nvram_read(struct file *filp, struct kobject *kobj,
526 struct bin_attribute *attr,
527 char *buf, loff_t off, size_t count)
528{
529 struct spi_device *spi;
530 u8 addr;
531 struct spi_message m;
532 struct spi_transfer x[2];
533 int status;
534
535 spi = to_spi_device(kobj_to_dev(kobj));
536
537 addr = DS1305_NVRAM + off;
538 msg_init(&m, x, &addr, count, NULL, buf);
539
540 status = spi_sync(spi, &m);
541 if (status < 0)
542 dev_err(&spi->dev, "nvram %s error %d\n", "read", status);
543 return (status < 0) ? status : count;
544}
545
546static ssize_t
547ds1305_nvram_write(struct file *filp, struct kobject *kobj,
548 struct bin_attribute *attr,
549 char *buf, loff_t off, size_t count)
550{
551 struct spi_device *spi;
552 u8 addr;
553 struct spi_message m;
554 struct spi_transfer x[2];
555 int status;
556
557 spi = to_spi_device(kobj_to_dev(kobj));
558
559 addr = (DS1305_WRITE | DS1305_NVRAM) + off;
560 msg_init(&m, x, &addr, count, buf, NULL);
561
562 status = spi_sync(spi, &m);
563 if (status < 0)
564 dev_err(&spi->dev, "nvram %s error %d\n", "write", status);
565 return (status < 0) ? status : count;
566}
567
568static struct bin_attribute nvram = {
569 .attr.name = "nvram",
570 .attr.mode = S_IRUGO | S_IWUSR,
571 .read = ds1305_nvram_read,
572 .write = ds1305_nvram_write,
573 .size = DS1305_NVRAM_LEN,
574};
575
576
577
578
579
580
581
582static int ds1305_probe(struct spi_device *spi)
583{
584 struct ds1305 *ds1305;
585 int status;
586 u8 addr, value;
587 struct ds1305_platform_data *pdata = dev_get_platdata(&spi->dev);
588 bool write_ctrl = false;
589
590
591
592
593
594 if ((spi->bits_per_word && spi->bits_per_word != 8)
595 || (spi->max_speed_hz > 2000000)
596 || !(spi->mode & SPI_CPHA))
597 return -EINVAL;
598
599
600 ds1305 = devm_kzalloc(&spi->dev, sizeof(*ds1305), GFP_KERNEL);
601 if (!ds1305)
602 return -ENOMEM;
603 ds1305->spi = spi;
604 spi_set_drvdata(spi, ds1305);
605
606
607 addr = DS1305_CONTROL;
608 status = spi_write_then_read(spi, &addr, sizeof(addr),
609 ds1305->ctrl, sizeof(ds1305->ctrl));
610 if (status < 0) {
611 dev_dbg(&spi->dev, "can't %s, %d\n",
612 "read", status);
613 return status;
614 }
615
616 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "read", ds1305->ctrl);
617
618
619
620
621
622
623 if ((ds1305->ctrl[0] & 0x38) != 0 || (ds1305->ctrl[1] & 0xfc) != 0) {
624 dev_dbg(&spi->dev, "RTC chip is not present\n");
625 return -ENODEV;
626 }
627 if (ds1305->ctrl[2] == 0)
628 dev_dbg(&spi->dev, "chip may not be present\n");
629
630
631
632
633 if (ds1305->ctrl[0] & DS1305_WP) {
634 u8 buf[2];
635
636 ds1305->ctrl[0] &= ~DS1305_WP;
637
638 buf[0] = DS1305_WRITE | DS1305_CONTROL;
639 buf[1] = ds1305->ctrl[0];
640 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
641
642 dev_dbg(&spi->dev, "clear WP --> %d\n", status);
643 if (status < 0)
644 return status;
645 }
646
647
648
649
650 if (ds1305->ctrl[0] & DS1305_nEOSC) {
651 ds1305->ctrl[0] &= ~DS1305_nEOSC;
652 write_ctrl = true;
653 dev_warn(&spi->dev, "SET TIME!\n");
654 }
655
656
657 if (ds1305->ctrl[1]) {
658 ds1305->ctrl[1] = 0;
659 write_ctrl = true;
660 }
661
662
663 if (pdata) {
664
665 if (((ds1305->ctrl[2] & 0xf0) != DS1305_TRICKLE_MAGIC)) {
666 ds1305->ctrl[2] = DS1305_TRICKLE_MAGIC
667 | pdata->trickle;
668 write_ctrl = true;
669 }
670
671
672 if (pdata->is_ds1306) {
673 if (pdata->en_1hz) {
674 if (!(ds1305->ctrl[0] & DS1306_1HZ)) {
675 ds1305->ctrl[0] |= DS1306_1HZ;
676 write_ctrl = true;
677 }
678 } else {
679 if (ds1305->ctrl[0] & DS1306_1HZ) {
680 ds1305->ctrl[0] &= ~DS1306_1HZ;
681 write_ctrl = true;
682 }
683 }
684 }
685 }
686
687 if (write_ctrl) {
688 u8 buf[4];
689
690 buf[0] = DS1305_WRITE | DS1305_CONTROL;
691 buf[1] = ds1305->ctrl[0];
692 buf[2] = ds1305->ctrl[1];
693 buf[3] = ds1305->ctrl[2];
694 status = spi_write_then_read(spi, buf, sizeof(buf), NULL, 0);
695 if (status < 0) {
696 dev_dbg(&spi->dev, "can't %s, %d\n",
697 "write", status);
698 return status;
699 }
700
701 dev_dbg(&spi->dev, "ctrl %s: %3ph\n", "write", ds1305->ctrl);
702 }
703
704
705 addr = DS1305_HOUR;
706 status = spi_write_then_read(spi, &addr, sizeof(addr),
707 &value, sizeof(value));
708 if (status < 0) {
709 dev_dbg(&spi->dev, "read HOUR --> %d\n", status);
710 return status;
711 }
712
713 ds1305->hr12 = (DS1305_HR_12 & value) != 0;
714 if (ds1305->hr12)
715 dev_dbg(&spi->dev, "AM/PM\n");
716
717
718 ds1305->rtc = devm_rtc_device_register(&spi->dev, "ds1305",
719 &ds1305_ops, THIS_MODULE);
720 if (IS_ERR(ds1305->rtc)) {
721 status = PTR_ERR(ds1305->rtc);
722 dev_dbg(&spi->dev, "register rtc --> %d\n", status);
723 return status;
724 }
725
726
727
728
729
730
731
732 if (spi->irq) {
733 INIT_WORK(&ds1305->work, ds1305_work);
734 status = devm_request_irq(&spi->dev, spi->irq, ds1305_irq,
735 0, dev_name(&ds1305->rtc->dev), ds1305);
736 if (status < 0) {
737 dev_err(&spi->dev, "request_irq %d --> %d\n",
738 spi->irq, status);
739 } else {
740 device_set_wakeup_capable(&spi->dev, 1);
741 }
742 }
743
744
745 status = sysfs_create_bin_file(&spi->dev.kobj, &nvram);
746 if (status < 0) {
747 dev_err(&spi->dev, "register nvram --> %d\n", status);
748 }
749
750 return 0;
751}
752
753static int ds1305_remove(struct spi_device *spi)
754{
755 struct ds1305 *ds1305 = spi_get_drvdata(spi);
756
757 sysfs_remove_bin_file(&spi->dev.kobj, &nvram);
758
759
760 if (spi->irq) {
761 set_bit(FLAG_EXITING, &ds1305->flags);
762 devm_free_irq(&spi->dev, spi->irq, ds1305);
763 cancel_work_sync(&ds1305->work);
764 }
765
766 return 0;
767}
768
769static struct spi_driver ds1305_driver = {
770 .driver.name = "rtc-ds1305",
771 .probe = ds1305_probe,
772 .remove = ds1305_remove,
773
774};
775
776module_spi_driver(ds1305_driver);
777
778MODULE_DESCRIPTION("RTC driver for DS1305 and DS1306 chips");
779MODULE_LICENSE("GPL");
780MODULE_ALIAS("spi:rtc-ds1305");
781