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19#ifndef __BFA_DEFS_H__
20#define __BFA_DEFS_H__
21
22#include "bfa_fc.h"
23#include "bfad_drv.h"
24
25#define BFA_MFG_SERIALNUM_SIZE 11
26#define STRSZ(_n) (((_n) + 4) & ~3)
27
28
29
30
31enum {
32 BFA_MFG_TYPE_CB_MAX = 825,
33 BFA_MFG_TYPE_FC8P2 = 825,
34 BFA_MFG_TYPE_FC8P1 = 815,
35 BFA_MFG_TYPE_FC4P2 = 425,
36 BFA_MFG_TYPE_FC4P1 = 415,
37 BFA_MFG_TYPE_CNA10P2 = 1020,
38 BFA_MFG_TYPE_CNA10P1 = 1010,
39 BFA_MFG_TYPE_JAYHAWK = 804,
40 BFA_MFG_TYPE_WANCHESE = 1007,
41 BFA_MFG_TYPE_ASTRA = 807,
42 BFA_MFG_TYPE_LIGHTNING_P0 = 902,
43 BFA_MFG_TYPE_LIGHTNING = 1741,
44 BFA_MFG_TYPE_PROWLER_F = 1560,
45 BFA_MFG_TYPE_PROWLER_N = 1410,
46 BFA_MFG_TYPE_PROWLER_C = 1710,
47 BFA_MFG_TYPE_PROWLER_D = 1860,
48 BFA_MFG_TYPE_CHINOOK = 1867,
49 BFA_MFG_TYPE_CHINOOK2 = 1869,
50 BFA_MFG_TYPE_INVALID = 0,
51};
52
53#pragma pack(1)
54
55
56
57
58#define bfa_mfg_is_mezz(type) (( \
59 (type) == BFA_MFG_TYPE_JAYHAWK || \
60 (type) == BFA_MFG_TYPE_WANCHESE || \
61 (type) == BFA_MFG_TYPE_ASTRA || \
62 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \
63 (type) == BFA_MFG_TYPE_LIGHTNING || \
64 (type) == BFA_MFG_TYPE_CHINOOK || \
65 (type) == BFA_MFG_TYPE_CHINOOK2))
66
67
68
69
70#define bfa_mfg_is_old_wwn_mac_model(type) (( \
71 (type) == BFA_MFG_TYPE_FC8P2 || \
72 (type) == BFA_MFG_TYPE_FC8P1 || \
73 (type) == BFA_MFG_TYPE_FC4P2 || \
74 (type) == BFA_MFG_TYPE_FC4P1 || \
75 (type) == BFA_MFG_TYPE_CNA10P2 || \
76 (type) == BFA_MFG_TYPE_CNA10P1 || \
77 (type) == BFA_MFG_TYPE_JAYHAWK || \
78 (type) == BFA_MFG_TYPE_WANCHESE))
79
80#define bfa_mfg_increment_wwn_mac(m, i) \
81do { \
82 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
83 (u32)(m)[2]; \
84 t += (i); \
85 (m)[0] = (t >> 16) & 0xFF; \
86 (m)[1] = (t >> 8) & 0xFF; \
87 (m)[2] = t & 0xFF; \
88} while (0)
89
90
91
92
93#define BFA_MFG_VPD_LEN 512
94
95
96
97
98enum {
99 BFA_MFG_VPD_UNKNOWN = 0,
100 BFA_MFG_VPD_IBM = 1,
101 BFA_MFG_VPD_HP = 2,
102 BFA_MFG_VPD_DELL = 3,
103 BFA_MFG_VPD_PCI_IBM = 0x08,
104 BFA_MFG_VPD_PCI_HP = 0x10,
105 BFA_MFG_VPD_PCI_DELL = 0x20,
106 BFA_MFG_VPD_PCI_BRCD = 0xf8,
107};
108
109
110
111
112struct bfa_mfg_vpd_s {
113 u8 version;
114 u8 vpd_sig[3];
115 u8 chksum;
116 u8 vendor;
117 u8 len;
118 u8 rsv;
119 u8 data[BFA_MFG_VPD_LEN];
120};
121
122#pragma pack()
123
124
125
126
127enum bfa_status {
128 BFA_STATUS_OK = 0,
129 BFA_STATUS_FAILED = 1,
130 BFA_STATUS_EINVAL = 2,
131
132 BFA_STATUS_ENOMEM = 3,
133 BFA_STATUS_ETIMER = 5,
134
135 BFA_STATUS_EPROTOCOL = 6,
136 BFA_STATUS_BADFLASH = 9,
137 BFA_STATUS_SFP_UNSUPP = 10,
138 BFA_STATUS_UNKNOWN_VFID = 11,
139 BFA_STATUS_DATACORRUPTED = 12,
140 BFA_STATUS_DEVBUSY = 13,
141 BFA_STATUS_HDMA_FAILED = 16,
142 BFA_STATUS_FLASH_BAD_LEN = 17,
143 BFA_STATUS_UNKNOWN_LWWN = 18,
144 BFA_STATUS_UNKNOWN_RWWN = 19,
145 BFA_STATUS_VPORT_EXISTS = 21,
146 BFA_STATUS_VPORT_MAX = 22,
147 BFA_STATUS_UNSUPP_SPEED = 23,
148 BFA_STATUS_INVLD_DFSZ = 24,
149 BFA_STATUS_CMD_NOTSUPP = 26,
150 BFA_STATUS_FABRIC_RJT = 29,
151 BFA_STATUS_UNKNOWN_VWWN = 30,
152 BFA_STATUS_PORT_OFFLINE = 34,
153 BFA_STATUS_VPORT_WWN_BP = 46,
154 BFA_STATUS_PORT_NOT_DISABLED = 47,
155 BFA_STATUS_NO_FCPIM_NEXUS = 52,
156 BFA_STATUS_IOC_FAILURE = 56,
157
158 BFA_STATUS_INVALID_WWN = 57,
159 BFA_STATUS_ADAPTER_ENABLED = 60,
160 BFA_STATUS_IOC_NON_OP = 61,
161 BFA_STATUS_VERSION_FAIL = 70,
162 BFA_STATUS_DIAG_BUSY = 71,
163 BFA_STATUS_BEACON_ON = 72,
164 BFA_STATUS_ENOFSAVE = 78,
165 BFA_STATUS_IOC_DISABLED = 82,
166 BFA_STATUS_ERROR_TRL_ENABLED = 87,
167 BFA_STATUS_ERROR_QOS_ENABLED = 88,
168 BFA_STATUS_NO_SFP_DEV = 89,
169 BFA_STATUS_MEMTEST_FAILED = 90,
170 BFA_STATUS_LEDTEST_OP = 109,
171 BFA_STATUS_INVALID_MAC = 134,
172 BFA_STATUS_CMD_NOTSUPP_CNA = 146,
173 BFA_STATUS_PBC = 154,
174
175 BFA_STATUS_BAD_FWCFG = 156,
176 BFA_STATUS_INVALID_VENDOR = 158,
177 BFA_STATUS_SFP_NOT_READY = 159,
178 BFA_STATUS_TRUNK_ENABLED = 164,
179
180 BFA_STATUS_TRUNK_DISABLED = 165,
181
182 BFA_STATUS_IOPROFILE_OFF = 175,
183 BFA_STATUS_PHY_NOT_PRESENT = 183,
184 BFA_STATUS_FEATURE_NOT_SUPPORTED = 192,
185 BFA_STATUS_ENTRY_EXISTS = 193,
186 BFA_STATUS_ENTRY_NOT_EXISTS = 194,
187 BFA_STATUS_NO_CHANGE = 195,
188 BFA_STATUS_FAA_ENABLED = 197,
189 BFA_STATUS_FAA_DISABLED = 198,
190 BFA_STATUS_FAA_ACQUIRED = 199,
191 BFA_STATUS_FAA_ACQ_ADDR = 200,
192 BFA_STATUS_BBCR_FC_ONLY = 201,
193
194 BFA_STATUS_ERROR_TRUNK_ENABLED = 203,
195 BFA_STATUS_MAX_ENTRY_REACHED = 212,
196 BFA_STATUS_TOPOLOGY_LOOP = 230,
197 BFA_STATUS_LOOP_UNSUPP_MEZZ = 231,
198
199 BFA_STATUS_INVALID_BW = 233,
200 BFA_STATUS_QOS_BW_INVALID = 234,
201
202 BFA_STATUS_DPORT_ENABLED = 235,
203 BFA_STATUS_DPORT_DISABLED = 236,
204 BFA_STATUS_CMD_NOTSUPP_MEZZ = 239,
205 BFA_STATUS_FRU_NOT_PRESENT = 240,
206 BFA_STATUS_DPORT_NO_SFP = 243,
207
208
209 BFA_STATUS_DPORT_ERR = 245,
210 BFA_STATUS_DPORT_ENOSYS = 254,
211 BFA_STATUS_DPORT_CANT_PERF = 255,
212
213 BFA_STATUS_DPORT_LOGICALERR = 256,
214 BFA_STATUS_DPORT_SWBUSY = 257,
215 BFA_STATUS_ERR_BBCR_SPEED_UNSUPPORT = 258,
216
217 BFA_STATUS_ERROR_BBCR_ENABLED = 259,
218
219 BFA_STATUS_INVALID_BBSCN = 260,
220
221 BFA_STATUS_DDPORT_ERR = 261,
222
223
224 BFA_STATUS_DPORT_SFPWRAP_ERR = 262,
225
226 BFA_STATUS_BBCR_CFG_NO_CHANGE = 265,
227
228 BFA_STATUS_DPORT_SW_NOTREADY = 268,
229
230
231 BFA_STATUS_DPORT_INV_SFP = 271,
232 BFA_STATUS_DPORT_CMD_NOTSUPP = 273,
233
234 BFA_STATUS_MAX_VAL
235};
236#define bfa_status_t enum bfa_status
237
238enum bfa_eproto_status {
239 BFA_EPROTO_BAD_ACCEPT = 0,
240 BFA_EPROTO_UNKNOWN_RSP = 1
241};
242#define bfa_eproto_status_t enum bfa_eproto_status
243
244enum bfa_boolean {
245 BFA_FALSE = 0,
246 BFA_TRUE = 1
247};
248#define bfa_boolean_t enum bfa_boolean
249
250#define BFA_STRING_32 32
251#define BFA_VERSION_LEN 64
252
253
254
255
256
257
258
259
260enum {
261 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
262
263
264
265 BFA_ADAPTER_MODEL_NAME_LEN = 16,
266 BFA_ADAPTER_MODEL_DESCR_LEN = 128,
267 BFA_ADAPTER_MFG_NAME_LEN = 8,
268 BFA_ADAPTER_SYM_NAME_LEN = 64,
269 BFA_ADAPTER_OS_TYPE_LEN = 64,
270 BFA_ADAPTER_UUID_LEN = 16,
271};
272
273struct bfa_adapter_attr_s {
274 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
275 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
276 u32 card_type;
277 char model[BFA_ADAPTER_MODEL_NAME_LEN];
278 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
279 wwn_t pwwn;
280 char node_symname[FC_SYMNAME_MAX];
281 char hw_ver[BFA_VERSION_LEN];
282 char fw_ver[BFA_VERSION_LEN];
283 char optrom_ver[BFA_VERSION_LEN];
284 char os_type[BFA_ADAPTER_OS_TYPE_LEN];
285 struct bfa_mfg_vpd_s vpd;
286 struct mac_s mac;
287
288 u8 nports;
289 u8 max_speed;
290 u8 prototype;
291 char asic_rev;
292
293 u8 pcie_gen;
294 u8 pcie_lanes_orig;
295 u8 pcie_lanes;
296 u8 cna_capable;
297
298 u8 is_mezz;
299 u8 trunk_capable;
300 u8 mfg_day;
301 u8 mfg_month;
302 u16 mfg_year;
303 u16 rsvd;
304 u8 uuid[BFA_ADAPTER_UUID_LEN];
305};
306
307
308
309
310
311enum {
312 BFA_IOC_DRIVER_LEN = 16,
313 BFA_IOC_CHIP_REV_LEN = 8,
314};
315
316
317
318
319struct bfa_ioc_driver_attr_s {
320 char driver[BFA_IOC_DRIVER_LEN];
321 char driver_ver[BFA_VERSION_LEN];
322 char fw_ver[BFA_VERSION_LEN];
323 char bios_ver[BFA_VERSION_LEN];
324 char efi_ver[BFA_VERSION_LEN];
325 char ob_ver[BFA_VERSION_LEN];
326};
327
328
329
330
331struct bfa_ioc_pci_attr_s {
332 u16 vendor_id;
333 u16 device_id;
334 u16 ssid;
335 u16 ssvid;
336 u32 pcifn;
337 u32 rsvd;
338 char chip_rev[BFA_IOC_CHIP_REV_LEN];
339};
340
341
342
343
344enum bfa_ioc_state {
345 BFA_IOC_UNINIT = 1,
346 BFA_IOC_RESET = 2,
347 BFA_IOC_SEMWAIT = 3,
348 BFA_IOC_HWINIT = 4,
349 BFA_IOC_GETATTR = 5,
350 BFA_IOC_OPERATIONAL = 6,
351 BFA_IOC_INITFAIL = 7,
352 BFA_IOC_FAIL = 8,
353 BFA_IOC_DISABLING = 9,
354 BFA_IOC_DISABLED = 10,
355 BFA_IOC_FWMISMATCH = 11,
356 BFA_IOC_ENABLING = 12,
357 BFA_IOC_HWFAIL = 13,
358 BFA_IOC_ACQ_ADDR = 14,
359};
360
361
362
363
364struct bfa_fw_ioc_stats_s {
365 u32 enable_reqs;
366 u32 disable_reqs;
367 u32 get_attr_reqs;
368 u32 dbg_sync;
369 u32 dbg_dump;
370 u32 unknown_reqs;
371};
372
373
374
375
376struct bfa_ioc_drv_stats_s {
377 u32 ioc_isrs;
378 u32 ioc_enables;
379 u32 ioc_disables;
380 u32 ioc_hbfails;
381 u32 ioc_boots;
382 u32 stats_tmos;
383 u32 hb_count;
384 u32 disable_reqs;
385 u32 enable_reqs;
386 u32 disable_replies;
387 u32 enable_replies;
388 u32 rsvd;
389};
390
391
392
393
394struct bfa_ioc_stats_s {
395 struct bfa_ioc_drv_stats_s drv_stats;
396 struct bfa_fw_ioc_stats_s fw_stats;
397};
398
399enum bfa_ioc_type_e {
400 BFA_IOC_TYPE_FC = 1,
401 BFA_IOC_TYPE_FCoE = 2,
402 BFA_IOC_TYPE_LL = 3,
403};
404
405
406
407
408struct bfa_ioc_attr_s {
409 enum bfa_ioc_type_e ioc_type;
410 enum bfa_ioc_state state;
411 struct bfa_adapter_attr_s adapter_attr;
412 struct bfa_ioc_driver_attr_s driver_attr;
413 struct bfa_ioc_pci_attr_s pci_attr;
414 u8 port_id;
415 u8 port_mode;
416 u8 cap_bm;
417 u8 port_mode_cfg;
418 u8 def_fn;
419 u8 rsvd[3];
420};
421
422
423
424
425enum bfa_aen_category {
426 BFA_AEN_CAT_ADAPTER = 1,
427 BFA_AEN_CAT_PORT = 2,
428 BFA_AEN_CAT_LPORT = 3,
429 BFA_AEN_CAT_RPORT = 4,
430 BFA_AEN_CAT_ITNIM = 5,
431 BFA_AEN_CAT_AUDIT = 8,
432 BFA_AEN_CAT_IOC = 9,
433};
434
435
436enum bfa_adapter_aen_event {
437 BFA_ADAPTER_AEN_ADD = 1,
438 BFA_ADAPTER_AEN_REMOVE = 2,
439};
440
441struct bfa_adapter_aen_data_s {
442 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
443 u32 nports;
444 wwn_t pwwn;
445};
446
447
448enum bfa_port_aen_event {
449 BFA_PORT_AEN_ONLINE = 1,
450 BFA_PORT_AEN_OFFLINE = 2,
451 BFA_PORT_AEN_RLIR = 3,
452 BFA_PORT_AEN_SFP_INSERT = 4,
453 BFA_PORT_AEN_SFP_REMOVE = 5,
454 BFA_PORT_AEN_SFP_POM = 6,
455 BFA_PORT_AEN_ENABLE = 7,
456 BFA_PORT_AEN_DISABLE = 8,
457 BFA_PORT_AEN_AUTH_ON = 9,
458 BFA_PORT_AEN_AUTH_OFF = 10,
459 BFA_PORT_AEN_DISCONNECT = 11,
460 BFA_PORT_AEN_QOS_NEG = 12,
461 BFA_PORT_AEN_FABRIC_NAME_CHANGE = 13,
462 BFA_PORT_AEN_SFP_ACCESS_ERROR = 14,
463 BFA_PORT_AEN_SFP_UNSUPPORT = 15,
464};
465
466enum bfa_port_aen_sfp_pom {
467 BFA_PORT_AEN_SFP_POM_GREEN = 1,
468 BFA_PORT_AEN_SFP_POM_AMBER = 2,
469 BFA_PORT_AEN_SFP_POM_RED = 3,
470 BFA_PORT_AEN_SFP_POM_MAX = BFA_PORT_AEN_SFP_POM_RED
471};
472
473struct bfa_port_aen_data_s {
474 wwn_t pwwn;
475 wwn_t fwwn;
476 u32 phy_port_num;
477 u16 ioc_type;
478 u16 level;
479 mac_t mac;
480 u16 rsvd;
481};
482
483
484enum bfa_lport_aen_event {
485 BFA_LPORT_AEN_NEW = 1,
486 BFA_LPORT_AEN_DELETE = 2,
487 BFA_LPORT_AEN_ONLINE = 3,
488 BFA_LPORT_AEN_OFFLINE = 4,
489 BFA_LPORT_AEN_DISCONNECT = 5,
490 BFA_LPORT_AEN_NEW_PROP = 6,
491 BFA_LPORT_AEN_DELETE_PROP = 7,
492 BFA_LPORT_AEN_NEW_STANDARD = 8,
493 BFA_LPORT_AEN_DELETE_STANDARD = 9,
494 BFA_LPORT_AEN_NPIV_DUP_WWN = 10,
495 BFA_LPORT_AEN_NPIV_FABRIC_MAX = 11,
496 BFA_LPORT_AEN_NPIV_UNKNOWN = 12,
497};
498
499struct bfa_lport_aen_data_s {
500 u16 vf_id;
501 u16 roles;
502 u32 rsvd;
503 wwn_t ppwwn;
504 wwn_t lpwwn;
505};
506
507
508enum bfa_itnim_aen_event {
509 BFA_ITNIM_AEN_ONLINE = 1,
510 BFA_ITNIM_AEN_OFFLINE = 2,
511 BFA_ITNIM_AEN_DISCONNECT = 3,
512};
513
514struct bfa_itnim_aen_data_s {
515 u16 vf_id;
516 u16 rsvd[3];
517 wwn_t ppwwn;
518 wwn_t lpwwn;
519 wwn_t rpwwn;
520};
521
522
523enum bfa_audit_aen_event {
524 BFA_AUDIT_AEN_AUTH_ENABLE = 1,
525 BFA_AUDIT_AEN_AUTH_DISABLE = 2,
526 BFA_AUDIT_AEN_FLASH_ERASE = 3,
527 BFA_AUDIT_AEN_FLASH_UPDATE = 4,
528};
529
530struct bfa_audit_aen_data_s {
531 wwn_t pwwn;
532 int partition_inst;
533 int partition_type;
534};
535
536
537enum bfa_ioc_aen_event {
538 BFA_IOC_AEN_HBGOOD = 1,
539 BFA_IOC_AEN_HBFAIL = 2,
540 BFA_IOC_AEN_ENABLE = 3,
541 BFA_IOC_AEN_DISABLE = 4,
542 BFA_IOC_AEN_FWMISMATCH = 5,
543 BFA_IOC_AEN_FWCFG_ERROR = 6,
544 BFA_IOC_AEN_INVALID_VENDOR = 7,
545 BFA_IOC_AEN_INVALID_NWWN = 8,
546 BFA_IOC_AEN_INVALID_PWWN = 9
547};
548
549struct bfa_ioc_aen_data_s {
550 wwn_t pwwn;
551 u16 ioc_type;
552 mac_t mac;
553};
554
555
556
557
558
559
560
561
562#define BFA_MFG_CHKSUM_SIZE 16
563
564#define BFA_MFG_PARTNUM_SIZE 14
565#define BFA_MFG_SUPPLIER_ID_SIZE 10
566#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
567#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
568#define BFA_MFG_SUPPLIER_REVISION_SIZE 4
569
570
571
572#define BFA_MFG_IC_FC 0x01
573#define BFA_MFG_IC_ETH 0x02
574
575
576
577
578#define BFA_CM_HBA 0x01
579#define BFA_CM_CNA 0x02
580#define BFA_CM_NIC 0x04
581#define BFA_CM_FC16G 0x08
582#define BFA_CM_SRIOV 0x10
583#define BFA_CM_MEZZ 0x20
584
585#pragma pack(1)
586
587
588
589
590struct bfa_mfg_block_s {
591 u8 version;
592 u8 mfg_sig[3];
593 u16 mfgsize;
594 u16 u16_chksum;
595 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
596 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)];
597 u8 mfg_day;
598 u8 mfg_month;
599 u16 mfg_year;
600 wwn_t mfg_wwn;
601 u8 num_wwn;
602 u8 mfg_speeds;
603 u8 rsv[2];
604 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)];
605 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
606 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
607 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
608 mac_t mfg_mac;
609 u8 num_mac;
610 u8 rsv2;
611 u32 card_type;
612 char cap_nic;
613 char cap_cna;
614 char cap_hba;
615 char cap_fc16g;
616 char cap_sriov;
617 char cap_mezz;
618 u8 rsv3;
619 u8 mfg_nports;
620 char media[8];
621 char initial_mode[8];
622 u8 rsv4[84];
623 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE];
624};
625
626#pragma pack()
627
628
629
630
631
632
633
634
635enum {
636 BFA_PCI_VENDOR_ID_BROCADE = 0x1657,
637 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13,
638 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17,
639 BFA_PCI_DEVICE_ID_CT = 0x14,
640 BFA_PCI_DEVICE_ID_CT_FC = 0x21,
641 BFA_PCI_DEVICE_ID_CT2 = 0x22,
642 BFA_PCI_DEVICE_ID_CT2_QUAD = 0x23,
643};
644
645#define bfa_asic_id_cb(__d) \
646 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \
647 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P)
648#define bfa_asic_id_ct(__d) \
649 ((__d) == BFA_PCI_DEVICE_ID_CT || \
650 (__d) == BFA_PCI_DEVICE_ID_CT_FC)
651#define bfa_asic_id_ct2(__d) \
652 ((__d) == BFA_PCI_DEVICE_ID_CT2 || \
653 (__d) == BFA_PCI_DEVICE_ID_CT2_QUAD)
654#define bfa_asic_id_ctc(__d) \
655 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d))
656
657
658
659
660enum {
661 BFA_PCI_FCOE_SSDEVICE_ID = 0x14,
662 BFA_PCI_CT2_SSID_FCoE = 0x22,
663 BFA_PCI_CT2_SSID_ETH = 0x23,
664 BFA_PCI_CT2_SSID_FC = 0x24,
665};
666
667
668
669
670#define BFA_PCI_ACCESS_RANGES 1
671
672
673
674
675
676enum bfa_port_speed {
677 BFA_PORT_SPEED_UNKNOWN = 0,
678 BFA_PORT_SPEED_1GBPS = 1,
679 BFA_PORT_SPEED_2GBPS = 2,
680 BFA_PORT_SPEED_4GBPS = 4,
681 BFA_PORT_SPEED_8GBPS = 8,
682 BFA_PORT_SPEED_10GBPS = 10,
683 BFA_PORT_SPEED_16GBPS = 16,
684 BFA_PORT_SPEED_AUTO = 0xf,
685};
686#define bfa_port_speed_t enum bfa_port_speed
687
688enum {
689 BFA_BOOT_BOOTLUN_MAX = 4,
690 BFA_PREBOOT_BOOTLUN_MAX = 8,
691};
692
693#define BOOT_CFG_REV1 1
694#define BOOT_CFG_VLAN 1
695
696
697
698
699
700enum bfa_boot_bootopt {
701 BFA_BOOT_AUTO_DISCOVER = 0,
702 BFA_BOOT_STORED_BLUN = 1,
703 BFA_BOOT_FIRST_LUN = 2,
704 BFA_BOOT_PBC = 3,
705};
706
707#pragma pack(1)
708
709
710
711struct bfa_boot_bootlun_s {
712 wwn_t pwwn;
713 struct scsi_lun lun;
714};
715#pragma pack()
716
717
718
719
720struct bfa_boot_cfg_s {
721 u8 version;
722 u8 rsvd1;
723 u16 chksum;
724 u8 enable;
725 u8 speed;
726 u8 topology;
727 u8 bootopt;
728 u32 nbluns;
729 u32 rsvd2;
730 struct bfa_boot_bootlun_s blun[BFA_BOOT_BOOTLUN_MAX];
731 struct bfa_boot_bootlun_s blun_disc[BFA_BOOT_BOOTLUN_MAX];
732};
733
734struct bfa_boot_pbc_s {
735 u8 enable;
736 u8 speed;
737 u8 topology;
738 u8 rsvd1;
739 u32 nbluns;
740 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX];
741};
742
743struct bfa_ethboot_cfg_s {
744 u8 version;
745 u8 rsvd1;
746 u16 chksum;
747 u8 enable;
748 u8 rsvd2;
749 u16 vlan;
750};
751
752
753
754
755#define BFA_ABLK_MAX_PORTS 2
756#define BFA_ABLK_MAX_PFS 16
757#define BFA_ABLK_MAX 2
758
759#pragma pack(1)
760enum bfa_mode_s {
761 BFA_MODE_HBA = 1,
762 BFA_MODE_CNA = 2,
763 BFA_MODE_NIC = 3
764};
765
766struct bfa_adapter_cfg_mode_s {
767 u16 max_pf;
768 u16 max_vf;
769 enum bfa_mode_s mode;
770};
771
772struct bfa_ablk_cfg_pf_s {
773 u16 pers;
774 u8 port_id;
775 u8 optrom;
776 u8 valid;
777 u8 sriov;
778 u8 max_vfs;
779 u8 rsvd[1];
780 u16 num_qpairs;
781 u16 num_vectors;
782 u16 bw_min;
783 u16 bw_max;
784};
785
786struct bfa_ablk_cfg_port_s {
787 u8 mode;
788 u8 type;
789 u8 max_pfs;
790 u8 rsvd[5];
791};
792
793struct bfa_ablk_cfg_inst_s {
794 u8 nports;
795 u8 max_pfs;
796 u8 rsvd[6];
797 struct bfa_ablk_cfg_pf_s pf_cfg[BFA_ABLK_MAX_PFS];
798 struct bfa_ablk_cfg_port_s port_cfg[BFA_ABLK_MAX_PORTS];
799};
800
801struct bfa_ablk_cfg_s {
802 struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX];
803};
804
805
806
807
808
809#define SFP_DIAGMON_SIZE 10
810
811
812#define BFA_SFP_SCN_REMOVED 0
813#define BFA_SFP_SCN_INSERTED 1
814#define BFA_SFP_SCN_POM 2
815#define BFA_SFP_SCN_FAILED 3
816#define BFA_SFP_SCN_UNSUPPORT 4
817#define BFA_SFP_SCN_VALID 5
818
819enum bfa_defs_sfp_media_e {
820 BFA_SFP_MEDIA_UNKNOWN = 0x00,
821 BFA_SFP_MEDIA_CU = 0x01,
822 BFA_SFP_MEDIA_LW = 0x02,
823 BFA_SFP_MEDIA_SW = 0x03,
824 BFA_SFP_MEDIA_EL = 0x04,
825 BFA_SFP_MEDIA_UNSUPPORT = 0x05,
826};
827
828
829
830
831enum {
832 SFP_XMTR_TECH_CU = (1 << 0),
833 SFP_XMTR_TECH_CP = (1 << 1),
834 SFP_XMTR_TECH_CA = (1 << 2),
835 SFP_XMTR_TECH_LL = (1 << 3),
836 SFP_XMTR_TECH_SL = (1 << 4),
837 SFP_XMTR_TECH_SN = (1 << 5),
838 SFP_XMTR_TECH_EL_INTRA = (1 << 6),
839 SFP_XMTR_TECH_EL_INTER = (1 << 7),
840 SFP_XMTR_TECH_LC = (1 << 8),
841 SFP_XMTR_TECH_SA = (1 << 9)
842};
843
844
845
846
847
848struct sfp_srlid_base_s {
849 u8 id;
850 u8 extid;
851 u8 connector;
852 u8 xcvr[8];
853 u8 encoding;
854 u8 br_norm;
855 u8 rate_id;
856 u8 len_km;
857 u8 len_100m;
858 u8 len_om2;
859 u8 len_om1;
860 u8 len_cu;
861 u8 len_om3;
862 u8 vendor_name[16];
863 u8 unalloc1;
864 u8 vendor_oui[3];
865 u8 vendor_pn[16];
866 u8 vendor_rev[4];
867 u8 wavelen[2];
868 u8 unalloc2;
869 u8 cc_base;
870};
871
872
873
874
875
876struct sfp_srlid_ext_s {
877 u8 options[2];
878 u8 br_max;
879 u8 br_min;
880 u8 vendor_sn[16];
881 u8 date_code[8];
882 u8 diag_mon_type;
883 u8 en_options;
884 u8 sff_8472;
885 u8 cc_ext;
886};
887
888
889
890
891
892struct sfp_diag_base_s {
893
894
895
896 u8 temp_high_alarm[2];
897 u8 temp_low_alarm[2];
898 u8 temp_high_warning[2];
899 u8 temp_low_warning[2];
900
901 u8 volt_high_alarm[2];
902 u8 volt_low_alarm[2];
903 u8 volt_high_warning[2];
904 u8 volt_low_warning[2];
905
906 u8 bias_high_alarm[2];
907 u8 bias_low_alarm[2];
908 u8 bias_high_warning[2];
909 u8 bias_low_warning[2];
910
911 u8 tx_pwr_high_alarm[2];
912 u8 tx_pwr_low_alarm[2];
913 u8 tx_pwr_high_warning[2];
914 u8 tx_pwr_low_warning[2];
915
916 u8 rx_pwr_high_alarm[2];
917 u8 rx_pwr_low_alarm[2];
918 u8 rx_pwr_high_warning[2];
919 u8 rx_pwr_low_warning[2];
920
921 u8 unallocate_1[16];
922
923
924
925
926 u8 rx_pwr[20];
927 u8 tx_i[4];
928 u8 tx_pwr[4];
929 u8 temp[4];
930 u8 volt[4];
931 u8 unallocate_2[3];
932 u8 cc_dmi;
933};
934
935
936
937
938
939struct sfp_diag_ext_s {
940 u8 diag[SFP_DIAGMON_SIZE];
941 u8 unalloc1[4];
942 u8 status_ctl;
943 u8 rsvd;
944 u8 alarm_flags[2];
945 u8 unalloc2[2];
946 u8 warning_flags[2];
947 u8 ext_status_ctl[2];
948};
949
950
951
952
953
954
955struct sfp_usr_eeprom_s {
956 u8 rsvd1[2];
957 u8 ewrap;
958 u8 rsvd2[2];
959 u8 owrap;
960 u8 rsvd3[2];
961 u8 prbs;
962 u8 rsvd4[2];
963 u8 tx_eqz_16;
964 u8 tx_eqz_8;
965 u8 rsvd5[2];
966 u8 rx_emp_16;
967 u8 rx_emp_8;
968 u8 rsvd6[2];
969 u8 tx_eye_adj;
970 u8 rsvd7[3];
971 u8 tx_eye_qctl;
972 u8 tx_eye_qres;
973 u8 rsvd8[2];
974 u8 poh[3];
975 u8 rsvd9[2];
976};
977
978struct sfp_mem_s {
979 struct sfp_srlid_base_s srlid_base;
980 struct sfp_srlid_ext_s srlid_ext;
981 struct sfp_diag_base_s diag_base;
982 struct sfp_diag_ext_s diag_ext;
983 struct sfp_usr_eeprom_s usr_eeprom;
984};
985
986
987
988
989union sfp_xcvr_e10g_code_u {
990 u8 b;
991 struct {
992#ifdef __BIG_ENDIAN
993 u8 e10g_unall:1;
994 u8 e10g_lrm:1;
995 u8 e10g_lr:1;
996 u8 e10g_sr:1;
997 u8 ib_sx:1;
998 u8 ib_lx:1;
999 u8 ib_cu_a:1;
1000 u8 ib_cu_p:1;
1001#else
1002 u8 ib_cu_p:1;
1003 u8 ib_cu_a:1;
1004 u8 ib_lx:1;
1005 u8 ib_sx:1;
1006 u8 e10g_sr:1;
1007 u8 e10g_lr:1;
1008 u8 e10g_lrm:1;
1009 u8 e10g_unall:1;
1010#endif
1011 } r;
1012};
1013
1014union sfp_xcvr_so1_code_u {
1015 u8 b;
1016 struct {
1017 u8 escon:2;
1018 u8 oc192_reach:1;
1019 u8 so_reach:2;
1020 u8 oc48_reach:3;
1021 } r;
1022};
1023
1024union sfp_xcvr_so2_code_u {
1025 u8 b;
1026 struct {
1027 u8 reserved:1;
1028 u8 oc12_reach:3;
1029 u8 reserved1:1;
1030 u8 oc3_reach:3;
1031 } r;
1032};
1033
1034union sfp_xcvr_eth_code_u {
1035 u8 b;
1036 struct {
1037 u8 base_px:1;
1038 u8 base_bx10:1;
1039 u8 e100base_fx:1;
1040 u8 e100base_lx:1;
1041 u8 e1000base_t:1;
1042 u8 e1000base_cx:1;
1043 u8 e1000base_lx:1;
1044 u8 e1000base_sx:1;
1045 } r;
1046};
1047
1048struct sfp_xcvr_fc1_code_s {
1049 u8 link_len:5;
1050 u8 xmtr_tech2:3;
1051 u8 xmtr_tech1:7;
1052 u8 reserved1:1;
1053};
1054
1055union sfp_xcvr_fc2_code_u {
1056 u8 b;
1057 struct {
1058 u8 tw_media:1;
1059 u8 tp_media:1;
1060 u8 mi_media:1;
1061 u8 tv_media:1;
1062 u8 m6_media:1;
1063 u8 m5_media:1;
1064 u8 reserved:1;
1065 u8 sm_media:1;
1066 } r;
1067};
1068
1069union sfp_xcvr_fc3_code_u {
1070 u8 b;
1071 struct {
1072#ifdef __BIG_ENDIAN
1073 u8 rsv4:1;
1074 u8 mb800:1;
1075 u8 mb1600:1;
1076 u8 mb400:1;
1077 u8 rsv2:1;
1078 u8 mb200:1;
1079 u8 rsv1:1;
1080 u8 mb100:1;
1081#else
1082 u8 mb100:1;
1083 u8 rsv1:1;
1084 u8 mb200:1;
1085 u8 rsv2:1;
1086 u8 mb400:1;
1087 u8 mb1600:1;
1088 u8 mb800:1;
1089 u8 rsv4:1;
1090#endif
1091 } r;
1092};
1093
1094struct sfp_xcvr_s {
1095 union sfp_xcvr_e10g_code_u e10g;
1096 union sfp_xcvr_so1_code_u so1;
1097 union sfp_xcvr_so2_code_u so2;
1098 union sfp_xcvr_eth_code_u eth;
1099 struct sfp_xcvr_fc1_code_s fc1;
1100 union sfp_xcvr_fc2_code_u fc2;
1101 union sfp_xcvr_fc3_code_u fc3;
1102};
1103
1104
1105
1106
1107#define BFA_FLASH_PART_ENTRY_SIZE 32
1108#define BFA_FLASH_PART_MAX 32
1109
1110enum bfa_flash_part_type {
1111 BFA_FLASH_PART_OPTROM = 1,
1112 BFA_FLASH_PART_FWIMG = 2,
1113 BFA_FLASH_PART_FWCFG = 3,
1114 BFA_FLASH_PART_DRV = 4,
1115 BFA_FLASH_PART_BOOT = 5,
1116 BFA_FLASH_PART_ASIC = 6,
1117 BFA_FLASH_PART_MFG = 7,
1118 BFA_FLASH_PART_OPTROM2 = 8,
1119 BFA_FLASH_PART_VPD = 9,
1120 BFA_FLASH_PART_PBC = 10,
1121 BFA_FLASH_PART_BOOTOVL = 11,
1122 BFA_FLASH_PART_LOG = 12,
1123 BFA_FLASH_PART_PXECFG = 13,
1124 BFA_FLASH_PART_PXEOVL = 14,
1125 BFA_FLASH_PART_PORTCFG = 15,
1126 BFA_FLASH_PART_ASICBK = 16,
1127};
1128
1129
1130
1131
1132struct bfa_flash_part_attr_s {
1133 u32 part_type;
1134 u32 part_instance;
1135 u32 part_off;
1136 u32 part_size;
1137 u32 part_len;
1138 u32 part_status;
1139 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24];
1140};
1141
1142
1143
1144
1145struct bfa_flash_attr_s {
1146 u32 status;
1147 u32 npart;
1148 struct bfa_flash_part_attr_s part[BFA_FLASH_PART_MAX];
1149};
1150
1151
1152
1153
1154#define LB_PATTERN_DEFAULT 0xB5B5B5B5
1155#define QTEST_CNT_DEFAULT 10
1156#define QTEST_PAT_DEFAULT LB_PATTERN_DEFAULT
1157#define DPORT_ENABLE_LOOPCNT_DEFAULT (1024 * 1024)
1158
1159struct bfa_diag_memtest_s {
1160 u8 algo;
1161 u8 rsvd[7];
1162};
1163
1164struct bfa_diag_memtest_result {
1165 u32 status;
1166 u32 addr;
1167 u32 exp;
1168 u32 act;
1169 u32 err_status;
1170 u32 err_status1;
1171 u32 err_addr;
1172 u8 algo;
1173 u8 rsv[3];
1174};
1175
1176struct bfa_diag_loopback_result_s {
1177 u32 numtxmfrm;
1178 u32 numosffrm;
1179 u32 numrcvfrm;
1180 u32 badfrminf;
1181 u32 badfrmnum;
1182 u8 status;
1183 u8 rsvd[3];
1184};
1185
1186enum bfa_diag_dport_test_status {
1187 DPORT_TEST_ST_IDLE = 0,
1188 DPORT_TEST_ST_FINAL = 1,
1189 DPORT_TEST_ST_SKIP = 2,
1190 DPORT_TEST_ST_FAIL = 3,
1191 DPORT_TEST_ST_INPRG = 4,
1192 DPORT_TEST_ST_RESPONDER = 5,
1193 DPORT_TEST_ST_STOPPED = 6,
1194 DPORT_TEST_ST_MAX
1195};
1196
1197enum bfa_diag_dport_test_type {
1198 DPORT_TEST_ELOOP = 0,
1199 DPORT_TEST_OLOOP = 1,
1200 DPORT_TEST_ROLOOP = 2,
1201 DPORT_TEST_LINK = 3,
1202 DPORT_TEST_MAX
1203};
1204
1205enum bfa_diag_dport_test_opmode {
1206 BFA_DPORT_OPMODE_AUTO = 0,
1207 BFA_DPORT_OPMODE_MANU = 1,
1208};
1209
1210struct bfa_diag_dport_subtest_result_s {
1211 u8 status;
1212 u8 rsvd[7];
1213 u64 start_time;
1214};
1215
1216struct bfa_diag_dport_result_s {
1217 wwn_t rp_pwwn;
1218 wwn_t rp_nwwn;
1219 u64 start_time;
1220 u64 end_time;
1221 u8 status;
1222 u8 mode;
1223 u8 rsvd;
1224 u8 speed;
1225 u16 buffer_required;
1226 u16 frmsz;
1227 u32 lpcnt;
1228 u32 pat;
1229 u32 roundtrip_latency;
1230 u32 est_cable_distance;
1231 struct bfa_diag_dport_subtest_result_s subtest[DPORT_TEST_MAX];
1232};
1233
1234struct bfa_diag_ledtest_s {
1235 u32 cmd;
1236 u32 color;
1237 u16 freq;
1238 u8 led;
1239 u8 rsvd[5];
1240};
1241
1242struct bfa_diag_loopback_s {
1243 u32 loopcnt;
1244 u32 pattern;
1245 u8 lb_mode;
1246 u8 speed;
1247 u8 rsvd[2];
1248};
1249
1250
1251
1252
1253enum bfa_phy_status_e {
1254 BFA_PHY_STATUS_GOOD = 0,
1255 BFA_PHY_STATUS_NOT_PRESENT = 1,
1256 BFA_PHY_STATUS_BAD = 2,
1257};
1258
1259
1260
1261
1262struct bfa_phy_attr_s {
1263 u32 status;
1264 u32 length;
1265 u32 fw_ver;
1266 u32 an_status;
1267 u32 pma_pmd_status;
1268 u32 pma_pmd_signal;
1269 u32 pcs_status;
1270};
1271
1272
1273
1274
1275struct bfa_phy_stats_s {
1276 u32 status;
1277 u32 link_breaks;
1278 u32 pma_pmd_fault;
1279 u32 pcs_fault;
1280 u32 speed_neg;
1281 u32 tx_eq_training;
1282 u32 tx_eq_timeout;
1283 u32 crc_error;
1284};
1285
1286#pragma pack()
1287
1288#endif
1289