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164#include <asm/io.h>
165#include <asm/byteorder.h>
166#include <asm/page.h>
167#include <linux/stddef.h>
168#include <linux/string.h>
169#include <linux/errno.h>
170#include <linux/kernel.h>
171#include <linux/ioport.h>
172#include <linux/slab.h>
173#include <linux/delay.h>
174#include <linux/pci.h>
175#include <linux/proc_fs.h>
176#include <linux/reboot.h>
177#include <linux/interrupt.h>
178
179#include <linux/blkdev.h>
180#include <linux/types.h>
181#include <linux/dma-mapping.h>
182
183#include <scsi/sg.h>
184#include "scsi.h"
185#include <scsi/scsi_host.h>
186
187#include "ips.h"
188
189#include <linux/module.h>
190
191#include <linux/stat.h>
192
193#include <linux/spinlock.h>
194#include <linux/init.h>
195
196#include <linux/smp.h>
197
198#ifdef MODULE
199static char *ips = NULL;
200module_param(ips, charp, 0);
201#endif
202
203
204
205
206#define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
207#define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
208
209#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
210 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
211 PCI_DMA_BIDIRECTIONAL : \
212 scb->scsi_cmd->sc_data_direction)
213
214#ifdef IPS_DEBUG
215#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
216#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
217#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
218#else
219#define METHOD_TRACE(s, i)
220#define DEBUG(i, s)
221#define DEBUG_VAR(i, s, v...)
222#endif
223
224
225
226
227static int ips_detect(struct scsi_host_template *);
228static int ips_release(struct Scsi_Host *);
229static int ips_eh_abort(struct scsi_cmnd *);
230static int ips_eh_reset(struct scsi_cmnd *);
231static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
232static const char *ips_info(struct Scsi_Host *);
233static irqreturn_t do_ipsintr(int, void *);
234static int ips_hainit(ips_ha_t *);
235static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
236static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
237static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
238static int ips_online(ips_ha_t *, ips_scb_t *);
239static int ips_inquiry(ips_ha_t *, ips_scb_t *);
240static int ips_rdcap(ips_ha_t *, ips_scb_t *);
241static int ips_msense(ips_ha_t *, ips_scb_t *);
242static int ips_reqsen(ips_ha_t *, ips_scb_t *);
243static int ips_deallocatescbs(ips_ha_t *, int);
244static int ips_allocatescbs(ips_ha_t *);
245static int ips_reset_copperhead(ips_ha_t *);
246static int ips_reset_copperhead_memio(ips_ha_t *);
247static int ips_reset_morpheus(ips_ha_t *);
248static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
249static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
250static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
251static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
252static int ips_isintr_copperhead(ips_ha_t *);
253static int ips_isintr_copperhead_memio(ips_ha_t *);
254static int ips_isintr_morpheus(ips_ha_t *);
255static int ips_wait(ips_ha_t *, int, int);
256static int ips_write_driver_status(ips_ha_t *, int);
257static int ips_read_adapter_status(ips_ha_t *, int);
258static int ips_read_subsystem_parameters(ips_ha_t *, int);
259static int ips_read_config(ips_ha_t *, int);
260static int ips_clear_adapter(ips_ha_t *, int);
261static int ips_readwrite_page5(ips_ha_t *, int, int);
262static int ips_init_copperhead(ips_ha_t *);
263static int ips_init_copperhead_memio(ips_ha_t *);
264static int ips_init_morpheus(ips_ha_t *);
265static int ips_isinit_copperhead(ips_ha_t *);
266static int ips_isinit_copperhead_memio(ips_ha_t *);
267static int ips_isinit_morpheus(ips_ha_t *);
268static int ips_erase_bios(ips_ha_t *);
269static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
270static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
271static int ips_erase_bios_memio(ips_ha_t *);
272static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
273static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
274static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
275static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
276static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
277static void ips_free_flash_copperhead(ips_ha_t * ha);
278static void ips_get_bios_version(ips_ha_t *, int);
279static void ips_identify_controller(ips_ha_t *);
280static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
281static void ips_enable_int_copperhead(ips_ha_t *);
282static void ips_enable_int_copperhead_memio(ips_ha_t *);
283static void ips_enable_int_morpheus(ips_ha_t *);
284static int ips_intr_copperhead(ips_ha_t *);
285static int ips_intr_morpheus(ips_ha_t *);
286static void ips_next(ips_ha_t *, int);
287static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
288static void ipsintr_done(ips_ha_t *, struct ips_scb *);
289static void ips_done(ips_ha_t *, ips_scb_t *);
290static void ips_free(ips_ha_t *);
291static void ips_init_scb(ips_ha_t *, ips_scb_t *);
292static void ips_freescb(ips_ha_t *, ips_scb_t *);
293static void ips_setup_funclist(ips_ha_t *);
294static void ips_statinit(ips_ha_t *);
295static void ips_statinit_memio(ips_ha_t *);
296static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
297static void ips_ffdc_reset(ips_ha_t *, int);
298static void ips_ffdc_time(ips_ha_t *);
299static uint32_t ips_statupd_copperhead(ips_ha_t *);
300static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
301static uint32_t ips_statupd_morpheus(ips_ha_t *);
302static ips_scb_t *ips_getscb(ips_ha_t *);
303static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
304static void ips_putq_wait_tail(ips_wait_queue_t *, struct scsi_cmnd *);
305static void ips_putq_copp_tail(ips_copp_queue_t *,
306 ips_copp_wait_item_t *);
307static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
308static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
309static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
310static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *,
311 struct scsi_cmnd *);
312static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
313 ips_copp_wait_item_t *);
314static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
315
316static int ips_is_passthru(struct scsi_cmnd *);
317static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
318static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
319static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
320static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
321 unsigned int count);
322static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
323 unsigned int count);
324
325static int ips_write_info(struct Scsi_Host *, char *, int);
326static int ips_show_info(struct seq_file *, struct Scsi_Host *);
327static int ips_host_info(ips_ha_t *, struct seq_file *);
328static int ips_abort_init(ips_ha_t * ha, int index);
329static int ips_init_phase2(int index);
330
331static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
332static int ips_register_scsi(int index);
333
334static int ips_poll_for_flush_complete(ips_ha_t * ha);
335static void ips_flush_and_reset(ips_ha_t *ha);
336
337
338
339
340static const char ips_name[] = "ips";
341static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS];
342static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS];
343static unsigned int ips_next_controller;
344static unsigned int ips_num_controllers;
345static unsigned int ips_released_controllers;
346static int ips_hotplug;
347static int ips_cmd_timeout = 60;
348static int ips_reset_timeout = 60 * 5;
349static int ips_force_memio = 1;
350static int ips_force_i2o = 1;
351static int ips_ioctlsize = IPS_IOCTL_SIZE;
352static int ips_cd_boot;
353static char *ips_FlashData = NULL;
354static dma_addr_t ips_flashbusaddr;
355static long ips_FlashDataInUse;
356static uint32_t MaxLiteCmds = 32;
357static struct scsi_host_template ips_driver_template = {
358 .detect = ips_detect,
359 .release = ips_release,
360 .info = ips_info,
361 .queuecommand = ips_queue,
362 .eh_abort_handler = ips_eh_abort,
363 .eh_host_reset_handler = ips_eh_reset,
364 .proc_name = "ips",
365 .show_info = ips_show_info,
366 .write_info = ips_write_info,
367 .slave_configure = ips_slave_configure,
368 .bios_param = ips_biosparam,
369 .this_id = -1,
370 .sg_tablesize = IPS_MAX_SG,
371 .cmd_per_lun = 3,
372 .use_clustering = ENABLE_CLUSTERING,
373 .no_write_same = 1,
374};
375
376
377
378static struct pci_device_id ips_pci_table[] = {
379 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
380 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
381 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
382 { 0, }
383};
384
385MODULE_DEVICE_TABLE( pci, ips_pci_table );
386
387static char ips_hot_plug_name[] = "ips";
388
389static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
390static void ips_remove_device(struct pci_dev *pci_dev);
391
392static struct pci_driver ips_pci_driver = {
393 .name = ips_hot_plug_name,
394 .id_table = ips_pci_table,
395 .probe = ips_insert_device,
396 .remove = ips_remove_device,
397};
398
399
400
401
402
403static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
404
405#define MAX_ADAPTER_NAME 15
406
407static char ips_adapter_name[][30] = {
408 "ServeRAID",
409 "ServeRAID II",
410 "ServeRAID on motherboard",
411 "ServeRAID on motherboard",
412 "ServeRAID 3H",
413 "ServeRAID 3L",
414 "ServeRAID 4H",
415 "ServeRAID 4M",
416 "ServeRAID 4L",
417 "ServeRAID 4Mx",
418 "ServeRAID 4Lx",
419 "ServeRAID 5i",
420 "ServeRAID 5i",
421 "ServeRAID 6M",
422 "ServeRAID 6i",
423 "ServeRAID 7t",
424 "ServeRAID 7k",
425 "ServeRAID 7M"
426};
427
428static struct notifier_block ips_notifier = {
429 ips_halt, NULL, 0
430};
431
432
433
434
435static char ips_command_direction[] = {
436 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
437 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
438 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
439 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
440 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
441 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
442 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
443 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
444 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
445 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
446 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
447 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
448 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
449 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
450 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
451 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
453 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
454 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
470 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
471 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
472 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
487};
488
489
490
491
492
493
494
495
496
497
498
499static int
500ips_setup(char *ips_str)
501{
502
503 int i;
504 char *key;
505 char *value;
506 IPS_OPTION options[] = {
507 {"noi2o", &ips_force_i2o, 0},
508 {"nommap", &ips_force_memio, 0},
509 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
510 {"cdboot", &ips_cd_boot, 0},
511 {"maxcmds", &MaxLiteCmds, 32},
512 };
513
514
515
516 while ((key = strsep(&ips_str, ",."))) {
517 if (!*key)
518 continue;
519 value = strchr(key, ':');
520 if (value)
521 *value++ = '\0';
522
523
524
525
526 for (i = 0; i < ARRAY_SIZE(options); i++) {
527 if (strncasecmp
528 (key, options[i].option_name,
529 strlen(options[i].option_name)) == 0) {
530 if (value)
531 *options[i].option_flag =
532 simple_strtoul(value, NULL, 0);
533 else
534 *options[i].option_flag =
535 options[i].option_value;
536 break;
537 }
538 }
539 }
540
541 return (1);
542}
543
544__setup("ips=", ips_setup);
545
546
547
548
549
550
551
552
553
554
555
556
557static int
558ips_detect(struct scsi_host_template * SHT)
559{
560 int i;
561
562 METHOD_TRACE("ips_detect", 1);
563
564#ifdef MODULE
565 if (ips)
566 ips_setup(ips);
567#endif
568
569 for (i = 0; i < ips_num_controllers; i++) {
570 if (ips_register_scsi(i))
571 ips_free(ips_ha[i]);
572 ips_released_controllers++;
573 }
574 ips_hotplug = 1;
575 return (ips_num_controllers);
576}
577
578
579
580
581
582static void
583ips_setup_funclist(ips_ha_t * ha)
584{
585
586
587
588
589 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
590
591 ha->func.isintr = ips_isintr_morpheus;
592 ha->func.isinit = ips_isinit_morpheus;
593 ha->func.issue = ips_issue_i2o_memio;
594 ha->func.init = ips_init_morpheus;
595 ha->func.statupd = ips_statupd_morpheus;
596 ha->func.reset = ips_reset_morpheus;
597 ha->func.intr = ips_intr_morpheus;
598 ha->func.enableint = ips_enable_int_morpheus;
599 } else if (IPS_USE_MEMIO(ha)) {
600
601 ha->func.isintr = ips_isintr_copperhead_memio;
602 ha->func.isinit = ips_isinit_copperhead_memio;
603 ha->func.init = ips_init_copperhead_memio;
604 ha->func.statupd = ips_statupd_copperhead_memio;
605 ha->func.statinit = ips_statinit_memio;
606 ha->func.reset = ips_reset_copperhead_memio;
607 ha->func.intr = ips_intr_copperhead;
608 ha->func.erasebios = ips_erase_bios_memio;
609 ha->func.programbios = ips_program_bios_memio;
610 ha->func.verifybios = ips_verify_bios_memio;
611 ha->func.enableint = ips_enable_int_copperhead_memio;
612 if (IPS_USE_I2O_DELIVER(ha))
613 ha->func.issue = ips_issue_i2o_memio;
614 else
615 ha->func.issue = ips_issue_copperhead_memio;
616 } else {
617
618 ha->func.isintr = ips_isintr_copperhead;
619 ha->func.isinit = ips_isinit_copperhead;
620 ha->func.init = ips_init_copperhead;
621 ha->func.statupd = ips_statupd_copperhead;
622 ha->func.statinit = ips_statinit;
623 ha->func.reset = ips_reset_copperhead;
624 ha->func.intr = ips_intr_copperhead;
625 ha->func.erasebios = ips_erase_bios;
626 ha->func.programbios = ips_program_bios;
627 ha->func.verifybios = ips_verify_bios;
628 ha->func.enableint = ips_enable_int_copperhead;
629
630 if (IPS_USE_I2O_DELIVER(ha))
631 ha->func.issue = ips_issue_i2o;
632 else
633 ha->func.issue = ips_issue_copperhead;
634 }
635}
636
637
638
639
640
641
642
643
644
645
646static int
647ips_release(struct Scsi_Host *sh)
648{
649 ips_scb_t *scb;
650 ips_ha_t *ha;
651 int i;
652
653 METHOD_TRACE("ips_release", 1);
654
655 scsi_remove_host(sh);
656
657 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
658
659 if (i == IPS_MAX_ADAPTERS) {
660 printk(KERN_WARNING
661 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
662 BUG();
663 return (FALSE);
664 }
665
666 ha = IPS_HA(sh);
667
668 if (!ha)
669 return (FALSE);
670
671
672 scb = &ha->scbs[ha->max_cmds - 1];
673
674 ips_init_scb(ha, scb);
675
676 scb->timeout = ips_cmd_timeout;
677 scb->cdb[0] = IPS_CMD_FLUSH;
678
679 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
680 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
681 scb->cmd.flush_cache.state = IPS_NORM_STATE;
682 scb->cmd.flush_cache.reserved = 0;
683 scb->cmd.flush_cache.reserved2 = 0;
684 scb->cmd.flush_cache.reserved3 = 0;
685 scb->cmd.flush_cache.reserved4 = 0;
686
687 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
688
689
690 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
691 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
692
693 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
694
695 ips_sh[i] = NULL;
696 ips_ha[i] = NULL;
697
698
699 ips_free(ha);
700
701
702 free_irq(ha->pcidev->irq, ha);
703
704 scsi_host_put(sh);
705
706 ips_released_controllers++;
707
708 return (FALSE);
709}
710
711
712
713
714
715
716
717
718
719
720static int
721ips_halt(struct notifier_block *nb, ulong event, void *buf)
722{
723 ips_scb_t *scb;
724 ips_ha_t *ha;
725 int i;
726
727 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
728 (event != SYS_POWER_OFF))
729 return (NOTIFY_DONE);
730
731 for (i = 0; i < ips_next_controller; i++) {
732 ha = (ips_ha_t *) ips_ha[i];
733
734 if (!ha)
735 continue;
736
737 if (!ha->active)
738 continue;
739
740
741 scb = &ha->scbs[ha->max_cmds - 1];
742
743 ips_init_scb(ha, scb);
744
745 scb->timeout = ips_cmd_timeout;
746 scb->cdb[0] = IPS_CMD_FLUSH;
747
748 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
749 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
750 scb->cmd.flush_cache.state = IPS_NORM_STATE;
751 scb->cmd.flush_cache.reserved = 0;
752 scb->cmd.flush_cache.reserved2 = 0;
753 scb->cmd.flush_cache.reserved3 = 0;
754 scb->cmd.flush_cache.reserved4 = 0;
755
756 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
757
758
759 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
760 IPS_FAILURE)
761 IPS_PRINTK(KERN_WARNING, ha->pcidev,
762 "Incomplete Flush.\n");
763 else
764 IPS_PRINTK(KERN_WARNING, ha->pcidev,
765 "Flushing Complete.\n");
766 }
767
768 return (NOTIFY_OK);
769}
770
771
772
773
774
775
776
777
778
779
780int ips_eh_abort(struct scsi_cmnd *SC)
781{
782 ips_ha_t *ha;
783 ips_copp_wait_item_t *item;
784 int ret;
785 struct Scsi_Host *host;
786
787 METHOD_TRACE("ips_eh_abort", 1);
788
789 if (!SC)
790 return (FAILED);
791
792 host = SC->device->host;
793 ha = (ips_ha_t *) SC->device->host->hostdata;
794
795 if (!ha)
796 return (FAILED);
797
798 if (!ha->active)
799 return (FAILED);
800
801 spin_lock(host->host_lock);
802
803
804 item = ha->copp_waitlist.head;
805 while ((item) && (item->scsi_cmd != SC))
806 item = item->next;
807
808 if (item) {
809
810 ips_removeq_copp(&ha->copp_waitlist, item);
811 ret = (SUCCESS);
812
813
814 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
815
816 ret = (SUCCESS);
817 } else {
818
819 ret = (FAILED);
820 }
821
822 spin_unlock(host->host_lock);
823 return ret;
824}
825
826
827
828
829
830
831
832
833
834
835
836
837static int __ips_eh_reset(struct scsi_cmnd *SC)
838{
839 int ret;
840 int i;
841 ips_ha_t *ha;
842 ips_scb_t *scb;
843 ips_copp_wait_item_t *item;
844
845 METHOD_TRACE("ips_eh_reset", 1);
846
847#ifdef NO_IPS_RESET
848 return (FAILED);
849#else
850
851 if (!SC) {
852 DEBUG(1, "Reset called with NULL scsi command");
853
854 return (FAILED);
855 }
856
857 ha = (ips_ha_t *) SC->device->host->hostdata;
858
859 if (!ha) {
860 DEBUG(1, "Reset called with NULL ha struct");
861
862 return (FAILED);
863 }
864
865 if (!ha->active)
866 return (FAILED);
867
868
869 item = ha->copp_waitlist.head;
870 while ((item) && (item->scsi_cmd != SC))
871 item = item->next;
872
873 if (item) {
874
875 ips_removeq_copp(&ha->copp_waitlist, item);
876 return (SUCCESS);
877 }
878
879
880 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
881
882 return (SUCCESS);
883 }
884
885
886
887
888
889
890
891
892
893
894
895 if (ha->ioctl_reset == 0) {
896 scb = &ha->scbs[ha->max_cmds - 1];
897
898 ips_init_scb(ha, scb);
899
900 scb->timeout = ips_cmd_timeout;
901 scb->cdb[0] = IPS_CMD_FLUSH;
902
903 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
904 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
905 scb->cmd.flush_cache.state = IPS_NORM_STATE;
906 scb->cmd.flush_cache.reserved = 0;
907 scb->cmd.flush_cache.reserved2 = 0;
908 scb->cmd.flush_cache.reserved3 = 0;
909 scb->cmd.flush_cache.reserved4 = 0;
910
911
912 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
913 if (ret == IPS_SUCCESS) {
914 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
915 "Reset Request - Flushed Cache\n");
916 return (SUCCESS);
917 }
918 }
919
920
921
922
923 ha->ioctl_reset = 0;
924
925
926
927
928
929 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
930 ret = (*ha->func.reset) (ha);
931
932 if (!ret) {
933 struct scsi_cmnd *scsi_cmd;
934
935 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
936 "Controller reset failed - controller now offline.\n");
937
938
939 DEBUG_VAR(1, "(%s%d) Failing active commands",
940 ips_name, ha->host_num);
941
942 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
943 scb->scsi_cmd->result = DID_ERROR << 16;
944 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
945 ips_freescb(ha, scb);
946 }
947
948
949 DEBUG_VAR(1, "(%s%d) Failing pending commands",
950 ips_name, ha->host_num);
951
952 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
953 scsi_cmd->result = DID_ERROR;
954 scsi_cmd->scsi_done(scsi_cmd);
955 }
956
957 ha->active = FALSE;
958 return (FAILED);
959 }
960
961 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
962 struct scsi_cmnd *scsi_cmd;
963
964 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
965 "Controller reset failed - controller now offline.\n");
966
967
968 DEBUG_VAR(1, "(%s%d) Failing active commands",
969 ips_name, ha->host_num);
970
971 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
972 scb->scsi_cmd->result = DID_ERROR << 16;
973 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
974 ips_freescb(ha, scb);
975 }
976
977
978 DEBUG_VAR(1, "(%s%d) Failing pending commands",
979 ips_name, ha->host_num);
980
981 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
982 scsi_cmd->result = DID_ERROR << 16;
983 scsi_cmd->scsi_done(scsi_cmd);
984 }
985
986 ha->active = FALSE;
987 return (FAILED);
988 }
989
990
991 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
992 struct timeval tv;
993
994 do_gettimeofday(&tv);
995 ha->last_ffdc = tv.tv_sec;
996 ha->reset_count++;
997 ips_ffdc_reset(ha, IPS_INTR_IORL);
998 }
999
1000
1001 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1002
1003 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1004 scb->scsi_cmd->result = DID_RESET << 16;
1005 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1006 ips_freescb(ha, scb);
1007 }
1008
1009
1010 for (i = 1; i < ha->nbus; i++)
1011 ha->dcdb_active[i - 1] = 0;
1012
1013
1014 ha->num_ioctl = 0;
1015
1016 ips_next(ha, IPS_INTR_IORL);
1017
1018 return (SUCCESS);
1019#endif
1020
1021}
1022
1023static int ips_eh_reset(struct scsi_cmnd *SC)
1024{
1025 int rc;
1026
1027 spin_lock_irq(SC->device->host->host_lock);
1028 rc = __ips_eh_reset(SC);
1029 spin_unlock_irq(SC->device->host->host_lock);
1030
1031 return rc;
1032}
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
1047{
1048 ips_ha_t *ha;
1049 ips_passthru_t *pt;
1050
1051 METHOD_TRACE("ips_queue", 1);
1052
1053 ha = (ips_ha_t *) SC->device->host->hostdata;
1054
1055 if (!ha)
1056 return (1);
1057
1058 if (!ha->active)
1059 return (DID_ERROR);
1060
1061 if (ips_is_passthru(SC)) {
1062 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1063 SC->result = DID_BUS_BUSY << 16;
1064 done(SC);
1065
1066 return (0);
1067 }
1068 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1069 SC->result = DID_BUS_BUSY << 16;
1070 done(SC);
1071
1072 return (0);
1073 }
1074
1075 SC->scsi_done = done;
1076
1077 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1078 ips_name,
1079 ha->host_num,
1080 SC->cmnd[0],
1081 SC->device->channel, SC->device->id, SC->device->lun);
1082
1083
1084 if ((scmd_channel(SC) > 0)
1085 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1086 SC->result = DID_NO_CONNECT << 16;
1087 done(SC);
1088
1089 return (0);
1090 }
1091
1092 if (ips_is_passthru(SC)) {
1093
1094 ips_copp_wait_item_t *scratch;
1095
1096
1097
1098
1099 pt = (ips_passthru_t *) scsi_sglist(SC);
1100 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1101 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1102 if (ha->scb_activelist.count != 0) {
1103 SC->result = DID_BUS_BUSY << 16;
1104 done(SC);
1105 return (0);
1106 }
1107 ha->ioctl_reset = 1;
1108 __ips_eh_reset(SC);
1109 SC->result = DID_OK << 16;
1110 SC->scsi_done(SC);
1111 return (0);
1112 }
1113
1114
1115 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1116
1117 if (!scratch) {
1118 SC->result = DID_ERROR << 16;
1119 done(SC);
1120
1121 return (0);
1122 }
1123
1124 scratch->scsi_cmd = SC;
1125 scratch->next = NULL;
1126
1127 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1128 } else {
1129 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1130 }
1131
1132 ips_next(ha, IPS_INTR_IORL);
1133
1134 return (0);
1135}
1136
1137static DEF_SCSI_QCMD(ips_queue)
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1149 sector_t capacity, int geom[])
1150{
1151 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1152 int heads;
1153 int sectors;
1154 int cylinders;
1155
1156 METHOD_TRACE("ips_biosparam", 1);
1157
1158 if (!ha)
1159
1160 return (0);
1161
1162 if (!ha->active)
1163 return (0);
1164
1165 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1166
1167 return (0);
1168
1169 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1170 heads = IPS_NORM_HEADS;
1171 sectors = IPS_NORM_SECTORS;
1172 } else {
1173 heads = IPS_COMP_HEADS;
1174 sectors = IPS_COMP_SECTORS;
1175 }
1176
1177 cylinders = (unsigned long) capacity / (heads * sectors);
1178
1179 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1180 heads, sectors, cylinders);
1181
1182 geom[0] = heads;
1183 geom[1] = sectors;
1184 geom[2] = cylinders;
1185
1186 return (0);
1187}
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198static int
1199ips_slave_configure(struct scsi_device * SDptr)
1200{
1201 ips_ha_t *ha;
1202 int min;
1203
1204 ha = IPS_HA(SDptr->host);
1205 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1206 min = ha->max_cmds / 2;
1207 if (ha->enq->ucLogDriveCount <= 2)
1208 min = ha->max_cmds - 1;
1209 scsi_change_queue_depth(SDptr, min);
1210 }
1211
1212 SDptr->skip_ms_page_8 = 1;
1213 SDptr->skip_ms_page_3f = 1;
1214 return 0;
1215}
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226static irqreturn_t
1227do_ipsintr(int irq, void *dev_id)
1228{
1229 ips_ha_t *ha;
1230 struct Scsi_Host *host;
1231 int irqstatus;
1232
1233 METHOD_TRACE("do_ipsintr", 2);
1234
1235 ha = (ips_ha_t *) dev_id;
1236 if (!ha)
1237 return IRQ_NONE;
1238 host = ips_sh[ha->host_num];
1239
1240 if (!host) {
1241 (*ha->func.intr) (ha);
1242 return IRQ_HANDLED;
1243 }
1244
1245 spin_lock(host->host_lock);
1246
1247 if (!ha->active) {
1248 spin_unlock(host->host_lock);
1249 return IRQ_HANDLED;
1250 }
1251
1252 irqstatus = (*ha->func.intr) (ha);
1253
1254 spin_unlock(host->host_lock);
1255
1256
1257 ips_next(ha, IPS_INTR_ON);
1258 return IRQ_RETVAL(irqstatus);
1259}
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272int
1273ips_intr_copperhead(ips_ha_t * ha)
1274{
1275 ips_stat_t *sp;
1276 ips_scb_t *scb;
1277 IPS_STATUS cstatus;
1278 int intrstatus;
1279
1280 METHOD_TRACE("ips_intr", 2);
1281
1282 if (!ha)
1283 return 0;
1284
1285 if (!ha->active)
1286 return 0;
1287
1288 intrstatus = (*ha->func.isintr) (ha);
1289
1290 if (!intrstatus) {
1291
1292
1293
1294
1295 return 0;
1296 }
1297
1298 while (TRUE) {
1299 sp = &ha->sp;
1300
1301 intrstatus = (*ha->func.isintr) (ha);
1302
1303 if (!intrstatus)
1304 break;
1305 else
1306 cstatus.value = (*ha->func.statupd) (ha);
1307
1308 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1309
1310 continue;
1311 }
1312
1313 ips_chkstatus(ha, &cstatus);
1314 scb = (ips_scb_t *) sp->scb_addr;
1315
1316
1317
1318
1319
1320 (*scb->callback) (ha, scb);
1321 }
1322 return 1;
1323}
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336int
1337ips_intr_morpheus(ips_ha_t * ha)
1338{
1339 ips_stat_t *sp;
1340 ips_scb_t *scb;
1341 IPS_STATUS cstatus;
1342 int intrstatus;
1343
1344 METHOD_TRACE("ips_intr_morpheus", 2);
1345
1346 if (!ha)
1347 return 0;
1348
1349 if (!ha->active)
1350 return 0;
1351
1352 intrstatus = (*ha->func.isintr) (ha);
1353
1354 if (!intrstatus) {
1355
1356
1357
1358
1359 return 0;
1360 }
1361
1362 while (TRUE) {
1363 sp = &ha->sp;
1364
1365 intrstatus = (*ha->func.isintr) (ha);
1366
1367 if (!intrstatus)
1368 break;
1369 else
1370 cstatus.value = (*ha->func.statupd) (ha);
1371
1372 if (cstatus.value == 0xffffffff)
1373
1374 break;
1375
1376 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1377 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1378 "Spurious interrupt; no ccb.\n");
1379
1380 continue;
1381 }
1382
1383 ips_chkstatus(ha, &cstatus);
1384 scb = (ips_scb_t *) sp->scb_addr;
1385
1386
1387
1388
1389
1390 (*scb->callback) (ha, scb);
1391 }
1392 return 1;
1393}
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404static const char *
1405ips_info(struct Scsi_Host *SH)
1406{
1407 static char buffer[256];
1408 char *bp;
1409 ips_ha_t *ha;
1410
1411 METHOD_TRACE("ips_info", 1);
1412
1413 ha = IPS_HA(SH);
1414
1415 if (!ha)
1416 return (NULL);
1417
1418 bp = &buffer[0];
1419 memset(bp, 0, sizeof (buffer));
1420
1421 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1422 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1423
1424 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1425 strcat(bp, " <");
1426 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1427 strcat(bp, ">");
1428 }
1429
1430 return (bp);
1431}
1432
1433static int
1434ips_write_info(struct Scsi_Host *host, char *buffer, int length)
1435{
1436 int i;
1437 ips_ha_t *ha = NULL;
1438
1439
1440 for (i = 0; i < ips_next_controller; i++) {
1441 if (ips_sh[i]) {
1442 if (ips_sh[i] == host) {
1443 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1444 break;
1445 }
1446 }
1447 }
1448
1449 if (!ha)
1450 return (-EINVAL);
1451
1452 return 0;
1453}
1454
1455static int
1456ips_show_info(struct seq_file *m, struct Scsi_Host *host)
1457{
1458 int i;
1459 ips_ha_t *ha = NULL;
1460
1461
1462 for (i = 0; i < ips_next_controller; i++) {
1463 if (ips_sh[i]) {
1464 if (ips_sh[i] == host) {
1465 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1466 break;
1467 }
1468 }
1469 }
1470
1471 if (!ha)
1472 return (-EINVAL);
1473
1474 return ips_host_info(ha, m);
1475}
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490static int ips_is_passthru(struct scsi_cmnd *SC)
1491{
1492 unsigned long flags;
1493
1494 METHOD_TRACE("ips_is_passthru", 1);
1495
1496 if (!SC)
1497 return (0);
1498
1499 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1500 (SC->device->channel == 0) &&
1501 (SC->device->id == IPS_ADAPTER_ID) &&
1502 (SC->device->lun == 0) && scsi_sglist(SC)) {
1503 struct scatterlist *sg = scsi_sglist(SC);
1504 char *buffer;
1505
1506
1507
1508 local_irq_save(flags);
1509 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
1510 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1511 buffer[2] == 'P' && buffer[3] == 'P') {
1512 kunmap_atomic(buffer - sg->offset);
1513 local_irq_restore(flags);
1514 return 1;
1515 }
1516 kunmap_atomic(buffer - sg->offset);
1517 local_irq_restore(flags);
1518 }
1519 return 0;
1520}
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530static int
1531ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1532{
1533 void *bigger_buf;
1534 dma_addr_t dma_busaddr;
1535
1536 if (ha->ioctl_data && length <= ha->ioctl_len)
1537 return 0;
1538
1539 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1540 if (bigger_buf) {
1541
1542 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1543 ha->ioctl_busaddr);
1544
1545 ha->ioctl_data = (char *) bigger_buf;
1546 ha->ioctl_len = length;
1547 ha->ioctl_busaddr = dma_busaddr;
1548 } else {
1549 return -1;
1550 }
1551 return 0;
1552}
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563static int
1564ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1565{
1566 ips_passthru_t *pt;
1567 int length = 0;
1568 int i, ret;
1569 struct scatterlist *sg = scsi_sglist(SC);
1570
1571 METHOD_TRACE("ips_make_passthru", 1);
1572
1573 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1574 length += sg->length;
1575
1576 if (length < sizeof (ips_passthru_t)) {
1577
1578 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1579 ips_name, ha->host_num);
1580 return (IPS_FAILURE);
1581 }
1582 if (ips_alloc_passthru_buffer(ha, length)) {
1583
1584
1585 if (ha->ioctl_data) {
1586 pt = (ips_passthru_t *) ha->ioctl_data;
1587 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1588 pt->BasicStatus = 0x0B;
1589 pt->ExtendedStatus = 0x00;
1590 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1591 }
1592 return IPS_FAILURE;
1593 }
1594 ha->ioctl_datasize = length;
1595
1596 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1597 pt = (ips_passthru_t *) ha->ioctl_data;
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609 switch (pt->CoppCmd) {
1610 case IPS_NUMCTRLS:
1611 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1612 &ips_num_controllers, sizeof (int));
1613 ips_scmd_buf_write(SC, ha->ioctl_data,
1614 sizeof (ips_passthru_t) + sizeof (int));
1615 SC->result = DID_OK << 16;
1616
1617 return (IPS_SUCCESS_IMM);
1618
1619 case IPS_COPPUSRCMD:
1620 case IPS_COPPIOCCMD:
1621 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1622 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1623
1624 DEBUG_VAR(1,
1625 "(%s%d) Passthru structure wrong size",
1626 ips_name, ha->host_num);
1627
1628 return (IPS_FAILURE);
1629 }
1630
1631 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1632 pt->CoppCP.cmd.flashfw.op_code ==
1633 IPS_CMD_RW_BIOSFW) {
1634 ret = ips_flash_copperhead(ha, pt, scb);
1635 ips_scmd_buf_write(SC, ha->ioctl_data,
1636 sizeof (ips_passthru_t));
1637 return ret;
1638 }
1639 if (ips_usrcmd(ha, pt, scb))
1640 return (IPS_SUCCESS);
1641 else
1642 return (IPS_FAILURE);
1643 }
1644
1645 break;
1646
1647 }
1648
1649 return (IPS_FAILURE);
1650}
1651
1652
1653
1654
1655
1656
1657static int
1658ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1659{
1660 int datasize;
1661
1662
1663
1664 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1665 if (ips_usrcmd(ha, pt, scb))
1666 return IPS_SUCCESS;
1667 else
1668 return IPS_FAILURE;
1669 }
1670 pt->BasicStatus = 0x0B;
1671 pt->ExtendedStatus = 0;
1672 scb->scsi_cmd->result = DID_OK << 16;
1673
1674
1675 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1676 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1677 pt->BasicStatus = 0;
1678 return ips_flash_bios(ha, pt, scb);
1679 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1680 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1681 ha->flash_data = ips_FlashData;
1682 ha->flash_busaddr = ips_flashbusaddr;
1683 ha->flash_len = PAGE_SIZE << 7;
1684 ha->flash_datasize = 0;
1685 } else if (!ha->flash_data) {
1686 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1687 pt->CoppCP.cmd.flashfw.count;
1688 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1689 datasize,
1690 &ha->flash_busaddr);
1691 if (!ha->flash_data){
1692 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1693 return IPS_FAILURE;
1694 }
1695 ha->flash_datasize = 0;
1696 ha->flash_len = datasize;
1697 } else
1698 return IPS_FAILURE;
1699 } else {
1700 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1701 ha->flash_len) {
1702 ips_free_flash_copperhead(ha);
1703 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1704 "failed size sanity check\n");
1705 return IPS_FAILURE;
1706 }
1707 }
1708 if (!ha->flash_data)
1709 return IPS_FAILURE;
1710 pt->BasicStatus = 0;
1711 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1712 pt->CoppCP.cmd.flashfw.count);
1713 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1714 if (pt->CoppCP.cmd.flashfw.packet_num ==
1715 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1716 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1717 return ips_flash_bios(ha, pt, scb);
1718 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1719 return ips_flash_firmware(ha, pt, scb);
1720 }
1721 return IPS_SUCCESS_IMM;
1722}
1723
1724
1725
1726
1727
1728
1729static int
1730ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1731{
1732
1733 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1734 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1735 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1736 (!ha->func.verifybios))
1737 goto error;
1738 if ((*ha->func.erasebios) (ha)) {
1739 DEBUG_VAR(1,
1740 "(%s%d) flash bios failed - unable to erase flash",
1741 ips_name, ha->host_num);
1742 goto error;
1743 } else
1744 if ((*ha->func.programbios) (ha,
1745 ha->flash_data +
1746 IPS_BIOS_HEADER,
1747 ha->flash_datasize -
1748 IPS_BIOS_HEADER, 0)) {
1749 DEBUG_VAR(1,
1750 "(%s%d) flash bios failed - unable to flash",
1751 ips_name, ha->host_num);
1752 goto error;
1753 } else
1754 if ((*ha->func.verifybios) (ha,
1755 ha->flash_data +
1756 IPS_BIOS_HEADER,
1757 ha->flash_datasize -
1758 IPS_BIOS_HEADER, 0)) {
1759 DEBUG_VAR(1,
1760 "(%s%d) flash bios failed - unable to verify flash",
1761 ips_name, ha->host_num);
1762 goto error;
1763 }
1764 ips_free_flash_copperhead(ha);
1765 return IPS_SUCCESS_IMM;
1766 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1767 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1768 if (!ha->func.erasebios)
1769 goto error;
1770 if ((*ha->func.erasebios) (ha)) {
1771 DEBUG_VAR(1,
1772 "(%s%d) flash bios failed - unable to erase flash",
1773 ips_name, ha->host_num);
1774 goto error;
1775 }
1776 return IPS_SUCCESS_IMM;
1777 }
1778 error:
1779 pt->BasicStatus = 0x0B;
1780 pt->ExtendedStatus = 0x00;
1781 ips_free_flash_copperhead(ha);
1782 return IPS_FAILURE;
1783}
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793static int
1794ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1795 ips_scb_t * scb, int indx, unsigned int e_len)
1796{
1797
1798 int ret_val = 0;
1799
1800 if ((scb->data_len + e_len) > ha->max_xfer) {
1801 e_len = ha->max_xfer - scb->data_len;
1802 scb->breakup = indx;
1803 ++scb->sg_break;
1804 ret_val = -1;
1805 } else {
1806 scb->breakup = 0;
1807 scb->sg_break = 0;
1808 }
1809 if (IPS_USE_ENH_SGLIST(ha)) {
1810 scb->sg_list.enh_list[indx].address_lo =
1811 cpu_to_le32(pci_dma_lo32(busaddr));
1812 scb->sg_list.enh_list[indx].address_hi =
1813 cpu_to_le32(pci_dma_hi32(busaddr));
1814 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1815 } else {
1816 scb->sg_list.std_list[indx].address =
1817 cpu_to_le32(pci_dma_lo32(busaddr));
1818 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1819 }
1820
1821 ++scb->sg_len;
1822 scb->data_len += e_len;
1823 return ret_val;
1824}
1825
1826
1827
1828
1829
1830
1831static int
1832ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1833{
1834 IPS_SG_LIST sg_list;
1835 uint32_t cmd_busaddr;
1836
1837 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1838 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1839 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1840 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1841 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1842 } else {
1843 pt->BasicStatus = 0x0B;
1844 pt->ExtendedStatus = 0x00;
1845 ips_free_flash_copperhead(ha);
1846 return IPS_FAILURE;
1847 }
1848
1849 sg_list.list = scb->sg_list.list;
1850 cmd_busaddr = scb->scb_busaddr;
1851
1852 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1853
1854 scb->sg_list.list = sg_list.list;
1855 scb->scb_busaddr = cmd_busaddr;
1856 scb->bus = scb->scsi_cmd->device->channel;
1857 scb->target_id = scb->scsi_cmd->device->id;
1858 scb->lun = scb->scsi_cmd->device->lun;
1859 scb->sg_len = 0;
1860 scb->data_len = 0;
1861 scb->flags = 0;
1862 scb->op_code = 0;
1863 scb->callback = ipsintr_done;
1864 scb->timeout = ips_cmd_timeout;
1865
1866 scb->data_len = ha->flash_datasize;
1867 scb->data_busaddr =
1868 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1869 IPS_DMA_DIR(scb));
1870 scb->flags |= IPS_SCB_MAP_SINGLE;
1871 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1872 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1873 if (pt->TimeOut)
1874 scb->timeout = pt->TimeOut;
1875 scb->scsi_cmd->result = DID_OK << 16;
1876 return IPS_SUCCESS;
1877}
1878
1879
1880
1881
1882
1883
1884static void
1885ips_free_flash_copperhead(ips_ha_t * ha)
1886{
1887 if (ha->flash_data == ips_FlashData)
1888 test_and_clear_bit(0, &ips_FlashDataInUse);
1889 else if (ha->flash_data)
1890 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1891 ha->flash_busaddr);
1892 ha->flash_data = NULL;
1893}
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904static int
1905ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1906{
1907 IPS_SG_LIST sg_list;
1908 uint32_t cmd_busaddr;
1909
1910 METHOD_TRACE("ips_usrcmd", 1);
1911
1912 if ((!scb) || (!pt) || (!ha))
1913 return (0);
1914
1915
1916 sg_list.list = scb->sg_list.list;
1917 cmd_busaddr = scb->scb_busaddr;
1918
1919 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1920 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1921
1922
1923 scb->sg_list.list = sg_list.list;
1924 scb->scb_busaddr = cmd_busaddr;
1925 scb->bus = scb->scsi_cmd->device->channel;
1926 scb->target_id = scb->scsi_cmd->device->id;
1927 scb->lun = scb->scsi_cmd->device->lun;
1928 scb->sg_len = 0;
1929 scb->data_len = 0;
1930 scb->flags = 0;
1931 scb->op_code = 0;
1932 scb->callback = ipsintr_done;
1933 scb->timeout = ips_cmd_timeout;
1934 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1935
1936
1937 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1938 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1939 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1940 return (0);
1941
1942 if (pt->CmdBSize) {
1943 scb->data_len = pt->CmdBSize;
1944 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1945 } else {
1946 scb->data_busaddr = 0L;
1947 }
1948
1949 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1950 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1951 (unsigned long) &scb->
1952 dcdb -
1953 (unsigned long) scb);
1954
1955 if (pt->CmdBSize) {
1956 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1957 scb->dcdb.buffer_pointer =
1958 cpu_to_le32(scb->data_busaddr);
1959 else
1960 scb->cmd.basic_io.sg_addr =
1961 cpu_to_le32(scb->data_busaddr);
1962 }
1963
1964
1965 if (pt->TimeOut) {
1966 scb->timeout = pt->TimeOut;
1967
1968 if (pt->TimeOut <= 10)
1969 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1970 else if (pt->TimeOut <= 60)
1971 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1972 else
1973 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1974 }
1975
1976
1977 scb->scsi_cmd->result = DID_OK << 16;
1978
1979
1980 return (1);
1981}
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992static void
1993ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1994{
1995 ips_passthru_t *pt;
1996
1997 METHOD_TRACE("ips_cleanup_passthru", 1);
1998
1999 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
2000 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2001 ips_name, ha->host_num);
2002
2003 return;
2004 }
2005 pt = (ips_passthru_t *) ha->ioctl_data;
2006
2007
2008 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2009 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2010
2011 pt->BasicStatus = scb->basic_status;
2012 pt->ExtendedStatus = scb->extended_status;
2013 pt->AdapterType = ha->ad_type;
2014
2015 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2016 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2017 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2018 ips_free_flash_copperhead(ha);
2019
2020 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2021}
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032static int
2033ips_host_info(ips_ha_t *ha, struct seq_file *m)
2034{
2035 METHOD_TRACE("ips_host_info", 1);
2036
2037 seq_puts(m, "\nIBM ServeRAID General Information:\n\n");
2038
2039 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2040 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2041 seq_printf(m, "\tController Type : %s\n",
2042 ips_adapter_name[ha->ad_type - 1]);
2043 else
2044 seq_puts(m, "\tController Type : Unknown\n");
2045
2046 if (ha->io_addr)
2047 seq_printf(m,
2048 "\tIO region : 0x%x (%d bytes)\n",
2049 ha->io_addr, ha->io_len);
2050
2051 if (ha->mem_addr) {
2052 seq_printf(m,
2053 "\tMemory region : 0x%x (%d bytes)\n",
2054 ha->mem_addr, ha->mem_len);
2055 seq_printf(m,
2056 "\tShared memory address : 0x%lx\n",
2057 (unsigned long)ha->mem_ptr);
2058 }
2059
2060 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
2061
2062
2063
2064
2065 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2066 if (ha->nvram->bios_low[3] == 0) {
2067 seq_printf(m,
2068 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2069 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2070 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2071 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2072 ha->nvram->bios_low[2]);
2073
2074 } else {
2075 seq_printf(m,
2076 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2077 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2078 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2079 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2080 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2081 }
2082
2083 }
2084
2085 if (ha->enq->CodeBlkVersion[7] == 0) {
2086 seq_printf(m,
2087 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2088 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2089 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2090 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2091 ha->enq->CodeBlkVersion[6]);
2092 } else {
2093 seq_printf(m,
2094 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2095 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2096 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2097 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2098 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2099 }
2100
2101 if (ha->enq->BootBlkVersion[7] == 0) {
2102 seq_printf(m,
2103 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2104 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2105 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2106 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2107 ha->enq->BootBlkVersion[6]);
2108 } else {
2109 seq_printf(m,
2110 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2111 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2112 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2113 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2114 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2115 }
2116
2117 seq_printf(m, "\tDriver Version : %s%s\n",
2118 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2119
2120 seq_printf(m, "\tDriver Build : %d\n",
2121 IPS_BUILD_IDENT);
2122
2123 seq_printf(m, "\tMax Physical Devices : %d\n",
2124 ha->enq->ucMaxPhysicalDevices);
2125 seq_printf(m, "\tMax Active Commands : %d\n",
2126 ha->max_cmds);
2127 seq_printf(m, "\tCurrent Queued Commands : %d\n",
2128 ha->scb_waitlist.count);
2129 seq_printf(m, "\tCurrent Active Commands : %d\n",
2130 ha->scb_activelist.count - ha->num_ioctl);
2131 seq_printf(m, "\tCurrent Queued PT Commands : %d\n",
2132 ha->copp_waitlist.count);
2133 seq_printf(m, "\tCurrent Active PT Commands : %d\n",
2134 ha->num_ioctl);
2135
2136 seq_putc(m, '\n');
2137
2138 return 0;
2139}
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150static void
2151ips_identify_controller(ips_ha_t * ha)
2152{
2153 METHOD_TRACE("ips_identify_controller", 1);
2154
2155 switch (ha->pcidev->device) {
2156 case IPS_DEVICEID_COPPERHEAD:
2157 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2158 ha->ad_type = IPS_ADTYPE_SERVERAID;
2159 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2160 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2161 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2162 ha->ad_type = IPS_ADTYPE_NAVAJO;
2163 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2164 && (ha->slot_num == 0)) {
2165 ha->ad_type = IPS_ADTYPE_KIOWA;
2166 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2167 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2168 if (ha->enq->ucMaxPhysicalDevices == 15)
2169 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2170 else
2171 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2172 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2173 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2174 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2175 }
2176 break;
2177
2178 case IPS_DEVICEID_MORPHEUS:
2179 switch (ha->pcidev->subsystem_device) {
2180 case IPS_SUBDEVICEID_4L:
2181 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2182 break;
2183
2184 case IPS_SUBDEVICEID_4M:
2185 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2186 break;
2187
2188 case IPS_SUBDEVICEID_4MX:
2189 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2190 break;
2191
2192 case IPS_SUBDEVICEID_4LX:
2193 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2194 break;
2195
2196 case IPS_SUBDEVICEID_5I2:
2197 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2198 break;
2199
2200 case IPS_SUBDEVICEID_5I1:
2201 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2202 break;
2203 }
2204
2205 break;
2206
2207 case IPS_DEVICEID_MARCO:
2208 switch (ha->pcidev->subsystem_device) {
2209 case IPS_SUBDEVICEID_6M:
2210 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2211 break;
2212 case IPS_SUBDEVICEID_6I:
2213 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2214 break;
2215 case IPS_SUBDEVICEID_7k:
2216 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2217 break;
2218 case IPS_SUBDEVICEID_7M:
2219 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2220 break;
2221 }
2222 break;
2223 }
2224}
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235static void
2236ips_get_bios_version(ips_ha_t * ha, int intr)
2237{
2238 ips_scb_t *scb;
2239 int ret;
2240 uint8_t major;
2241 uint8_t minor;
2242 uint8_t subminor;
2243 uint8_t *buffer;
2244 char hexDigits[] =
2245 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2246 'D', 'E', 'F' };
2247
2248 METHOD_TRACE("ips_get_bios_version", 1);
2249
2250 major = 0;
2251 minor = 0;
2252
2253 strncpy(ha->bios_version, " ?", 8);
2254
2255 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2256 if (IPS_USE_MEMIO(ha)) {
2257
2258
2259
2260 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2261 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2262 udelay(25);
2263
2264 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2265 return;
2266
2267 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2268 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2269 udelay(25);
2270
2271 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2272 return;
2273
2274
2275 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2276 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2277 udelay(25);
2278
2279 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2280
2281
2282 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2283 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2284 udelay(25);
2285 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2286
2287
2288 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2289 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2290 udelay(25);
2291 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2292
2293 } else {
2294
2295
2296
2297 outl(0, ha->io_addr + IPS_REG_FLAP);
2298 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2299 udelay(25);
2300
2301 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2302 return;
2303
2304 outl(1, ha->io_addr + IPS_REG_FLAP);
2305 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2306 udelay(25);
2307
2308 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2309 return;
2310
2311
2312 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2313 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2314 udelay(25);
2315
2316 major = inb(ha->io_addr + IPS_REG_FLDP);
2317
2318
2319 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2320 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2321 udelay(25);
2322
2323 minor = inb(ha->io_addr + IPS_REG_FLDP);
2324
2325
2326 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2327 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2328 udelay(25);
2329
2330 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2331
2332 }
2333 } else {
2334
2335
2336 buffer = ha->ioctl_data;
2337
2338 memset(buffer, 0, 0x1000);
2339
2340 scb = &ha->scbs[ha->max_cmds - 1];
2341
2342 ips_init_scb(ha, scb);
2343
2344 scb->timeout = ips_cmd_timeout;
2345 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2346
2347 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2348 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2349 scb->cmd.flashfw.type = 1;
2350 scb->cmd.flashfw.direction = 0;
2351 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2352 scb->cmd.flashfw.total_packets = 1;
2353 scb->cmd.flashfw.packet_num = 0;
2354 scb->data_len = 0x1000;
2355 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2356
2357
2358 if (((ret =
2359 ips_send_wait(ha, scb, ips_cmd_timeout,
2360 intr)) == IPS_FAILURE)
2361 || (ret == IPS_SUCCESS_IMM)
2362 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2363
2364
2365 return;
2366 }
2367
2368 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2369 major = buffer[0x1ff + 0xC0];
2370 minor = buffer[0x1fe + 0xC0];
2371 subminor = buffer[0x1fd + 0xC0];
2372 } else {
2373 return;
2374 }
2375 }
2376
2377 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2378 ha->bios_version[1] = '.';
2379 ha->bios_version[2] = hexDigits[major & 0x0F];
2380 ha->bios_version[3] = hexDigits[subminor];
2381 ha->bios_version[4] = '.';
2382 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2383 ha->bios_version[6] = hexDigits[minor & 0x0F];
2384 ha->bios_version[7] = 0;
2385}
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398static int
2399ips_hainit(ips_ha_t * ha)
2400{
2401 int i;
2402 struct timeval tv;
2403
2404 METHOD_TRACE("ips_hainit", 1);
2405
2406 if (!ha)
2407 return (0);
2408
2409 if (ha->func.statinit)
2410 (*ha->func.statinit) (ha);
2411
2412 if (ha->func.enableint)
2413 (*ha->func.enableint) (ha);
2414
2415
2416 ha->reset_count = 1;
2417 do_gettimeofday(&tv);
2418 ha->last_ffdc = tv.tv_sec;
2419 ips_ffdc_reset(ha, IPS_INTR_IORL);
2420
2421 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2422 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2423 "unable to read config from controller.\n");
2424
2425 return (0);
2426 }
2427
2428 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2429 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2430 "unable to read controller status.\n");
2431
2432 return (0);
2433 }
2434
2435
2436 ips_identify_controller(ha);
2437
2438 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2439 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2440 "unable to read subsystem parameters.\n");
2441
2442 return (0);
2443 }
2444
2445
2446 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2447 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2448 "unable to write driver info to controller.\n");
2449
2450 return (0);
2451 }
2452
2453
2454 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2455 ips_clear_adapter(ha, IPS_INTR_IORL);
2456
2457
2458 ha->ntargets = IPS_MAX_TARGETS + 1;
2459 ha->nlun = 1;
2460 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2461
2462 switch (ha->conf->logical_drive[0].ucStripeSize) {
2463 case 4:
2464 ha->max_xfer = 0x10000;
2465 break;
2466
2467 case 5:
2468 ha->max_xfer = 0x20000;
2469 break;
2470
2471 case 6:
2472 ha->max_xfer = 0x40000;
2473 break;
2474
2475 case 7:
2476 default:
2477 ha->max_xfer = 0x80000;
2478 break;
2479 }
2480
2481
2482 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2483
2484 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2485 } else {
2486
2487 switch (ha->conf->logical_drive[0].ucStripeSize) {
2488 case 4:
2489 ha->max_cmds = 32;
2490 break;
2491
2492 case 5:
2493 ha->max_cmds = 16;
2494 break;
2495
2496 case 6:
2497 ha->max_cmds = 8;
2498 break;
2499
2500 case 7:
2501 default:
2502 ha->max_cmds = 4;
2503 break;
2504 }
2505 }
2506
2507
2508 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2509 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2510 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2511 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2512 ha->max_cmds = MaxLiteCmds;
2513 }
2514
2515
2516 ha->ha_id[0] = IPS_ADAPTER_ID;
2517 for (i = 1; i < ha->nbus; i++) {
2518 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2519 ha->dcdb_active[i - 1] = 0;
2520 }
2521
2522 return (1);
2523}
2524
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534static void
2535ips_next(ips_ha_t * ha, int intr)
2536{
2537 ips_scb_t *scb;
2538 struct scsi_cmnd *SC;
2539 struct scsi_cmnd *p;
2540 struct scsi_cmnd *q;
2541 ips_copp_wait_item_t *item;
2542 int ret;
2543 struct Scsi_Host *host;
2544 METHOD_TRACE("ips_next", 1);
2545
2546 if (!ha)
2547 return;
2548 host = ips_sh[ha->host_num];
2549
2550
2551
2552
2553 if (intr == IPS_INTR_ON)
2554 spin_lock(host->host_lock);
2555
2556 if ((ha->subsys->param[3] & 0x300000)
2557 && (ha->scb_activelist.count == 0)) {
2558 struct timeval tv;
2559
2560 do_gettimeofday(&tv);
2561
2562 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2563 ha->last_ffdc = tv.tv_sec;
2564 ips_ffdc_time(ha);
2565 }
2566 }
2567
2568
2569
2570
2571
2572
2573
2574
2575 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2576 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2577
2578 item = ips_removeq_copp_head(&ha->copp_waitlist);
2579 ha->num_ioctl++;
2580 if (intr == IPS_INTR_ON)
2581 spin_unlock(host->host_lock);
2582 scb->scsi_cmd = item->scsi_cmd;
2583 kfree(item);
2584
2585 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2586
2587 if (intr == IPS_INTR_ON)
2588 spin_lock(host->host_lock);
2589 switch (ret) {
2590 case IPS_FAILURE:
2591 if (scb->scsi_cmd) {
2592 scb->scsi_cmd->result = DID_ERROR << 16;
2593 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2594 }
2595
2596 ips_freescb(ha, scb);
2597 break;
2598 case IPS_SUCCESS_IMM:
2599 if (scb->scsi_cmd) {
2600 scb->scsi_cmd->result = DID_OK << 16;
2601 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2602 }
2603
2604 ips_freescb(ha, scb);
2605 break;
2606 default:
2607 break;
2608 }
2609
2610 if (ret != IPS_SUCCESS) {
2611 ha->num_ioctl--;
2612 continue;
2613 }
2614
2615 ret = ips_send_cmd(ha, scb);
2616
2617 if (ret == IPS_SUCCESS)
2618 ips_putq_scb_head(&ha->scb_activelist, scb);
2619 else
2620 ha->num_ioctl--;
2621
2622 switch (ret) {
2623 case IPS_FAILURE:
2624 if (scb->scsi_cmd) {
2625 scb->scsi_cmd->result = DID_ERROR << 16;
2626 }
2627
2628 ips_freescb(ha, scb);
2629 break;
2630 case IPS_SUCCESS_IMM:
2631 ips_freescb(ha, scb);
2632 break;
2633 default:
2634 break;
2635 }
2636
2637 }
2638
2639
2640
2641
2642
2643 p = ha->scb_waitlist.head;
2644 while ((p) && (scb = ips_getscb(ha))) {
2645 if ((scmd_channel(p) > 0)
2646 && (ha->
2647 dcdb_active[scmd_channel(p) -
2648 1] & (1 << scmd_id(p)))) {
2649 ips_freescb(ha, scb);
2650 p = (struct scsi_cmnd *) p->host_scribble;
2651 continue;
2652 }
2653
2654 q = p;
2655 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2656
2657 if (intr == IPS_INTR_ON)
2658 spin_unlock(host->host_lock);
2659
2660 SC->result = DID_OK;
2661 SC->host_scribble = NULL;
2662
2663 scb->target_id = SC->device->id;
2664 scb->lun = SC->device->lun;
2665 scb->bus = SC->device->channel;
2666 scb->scsi_cmd = SC;
2667 scb->breakup = 0;
2668 scb->data_len = 0;
2669 scb->callback = ipsintr_done;
2670 scb->timeout = ips_cmd_timeout;
2671 memset(&scb->cmd, 0, 16);
2672
2673
2674 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2675
2676 scb->sg_count = scsi_dma_map(SC);
2677 BUG_ON(scb->sg_count < 0);
2678 if (scb->sg_count) {
2679 struct scatterlist *sg;
2680 int i;
2681
2682 scb->flags |= IPS_SCB_MAP_SG;
2683
2684 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2685 if (ips_fill_scb_sg_single
2686 (ha, sg_dma_address(sg), scb, i,
2687 sg_dma_len(sg)) < 0)
2688 break;
2689 }
2690 scb->dcdb.transfer_length = scb->data_len;
2691 } else {
2692 scb->data_busaddr = 0L;
2693 scb->sg_len = 0;
2694 scb->data_len = 0;
2695 scb->dcdb.transfer_length = 0;
2696 }
2697
2698 scb->dcdb.cmd_attribute =
2699 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2700
2701
2702
2703 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2704 (scb->data_len == 0))
2705 scb->dcdb.cmd_attribute = 0;
2706
2707 if (!(scb->dcdb.cmd_attribute & 0x3))
2708 scb->dcdb.transfer_length = 0;
2709
2710 if (scb->data_len >= IPS_MAX_XFER) {
2711 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2712 scb->dcdb.transfer_length = 0;
2713 }
2714 if (intr == IPS_INTR_ON)
2715 spin_lock(host->host_lock);
2716
2717 ret = ips_send_cmd(ha, scb);
2718
2719 switch (ret) {
2720 case IPS_SUCCESS:
2721 ips_putq_scb_head(&ha->scb_activelist, scb);
2722 break;
2723 case IPS_FAILURE:
2724 if (scb->scsi_cmd) {
2725 scb->scsi_cmd->result = DID_ERROR << 16;
2726 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2727 }
2728
2729 if (scb->bus)
2730 ha->dcdb_active[scb->bus - 1] &=
2731 ~(1 << scb->target_id);
2732
2733 ips_freescb(ha, scb);
2734 break;
2735 case IPS_SUCCESS_IMM:
2736 if (scb->scsi_cmd)
2737 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2738
2739 if (scb->bus)
2740 ha->dcdb_active[scb->bus - 1] &=
2741 ~(1 << scb->target_id);
2742
2743 ips_freescb(ha, scb);
2744 break;
2745 default:
2746 break;
2747 }
2748
2749 p = (struct scsi_cmnd *) p->host_scribble;
2750
2751 }
2752
2753 if (intr == IPS_INTR_ON)
2754 spin_unlock(host->host_lock);
2755}
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768static void
2769ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2770{
2771 METHOD_TRACE("ips_putq_scb_head", 1);
2772
2773 if (!item)
2774 return;
2775
2776 item->q_next = queue->head;
2777 queue->head = item;
2778
2779 if (!queue->tail)
2780 queue->tail = item;
2781
2782 queue->count++;
2783}
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796static ips_scb_t *
2797ips_removeq_scb_head(ips_scb_queue_t * queue)
2798{
2799 ips_scb_t *item;
2800
2801 METHOD_TRACE("ips_removeq_scb_head", 1);
2802
2803 item = queue->head;
2804
2805 if (!item) {
2806 return (NULL);
2807 }
2808
2809 queue->head = item->q_next;
2810 item->q_next = NULL;
2811
2812 if (queue->tail == item)
2813 queue->tail = NULL;
2814
2815 queue->count--;
2816
2817 return (item);
2818}
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831static ips_scb_t *
2832ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2833{
2834 ips_scb_t *p;
2835
2836 METHOD_TRACE("ips_removeq_scb", 1);
2837
2838 if (!item)
2839 return (NULL);
2840
2841 if (item == queue->head) {
2842 return (ips_removeq_scb_head(queue));
2843 }
2844
2845 p = queue->head;
2846
2847 while ((p) && (item != p->q_next))
2848 p = p->q_next;
2849
2850 if (p) {
2851
2852 p->q_next = item->q_next;
2853
2854 if (!item->q_next)
2855 queue->tail = p;
2856
2857 item->q_next = NULL;
2858 queue->count--;
2859
2860 return (item);
2861 }
2862
2863 return (NULL);
2864}
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877static void ips_putq_wait_tail(ips_wait_queue_t *queue, struct scsi_cmnd *item)
2878{
2879 METHOD_TRACE("ips_putq_wait_tail", 1);
2880
2881 if (!item)
2882 return;
2883
2884 item->host_scribble = NULL;
2885
2886 if (queue->tail)
2887 queue->tail->host_scribble = (char *) item;
2888
2889 queue->tail = item;
2890
2891 if (!queue->head)
2892 queue->head = item;
2893
2894 queue->count++;
2895}
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906
2907
2908static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_t *queue)
2909{
2910 struct scsi_cmnd *item;
2911
2912 METHOD_TRACE("ips_removeq_wait_head", 1);
2913
2914 item = queue->head;
2915
2916 if (!item) {
2917 return (NULL);
2918 }
2919
2920 queue->head = (struct scsi_cmnd *) item->host_scribble;
2921 item->host_scribble = NULL;
2922
2923 if (queue->tail == item)
2924 queue->tail = NULL;
2925
2926 queue->count--;
2927
2928 return (item);
2929}
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_t *queue,
2943 struct scsi_cmnd *item)
2944{
2945 struct scsi_cmnd *p;
2946
2947 METHOD_TRACE("ips_removeq_wait", 1);
2948
2949 if (!item)
2950 return (NULL);
2951
2952 if (item == queue->head) {
2953 return (ips_removeq_wait_head(queue));
2954 }
2955
2956 p = queue->head;
2957
2958 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
2959 p = (struct scsi_cmnd *) p->host_scribble;
2960
2961 if (p) {
2962
2963 p->host_scribble = item->host_scribble;
2964
2965 if (!item->host_scribble)
2966 queue->tail = p;
2967
2968 item->host_scribble = NULL;
2969 queue->count--;
2970
2971 return (item);
2972 }
2973
2974 return (NULL);
2975}
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986
2987
2988static void
2989ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
2990{
2991 METHOD_TRACE("ips_putq_copp_tail", 1);
2992
2993 if (!item)
2994 return;
2995
2996 item->next = NULL;
2997
2998 if (queue->tail)
2999 queue->tail->next = item;
3000
3001 queue->tail = item;
3002
3003 if (!queue->head)
3004 queue->head = item;
3005
3006 queue->count++;
3007}
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020static ips_copp_wait_item_t *
3021ips_removeq_copp_head(ips_copp_queue_t * queue)
3022{
3023 ips_copp_wait_item_t *item;
3024
3025 METHOD_TRACE("ips_removeq_copp_head", 1);
3026
3027 item = queue->head;
3028
3029 if (!item) {
3030 return (NULL);
3031 }
3032
3033 queue->head = item->next;
3034 item->next = NULL;
3035
3036 if (queue->tail == item)
3037 queue->tail = NULL;
3038
3039 queue->count--;
3040
3041 return (item);
3042}
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052
3053
3054
3055static ips_copp_wait_item_t *
3056ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3057{
3058 ips_copp_wait_item_t *p;
3059
3060 METHOD_TRACE("ips_removeq_copp", 1);
3061
3062 if (!item)
3063 return (NULL);
3064
3065 if (item == queue->head) {
3066 return (ips_removeq_copp_head(queue));
3067 }
3068
3069 p = queue->head;
3070
3071 while ((p) && (item != p->next))
3072 p = p->next;
3073
3074 if (p) {
3075
3076 p->next = item->next;
3077
3078 if (!item->next)
3079 queue->tail = p;
3080
3081 item->next = NULL;
3082 queue->count--;
3083
3084 return (item);
3085 }
3086
3087 return (NULL);
3088}
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
3099static void
3100ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3101{
3102 METHOD_TRACE("ipsintr_blocking", 2);
3103
3104 ips_freescb(ha, scb);
3105 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3106 ha->waitflag = FALSE;
3107
3108 return;
3109 }
3110}
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121static void
3122ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3123{
3124 METHOD_TRACE("ipsintr_done", 2);
3125
3126 if (!scb) {
3127 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3128 "Spurious interrupt; scb NULL.\n");
3129
3130 return;
3131 }
3132
3133 if (scb->scsi_cmd == NULL) {
3134
3135 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3136 "Spurious interrupt; scsi_cmd not set.\n");
3137
3138 return;
3139 }
3140
3141 ips_done(ha, scb);
3142}
3143
3144
3145
3146
3147
3148
3149
3150
3151
3152
3153static void
3154ips_done(ips_ha_t * ha, ips_scb_t * scb)
3155{
3156 int ret;
3157
3158 METHOD_TRACE("ips_done", 1);
3159
3160 if (!scb)
3161 return;
3162
3163 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3164 ips_cleanup_passthru(ha, scb);
3165 ha->num_ioctl--;
3166 } else {
3167
3168
3169
3170
3171
3172 if ((scb->breakup) || (scb->sg_break)) {
3173 struct scatterlist *sg;
3174 int i, sg_dma_index, ips_sg_index = 0;
3175
3176
3177 scb->data_len = 0;
3178
3179 sg = scsi_sglist(scb->scsi_cmd);
3180
3181
3182 sg_dma_index = scb->breakup;
3183 for (i = 0; i < scb->breakup; i++)
3184 sg = sg_next(sg);
3185
3186
3187 ips_fill_scb_sg_single(ha,
3188 sg_dma_address(sg),
3189 scb, ips_sg_index++,
3190 sg_dma_len(sg));
3191
3192 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3193 sg_dma_index++, sg = sg_next(sg)) {
3194 if (ips_fill_scb_sg_single
3195 (ha,
3196 sg_dma_address(sg),
3197 scb, ips_sg_index++,
3198 sg_dma_len(sg)) < 0)
3199 break;
3200 }
3201
3202 scb->dcdb.transfer_length = scb->data_len;
3203 scb->dcdb.cmd_attribute |=
3204 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3205
3206 if (!(scb->dcdb.cmd_attribute & 0x3))
3207 scb->dcdb.transfer_length = 0;
3208
3209 if (scb->data_len >= IPS_MAX_XFER) {
3210 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3211 scb->dcdb.transfer_length = 0;
3212 }
3213
3214 ret = ips_send_cmd(ha, scb);
3215
3216 switch (ret) {
3217 case IPS_FAILURE:
3218 if (scb->scsi_cmd) {
3219 scb->scsi_cmd->result = DID_ERROR << 16;
3220 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3221 }
3222
3223 ips_freescb(ha, scb);
3224 break;
3225 case IPS_SUCCESS_IMM:
3226 if (scb->scsi_cmd) {
3227 scb->scsi_cmd->result = DID_ERROR << 16;
3228 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3229 }
3230
3231 ips_freescb(ha, scb);
3232 break;
3233 default:
3234 break;
3235 }
3236
3237 return;
3238 }
3239 }
3240
3241 if (scb->bus) {
3242 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3243 }
3244
3245 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3246
3247 ips_freescb(ha, scb);
3248}
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259static int
3260ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3261{
3262 int errcode;
3263 int device_error;
3264 uint32_t transfer_len;
3265 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3266 IPS_SCSI_INQ_DATA inquiryData;
3267
3268 METHOD_TRACE("ips_map_status", 1);
3269
3270 if (scb->bus) {
3271 DEBUG_VAR(2,
3272 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3273 ips_name, ha->host_num,
3274 scb->scsi_cmd->device->channel,
3275 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3276 scb->basic_status, scb->extended_status,
3277 scb->extended_status ==
3278 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3279 scb->extended_status ==
3280 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3281 scb->extended_status ==
3282 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3283 }
3284
3285
3286 errcode = DID_ERROR;
3287 device_error = 0;
3288
3289 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3290 case IPS_CMD_TIMEOUT:
3291 errcode = DID_TIME_OUT;
3292 break;
3293
3294 case IPS_INVAL_OPCO:
3295 case IPS_INVAL_CMD_BLK:
3296 case IPS_INVAL_PARM_BLK:
3297 case IPS_LD_ERROR:
3298 case IPS_CMD_CMPLT_WERROR:
3299 break;
3300
3301 case IPS_PHYS_DRV_ERROR:
3302 switch (scb->extended_status) {
3303 case IPS_ERR_SEL_TO:
3304 if (scb->bus)
3305 errcode = DID_NO_CONNECT;
3306
3307 break;
3308
3309 case IPS_ERR_OU_RUN:
3310 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3311 (scb->cmd.dcdb.op_code ==
3312 IPS_CMD_EXTENDED_DCDB_SG)) {
3313 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3314 transfer_len = tapeDCDB->transfer_length;
3315 } else {
3316 transfer_len =
3317 (uint32_t) scb->dcdb.transfer_length;
3318 }
3319
3320 if ((scb->bus) && (transfer_len < scb->data_len)) {
3321
3322 errcode = DID_OK;
3323
3324
3325 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3326 ips_scmd_buf_read(scb->scsi_cmd,
3327 &inquiryData, sizeof (inquiryData));
3328 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3329 errcode = DID_TIME_OUT;
3330 break;
3331 }
3332 }
3333 } else
3334 errcode = DID_ERROR;
3335
3336 break;
3337
3338 case IPS_ERR_RECOVERY:
3339
3340 if (scb->bus)
3341 errcode = DID_OK;
3342
3343 break;
3344
3345 case IPS_ERR_HOST_RESET:
3346 case IPS_ERR_DEV_RESET:
3347 errcode = DID_RESET;
3348 break;
3349
3350 case IPS_ERR_CKCOND:
3351 if (scb->bus) {
3352 if ((scb->cmd.dcdb.op_code ==
3353 IPS_CMD_EXTENDED_DCDB)
3354 || (scb->cmd.dcdb.op_code ==
3355 IPS_CMD_EXTENDED_DCDB_SG)) {
3356 tapeDCDB =
3357 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3358 memcpy(scb->scsi_cmd->sense_buffer,
3359 tapeDCDB->sense_info,
3360 SCSI_SENSE_BUFFERSIZE);
3361 } else {
3362 memcpy(scb->scsi_cmd->sense_buffer,
3363 scb->dcdb.sense_info,
3364 SCSI_SENSE_BUFFERSIZE);
3365 }
3366 device_error = 2;
3367 }
3368
3369 errcode = DID_OK;
3370
3371 break;
3372
3373 default:
3374 errcode = DID_ERROR;
3375 break;
3376
3377 }
3378 }
3379
3380 scb->scsi_cmd->result = device_error | (errcode << 16);
3381
3382 return (1);
3383}
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393
3394
3395
3396static int
3397ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3398{
3399 int ret;
3400
3401 METHOD_TRACE("ips_send_wait", 1);
3402
3403 if (intr != IPS_FFDC) {
3404 ha->waitflag = TRUE;
3405 ha->cmd_in_progress = scb->cdb[0];
3406 }
3407 scb->callback = ipsintr_blocking;
3408 ret = ips_send_cmd(ha, scb);
3409
3410 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3411 return (ret);
3412
3413 if (intr != IPS_FFDC)
3414 ret = ips_wait(ha, timeout, intr);
3415
3416 return (ret);
3417}
3418
3419
3420
3421
3422
3423
3424
3425
3426static void
3427ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3428{
3429 unsigned long flags;
3430
3431 local_irq_save(flags);
3432 scsi_sg_copy_from_buffer(scmd, data, count);
3433 local_irq_restore(flags);
3434}
3435
3436
3437
3438
3439
3440
3441
3442
3443static void
3444ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3445{
3446 unsigned long flags;
3447
3448 local_irq_save(flags);
3449 scsi_sg_copy_to_buffer(scmd, data, count);
3450 local_irq_restore(flags);
3451}
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462static int
3463ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3464{
3465 int ret;
3466 char *sp;
3467 int device_error;
3468 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3469 int TimeOut;
3470
3471 METHOD_TRACE("ips_send_cmd", 1);
3472
3473 ret = IPS_SUCCESS;
3474
3475 if (!scb->scsi_cmd) {
3476
3477
3478 if (scb->bus > 0) {
3479
3480
3481 if ((ha->waitflag == TRUE) &&
3482 (ha->cmd_in_progress == scb->cdb[0])) {
3483 ha->waitflag = FALSE;
3484 }
3485
3486 return (1);
3487 }
3488 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3489
3490 ret = IPS_SUCCESS_IMM;
3491
3492 switch (scb->scsi_cmd->cmnd[0]) {
3493 case ALLOW_MEDIUM_REMOVAL:
3494 case REZERO_UNIT:
3495 case ERASE:
3496 case WRITE_FILEMARKS:
3497 case SPACE:
3498 scb->scsi_cmd->result = DID_ERROR << 16;
3499 break;
3500
3501 case START_STOP:
3502 scb->scsi_cmd->result = DID_OK << 16;
3503
3504 case TEST_UNIT_READY:
3505 case INQUIRY:
3506 if (scb->target_id == IPS_ADAPTER_ID) {
3507
3508
3509
3510
3511 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3512 scb->scsi_cmd->result = DID_OK << 16;
3513
3514 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3515 IPS_SCSI_INQ_DATA inquiry;
3516
3517 memset(&inquiry, 0,
3518 sizeof (IPS_SCSI_INQ_DATA));
3519
3520 inquiry.DeviceType =
3521 IPS_SCSI_INQ_TYPE_PROCESSOR;
3522 inquiry.DeviceTypeQualifier =
3523 IPS_SCSI_INQ_LU_CONNECTED;
3524 inquiry.Version = IPS_SCSI_INQ_REV2;
3525 inquiry.ResponseDataFormat =
3526 IPS_SCSI_INQ_RD_REV2;
3527 inquiry.AdditionalLength = 31;
3528 inquiry.Flags[0] =
3529 IPS_SCSI_INQ_Address16;
3530 inquiry.Flags[1] =
3531 IPS_SCSI_INQ_WBus16 |
3532 IPS_SCSI_INQ_Sync;
3533 strncpy(inquiry.VendorId, "IBM ",
3534 8);
3535 strncpy(inquiry.ProductId,
3536 "SERVERAID ", 16);
3537 strncpy(inquiry.ProductRevisionLevel,
3538 "1.00", 4);
3539
3540 ips_scmd_buf_write(scb->scsi_cmd,
3541 &inquiry,
3542 sizeof (inquiry));
3543
3544 scb->scsi_cmd->result = DID_OK << 16;
3545 }
3546 } else {
3547 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3548 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3549 scb->cmd.logical_info.reserved = 0;
3550 scb->cmd.logical_info.reserved2 = 0;
3551 scb->data_len = sizeof (IPS_LD_INFO);
3552 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3553 scb->flags = 0;
3554 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3555 ret = IPS_SUCCESS;
3556 }
3557
3558 break;
3559
3560 case REQUEST_SENSE:
3561 ips_reqsen(ha, scb);
3562 scb->scsi_cmd->result = DID_OK << 16;
3563 break;
3564
3565 case READ_6:
3566 case WRITE_6:
3567 if (!scb->sg_len) {
3568 scb->cmd.basic_io.op_code =
3569 (scb->scsi_cmd->cmnd[0] ==
3570 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3571 scb->cmd.basic_io.enhanced_sg = 0;
3572 scb->cmd.basic_io.sg_addr =
3573 cpu_to_le32(scb->data_busaddr);
3574 } else {
3575 scb->cmd.basic_io.op_code =
3576 (scb->scsi_cmd->cmnd[0] ==
3577 READ_6) ? IPS_CMD_READ_SG :
3578 IPS_CMD_WRITE_SG;
3579 scb->cmd.basic_io.enhanced_sg =
3580 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3581 scb->cmd.basic_io.sg_addr =
3582 cpu_to_le32(scb->sg_busaddr);
3583 }
3584
3585 scb->cmd.basic_io.segment_4G = 0;
3586 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3587 scb->cmd.basic_io.log_drv = scb->target_id;
3588 scb->cmd.basic_io.sg_count = scb->sg_len;
3589
3590 if (scb->cmd.basic_io.lba)
3591 le32_add_cpu(&scb->cmd.basic_io.lba,
3592 le16_to_cpu(scb->cmd.basic_io.
3593 sector_count));
3594 else
3595 scb->cmd.basic_io.lba =
3596 (((scb->scsi_cmd->
3597 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3598 cmnd[2] << 8) |
3599 (scb->scsi_cmd->cmnd[3]));
3600
3601 scb->cmd.basic_io.sector_count =
3602 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3603
3604 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3605 scb->cmd.basic_io.sector_count =
3606 cpu_to_le16(256);
3607
3608 ret = IPS_SUCCESS;
3609 break;
3610
3611 case READ_10:
3612 case WRITE_10:
3613 if (!scb->sg_len) {
3614 scb->cmd.basic_io.op_code =
3615 (scb->scsi_cmd->cmnd[0] ==
3616 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3617 scb->cmd.basic_io.enhanced_sg = 0;
3618 scb->cmd.basic_io.sg_addr =
3619 cpu_to_le32(scb->data_busaddr);
3620 } else {
3621 scb->cmd.basic_io.op_code =
3622 (scb->scsi_cmd->cmnd[0] ==
3623 READ_10) ? IPS_CMD_READ_SG :
3624 IPS_CMD_WRITE_SG;
3625 scb->cmd.basic_io.enhanced_sg =
3626 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3627 scb->cmd.basic_io.sg_addr =
3628 cpu_to_le32(scb->sg_busaddr);
3629 }
3630
3631 scb->cmd.basic_io.segment_4G = 0;
3632 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3633 scb->cmd.basic_io.log_drv = scb->target_id;
3634 scb->cmd.basic_io.sg_count = scb->sg_len;
3635
3636 if (scb->cmd.basic_io.lba)
3637 le32_add_cpu(&scb->cmd.basic_io.lba,
3638 le16_to_cpu(scb->cmd.basic_io.
3639 sector_count));
3640 else
3641 scb->cmd.basic_io.lba =
3642 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3643 scsi_cmd->
3644 cmnd[3]
3645 << 16) |
3646 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3647 scsi_cmd->cmnd[5]);
3648
3649 scb->cmd.basic_io.sector_count =
3650 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3651
3652 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3653
3654
3655
3656
3657
3658 scb->scsi_cmd->result = DID_OK << 16;
3659 } else
3660 ret = IPS_SUCCESS;
3661
3662 break;
3663
3664 case RESERVE:
3665 case RELEASE:
3666 scb->scsi_cmd->result = DID_OK << 16;
3667 break;
3668
3669 case MODE_SENSE:
3670 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3671 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3672 scb->cmd.basic_io.segment_4G = 0;
3673 scb->cmd.basic_io.enhanced_sg = 0;
3674 scb->data_len = sizeof (*ha->enq);
3675 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3676 ret = IPS_SUCCESS;
3677 break;
3678
3679 case READ_CAPACITY:
3680 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3681 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3682 scb->cmd.logical_info.reserved = 0;
3683 scb->cmd.logical_info.reserved2 = 0;
3684 scb->cmd.logical_info.reserved3 = 0;
3685 scb->data_len = sizeof (IPS_LD_INFO);
3686 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3687 scb->flags = 0;
3688 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3689 ret = IPS_SUCCESS;
3690 break;
3691
3692 case SEND_DIAGNOSTIC:
3693 case REASSIGN_BLOCKS:
3694 case FORMAT_UNIT:
3695 case SEEK_10:
3696 case VERIFY:
3697 case READ_DEFECT_DATA:
3698 case READ_BUFFER:
3699 case WRITE_BUFFER:
3700 scb->scsi_cmd->result = DID_OK << 16;
3701 break;
3702
3703 default:
3704
3705
3706
3707 sp = (char *) scb->scsi_cmd->sense_buffer;
3708
3709 sp[0] = 0x70;
3710 sp[2] = ILLEGAL_REQUEST;
3711 sp[7] = 0x0A;
3712 sp[12] = 0x20;
3713 sp[13] = 0x00;
3714
3715 device_error = 2;
3716 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3717 break;
3718 }
3719 }
3720
3721 if (ret == IPS_SUCCESS_IMM)
3722 return (ret);
3723
3724
3725 if (scb->bus > 0) {
3726
3727
3728
3729 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3730 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3731 return (IPS_SUCCESS_IMM);
3732 }
3733
3734 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3735 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3736 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3737 (unsigned long) &scb->
3738 dcdb -
3739 (unsigned long) scb);
3740 scb->cmd.dcdb.reserved = 0;
3741 scb->cmd.dcdb.reserved2 = 0;
3742 scb->cmd.dcdb.reserved3 = 0;
3743 scb->cmd.dcdb.segment_4G = 0;
3744 scb->cmd.dcdb.enhanced_sg = 0;
3745
3746 TimeOut = scb->scsi_cmd->request->timeout;
3747
3748 if (ha->subsys->param[4] & 0x00100000) {
3749 if (!scb->sg_len) {
3750 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3751 } else {
3752 scb->cmd.dcdb.op_code =
3753 IPS_CMD_EXTENDED_DCDB_SG;
3754 scb->cmd.dcdb.enhanced_sg =
3755 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3756 }
3757
3758 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3759 tapeDCDB->device_address =
3760 ((scb->bus - 1) << 4) | scb->target_id;
3761 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3762 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K;
3763
3764 if (TimeOut) {
3765 if (TimeOut < (10 * HZ))
3766 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10;
3767 else if (TimeOut < (60 * HZ))
3768 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60;
3769 else if (TimeOut < (1200 * HZ))
3770 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M;
3771 }
3772
3773 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3774 tapeDCDB->reserved_for_LUN = 0;
3775 tapeDCDB->transfer_length = scb->data_len;
3776 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3777 tapeDCDB->buffer_pointer =
3778 cpu_to_le32(scb->sg_busaddr);
3779 else
3780 tapeDCDB->buffer_pointer =
3781 cpu_to_le32(scb->data_busaddr);
3782 tapeDCDB->sg_count = scb->sg_len;
3783 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3784 tapeDCDB->scsi_status = 0;
3785 tapeDCDB->reserved = 0;
3786 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3787 scb->scsi_cmd->cmd_len);
3788 } else {
3789 if (!scb->sg_len) {
3790 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3791 } else {
3792 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3793 scb->cmd.dcdb.enhanced_sg =
3794 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3795 }
3796
3797 scb->dcdb.device_address =
3798 ((scb->bus - 1) << 4) | scb->target_id;
3799 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3800
3801 if (TimeOut) {
3802 if (TimeOut < (10 * HZ))
3803 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
3804 else if (TimeOut < (60 * HZ))
3805 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
3806 else if (TimeOut < (1200 * HZ))
3807 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
3808 }
3809
3810 scb->dcdb.transfer_length = scb->data_len;
3811 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3812 scb->dcdb.transfer_length = 0;
3813 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3814 scb->dcdb.buffer_pointer =
3815 cpu_to_le32(scb->sg_busaddr);
3816 else
3817 scb->dcdb.buffer_pointer =
3818 cpu_to_le32(scb->data_busaddr);
3819 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3820 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3821 scb->dcdb.sg_count = scb->sg_len;
3822 scb->dcdb.reserved = 0;
3823 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3824 scb->scsi_cmd->cmd_len);
3825 scb->dcdb.scsi_status = 0;
3826 scb->dcdb.reserved2[0] = 0;
3827 scb->dcdb.reserved2[1] = 0;
3828 scb->dcdb.reserved2[2] = 0;
3829 }
3830 }
3831
3832 return ((*ha->func.issue) (ha, scb));
3833}
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3844static void
3845ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3846{
3847 ips_scb_t *scb;
3848 ips_stat_t *sp;
3849 uint8_t basic_status;
3850 uint8_t ext_status;
3851 int errcode;
3852 IPS_SCSI_INQ_DATA inquiryData;
3853
3854 METHOD_TRACE("ips_chkstatus", 1);
3855
3856 scb = &ha->scbs[pstatus->fields.command_id];
3857 scb->basic_status = basic_status =
3858 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3859 scb->extended_status = ext_status = pstatus->fields.extended_status;
3860
3861 sp = &ha->sp;
3862 sp->residue_len = 0;
3863 sp->scb_addr = (void *) scb;
3864
3865
3866 ips_removeq_scb(&ha->scb_activelist, scb);
3867
3868 if (!scb->scsi_cmd)
3869
3870 return;
3871
3872 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3873 ips_name,
3874 ha->host_num,
3875 scb->cdb[0],
3876 scb->cmd.basic_io.command_id,
3877 scb->bus, scb->target_id, scb->lun);
3878
3879 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3880
3881 return;
3882
3883 errcode = DID_OK;
3884
3885 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3886 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3887
3888 if (scb->bus == 0) {
3889 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3890 IPS_CMD_RECOVERED_ERROR) {
3891 DEBUG_VAR(1,
3892 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3893 ips_name, ha->host_num,
3894 scb->cmd.basic_io.op_code,
3895 basic_status, ext_status);
3896 }
3897
3898 switch (scb->scsi_cmd->cmnd[0]) {
3899 case ALLOW_MEDIUM_REMOVAL:
3900 case REZERO_UNIT:
3901 case ERASE:
3902 case WRITE_FILEMARKS:
3903 case SPACE:
3904 errcode = DID_ERROR;
3905 break;
3906
3907 case START_STOP:
3908 break;
3909
3910 case TEST_UNIT_READY:
3911 if (!ips_online(ha, scb)) {
3912 errcode = DID_TIME_OUT;
3913 }
3914 break;
3915
3916 case INQUIRY:
3917 if (ips_online(ha, scb)) {
3918 ips_inquiry(ha, scb);
3919 } else {
3920 errcode = DID_TIME_OUT;
3921 }
3922 break;
3923
3924 case REQUEST_SENSE:
3925 ips_reqsen(ha, scb);
3926 break;
3927
3928 case READ_6:
3929 case WRITE_6:
3930 case READ_10:
3931 case WRITE_10:
3932 case RESERVE:
3933 case RELEASE:
3934 break;
3935
3936 case MODE_SENSE:
3937 if (!ips_online(ha, scb)
3938 || !ips_msense(ha, scb)) {
3939 errcode = DID_ERROR;
3940 }
3941 break;
3942
3943 case READ_CAPACITY:
3944 if (ips_online(ha, scb))
3945 ips_rdcap(ha, scb);
3946 else {
3947 errcode = DID_TIME_OUT;
3948 }
3949 break;
3950
3951 case SEND_DIAGNOSTIC:
3952 case REASSIGN_BLOCKS:
3953 break;
3954
3955 case FORMAT_UNIT:
3956 errcode = DID_ERROR;
3957 break;
3958
3959 case SEEK_10:
3960 case VERIFY:
3961 case READ_DEFECT_DATA:
3962 case READ_BUFFER:
3963 case WRITE_BUFFER:
3964 break;
3965
3966 default:
3967 errcode = DID_ERROR;
3968 }
3969
3970 scb->scsi_cmd->result = errcode << 16;
3971 } else {
3972
3973 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3974 ips_scmd_buf_read(scb->scsi_cmd,
3975 &inquiryData, sizeof (inquiryData));
3976 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
3977 scb->scsi_cmd->result = DID_TIME_OUT << 16;
3978 }
3979 }
3980 } else {
3981 if (scb->bus == 0) {
3982 DEBUG_VAR(1,
3983 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3984 ips_name, ha->host_num,
3985 scb->cmd.basic_io.op_code, basic_status,
3986 ext_status);
3987 }
3988
3989 ips_map_status(ha, scb, sp);
3990 }
3991}
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001
4002static int
4003ips_online(ips_ha_t * ha, ips_scb_t * scb)
4004{
4005 METHOD_TRACE("ips_online", 1);
4006
4007 if (scb->target_id >= IPS_MAX_LD)
4008 return (0);
4009
4010 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4011 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4012 return (0);
4013 }
4014
4015 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4016 IPS_LD_OFFLINE
4017 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4018 IPS_LD_FREE
4019 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4020 IPS_LD_CRS
4021 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4022 IPS_LD_SYS)
4023 return (1);
4024 else
4025 return (0);
4026}
4027
4028
4029
4030
4031
4032
4033
4034
4035
4036
4037static int
4038ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4039{
4040 IPS_SCSI_INQ_DATA inquiry;
4041
4042 METHOD_TRACE("ips_inquiry", 1);
4043
4044 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4045
4046 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4047 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4048 inquiry.Version = IPS_SCSI_INQ_REV2;
4049 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4050 inquiry.AdditionalLength = 31;
4051 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4052 inquiry.Flags[1] =
4053 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4054 strncpy(inquiry.VendorId, "IBM ", 8);
4055 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4056 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4057
4058 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4059
4060 return (1);
4061}
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072static int
4073ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4074{
4075 IPS_SCSI_CAPACITY cap;
4076
4077 METHOD_TRACE("ips_rdcap", 1);
4078
4079 if (scsi_bufflen(scb->scsi_cmd) < 8)
4080 return (0);
4081
4082 cap.lba =
4083 cpu_to_be32(le32_to_cpu
4084 (ha->logical_drive_info->
4085 drive_info[scb->target_id].sector_count) - 1);
4086 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4087
4088 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4089
4090 return (1);
4091}
4092
4093
4094
4095
4096
4097
4098
4099
4100
4101
4102static int
4103ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4104{
4105 uint16_t heads;
4106 uint16_t sectors;
4107 uint32_t cylinders;
4108 IPS_SCSI_MODE_PAGE_DATA mdata;
4109
4110 METHOD_TRACE("ips_msense", 1);
4111
4112 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4113 (ha->enq->ucMiscFlag & 0x8) == 0) {
4114 heads = IPS_NORM_HEADS;
4115 sectors = IPS_NORM_SECTORS;
4116 } else {
4117 heads = IPS_COMP_HEADS;
4118 sectors = IPS_COMP_SECTORS;
4119 }
4120
4121 cylinders =
4122 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4123 1) / (heads * sectors);
4124
4125 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4126
4127 mdata.hdr.BlockDescLength = 8;
4128
4129 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4130 case 0x03:
4131 mdata.pdata.pg3.PageCode = 3;
4132 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4133 mdata.hdr.DataLength =
4134 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4135 mdata.pdata.pg3.TracksPerZone = 0;
4136 mdata.pdata.pg3.AltSectorsPerZone = 0;
4137 mdata.pdata.pg3.AltTracksPerZone = 0;
4138 mdata.pdata.pg3.AltTracksPerVolume = 0;
4139 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4140 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4141 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4142 mdata.pdata.pg3.TrackSkew = 0;
4143 mdata.pdata.pg3.CylinderSkew = 0;
4144 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4145 break;
4146
4147 case 0x4:
4148 mdata.pdata.pg4.PageCode = 4;
4149 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4150 mdata.hdr.DataLength =
4151 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4152 mdata.pdata.pg4.CylindersHigh =
4153 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4154 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4155 mdata.pdata.pg4.Heads = heads;
4156 mdata.pdata.pg4.WritePrecompHigh = 0;
4157 mdata.pdata.pg4.WritePrecompLow = 0;
4158 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4159 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4160 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4161 mdata.pdata.pg4.LandingZoneHigh = 0;
4162 mdata.pdata.pg4.LandingZoneLow = 0;
4163 mdata.pdata.pg4.flags = 0;
4164 mdata.pdata.pg4.RotationalOffset = 0;
4165 mdata.pdata.pg4.MediumRotationRate = 0;
4166 break;
4167 case 0x8:
4168 mdata.pdata.pg8.PageCode = 8;
4169 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4170 mdata.hdr.DataLength =
4171 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4172
4173 break;
4174
4175 default:
4176 return (0);
4177 }
4178
4179 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4180
4181 return (1);
4182}
4183
4184
4185
4186
4187
4188
4189
4190
4191
4192
4193static int
4194ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4195{
4196 IPS_SCSI_REQSEN reqsen;
4197
4198 METHOD_TRACE("ips_reqsen", 1);
4199
4200 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4201
4202 reqsen.ResponseCode =
4203 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4204 reqsen.AdditionalLength = 10;
4205 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4206 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4207
4208 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4209
4210 return (1);
4211}
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222static void
4223ips_free(ips_ha_t * ha)
4224{
4225
4226 METHOD_TRACE("ips_free", 1);
4227
4228 if (ha) {
4229 if (ha->enq) {
4230 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4231 ha->enq, ha->enq_busaddr);
4232 ha->enq = NULL;
4233 }
4234
4235 kfree(ha->conf);
4236 ha->conf = NULL;
4237
4238 if (ha->adapt) {
4239 pci_free_consistent(ha->pcidev,
4240 sizeof (IPS_ADAPTER) +
4241 sizeof (IPS_IO_CMD), ha->adapt,
4242 ha->adapt->hw_status_start);
4243 ha->adapt = NULL;
4244 }
4245
4246 if (ha->logical_drive_info) {
4247 pci_free_consistent(ha->pcidev,
4248 sizeof (IPS_LD_INFO),
4249 ha->logical_drive_info,
4250 ha->logical_drive_info_dma_addr);
4251 ha->logical_drive_info = NULL;
4252 }
4253
4254 kfree(ha->nvram);
4255 ha->nvram = NULL;
4256
4257 kfree(ha->subsys);
4258 ha->subsys = NULL;
4259
4260 if (ha->ioctl_data) {
4261 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4262 ha->ioctl_data, ha->ioctl_busaddr);
4263 ha->ioctl_data = NULL;
4264 ha->ioctl_datasize = 0;
4265 ha->ioctl_len = 0;
4266 }
4267 ips_deallocatescbs(ha, ha->max_cmds);
4268
4269
4270 if (ha->mem_ptr) {
4271 iounmap(ha->ioremap_ptr);
4272 ha->ioremap_ptr = NULL;
4273 ha->mem_ptr = NULL;
4274 }
4275
4276 ha->mem_addr = 0;
4277
4278 }
4279}
4280
4281
4282
4283
4284
4285
4286
4287
4288
4289
4290static int
4291ips_deallocatescbs(ips_ha_t * ha, int cmds)
4292{
4293 if (ha->scbs) {
4294 pci_free_consistent(ha->pcidev,
4295 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4296 ha->scbs->sg_list.list,
4297 ha->scbs->sg_busaddr);
4298 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4299 ha->scbs, ha->scbs->scb_busaddr);
4300 ha->scbs = NULL;
4301 }
4302 return 1;
4303}
4304
4305
4306
4307
4308
4309
4310
4311
4312
4313
4314static int
4315ips_allocatescbs(ips_ha_t * ha)
4316{
4317 ips_scb_t *scb_p;
4318 IPS_SG_LIST ips_sg;
4319 int i;
4320 dma_addr_t command_dma, sg_dma;
4321
4322 METHOD_TRACE("ips_allocatescbs", 1);
4323
4324
4325 ha->scbs =
4326 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4327 &command_dma);
4328 if (ha->scbs == NULL)
4329 return 0;
4330 ips_sg.list =
4331 pci_alloc_consistent(ha->pcidev,
4332 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4333 ha->max_cmds, &sg_dma);
4334 if (ips_sg.list == NULL) {
4335 pci_free_consistent(ha->pcidev,
4336 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4337 command_dma);
4338 return 0;
4339 }
4340
4341 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4342
4343 for (i = 0; i < ha->max_cmds; i++) {
4344 scb_p = &ha->scbs[i];
4345 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4346
4347 if (IPS_USE_ENH_SGLIST(ha)) {
4348 scb_p->sg_list.enh_list =
4349 ips_sg.enh_list + i * IPS_MAX_SG;
4350 scb_p->sg_busaddr =
4351 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4352 } else {
4353 scb_p->sg_list.std_list =
4354 ips_sg.std_list + i * IPS_MAX_SG;
4355 scb_p->sg_busaddr =
4356 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4357 }
4358
4359
4360 if (i < ha->max_cmds - 1) {
4361 scb_p->q_next = ha->scb_freelist;
4362 ha->scb_freelist = scb_p;
4363 }
4364 }
4365
4366
4367 return (1);
4368}
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379static void
4380ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4381{
4382 IPS_SG_LIST sg_list;
4383 uint32_t cmd_busaddr, sg_busaddr;
4384 METHOD_TRACE("ips_init_scb", 1);
4385
4386 if (scb == NULL)
4387 return;
4388
4389 sg_list.list = scb->sg_list.list;
4390 cmd_busaddr = scb->scb_busaddr;
4391 sg_busaddr = scb->sg_busaddr;
4392
4393 memset(scb, 0, sizeof (ips_scb_t));
4394 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4395
4396
4397 ha->dummy->op_code = 0xFF;
4398 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4399 + sizeof (IPS_ADAPTER));
4400 ha->dummy->command_id = IPS_MAX_CMDS;
4401
4402
4403 scb->scb_busaddr = cmd_busaddr;
4404 scb->sg_busaddr = sg_busaddr;
4405 scb->sg_list.list = sg_list.list;
4406
4407
4408 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4409 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4410 + sizeof (IPS_ADAPTER));
4411}
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424static ips_scb_t *
4425ips_getscb(ips_ha_t * ha)
4426{
4427 ips_scb_t *scb;
4428
4429 METHOD_TRACE("ips_getscb", 1);
4430
4431 if ((scb = ha->scb_freelist) == NULL) {
4432
4433 return (NULL);
4434 }
4435
4436 ha->scb_freelist = scb->q_next;
4437 scb->flags = 0;
4438 scb->q_next = NULL;
4439
4440 ips_init_scb(ha, scb);
4441
4442 return (scb);
4443}
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453
4454
4455
4456static void
4457ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4458{
4459
4460 METHOD_TRACE("ips_freescb", 1);
4461 if (scb->flags & IPS_SCB_MAP_SG)
4462 scsi_dma_unmap(scb->scsi_cmd);
4463 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4464 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4465 IPS_DMA_DIR(scb));
4466
4467
4468 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4469 scb->q_next = ha->scb_freelist;
4470 ha->scb_freelist = scb;
4471 }
4472}
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483static int
4484ips_isinit_copperhead(ips_ha_t * ha)
4485{
4486 uint8_t scpr;
4487 uint8_t isr;
4488
4489 METHOD_TRACE("ips_isinit_copperhead", 1);
4490
4491 isr = inb(ha->io_addr + IPS_REG_HISR);
4492 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4493
4494 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4495 return (0);
4496 else
4497 return (1);
4498}
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509static int
4510ips_isinit_copperhead_memio(ips_ha_t * ha)
4511{
4512 uint8_t isr = 0;
4513 uint8_t scpr;
4514
4515 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4516
4517 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4518 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4519
4520 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4521 return (0);
4522 else
4523 return (1);
4524}
4525
4526
4527
4528
4529
4530
4531
4532
4533
4534
4535static int
4536ips_isinit_morpheus(ips_ha_t * ha)
4537{
4538 uint32_t post;
4539 uint32_t bits;
4540
4541 METHOD_TRACE("ips_is_init_morpheus", 1);
4542
4543 if (ips_isintr_morpheus(ha))
4544 ips_flush_and_reset(ha);
4545
4546 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4547 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4548
4549 if (post == 0)
4550 return (0);
4551 else if (bits & 0x3)
4552 return (0);
4553 else
4554 return (1);
4555}
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566
4567static void
4568ips_flush_and_reset(ips_ha_t *ha)
4569{
4570 ips_scb_t *scb;
4571 int ret;
4572 int time;
4573 int done;
4574 dma_addr_t command_dma;
4575
4576
4577 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma);
4578 if (scb) {
4579 memset(scb, 0, sizeof(ips_scb_t));
4580 ips_init_scb(ha, scb);
4581 scb->scb_busaddr = command_dma;
4582
4583 scb->timeout = ips_cmd_timeout;
4584 scb->cdb[0] = IPS_CMD_FLUSH;
4585
4586 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4587 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS;
4588 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4589 scb->cmd.flush_cache.reserved = 0;
4590 scb->cmd.flush_cache.reserved2 = 0;
4591 scb->cmd.flush_cache.reserved3 = 0;
4592 scb->cmd.flush_cache.reserved4 = 0;
4593
4594 ret = ips_send_cmd(ha, scb);
4595
4596 if (ret == IPS_SUCCESS) {
4597 time = 60 * IPS_ONE_SEC;
4598 done = 0;
4599
4600 while ((time > 0) && (!done)) {
4601 done = ips_poll_for_flush_complete(ha);
4602
4603 udelay(1000);
4604 time--;
4605 }
4606 }
4607 }
4608
4609
4610 (*ha->func.reset) (ha);
4611
4612 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma);
4613 return;
4614}
4615
4616
4617
4618
4619
4620
4621
4622
4623
4624
4625
4626static int
4627ips_poll_for_flush_complete(ips_ha_t * ha)
4628{
4629 IPS_STATUS cstatus;
4630
4631 while (TRUE) {
4632 cstatus.value = (*ha->func.statupd) (ha);
4633
4634 if (cstatus.value == 0xffffffff)
4635 break;
4636
4637
4638 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4639 return 1;
4640 }
4641
4642 return 0;
4643}
4644
4645
4646
4647
4648
4649
4650
4651
4652
4653static void
4654ips_enable_int_copperhead(ips_ha_t * ha)
4655{
4656 METHOD_TRACE("ips_enable_int_copperhead", 1);
4657
4658 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4659 inb(ha->io_addr + IPS_REG_HISR);
4660}
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670static void
4671ips_enable_int_copperhead_memio(ips_ha_t * ha)
4672{
4673 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4674
4675 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4676 readb(ha->mem_ptr + IPS_REG_HISR);
4677}
4678
4679
4680
4681
4682
4683
4684
4685
4686
4687static void
4688ips_enable_int_morpheus(ips_ha_t * ha)
4689{
4690 uint32_t Oimr;
4691
4692 METHOD_TRACE("ips_enable_int_morpheus", 1);
4693
4694 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4695 Oimr &= ~0x08;
4696 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4697 readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4698}
4699
4700
4701
4702
4703
4704
4705
4706
4707
4708
4709static int
4710ips_init_copperhead(ips_ha_t * ha)
4711{
4712 uint8_t Isr;
4713 uint8_t Cbsp;
4714 uint8_t PostByte[IPS_MAX_POST_BYTES];
4715 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4716 int i, j;
4717
4718 METHOD_TRACE("ips_init_copperhead", 1);
4719
4720 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4721 for (j = 0; j < 45; j++) {
4722 Isr = inb(ha->io_addr + IPS_REG_HISR);
4723 if (Isr & IPS_BIT_GHI)
4724 break;
4725
4726
4727 MDELAY(IPS_ONE_SEC);
4728 }
4729
4730 if (j >= 45)
4731
4732 return (0);
4733
4734 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4735 outb(Isr, ha->io_addr + IPS_REG_HISR);
4736 }
4737
4738 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4739 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4740 "reset controller fails (post status %x %x).\n",
4741 PostByte[0], PostByte[1]);
4742
4743 return (0);
4744 }
4745
4746 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4747 for (j = 0; j < 240; j++) {
4748 Isr = inb(ha->io_addr + IPS_REG_HISR);
4749 if (Isr & IPS_BIT_GHI)
4750 break;
4751
4752
4753 MDELAY(IPS_ONE_SEC);
4754 }
4755
4756 if (j >= 240)
4757
4758 return (0);
4759
4760 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4761 outb(Isr, ha->io_addr + IPS_REG_HISR);
4762 }
4763
4764 for (i = 0; i < 240; i++) {
4765 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4766
4767 if ((Cbsp & IPS_BIT_OP) == 0)
4768 break;
4769
4770
4771 MDELAY(IPS_ONE_SEC);
4772 }
4773
4774 if (i >= 240)
4775
4776 return (0);
4777
4778
4779 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4780
4781
4782 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4783
4784 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4785
4786 outl(0, ha->io_addr + IPS_REG_NDAE);
4787
4788
4789 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4790
4791 return (1);
4792}
4793
4794
4795
4796
4797
4798
4799
4800
4801
4802
4803static int
4804ips_init_copperhead_memio(ips_ha_t * ha)
4805{
4806 uint8_t Isr = 0;
4807 uint8_t Cbsp;
4808 uint8_t PostByte[IPS_MAX_POST_BYTES];
4809 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4810 int i, j;
4811
4812 METHOD_TRACE("ips_init_copperhead_memio", 1);
4813
4814 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4815 for (j = 0; j < 45; j++) {
4816 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4817 if (Isr & IPS_BIT_GHI)
4818 break;
4819
4820
4821 MDELAY(IPS_ONE_SEC);
4822 }
4823
4824 if (j >= 45)
4825
4826 return (0);
4827
4828 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4829 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4830 }
4831
4832 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4833 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4834 "reset controller fails (post status %x %x).\n",
4835 PostByte[0], PostByte[1]);
4836
4837 return (0);
4838 }
4839
4840 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4841 for (j = 0; j < 240; j++) {
4842 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4843 if (Isr & IPS_BIT_GHI)
4844 break;
4845
4846
4847 MDELAY(IPS_ONE_SEC);
4848 }
4849
4850 if (j >= 240)
4851
4852 return (0);
4853
4854 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4855 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4856 }
4857
4858 for (i = 0; i < 240; i++) {
4859 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4860
4861 if ((Cbsp & IPS_BIT_OP) == 0)
4862 break;
4863
4864
4865 MDELAY(IPS_ONE_SEC);
4866 }
4867
4868 if (i >= 240)
4869
4870 return (0);
4871
4872
4873 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4874
4875
4876 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4877
4878 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4879
4880 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4881
4882
4883 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4884
4885
4886 return (1);
4887}
4888
4889
4890
4891
4892
4893
4894
4895
4896
4897
4898static int
4899ips_init_morpheus(ips_ha_t * ha)
4900{
4901 uint32_t Post;
4902 uint32_t Config;
4903 uint32_t Isr;
4904 uint32_t Oimr;
4905 int i;
4906
4907 METHOD_TRACE("ips_init_morpheus", 1);
4908
4909
4910 for (i = 0; i < 45; i++) {
4911 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4912
4913 if (Isr & IPS_BIT_I960_MSG0I)
4914 break;
4915
4916
4917 MDELAY(IPS_ONE_SEC);
4918 }
4919
4920 if (i >= 45) {
4921
4922 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4923 "timeout waiting for post.\n");
4924
4925 return (0);
4926 }
4927
4928 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4929
4930 if (Post == 0x4F00) {
4931 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4932 "Flashing Battery PIC, Please wait ...\n");
4933
4934
4935 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4936 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4937
4938 for (i = 0; i < 120; i++) {
4939 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4940 if (Post != 0x4F00)
4941 break;
4942
4943 MDELAY(IPS_ONE_SEC);
4944 }
4945
4946 if (i >= 120) {
4947 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4948 "timeout waiting for Battery PIC Flash\n");
4949 return (0);
4950 }
4951
4952 }
4953
4954
4955 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4956 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4957
4958 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
4959 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4960 "reset controller fails (post status %x).\n", Post);
4961
4962 return (0);
4963 }
4964
4965
4966 for (i = 0; i < 240; i++) {
4967 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4968
4969 if (Isr & IPS_BIT_I960_MSG1I)
4970 break;
4971
4972
4973 MDELAY(IPS_ONE_SEC);
4974 }
4975
4976 if (i >= 240) {
4977
4978 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4979 "timeout waiting for config.\n");
4980
4981 return (0);
4982 }
4983
4984 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4985
4986
4987 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
4988 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4989
4990
4991 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4992 Oimr &= ~0x8;
4993 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4994
4995
4996
4997
4998 if (Post == 0xEF10) {
4999 if ((Config == 0x000F) || (Config == 0x0009))
5000 ha->requires_esl = 1;
5001 }
5002
5003 return (1);
5004}
5005
5006
5007
5008
5009
5010
5011
5012
5013
5014
5015static int
5016ips_reset_copperhead(ips_ha_t * ha)
5017{
5018 int reset_counter;
5019
5020 METHOD_TRACE("ips_reset_copperhead", 1);
5021
5022 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5023 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5024
5025 reset_counter = 0;
5026
5027 while (reset_counter < 2) {
5028 reset_counter++;
5029
5030 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5031
5032
5033 MDELAY(IPS_ONE_SEC);
5034
5035 outb(0, ha->io_addr + IPS_REG_SCPR);
5036
5037
5038 MDELAY(IPS_ONE_SEC);
5039
5040 if ((*ha->func.init) (ha))
5041 break;
5042 else if (reset_counter >= 2) {
5043
5044 return (0);
5045 }
5046 }
5047
5048 return (1);
5049}
5050
5051
5052
5053
5054
5055
5056
5057
5058
5059
5060static int
5061ips_reset_copperhead_memio(ips_ha_t * ha)
5062{
5063 int reset_counter;
5064
5065 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5066
5067 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5068 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5069
5070 reset_counter = 0;
5071
5072 while (reset_counter < 2) {
5073 reset_counter++;
5074
5075 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5076
5077
5078 MDELAY(IPS_ONE_SEC);
5079
5080 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5081
5082
5083 MDELAY(IPS_ONE_SEC);
5084
5085 if ((*ha->func.init) (ha))
5086 break;
5087 else if (reset_counter >= 2) {
5088
5089 return (0);
5090 }
5091 }
5092
5093 return (1);
5094}
5095
5096
5097
5098
5099
5100
5101
5102
5103
5104
5105static int
5106ips_reset_morpheus(ips_ha_t * ha)
5107{
5108 int reset_counter;
5109 uint8_t junk;
5110
5111 METHOD_TRACE("ips_reset_morpheus", 1);
5112
5113 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5114 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5115
5116 reset_counter = 0;
5117
5118 while (reset_counter < 2) {
5119 reset_counter++;
5120
5121 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5122
5123
5124 MDELAY(5 * IPS_ONE_SEC);
5125
5126
5127 pci_read_config_byte(ha->pcidev, 4, &junk);
5128
5129 if ((*ha->func.init) (ha))
5130 break;
5131 else if (reset_counter >= 2) {
5132
5133 return (0);
5134 }
5135 }
5136
5137 return (1);
5138}
5139
5140
5141
5142
5143
5144
5145
5146
5147
5148
5149static void
5150ips_statinit(ips_ha_t * ha)
5151{
5152 uint32_t phys_status_start;
5153
5154 METHOD_TRACE("ips_statinit", 1);
5155
5156 ha->adapt->p_status_start = ha->adapt->status;
5157 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5158 ha->adapt->p_status_tail = ha->adapt->status;
5159
5160 phys_status_start = ha->adapt->hw_status_start;
5161 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5162 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5163 ha->io_addr + IPS_REG_SQER);
5164 outl(phys_status_start + IPS_STATUS_SIZE,
5165 ha->io_addr + IPS_REG_SQHR);
5166 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5167
5168 ha->adapt->hw_status_tail = phys_status_start;
5169}
5170
5171
5172
5173
5174
5175
5176
5177
5178
5179
5180static void
5181ips_statinit_memio(ips_ha_t * ha)
5182{
5183 uint32_t phys_status_start;
5184
5185 METHOD_TRACE("ips_statinit_memio", 1);
5186
5187 ha->adapt->p_status_start = ha->adapt->status;
5188 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5189 ha->adapt->p_status_tail = ha->adapt->status;
5190
5191 phys_status_start = ha->adapt->hw_status_start;
5192 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5193 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5194 ha->mem_ptr + IPS_REG_SQER);
5195 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5196 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5197
5198 ha->adapt->hw_status_tail = phys_status_start;
5199}
5200
5201
5202
5203
5204
5205
5206
5207
5208
5209
5210static uint32_t
5211ips_statupd_copperhead(ips_ha_t * ha)
5212{
5213 METHOD_TRACE("ips_statupd_copperhead", 1);
5214
5215 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5216 ha->adapt->p_status_tail++;
5217 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5218 } else {
5219 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5220 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5221 }
5222
5223 outl(ha->adapt->hw_status_tail,
5224 ha->io_addr + IPS_REG_SQTR);
5225
5226 return (ha->adapt->p_status_tail->value);
5227}
5228
5229
5230
5231
5232
5233
5234
5235
5236
5237
5238static uint32_t
5239ips_statupd_copperhead_memio(ips_ha_t * ha)
5240{
5241 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5242
5243 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5244 ha->adapt->p_status_tail++;
5245 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5246 } else {
5247 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5248 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5249 }
5250
5251 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5252
5253 return (ha->adapt->p_status_tail->value);
5254}
5255
5256
5257
5258
5259
5260
5261
5262
5263
5264
5265static uint32_t
5266ips_statupd_morpheus(ips_ha_t * ha)
5267{
5268 uint32_t val;
5269
5270 METHOD_TRACE("ips_statupd_morpheus", 1);
5271
5272 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5273
5274 return (val);
5275}
5276
5277
5278
5279
5280
5281
5282
5283
5284
5285
5286static int
5287ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5288{
5289 uint32_t TimeOut;
5290 uint32_t val;
5291
5292 METHOD_TRACE("ips_issue_copperhead", 1);
5293
5294 if (scb->scsi_cmd) {
5295 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5296 ips_name,
5297 ha->host_num,
5298 scb->cdb[0],
5299 scb->cmd.basic_io.command_id,
5300 scb->bus, scb->target_id, scb->lun);
5301 } else {
5302 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5303 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5304 }
5305
5306 TimeOut = 0;
5307
5308 while ((val =
5309 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5310 udelay(1000);
5311
5312 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5313 if (!(val & IPS_BIT_START_STOP))
5314 break;
5315
5316 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5317 "ips_issue val [0x%x].\n", val);
5318 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5319 "ips_issue semaphore chk timeout.\n");
5320
5321 return (IPS_FAILURE);
5322 }
5323 }
5324
5325 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5326 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5327
5328 return (IPS_SUCCESS);
5329}
5330
5331
5332
5333
5334
5335
5336
5337
5338
5339
5340static int
5341ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5342{
5343 uint32_t TimeOut;
5344 uint32_t val;
5345
5346 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5347
5348 if (scb->scsi_cmd) {
5349 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5350 ips_name,
5351 ha->host_num,
5352 scb->cdb[0],
5353 scb->cmd.basic_io.command_id,
5354 scb->bus, scb->target_id, scb->lun);
5355 } else {
5356 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5357 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5358 }
5359
5360 TimeOut = 0;
5361
5362 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5363 udelay(1000);
5364
5365 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5366 if (!(val & IPS_BIT_START_STOP))
5367 break;
5368
5369 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5370 "ips_issue val [0x%x].\n", val);
5371 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5372 "ips_issue semaphore chk timeout.\n");
5373
5374 return (IPS_FAILURE);
5375 }
5376 }
5377
5378 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5379 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5380
5381 return (IPS_SUCCESS);
5382}
5383
5384
5385
5386
5387
5388
5389
5390
5391
5392
5393static int
5394ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5395{
5396
5397 METHOD_TRACE("ips_issue_i2o", 1);
5398
5399 if (scb->scsi_cmd) {
5400 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5401 ips_name,
5402 ha->host_num,
5403 scb->cdb[0],
5404 scb->cmd.basic_io.command_id,
5405 scb->bus, scb->target_id, scb->lun);
5406 } else {
5407 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5408 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5409 }
5410
5411 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5412
5413 return (IPS_SUCCESS);
5414}
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425static int
5426ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5427{
5428
5429 METHOD_TRACE("ips_issue_i2o_memio", 1);
5430
5431 if (scb->scsi_cmd) {
5432 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5433 ips_name,
5434 ha->host_num,
5435 scb->cdb[0],
5436 scb->cmd.basic_io.command_id,
5437 scb->bus, scb->target_id, scb->lun);
5438 } else {
5439 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5440 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5441 }
5442
5443 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5444
5445 return (IPS_SUCCESS);
5446}
5447
5448
5449
5450
5451
5452
5453
5454
5455
5456
5457static int
5458ips_isintr_copperhead(ips_ha_t * ha)
5459{
5460 uint8_t Isr;
5461
5462 METHOD_TRACE("ips_isintr_copperhead", 2);
5463
5464 Isr = inb(ha->io_addr + IPS_REG_HISR);
5465
5466 if (Isr == 0xFF)
5467
5468 return (0);
5469
5470 if (Isr & IPS_BIT_SCE)
5471 return (1);
5472 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5473
5474
5475 outb(Isr, ha->io_addr + IPS_REG_HISR);
5476 }
5477
5478 return (0);
5479}
5480
5481
5482
5483
5484
5485
5486
5487
5488
5489
5490static int
5491ips_isintr_copperhead_memio(ips_ha_t * ha)
5492{
5493 uint8_t Isr;
5494
5495 METHOD_TRACE("ips_isintr_memio", 2);
5496
5497 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5498
5499 if (Isr == 0xFF)
5500
5501 return (0);
5502
5503 if (Isr & IPS_BIT_SCE)
5504 return (1);
5505 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5506
5507
5508 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5509 }
5510
5511 return (0);
5512}
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522
5523static int
5524ips_isintr_morpheus(ips_ha_t * ha)
5525{
5526 uint32_t Isr;
5527
5528 METHOD_TRACE("ips_isintr_morpheus", 2);
5529
5530 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5531
5532 if (Isr & IPS_BIT_I2O_OPQI)
5533 return (1);
5534 else
5535 return (0);
5536}
5537
5538
5539
5540
5541
5542
5543
5544
5545
5546
5547static int
5548ips_wait(ips_ha_t * ha, int time, int intr)
5549{
5550 int ret;
5551 int done;
5552
5553 METHOD_TRACE("ips_wait", 1);
5554
5555 ret = IPS_FAILURE;
5556 done = FALSE;
5557
5558 time *= IPS_ONE_SEC;
5559
5560 while ((time > 0) && (!done)) {
5561 if (intr == IPS_INTR_ON) {
5562 if (ha->waitflag == FALSE) {
5563 ret = IPS_SUCCESS;
5564 done = TRUE;
5565 break;
5566 }
5567 } else if (intr == IPS_INTR_IORL) {
5568 if (ha->waitflag == FALSE) {
5569
5570
5571
5572
5573
5574 ret = IPS_SUCCESS;
5575 done = TRUE;
5576 break;
5577 }
5578
5579
5580
5581
5582
5583
5584
5585 (*ha->func.intr) (ha);
5586 }
5587
5588
5589 udelay(1000);
5590 time--;
5591 }
5592
5593 return (ret);
5594}
5595
5596
5597
5598
5599
5600
5601
5602
5603
5604
5605static int
5606ips_write_driver_status(ips_ha_t * ha, int intr)
5607{
5608 METHOD_TRACE("ips_write_driver_status", 1);
5609
5610 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5611 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5612 "unable to read NVRAM page 5.\n");
5613
5614 return (0);
5615 }
5616
5617
5618
5619 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5620 DEBUG_VAR(1,
5621 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5622 ips_name, ha->host_num, ha->nvram->signature);
5623 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5624 }
5625
5626 DEBUG_VAR(2,
5627 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5628 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5629 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5630 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5631 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5632 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5633 ha->nvram->bios_low[3]);
5634
5635 ips_get_bios_version(ha, intr);
5636
5637
5638 ha->nvram->operating_system = IPS_OS_LINUX;
5639 ha->nvram->adapter_type = ha->ad_type;
5640 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5641 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5642 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5643 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5644
5645 ha->nvram->versioning = 0;
5646
5647
5648 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5649 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5650 "unable to write NVRAM page 5.\n");
5651
5652 return (0);
5653 }
5654
5655
5656 ha->slot_num = ha->nvram->adapter_slot;
5657
5658 return (1);
5659}
5660
5661
5662
5663
5664
5665
5666
5667
5668
5669
5670static int
5671ips_read_adapter_status(ips_ha_t * ha, int intr)
5672{
5673 ips_scb_t *scb;
5674 int ret;
5675
5676 METHOD_TRACE("ips_read_adapter_status", 1);
5677
5678 scb = &ha->scbs[ha->max_cmds - 1];
5679
5680 ips_init_scb(ha, scb);
5681
5682 scb->timeout = ips_cmd_timeout;
5683 scb->cdb[0] = IPS_CMD_ENQUIRY;
5684
5685 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5686 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5687 scb->cmd.basic_io.sg_count = 0;
5688 scb->cmd.basic_io.lba = 0;
5689 scb->cmd.basic_io.sector_count = 0;
5690 scb->cmd.basic_io.log_drv = 0;
5691 scb->data_len = sizeof (*ha->enq);
5692 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5693
5694
5695 if (((ret =
5696 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5697 || (ret == IPS_SUCCESS_IMM)
5698 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5699 return (0);
5700
5701 return (1);
5702}
5703
5704
5705
5706
5707
5708
5709
5710
5711
5712
5713static int
5714ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5715{
5716 ips_scb_t *scb;
5717 int ret;
5718
5719 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5720
5721 scb = &ha->scbs[ha->max_cmds - 1];
5722
5723 ips_init_scb(ha, scb);
5724
5725 scb->timeout = ips_cmd_timeout;
5726 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5727
5728 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5729 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5730 scb->cmd.basic_io.sg_count = 0;
5731 scb->cmd.basic_io.lba = 0;
5732 scb->cmd.basic_io.sector_count = 0;
5733 scb->cmd.basic_io.log_drv = 0;
5734 scb->data_len = sizeof (*ha->subsys);
5735 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5736
5737
5738 if (((ret =
5739 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5740 || (ret == IPS_SUCCESS_IMM)
5741 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5742 return (0);
5743
5744 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5745 return (1);
5746}
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756
5757static int
5758ips_read_config(ips_ha_t * ha, int intr)
5759{
5760 ips_scb_t *scb;
5761 int i;
5762 int ret;
5763
5764 METHOD_TRACE("ips_read_config", 1);
5765
5766
5767 for (i = 0; i < 4; i++)
5768 ha->conf->init_id[i] = 7;
5769
5770 scb = &ha->scbs[ha->max_cmds - 1];
5771
5772 ips_init_scb(ha, scb);
5773
5774 scb->timeout = ips_cmd_timeout;
5775 scb->cdb[0] = IPS_CMD_READ_CONF;
5776
5777 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5778 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5779 scb->data_len = sizeof (*ha->conf);
5780 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5781
5782
5783 if (((ret =
5784 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5785 || (ret == IPS_SUCCESS_IMM)
5786 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5787
5788 memset(ha->conf, 0, sizeof (IPS_CONF));
5789
5790
5791 for (i = 0; i < 4; i++)
5792 ha->conf->init_id[i] = 7;
5793
5794
5795 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5796 IPS_CMD_CMPLT_WERROR)
5797 return (1);
5798
5799 return (0);
5800 }
5801
5802 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5803 return (1);
5804}
5805
5806
5807
5808
5809
5810
5811
5812
5813
5814
5815static int
5816ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5817{
5818 ips_scb_t *scb;
5819 int ret;
5820
5821 METHOD_TRACE("ips_readwrite_page5", 1);
5822
5823 scb = &ha->scbs[ha->max_cmds - 1];
5824
5825 ips_init_scb(ha, scb);
5826
5827 scb->timeout = ips_cmd_timeout;
5828 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5829
5830 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5831 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5832 scb->cmd.nvram.page = 5;
5833 scb->cmd.nvram.write = write;
5834 scb->cmd.nvram.reserved = 0;
5835 scb->cmd.nvram.reserved2 = 0;
5836 scb->data_len = sizeof (*ha->nvram);
5837 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5838 if (write)
5839 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5840
5841
5842 if (((ret =
5843 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5844 || (ret == IPS_SUCCESS_IMM)
5845 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5846
5847 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5848
5849 return (0);
5850 }
5851 if (!write)
5852 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5853 return (1);
5854}
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865static int
5866ips_clear_adapter(ips_ha_t * ha, int intr)
5867{
5868 ips_scb_t *scb;
5869 int ret;
5870
5871 METHOD_TRACE("ips_clear_adapter", 1);
5872
5873 scb = &ha->scbs[ha->max_cmds - 1];
5874
5875 ips_init_scb(ha, scb);
5876
5877 scb->timeout = ips_reset_timeout;
5878 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5879
5880 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5881 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5882 scb->cmd.config_sync.channel = 0;
5883 scb->cmd.config_sync.source_target = IPS_POCL;
5884 scb->cmd.config_sync.reserved = 0;
5885 scb->cmd.config_sync.reserved2 = 0;
5886 scb->cmd.config_sync.reserved3 = 0;
5887
5888
5889 if (((ret =
5890 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5891 || (ret == IPS_SUCCESS_IMM)
5892 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5893 return (0);
5894
5895
5896 ips_init_scb(ha, scb);
5897
5898 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5899 scb->timeout = ips_reset_timeout;
5900
5901 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5902 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5903 scb->cmd.unlock_stripe.log_drv = 0;
5904 scb->cmd.unlock_stripe.control = IPS_CSL;
5905 scb->cmd.unlock_stripe.reserved = 0;
5906 scb->cmd.unlock_stripe.reserved2 = 0;
5907 scb->cmd.unlock_stripe.reserved3 = 0;
5908
5909
5910 if (((ret =
5911 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5912 || (ret == IPS_SUCCESS_IMM)
5913 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5914 return (0);
5915
5916 return (1);
5917}
5918
5919
5920
5921
5922
5923
5924
5925
5926
5927
5928static void
5929ips_ffdc_reset(ips_ha_t * ha, int intr)
5930{
5931 ips_scb_t *scb;
5932
5933 METHOD_TRACE("ips_ffdc_reset", 1);
5934
5935 scb = &ha->scbs[ha->max_cmds - 1];
5936
5937 ips_init_scb(ha, scb);
5938
5939 scb->timeout = ips_cmd_timeout;
5940 scb->cdb[0] = IPS_CMD_FFDC;
5941 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5942 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5943 scb->cmd.ffdc.reset_count = ha->reset_count;
5944 scb->cmd.ffdc.reset_type = 0x80;
5945
5946
5947 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5948
5949
5950 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5951}
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962static void
5963ips_ffdc_time(ips_ha_t * ha)
5964{
5965 ips_scb_t *scb;
5966
5967 METHOD_TRACE("ips_ffdc_time", 1);
5968
5969 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5970
5971 scb = &ha->scbs[ha->max_cmds - 1];
5972
5973 ips_init_scb(ha, scb);
5974
5975 scb->timeout = ips_cmd_timeout;
5976 scb->cdb[0] = IPS_CMD_FFDC;
5977 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5978 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5979 scb->cmd.ffdc.reset_count = 0;
5980 scb->cmd.ffdc.reset_type = 0;
5981
5982
5983 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5984
5985
5986 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5987}
5988
5989
5990
5991
5992
5993
5994
5995
5996
5997static void
5998ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
5999{
6000 long days;
6001 long rem;
6002 int i;
6003 int year;
6004 int yleap;
6005 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6006 int month_lengths[12][2] = { {31, 31},
6007 {28, 29},
6008 {31, 31},
6009 {30, 30},
6010 {31, 31},
6011 {30, 30},
6012 {31, 31},
6013 {31, 31},
6014 {30, 30},
6015 {31, 31},
6016 {30, 30},
6017 {31, 31}
6018 };
6019
6020 METHOD_TRACE("ips_fix_ffdc_time", 1);
6021
6022 days = current_time / IPS_SECS_DAY;
6023 rem = current_time % IPS_SECS_DAY;
6024
6025 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6026 rem = rem % IPS_SECS_HOUR;
6027 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6028 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6029
6030 year = IPS_EPOCH_YEAR;
6031 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6032 int newy;
6033
6034 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6035 if (days < 0)
6036 --newy;
6037 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6038 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6039 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6040 year = newy;
6041 }
6042
6043 scb->cmd.ffdc.yearH = year / 100;
6044 scb->cmd.ffdc.yearL = year % 100;
6045
6046 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6047 days -= month_lengths[i][yleap];
6048
6049 scb->cmd.ffdc.month = i + 1;
6050 scb->cmd.ffdc.day = days + 1;
6051}
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062
6063
6064
6065static int
6066ips_erase_bios(ips_ha_t * ha)
6067{
6068 int timeout;
6069 uint8_t status = 0;
6070
6071 METHOD_TRACE("ips_erase_bios", 1);
6072
6073 status = 0;
6074
6075
6076 outl(0, ha->io_addr + IPS_REG_FLAP);
6077 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6078 udelay(25);
6079
6080 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6081 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6082 udelay(25);
6083
6084
6085 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6086 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6087 udelay(25);
6088
6089
6090 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6091 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6092 udelay(25);
6093
6094
6095 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6096 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6097 udelay(25);
6098
6099 timeout = 80000;
6100
6101 while (timeout > 0) {
6102 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6103 outl(0, ha->io_addr + IPS_REG_FLAP);
6104 udelay(25);
6105 }
6106
6107 status = inb(ha->io_addr + IPS_REG_FLDP);
6108
6109 if (status & 0x80)
6110 break;
6111
6112 MDELAY(1);
6113 timeout--;
6114 }
6115
6116
6117 if (timeout <= 0) {
6118
6119
6120
6121 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6122 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6123 udelay(25);
6124
6125
6126 timeout = 10000;
6127 while (timeout > 0) {
6128 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6129 outl(0, ha->io_addr + IPS_REG_FLAP);
6130 udelay(25);
6131 }
6132
6133 status = inb(ha->io_addr + IPS_REG_FLDP);
6134
6135 if (status & 0xC0)
6136 break;
6137
6138 MDELAY(1);
6139 timeout--;
6140 }
6141
6142 return (1);
6143 }
6144
6145
6146 if (status & 0x08)
6147
6148 return (1);
6149
6150
6151 if (status & 0x30)
6152
6153 return (1);
6154
6155
6156
6157 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6158 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6159 udelay(25);
6160
6161
6162 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6163 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6164 udelay(25);
6165
6166 return (0);
6167}
6168
6169
6170
6171
6172
6173
6174
6175
6176
6177static int
6178ips_erase_bios_memio(ips_ha_t * ha)
6179{
6180 int timeout;
6181 uint8_t status;
6182
6183 METHOD_TRACE("ips_erase_bios_memio", 1);
6184
6185 status = 0;
6186
6187
6188 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6189 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6190 udelay(25);
6191
6192 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6193 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6194 udelay(25);
6195
6196
6197 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6198 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6199 udelay(25);
6200
6201
6202 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6203 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6204 udelay(25);
6205
6206
6207 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6208 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6209 udelay(25);
6210
6211 timeout = 80000;
6212
6213 while (timeout > 0) {
6214 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6215 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6216 udelay(25);
6217 }
6218
6219 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6220
6221 if (status & 0x80)
6222 break;
6223
6224 MDELAY(1);
6225 timeout--;
6226 }
6227
6228
6229 if (timeout <= 0) {
6230
6231
6232
6233 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6234 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6235 udelay(25);
6236
6237
6238 timeout = 10000;
6239 while (timeout > 0) {
6240 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6241 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6242 udelay(25);
6243 }
6244
6245 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6246
6247 if (status & 0xC0)
6248 break;
6249
6250 MDELAY(1);
6251 timeout--;
6252 }
6253
6254 return (1);
6255 }
6256
6257
6258 if (status & 0x08)
6259
6260 return (1);
6261
6262
6263 if (status & 0x30)
6264
6265 return (1);
6266
6267
6268
6269 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6270 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6271 udelay(25);
6272
6273
6274 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6275 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6276 udelay(25);
6277
6278 return (0);
6279}
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289static int
6290ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6291 uint32_t offset)
6292{
6293 int i;
6294 int timeout;
6295 uint8_t status = 0;
6296
6297 METHOD_TRACE("ips_program_bios", 1);
6298
6299 status = 0;
6300
6301 for (i = 0; i < buffersize; i++) {
6302
6303 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6304 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6305 udelay(25);
6306
6307 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6308 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6309 udelay(25);
6310
6311 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6312 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6313 udelay(25);
6314
6315
6316 timeout = 1000;
6317 while (timeout > 0) {
6318 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6319 outl(0, ha->io_addr + IPS_REG_FLAP);
6320 udelay(25);
6321 }
6322
6323 status = inb(ha->io_addr + IPS_REG_FLDP);
6324
6325 if (status & 0x80)
6326 break;
6327
6328 MDELAY(1);
6329 timeout--;
6330 }
6331
6332 if (timeout == 0) {
6333
6334 outl(0, ha->io_addr + IPS_REG_FLAP);
6335 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6336 udelay(25);
6337
6338 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6339 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6340 udelay(25);
6341
6342 return (1);
6343 }
6344
6345
6346 if (status & 0x18) {
6347
6348 outl(0, ha->io_addr + IPS_REG_FLAP);
6349 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6350 udelay(25);
6351
6352 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6353 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6354 udelay(25);
6355
6356 return (1);
6357 }
6358 }
6359
6360
6361 outl(0, ha->io_addr + IPS_REG_FLAP);
6362 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6363 udelay(25);
6364
6365 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6366 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6367 udelay(25);
6368
6369 return (0);
6370}
6371
6372
6373
6374
6375
6376
6377
6378
6379
6380static int
6381ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6382 uint32_t offset)
6383{
6384 int i;
6385 int timeout;
6386 uint8_t status = 0;
6387
6388 METHOD_TRACE("ips_program_bios_memio", 1);
6389
6390 status = 0;
6391
6392 for (i = 0; i < buffersize; i++) {
6393
6394 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6395 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6396 udelay(25);
6397
6398 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6399 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6400 udelay(25);
6401
6402 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6403 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6404 udelay(25);
6405
6406
6407 timeout = 1000;
6408 while (timeout > 0) {
6409 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6410 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6411 udelay(25);
6412 }
6413
6414 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6415
6416 if (status & 0x80)
6417 break;
6418
6419 MDELAY(1);
6420 timeout--;
6421 }
6422
6423 if (timeout == 0) {
6424
6425 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6426 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6427 udelay(25);
6428
6429 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6430 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6431 udelay(25);
6432
6433 return (1);
6434 }
6435
6436
6437 if (status & 0x18) {
6438
6439 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6440 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6441 udelay(25);
6442
6443 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6444 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6445 udelay(25);
6446
6447 return (1);
6448 }
6449 }
6450
6451
6452 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6453 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6454 udelay(25);
6455
6456 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6457 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6458 udelay(25);
6459
6460 return (0);
6461}
6462
6463
6464
6465
6466
6467
6468
6469
6470
6471static int
6472ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6473 uint32_t offset)
6474{
6475 uint8_t checksum;
6476 int i;
6477
6478 METHOD_TRACE("ips_verify_bios", 1);
6479
6480
6481 outl(0, ha->io_addr + IPS_REG_FLAP);
6482 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6483 udelay(25);
6484
6485 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6486 return (1);
6487
6488 outl(1, ha->io_addr + IPS_REG_FLAP);
6489 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6490 udelay(25);
6491 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6492 return (1);
6493
6494 checksum = 0xff;
6495 for (i = 2; i < buffersize; i++) {
6496
6497 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6498 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6499 udelay(25);
6500
6501 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6502 }
6503
6504 if (checksum != 0)
6505
6506 return (1);
6507 else
6508
6509 return (0);
6510}
6511
6512
6513
6514
6515
6516
6517
6518
6519
6520static int
6521ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6522 uint32_t offset)
6523{
6524 uint8_t checksum;
6525 int i;
6526
6527 METHOD_TRACE("ips_verify_bios_memio", 1);
6528
6529
6530 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6531 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6532 udelay(25);
6533
6534 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6535 return (1);
6536
6537 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6538 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6539 udelay(25);
6540 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6541 return (1);
6542
6543 checksum = 0xff;
6544 for (i = 2; i < buffersize; i++) {
6545
6546 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6547 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6548 udelay(25);
6549
6550 checksum =
6551 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6552 }
6553
6554 if (checksum != 0)
6555
6556 return (1);
6557 else
6558
6559 return (0);
6560}
6561
6562
6563
6564
6565
6566
6567
6568
6569static int
6570ips_abort_init(ips_ha_t * ha, int index)
6571{
6572 ha->active = 0;
6573 ips_free(ha);
6574 ips_ha[index] = NULL;
6575 ips_sh[index] = NULL;
6576 return -1;
6577}
6578
6579
6580
6581
6582
6583
6584
6585
6586static void
6587ips_shift_controllers(int lowindex, int highindex)
6588{
6589 ips_ha_t *ha_sav = ips_ha[highindex];
6590 struct Scsi_Host *sh_sav = ips_sh[highindex];
6591 int i;
6592
6593 for (i = highindex; i > lowindex; i--) {
6594 ips_ha[i] = ips_ha[i - 1];
6595 ips_sh[i] = ips_sh[i - 1];
6596 ips_ha[i]->host_num = i;
6597 }
6598 ha_sav->host_num = lowindex;
6599 ips_ha[lowindex] = ha_sav;
6600 ips_sh[lowindex] = sh_sav;
6601}
6602
6603
6604
6605
6606
6607
6608
6609
6610static void
6611ips_order_controllers(void)
6612{
6613 int i, j, tmp, position = 0;
6614 IPS_NVRAM_P5 *nvram;
6615 if (!ips_ha[0])
6616 return;
6617 nvram = ips_ha[0]->nvram;
6618
6619 if (nvram->adapter_order[0]) {
6620 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6621 for (j = position; j < ips_num_controllers; j++) {
6622 switch (ips_ha[j]->ad_type) {
6623 case IPS_ADTYPE_SERVERAID6M:
6624 case IPS_ADTYPE_SERVERAID7M:
6625 if (nvram->adapter_order[i] == 'M') {
6626 ips_shift_controllers(position,
6627 j);
6628 position++;
6629 }
6630 break;
6631 case IPS_ADTYPE_SERVERAID4L:
6632 case IPS_ADTYPE_SERVERAID4M:
6633 case IPS_ADTYPE_SERVERAID4MX:
6634 case IPS_ADTYPE_SERVERAID4LX:
6635 if (nvram->adapter_order[i] == 'N') {
6636 ips_shift_controllers(position,
6637 j);
6638 position++;
6639 }
6640 break;
6641 case IPS_ADTYPE_SERVERAID6I:
6642 case IPS_ADTYPE_SERVERAID5I2:
6643 case IPS_ADTYPE_SERVERAID5I1:
6644 case IPS_ADTYPE_SERVERAID7k:
6645 if (nvram->adapter_order[i] == 'S') {
6646 ips_shift_controllers(position,
6647 j);
6648 position++;
6649 }
6650 break;
6651 case IPS_ADTYPE_SERVERAID:
6652 case IPS_ADTYPE_SERVERAID2:
6653 case IPS_ADTYPE_NAVAJO:
6654 case IPS_ADTYPE_KIOWA:
6655 case IPS_ADTYPE_SERVERAID3L:
6656 case IPS_ADTYPE_SERVERAID3:
6657 case IPS_ADTYPE_SERVERAID4H:
6658 if (nvram->adapter_order[i] == 'A') {
6659 ips_shift_controllers(position,
6660 j);
6661 position++;
6662 }
6663 break;
6664 default:
6665 break;
6666 }
6667 }
6668 }
6669
6670 return;
6671 }
6672
6673 tmp = 0;
6674 for (i = position; i < ips_num_controllers; i++) {
6675 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6676 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6677 ips_shift_controllers(position, i);
6678 position++;
6679 tmp = 1;
6680 }
6681 }
6682
6683 if (!tmp)
6684 return;
6685 for (i = position; i < ips_num_controllers; i++) {
6686 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6687 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6688 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6689 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6690 ips_shift_controllers(position, i);
6691 position++;
6692 }
6693 }
6694
6695 return;
6696}
6697
6698
6699
6700
6701
6702
6703
6704
6705static int
6706ips_register_scsi(int index)
6707{
6708 struct Scsi_Host *sh;
6709 ips_ha_t *ha, *oldha = ips_ha[index];
6710 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6711 if (!sh) {
6712 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6713 "Unable to register controller with SCSI subsystem\n");
6714 return -1;
6715 }
6716 ha = IPS_HA(sh);
6717 memcpy(ha, oldha, sizeof (ips_ha_t));
6718 free_irq(oldha->pcidev->irq, oldha);
6719
6720 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6721 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6722 "Unable to install interrupt handler\n");
6723 goto err_out_sh;
6724 }
6725
6726 kfree(oldha);
6727
6728
6729 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6730 sh->sg_tablesize = sh->hostt->sg_tablesize;
6731 sh->can_queue = sh->hostt->can_queue;
6732 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6733 sh->use_clustering = sh->hostt->use_clustering;
6734 sh->max_sectors = 128;
6735
6736 sh->max_id = ha->ntargets;
6737 sh->max_lun = ha->nlun;
6738 sh->max_channel = ha->nbus - 1;
6739 sh->can_queue = ha->max_cmds - 1;
6740
6741 if (scsi_add_host(sh, &ha->pcidev->dev))
6742 goto err_out;
6743
6744 ips_sh[index] = sh;
6745 ips_ha[index] = ha;
6746
6747 scsi_scan_host(sh);
6748
6749 return 0;
6750
6751err_out:
6752 free_irq(ha->pcidev->irq, ha);
6753err_out_sh:
6754 scsi_host_put(sh);
6755 return -1;
6756}
6757
6758
6759
6760
6761
6762
6763
6764static void
6765ips_remove_device(struct pci_dev *pci_dev)
6766{
6767 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6768
6769 pci_set_drvdata(pci_dev, NULL);
6770
6771 ips_release(sh);
6772
6773 pci_release_regions(pci_dev);
6774 pci_disable_device(pci_dev);
6775}
6776
6777
6778
6779
6780
6781
6782
6783
6784static int __init
6785ips_module_init(void)
6786{
6787#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
6788 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n");
6789 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
6790#endif
6791
6792 if (pci_register_driver(&ips_pci_driver) < 0)
6793 return -ENODEV;
6794 ips_driver_template.module = THIS_MODULE;
6795 ips_order_controllers();
6796 if (!ips_detect(&ips_driver_template)) {
6797 pci_unregister_driver(&ips_pci_driver);
6798 return -ENODEV;
6799 }
6800 register_reboot_notifier(&ips_notifier);
6801 return 0;
6802}
6803
6804
6805
6806
6807
6808
6809
6810
6811static void __exit
6812ips_module_exit(void)
6813{
6814 pci_unregister_driver(&ips_pci_driver);
6815 unregister_reboot_notifier(&ips_notifier);
6816}
6817
6818module_init(ips_module_init);
6819module_exit(ips_module_exit);
6820
6821
6822
6823
6824
6825
6826
6827
6828
6829
6830static int
6831ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6832{
6833 int index = -1;
6834 int rc;
6835
6836 METHOD_TRACE("ips_insert_device", 1);
6837 rc = pci_enable_device(pci_dev);
6838 if (rc)
6839 return rc;
6840
6841 rc = pci_request_regions(pci_dev, "ips");
6842 if (rc)
6843 goto err_out;
6844
6845 rc = ips_init_phase1(pci_dev, &index);
6846 if (rc == SUCCESS)
6847 rc = ips_init_phase2(index);
6848
6849 if (ips_hotplug)
6850 if (ips_register_scsi(index)) {
6851 ips_free(ips_ha[index]);
6852 rc = -1;
6853 }
6854
6855 if (rc == SUCCESS)
6856 ips_num_controllers++;
6857
6858 ips_next_controller = ips_num_controllers;
6859
6860 if (rc < 0) {
6861 rc = -ENODEV;
6862 goto err_out_regions;
6863 }
6864
6865 pci_set_drvdata(pci_dev, ips_sh[index]);
6866 return 0;
6867
6868err_out_regions:
6869 pci_release_regions(pci_dev);
6870err_out:
6871 pci_disable_device(pci_dev);
6872 return rc;
6873}
6874
6875
6876
6877
6878
6879
6880
6881
6882
6883
6884static int
6885ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6886{
6887 ips_ha_t *ha;
6888 uint32_t io_addr;
6889 uint32_t mem_addr;
6890 uint32_t io_len;
6891 uint32_t mem_len;
6892 uint8_t bus;
6893 uint8_t func;
6894 int j;
6895 int index;
6896 dma_addr_t dma_address;
6897 char __iomem *ioremap_ptr;
6898 char __iomem *mem_ptr;
6899 uint32_t IsDead;
6900
6901 METHOD_TRACE("ips_init_phase1", 1);
6902 index = IPS_MAX_ADAPTERS;
6903 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6904 if (ips_ha[j] == NULL) {
6905 index = j;
6906 break;
6907 }
6908 }
6909
6910 if (index >= IPS_MAX_ADAPTERS)
6911 return -1;
6912
6913
6914 bus = pci_dev->bus->number;
6915 func = pci_dev->devfn;
6916
6917
6918 mem_addr = 0;
6919 io_addr = 0;
6920 mem_len = 0;
6921 io_len = 0;
6922
6923 for (j = 0; j < 2; j++) {
6924 if (!pci_resource_start(pci_dev, j))
6925 break;
6926
6927 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6928 io_addr = pci_resource_start(pci_dev, j);
6929 io_len = pci_resource_len(pci_dev, j);
6930 } else {
6931 mem_addr = pci_resource_start(pci_dev, j);
6932 mem_len = pci_resource_len(pci_dev, j);
6933 }
6934 }
6935
6936
6937 if (mem_addr) {
6938 uint32_t base;
6939 uint32_t offs;
6940
6941 base = mem_addr & PAGE_MASK;
6942 offs = mem_addr - base;
6943 ioremap_ptr = ioremap(base, PAGE_SIZE);
6944 if (!ioremap_ptr)
6945 return -1;
6946 mem_ptr = ioremap_ptr + offs;
6947 } else {
6948 ioremap_ptr = NULL;
6949 mem_ptr = NULL;
6950 }
6951
6952
6953 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
6954 if (ha == NULL) {
6955 IPS_PRINTK(KERN_WARNING, pci_dev,
6956 "Unable to allocate temporary ha struct\n");
6957 return -1;
6958 }
6959
6960 ips_sh[index] = NULL;
6961 ips_ha[index] = ha;
6962 ha->active = 1;
6963
6964
6965 ha->io_addr = io_addr;
6966 ha->io_len = io_len;
6967 ha->mem_addr = mem_addr;
6968 ha->mem_len = mem_len;
6969 ha->mem_ptr = mem_ptr;
6970 ha->ioremap_ptr = ioremap_ptr;
6971 ha->host_num = (uint32_t) index;
6972 ha->slot_num = PCI_SLOT(pci_dev->devfn);
6973 ha->pcidev = pci_dev;
6974
6975
6976
6977
6978
6979
6980
6981 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
6982 !pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(64))) {
6983 (ha)->flags |= IPS_HA_ENH_SG;
6984 } else {
6985 if (pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(32)) != 0) {
6986 printk(KERN_WARNING "Unable to set DMA Mask\n");
6987 return ips_abort_init(ha, index);
6988 }
6989 }
6990 if(ips_cd_boot && !ips_FlashData){
6991 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
6992 &ips_flashbusaddr);
6993 }
6994
6995 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
6996 &ha->enq_busaddr);
6997 if (!ha->enq) {
6998 IPS_PRINTK(KERN_WARNING, pci_dev,
6999 "Unable to allocate host inquiry structure\n");
7000 return ips_abort_init(ha, index);
7001 }
7002
7003 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7004 sizeof (IPS_IO_CMD), &dma_address);
7005 if (!ha->adapt) {
7006 IPS_PRINTK(KERN_WARNING, pci_dev,
7007 "Unable to allocate host adapt & dummy structures\n");
7008 return ips_abort_init(ha, index);
7009 }
7010 ha->adapt->hw_status_start = dma_address;
7011 ha->dummy = (void *) (ha->adapt + 1);
7012
7013
7014
7015 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7016 if (!ha->logical_drive_info) {
7017 IPS_PRINTK(KERN_WARNING, pci_dev,
7018 "Unable to allocate logical drive info structure\n");
7019 return ips_abort_init(ha, index);
7020 }
7021 ha->logical_drive_info_dma_addr = dma_address;
7022
7023
7024 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7025
7026 if (!ha->conf) {
7027 IPS_PRINTK(KERN_WARNING, pci_dev,
7028 "Unable to allocate host conf structure\n");
7029 return ips_abort_init(ha, index);
7030 }
7031
7032 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7033
7034 if (!ha->nvram) {
7035 IPS_PRINTK(KERN_WARNING, pci_dev,
7036 "Unable to allocate host NVRAM structure\n");
7037 return ips_abort_init(ha, index);
7038 }
7039
7040 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7041
7042 if (!ha->subsys) {
7043 IPS_PRINTK(KERN_WARNING, pci_dev,
7044 "Unable to allocate host subsystem structure\n");
7045 return ips_abort_init(ha, index);
7046 }
7047
7048
7049
7050 if (ips_ioctlsize < PAGE_SIZE)
7051 ips_ioctlsize = PAGE_SIZE;
7052
7053 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7054 &ha->ioctl_busaddr);
7055 ha->ioctl_len = ips_ioctlsize;
7056 if (!ha->ioctl_data) {
7057 IPS_PRINTK(KERN_WARNING, pci_dev,
7058 "Unable to allocate IOCTL data\n");
7059 return ips_abort_init(ha, index);
7060 }
7061
7062
7063
7064
7065 ips_setup_funclist(ha);
7066
7067 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7068
7069 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7070 if (IsDead == 0xDEADBEEF) {
7071 ips_reset_morpheus(ha);
7072 }
7073 }
7074
7075
7076
7077
7078
7079 if (!(*ha->func.isinit) (ha)) {
7080 if (!(*ha->func.init) (ha)) {
7081
7082
7083
7084 IPS_PRINTK(KERN_WARNING, pci_dev,
7085 "Unable to initialize controller\n");
7086 return ips_abort_init(ha, index);
7087 }
7088 }
7089
7090 *indexPtr = index;
7091 return SUCCESS;
7092}
7093
7094
7095
7096
7097
7098
7099
7100
7101
7102
7103static int
7104ips_init_phase2(int index)
7105{
7106 ips_ha_t *ha;
7107
7108 ha = ips_ha[index];
7109
7110 METHOD_TRACE("ips_init_phase2", 1);
7111 if (!ha->active) {
7112 ips_ha[index] = NULL;
7113 return -1;
7114 }
7115
7116
7117 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7118 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7119 "Unable to install interrupt handler\n");
7120 return ips_abort_init(ha, index);
7121 }
7122
7123
7124
7125
7126 ha->max_cmds = 1;
7127 if (!ips_allocatescbs(ha)) {
7128 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7129 "Unable to allocate a CCB\n");
7130 free_irq(ha->pcidev->irq, ha);
7131 return ips_abort_init(ha, index);
7132 }
7133
7134 if (!ips_hainit(ha)) {
7135 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7136 "Unable to initialize controller\n");
7137 free_irq(ha->pcidev->irq, ha);
7138 return ips_abort_init(ha, index);
7139 }
7140
7141 ips_deallocatescbs(ha, 1);
7142
7143
7144 if (!ips_allocatescbs(ha)) {
7145 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7146 "Unable to allocate CCBs\n");
7147 free_irq(ha->pcidev->irq, ha);
7148 return ips_abort_init(ha, index);
7149 }
7150
7151 return SUCCESS;
7152}
7153
7154MODULE_LICENSE("GPL");
7155MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7156MODULE_VERSION(IPS_VER_STRING);
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173
7174
7175
7176
7177
