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26#ifndef _MVS64XX_REG_H_
27#define _MVS64XX_REG_H_
28
29#include <linux/types.h>
30
31#define MAX_LINK_RATE SAS_LINK_RATE_3_0_GBPS
32
33
34enum hw_registers {
35 MVS_GBL_CTL = 0x04,
36 MVS_GBL_INT_STAT = 0x08,
37 MVS_GBL_PI = 0x0C,
38
39 MVS_PHY_CTL = 0x40,
40 MVS_PORTS_IMP = 0x9C,
41
42 MVS_GBL_PORT_TYPE = 0xa0,
43
44 MVS_CTL = 0x100,
45 MVS_PCS = 0x104,
46 MVS_CMD_LIST_LO = 0x108,
47 MVS_CMD_LIST_HI = 0x10C,
48 MVS_RX_FIS_LO = 0x110,
49 MVS_RX_FIS_HI = 0x114,
50
51 MVS_TX_CFG = 0x120,
52 MVS_TX_LO = 0x124,
53 MVS_TX_HI = 0x128,
54
55 MVS_TX_PROD_IDX = 0x12C,
56 MVS_TX_CONS_IDX = 0x130,
57 MVS_RX_CFG = 0x134,
58 MVS_RX_LO = 0x138,
59 MVS_RX_HI = 0x13C,
60 MVS_RX_CONS_IDX = 0x140,
61
62 MVS_INT_COAL = 0x148,
63 MVS_INT_COAL_TMOUT = 0x14C,
64 MVS_INT_STAT = 0x150,
65 MVS_INT_MASK = 0x154,
66 MVS_INT_STAT_SRS_0 = 0x158,
67 MVS_INT_MASK_SRS_0 = 0x15C,
68
69
70 MVS_P0_INT_STAT = 0x160,
71 MVS_P0_INT_MASK = 0x164,
72
73 MVS_P4_INT_STAT = 0x200,
74 MVS_P4_INT_MASK = 0x204,
75
76
77 MVS_P0_SER_CTLSTAT = 0x180,
78
79 MVS_P4_SER_CTLSTAT = 0x220,
80
81 MVS_CMD_ADDR = 0x1B8,
82 MVS_CMD_DATA = 0x1BC,
83
84
85 MVS_P0_CFG_ADDR = 0x1C0,
86 MVS_P0_CFG_DATA = 0x1C4,
87
88 MVS_P4_CFG_ADDR = 0x230,
89 MVS_P4_CFG_DATA = 0x234,
90
91
92 MVS_P0_VSR_ADDR = 0x1E0,
93 MVS_P0_VSR_DATA = 0x1E4,
94
95 MVS_P4_VSR_ADDR = 0x250,
96 MVS_P4_VSR_DATA = 0x254,
97};
98
99enum pci_cfg_registers {
100 PCR_PHY_CTL = 0x40,
101 PCR_PHY_CTL2 = 0x90,
102 PCR_DEV_CTRL = 0xE8,
103 PCR_LINK_STAT = 0xF2,
104};
105
106
107enum sas_sata_vsp_regs {
108 VSR_PHY_STAT = 0x00,
109 VSR_PHY_MODE1 = 0x01,
110 VSR_PHY_MODE2 = 0x02,
111 VSR_PHY_MODE3 = 0x03,
112 VSR_PHY_MODE4 = 0x04,
113 VSR_PHY_MODE5 = 0x05,
114 VSR_PHY_MODE6 = 0x06,
115 VSR_PHY_MODE7 = 0x07,
116 VSR_PHY_MODE8 = 0x08,
117 VSR_PHY_MODE9 = 0x09,
118 VSR_PHY_MODE10 = 0x0A,
119 VSR_PHY_MODE11 = 0x0B,
120 VSR_PHY_VS0 = 0x0C,
121 VSR_PHY_VS1 = 0x0D,
122};
123
124enum chip_register_bits {
125 PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
126 PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
127 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
128 PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
129 (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
130};
131
132#define MAX_SG_ENTRY 64
133
134struct mvs_prd {
135 __le64 addr;
136 __le32 reserved;
137 __le32 len;
138};
139
140#define SPI_CTRL_REG 0xc0
141#define SPI_CTRL_VENDOR_ENABLE (1U<<29)
142#define SPI_CTRL_SPIRDY (1U<<22)
143#define SPI_CTRL_SPISTART (1U<<20)
144
145#define SPI_CMD_REG 0xc4
146#define SPI_DATA_REG 0xc8
147
148#define SPI_CTRL_REG_64XX 0x10
149#define SPI_CMD_REG_64XX 0x14
150#define SPI_DATA_REG_64XX 0x18
151
152#endif
153
