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16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/errno.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/math64.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/regmap.h>
31#include <linux/sched.h>
32#include <linux/spi/spi.h>
33#include <linux/spi/spi_bitbang.h>
34#include <linux/time.h>
35
36#define DRIVER_NAME "fsl-dspi"
37
38#define TRAN_STATE_RX_VOID 0x01
39#define TRAN_STATE_TX_VOID 0x02
40#define TRAN_STATE_WORD_ODD_NUM 0x04
41
42#define DSPI_FIFO_SIZE 4
43
44#define SPI_MCR 0x00
45#define SPI_MCR_MASTER (1 << 31)
46#define SPI_MCR_PCSIS (0x3F << 16)
47#define SPI_MCR_CLR_TXF (1 << 11)
48#define SPI_MCR_CLR_RXF (1 << 10)
49
50#define SPI_TCR 0x08
51#define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
52
53#define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
54#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
55#define SPI_CTAR_CPOL(x) ((x) << 26)
56#define SPI_CTAR_CPHA(x) ((x) << 25)
57#define SPI_CTAR_LSBFE(x) ((x) << 24)
58#define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
59#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
60#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
61#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
62#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
63#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
64#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
65#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
66#define SPI_CTAR_SCALE_BITS 0xf
67
68#define SPI_CTAR0_SLAVE 0x0c
69
70#define SPI_SR 0x2c
71#define SPI_SR_EOQF 0x10000000
72#define SPI_SR_TCFQF 0x80000000
73
74#define SPI_RSER 0x30
75#define SPI_RSER_EOQFE 0x10000000
76#define SPI_RSER_TCFQE 0x80000000
77
78#define SPI_PUSHR 0x34
79#define SPI_PUSHR_CONT (1 << 31)
80#define SPI_PUSHR_CTAS(x) (((x) & 0x00000003) << 28)
81#define SPI_PUSHR_EOQ (1 << 27)
82#define SPI_PUSHR_CTCNT (1 << 26)
83#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
84#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
85
86#define SPI_PUSHR_SLAVE 0x34
87
88#define SPI_POPR 0x38
89#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
90
91#define SPI_TXFR0 0x3c
92#define SPI_TXFR1 0x40
93#define SPI_TXFR2 0x44
94#define SPI_TXFR3 0x48
95#define SPI_RXFR0 0x7c
96#define SPI_RXFR1 0x80
97#define SPI_RXFR2 0x84
98#define SPI_RXFR3 0x88
99
100#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
101#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
102#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
103#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
104
105#define SPI_CS_INIT 0x01
106#define SPI_CS_ASSERT 0x02
107#define SPI_CS_DROP 0x04
108
109#define SPI_TCR_TCNT_MAX 0x10000
110
111struct chip_data {
112 u32 mcr_val;
113 u32 ctar_val;
114 u16 void_write_data;
115};
116
117enum dspi_trans_mode {
118 DSPI_EOQ_MODE = 0,
119 DSPI_TCFQ_MODE,
120};
121
122struct fsl_dspi_devtype_data {
123 enum dspi_trans_mode trans_mode;
124};
125
126static const struct fsl_dspi_devtype_data vf610_data = {
127 .trans_mode = DSPI_EOQ_MODE,
128};
129
130static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
131 .trans_mode = DSPI_TCFQ_MODE,
132};
133
134static const struct fsl_dspi_devtype_data ls2085a_data = {
135 .trans_mode = DSPI_TCFQ_MODE,
136};
137
138struct fsl_dspi {
139 struct spi_master *master;
140 struct platform_device *pdev;
141
142 struct regmap *regmap;
143 int irq;
144 struct clk *clk;
145
146 struct spi_transfer *cur_transfer;
147 struct spi_message *cur_msg;
148 struct chip_data *cur_chip;
149 size_t len;
150 void *tx;
151 void *tx_end;
152 void *rx;
153 void *rx_end;
154 char dataflags;
155 u8 cs;
156 u16 void_write_data;
157 u32 cs_change;
158 struct fsl_dspi_devtype_data *devtype_data;
159
160 wait_queue_head_t waitq;
161 u32 waitflags;
162
163 u32 spi_tcnt;
164};
165
166static inline int is_double_byte_mode(struct fsl_dspi *dspi)
167{
168 unsigned int val;
169
170 regmap_read(dspi->regmap, SPI_CTAR(0), &val);
171
172 return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
173}
174
175static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
176 unsigned long clkrate)
177{
178
179 int pbr_tbl[4] = {2, 3, 5, 7};
180 int brs[16] = { 2, 4, 6, 8,
181 16, 32, 64, 128,
182 256, 512, 1024, 2048,
183 4096, 8192, 16384, 32768 };
184 int scale_needed, scale, minscale = INT_MAX;
185 int i, j;
186
187 scale_needed = clkrate / speed_hz;
188 if (clkrate % speed_hz)
189 scale_needed++;
190
191 for (i = 0; i < ARRAY_SIZE(brs); i++)
192 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
193 scale = brs[i] * pbr_tbl[j];
194 if (scale >= scale_needed) {
195 if (scale < minscale) {
196 minscale = scale;
197 *br = i;
198 *pbr = j;
199 }
200 break;
201 }
202 }
203
204 if (minscale == INT_MAX) {
205 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
206 speed_hz, clkrate);
207 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
208 *br = ARRAY_SIZE(brs) - 1;
209 }
210}
211
212static void ns_delay_scale(char *psc, char *sc, int delay_ns,
213 unsigned long clkrate)
214{
215 int pscale_tbl[4] = {1, 3, 5, 7};
216 int scale_needed, scale, minscale = INT_MAX;
217 int i, j;
218 u32 remainder;
219
220 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
221 &remainder);
222 if (remainder)
223 scale_needed++;
224
225 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
226 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
227 scale = pscale_tbl[i] * (2 << j);
228 if (scale >= scale_needed) {
229 if (scale < minscale) {
230 minscale = scale;
231 *psc = i;
232 *sc = j;
233 }
234 break;
235 }
236 }
237
238 if (minscale == INT_MAX) {
239 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
240 delay_ns, clkrate);
241 *psc = ARRAY_SIZE(pscale_tbl) - 1;
242 *sc = SPI_CTAR_SCALE_BITS;
243 }
244}
245
246static u32 dspi_data_to_pushr(struct fsl_dspi *dspi, int tx_word)
247{
248 u16 d16;
249
250 if (!(dspi->dataflags & TRAN_STATE_TX_VOID))
251 d16 = tx_word ? *(u16 *)dspi->tx : *(u8 *)dspi->tx;
252 else
253 d16 = dspi->void_write_data;
254
255 dspi->tx += tx_word + 1;
256 dspi->len -= tx_word + 1;
257
258 return SPI_PUSHR_TXDATA(d16) |
259 SPI_PUSHR_PCS(dspi->cs) |
260 SPI_PUSHR_CTAS(0) |
261 SPI_PUSHR_CONT;
262}
263
264static void dspi_data_from_popr(struct fsl_dspi *dspi, int rx_word)
265{
266 u16 d;
267 unsigned int val;
268
269 regmap_read(dspi->regmap, SPI_POPR, &val);
270 d = SPI_POPR_RXDATA(val);
271
272 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
273 rx_word ? (*(u16 *)dspi->rx = d) : (*(u8 *)dspi->rx = d);
274
275 dspi->rx += rx_word + 1;
276}
277
278static int dspi_eoq_write(struct fsl_dspi *dspi)
279{
280 int tx_count = 0;
281 int tx_word;
282 u32 dspi_pushr = 0;
283
284 tx_word = is_double_byte_mode(dspi);
285
286 while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
287
288
289
290
291 if (tx_word && (dspi->len == 1)) {
292 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
293 regmap_update_bits(dspi->regmap, SPI_CTAR(0),
294 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
295 tx_word = 0;
296 }
297
298 dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
299
300 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
301
302 dspi_pushr |= SPI_PUSHR_EOQ;
303 if ((dspi->cs_change) && (!dspi->len))
304 dspi_pushr &= ~SPI_PUSHR_CONT;
305 } else if (tx_word && (dspi->len == 1))
306 dspi_pushr |= SPI_PUSHR_EOQ;
307
308 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
309
310 tx_count++;
311 }
312
313 return tx_count * (tx_word + 1);
314}
315
316static int dspi_eoq_read(struct fsl_dspi *dspi)
317{
318 int rx_count = 0;
319 int rx_word = is_double_byte_mode(dspi);
320
321 while ((dspi->rx < dspi->rx_end)
322 && (rx_count < DSPI_FIFO_SIZE)) {
323 if (rx_word && (dspi->rx_end - dspi->rx) == 1)
324 rx_word = 0;
325
326 dspi_data_from_popr(dspi, rx_word);
327 rx_count++;
328 }
329
330 return rx_count;
331}
332
333static int dspi_tcfq_write(struct fsl_dspi *dspi)
334{
335 int tx_word;
336 u32 dspi_pushr = 0;
337
338 tx_word = is_double_byte_mode(dspi);
339
340 if (tx_word && (dspi->len == 1)) {
341 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
342 regmap_update_bits(dspi->regmap, SPI_CTAR(0),
343 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
344 tx_word = 0;
345 }
346
347 dspi_pushr = dspi_data_to_pushr(dspi, tx_word);
348
349 if ((dspi->cs_change) && (!dspi->len))
350 dspi_pushr &= ~SPI_PUSHR_CONT;
351
352 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
353
354 return tx_word + 1;
355}
356
357static void dspi_tcfq_read(struct fsl_dspi *dspi)
358{
359 int rx_word = is_double_byte_mode(dspi);
360
361 if (rx_word && (dspi->rx_end - dspi->rx) == 1)
362 rx_word = 0;
363
364 dspi_data_from_popr(dspi, rx_word);
365}
366
367static int dspi_transfer_one_message(struct spi_master *master,
368 struct spi_message *message)
369{
370 struct fsl_dspi *dspi = spi_master_get_devdata(master);
371 struct spi_device *spi = message->spi;
372 struct spi_transfer *transfer;
373 int status = 0;
374 enum dspi_trans_mode trans_mode;
375 u32 spi_tcr;
376
377 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
378 dspi->spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
379
380 message->actual_length = 0;
381
382 list_for_each_entry(transfer, &message->transfers, transfer_list) {
383 dspi->cur_transfer = transfer;
384 dspi->cur_msg = message;
385 dspi->cur_chip = spi_get_ctldata(spi);
386 dspi->cs = spi->chip_select;
387 dspi->cs_change = 0;
388 if (list_is_last(&dspi->cur_transfer->transfer_list,
389 &dspi->cur_msg->transfers) || transfer->cs_change)
390 dspi->cs_change = 1;
391 dspi->void_write_data = dspi->cur_chip->void_write_data;
392
393 dspi->dataflags = 0;
394 dspi->tx = (void *)transfer->tx_buf;
395 dspi->tx_end = dspi->tx + transfer->len;
396 dspi->rx = transfer->rx_buf;
397 dspi->rx_end = dspi->rx + transfer->len;
398 dspi->len = transfer->len;
399
400 if (!dspi->rx)
401 dspi->dataflags |= TRAN_STATE_RX_VOID;
402
403 if (!dspi->tx)
404 dspi->dataflags |= TRAN_STATE_TX_VOID;
405
406 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
407 regmap_update_bits(dspi->regmap, SPI_MCR,
408 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
409 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
410 regmap_write(dspi->regmap, SPI_CTAR(0),
411 dspi->cur_chip->ctar_val);
412
413 trans_mode = dspi->devtype_data->trans_mode;
414 switch (trans_mode) {
415 case DSPI_EOQ_MODE:
416 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
417 dspi_eoq_write(dspi);
418 break;
419 case DSPI_TCFQ_MODE:
420 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
421 dspi_tcfq_write(dspi);
422 break;
423 default:
424 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
425 trans_mode);
426 status = -EINVAL;
427 goto out;
428 }
429
430 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
431 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
432 dspi->waitflags = 0;
433
434 if (transfer->delay_usecs)
435 udelay(transfer->delay_usecs);
436 }
437
438out:
439 message->status = status;
440 spi_finalize_current_message(master);
441
442 return status;
443}
444
445static int dspi_setup(struct spi_device *spi)
446{
447 struct chip_data *chip;
448 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
449 u32 cs_sck_delay = 0, sck_cs_delay = 0;
450 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
451 unsigned char pasc = 0, asc = 0, fmsz = 0;
452 unsigned long clkrate;
453
454 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
455 fmsz = spi->bits_per_word - 1;
456 } else {
457 pr_err("Invalid wordsize\n");
458 return -ENODEV;
459 }
460
461
462 chip = spi_get_ctldata(spi);
463 if (chip == NULL) {
464 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
465 if (!chip)
466 return -ENOMEM;
467 }
468
469 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
470 &cs_sck_delay);
471
472 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
473 &sck_cs_delay);
474
475 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
476 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
477
478 chip->void_write_data = 0;
479
480 clkrate = clk_get_rate(dspi->clk);
481 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
482
483
484 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
485
486
487 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
488
489 chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
490 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
491 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
492 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
493 | SPI_CTAR_PCSSCK(pcssck)
494 | SPI_CTAR_CSSCK(cssck)
495 | SPI_CTAR_PASC(pasc)
496 | SPI_CTAR_ASC(asc)
497 | SPI_CTAR_PBR(pbr)
498 | SPI_CTAR_BR(br);
499
500 spi_set_ctldata(spi, chip);
501
502 return 0;
503}
504
505static void dspi_cleanup(struct spi_device *spi)
506{
507 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
508
509 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
510 spi->master->bus_num, spi->chip_select);
511
512 kfree(chip);
513}
514
515static irqreturn_t dspi_interrupt(int irq, void *dev_id)
516{
517 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
518 struct spi_message *msg = dspi->cur_msg;
519 enum dspi_trans_mode trans_mode;
520 u32 spi_sr, spi_tcr;
521 u32 spi_tcnt, tcnt_diff;
522 int tx_word;
523
524 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
525 regmap_write(dspi->regmap, SPI_SR, spi_sr);
526
527
528 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
529 tx_word = is_double_byte_mode(dspi);
530
531 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
532 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
533
534
535
536
537
538
539
540
541
542 tcnt_diff = ((spi_tcnt + SPI_TCR_TCNT_MAX) - dspi->spi_tcnt)
543 % SPI_TCR_TCNT_MAX;
544 tcnt_diff *= (tx_word + 1);
545 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
546 tcnt_diff--;
547
548 msg->actual_length += tcnt_diff;
549
550 dspi->spi_tcnt = spi_tcnt;
551
552 trans_mode = dspi->devtype_data->trans_mode;
553 switch (trans_mode) {
554 case DSPI_EOQ_MODE:
555 dspi_eoq_read(dspi);
556 break;
557 case DSPI_TCFQ_MODE:
558 dspi_tcfq_read(dspi);
559 break;
560 default:
561 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
562 trans_mode);
563 return IRQ_HANDLED;
564 }
565
566 if (!dspi->len) {
567 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) {
568 regmap_update_bits(dspi->regmap,
569 SPI_CTAR(0),
570 SPI_FRAME_BITS_MASK,
571 SPI_FRAME_BITS(16));
572 dspi->dataflags &= ~TRAN_STATE_WORD_ODD_NUM;
573 }
574
575 dspi->waitflags = 1;
576 wake_up_interruptible(&dspi->waitq);
577 } else {
578 switch (trans_mode) {
579 case DSPI_EOQ_MODE:
580 dspi_eoq_write(dspi);
581 break;
582 case DSPI_TCFQ_MODE:
583 dspi_tcfq_write(dspi);
584 break;
585 default:
586 dev_err(&dspi->pdev->dev,
587 "unsupported trans_mode %u\n",
588 trans_mode);
589 }
590 }
591 }
592
593 return IRQ_HANDLED;
594}
595
596static const struct of_device_id fsl_dspi_dt_ids[] = {
597 { .compatible = "fsl,vf610-dspi", .data = (void *)&vf610_data, },
598 { .compatible = "fsl,ls1021a-v1.0-dspi",
599 .data = (void *)&ls1021a_v1_data, },
600 { .compatible = "fsl,ls2085a-dspi", .data = (void *)&ls2085a_data, },
601 { }
602};
603MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
604
605#ifdef CONFIG_PM_SLEEP
606static int dspi_suspend(struct device *dev)
607{
608 struct spi_master *master = dev_get_drvdata(dev);
609 struct fsl_dspi *dspi = spi_master_get_devdata(master);
610
611 spi_master_suspend(master);
612 clk_disable_unprepare(dspi->clk);
613
614 pinctrl_pm_select_sleep_state(dev);
615
616 return 0;
617}
618
619static int dspi_resume(struct device *dev)
620{
621 struct spi_master *master = dev_get_drvdata(dev);
622 struct fsl_dspi *dspi = spi_master_get_devdata(master);
623
624 pinctrl_pm_select_default_state(dev);
625
626 clk_prepare_enable(dspi->clk);
627 spi_master_resume(master);
628
629 return 0;
630}
631#endif
632
633static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
634
635static const struct regmap_config dspi_regmap_config = {
636 .reg_bits = 32,
637 .val_bits = 32,
638 .reg_stride = 4,
639 .max_register = 0x88,
640};
641
642static int dspi_probe(struct platform_device *pdev)
643{
644 struct device_node *np = pdev->dev.of_node;
645 struct spi_master *master;
646 struct fsl_dspi *dspi;
647 struct resource *res;
648 void __iomem *base;
649 int ret = 0, cs_num, bus_num;
650 const struct of_device_id *of_id =
651 of_match_device(fsl_dspi_dt_ids, &pdev->dev);
652
653 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
654 if (!master)
655 return -ENOMEM;
656
657 dspi = spi_master_get_devdata(master);
658 dspi->pdev = pdev;
659 dspi->master = master;
660
661 master->transfer = NULL;
662 master->setup = dspi_setup;
663 master->transfer_one_message = dspi_transfer_one_message;
664 master->dev.of_node = pdev->dev.of_node;
665
666 master->cleanup = dspi_cleanup;
667 master->mode_bits = SPI_CPOL | SPI_CPHA;
668 master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
669 SPI_BPW_MASK(16);
670
671 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
672 if (ret < 0) {
673 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
674 goto out_master_put;
675 }
676 master->num_chipselect = cs_num;
677
678 ret = of_property_read_u32(np, "bus-num", &bus_num);
679 if (ret < 0) {
680 dev_err(&pdev->dev, "can't get bus-num\n");
681 goto out_master_put;
682 }
683 master->bus_num = bus_num;
684
685 dspi->devtype_data = (struct fsl_dspi_devtype_data *)of_id->data;
686 if (!dspi->devtype_data) {
687 dev_err(&pdev->dev, "can't get devtype_data\n");
688 ret = -EFAULT;
689 goto out_master_put;
690 }
691
692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
693 base = devm_ioremap_resource(&pdev->dev, res);
694 if (IS_ERR(base)) {
695 ret = PTR_ERR(base);
696 goto out_master_put;
697 }
698
699 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
700 &dspi_regmap_config);
701 if (IS_ERR(dspi->regmap)) {
702 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
703 PTR_ERR(dspi->regmap));
704 return PTR_ERR(dspi->regmap);
705 }
706
707 dspi->irq = platform_get_irq(pdev, 0);
708 if (dspi->irq < 0) {
709 dev_err(&pdev->dev, "can't get platform irq\n");
710 ret = dspi->irq;
711 goto out_master_put;
712 }
713
714 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
715 pdev->name, dspi);
716 if (ret < 0) {
717 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
718 goto out_master_put;
719 }
720
721 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
722 if (IS_ERR(dspi->clk)) {
723 ret = PTR_ERR(dspi->clk);
724 dev_err(&pdev->dev, "unable to get clock\n");
725 goto out_master_put;
726 }
727 clk_prepare_enable(dspi->clk);
728
729 init_waitqueue_head(&dspi->waitq);
730 platform_set_drvdata(pdev, master);
731
732 ret = spi_register_master(master);
733 if (ret != 0) {
734 dev_err(&pdev->dev, "Problem registering DSPI master\n");
735 goto out_clk_put;
736 }
737
738 return ret;
739
740out_clk_put:
741 clk_disable_unprepare(dspi->clk);
742out_master_put:
743 spi_master_put(master);
744
745 return ret;
746}
747
748static int dspi_remove(struct platform_device *pdev)
749{
750 struct spi_master *master = platform_get_drvdata(pdev);
751 struct fsl_dspi *dspi = spi_master_get_devdata(master);
752
753
754 clk_disable_unprepare(dspi->clk);
755 spi_unregister_master(dspi->master);
756 spi_master_put(dspi->master);
757
758 return 0;
759}
760
761static struct platform_driver fsl_dspi_driver = {
762 .driver.name = DRIVER_NAME,
763 .driver.of_match_table = fsl_dspi_dt_ids,
764 .driver.owner = THIS_MODULE,
765 .driver.pm = &dspi_pm,
766 .probe = dspi_probe,
767 .remove = dspi_remove,
768};
769module_platform_driver(fsl_dspi_driver);
770
771MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
772MODULE_LICENSE("GPL");
773MODULE_ALIAS("platform:" DRIVER_NAME);
774
