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16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21#include <linux/dma-mapping.h>
22#include <linux/dmaengine.h>
23#include <linux/platform_device.h>
24#include <linux/pm_runtime.h>
25#include <linux/spi/spi.h>
26#include <linux/gpio.h>
27#include <linux/of.h>
28#include <linux/of_gpio.h>
29
30#include <linux/platform_data/spi-s3c64xx.h>
31
32#define MAX_SPI_PORTS 6
33#define S3C64XX_SPI_QUIRK_POLL (1 << 0)
34#define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
35#define AUTOSUSPEND_TIMEOUT 2000
36
37
38
39#define S3C64XX_SPI_CH_CFG 0x00
40#define S3C64XX_SPI_CLK_CFG 0x04
41#define S3C64XX_SPI_MODE_CFG 0x08
42#define S3C64XX_SPI_SLAVE_SEL 0x0C
43#define S3C64XX_SPI_INT_EN 0x10
44#define S3C64XX_SPI_STATUS 0x14
45#define S3C64XX_SPI_TX_DATA 0x18
46#define S3C64XX_SPI_RX_DATA 0x1C
47#define S3C64XX_SPI_PACKET_CNT 0x20
48#define S3C64XX_SPI_PENDING_CLR 0x24
49#define S3C64XX_SPI_SWAP_CFG 0x28
50#define S3C64XX_SPI_FB_CLK 0x2C
51
52#define S3C64XX_SPI_CH_HS_EN (1<<6)
53#define S3C64XX_SPI_CH_SW_RST (1<<5)
54#define S3C64XX_SPI_CH_SLAVE (1<<4)
55#define S3C64XX_SPI_CPOL_L (1<<3)
56#define S3C64XX_SPI_CPHA_B (1<<2)
57#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
58#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
59
60#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
61#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
62#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
63#define S3C64XX_SPI_PSR_MASK 0xff
64
65#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
66#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
67#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
68#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
69#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
70#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
71#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
72#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
73#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
74#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
75#define S3C64XX_SPI_MODE_4BURST (1<<0)
76
77#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
78#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
79#define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4)
80
81#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
88
89#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
95
96#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
97
98#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
103
104#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
112
113#define S3C64XX_SPI_FBCLK_MSK (3<<0)
114
115#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
116#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
117 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
118#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
119#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
120 FIFO_LVL_MASK(i))
121
122#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
123#define S3C64XX_SPI_TRAILCNT_OFF 19
124
125#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
126
127#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
128#define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
129
130#define RXBUSY (1<<2)
131#define TXBUSY (1<<3)
132
133struct s3c64xx_spi_dma_data {
134 struct dma_chan *ch;
135 enum dma_transfer_direction direction;
136};
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151
152struct s3c64xx_spi_port_config {
153 int fifo_lvl_mask[MAX_SPI_PORTS];
154 int rx_lvl_offset;
155 int tx_st_done;
156 int quirks;
157 bool high_speed;
158 bool clk_from_cmu;
159};
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179
180struct s3c64xx_spi_driver_data {
181 void __iomem *regs;
182 struct clk *clk;
183 struct clk *src_clk;
184 struct platform_device *pdev;
185 struct spi_master *master;
186 struct s3c64xx_spi_info *cntrlr_info;
187 struct spi_device *tgl_spi;
188 spinlock_t lock;
189 unsigned long sfr_start;
190 struct completion xfer_completion;
191 unsigned state;
192 unsigned cur_mode, cur_bpw;
193 unsigned cur_speed;
194 struct s3c64xx_spi_dma_data rx_dma;
195 struct s3c64xx_spi_dma_data tx_dma;
196 struct s3c64xx_spi_port_config *port_conf;
197 unsigned int port_id;
198};
199
200static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
201{
202 void __iomem *regs = sdd->regs;
203 unsigned long loops;
204 u32 val;
205
206 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
207
208 val = readl(regs + S3C64XX_SPI_CH_CFG);
209 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
210 writel(val, regs + S3C64XX_SPI_CH_CFG);
211
212 val = readl(regs + S3C64XX_SPI_CH_CFG);
213 val |= S3C64XX_SPI_CH_SW_RST;
214 val &= ~S3C64XX_SPI_CH_HS_EN;
215 writel(val, regs + S3C64XX_SPI_CH_CFG);
216
217
218 loops = msecs_to_loops(1);
219 do {
220 val = readl(regs + S3C64XX_SPI_STATUS);
221 } while (TX_FIFO_LVL(val, sdd) && loops--);
222
223 if (loops == 0)
224 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
225
226
227 loops = msecs_to_loops(1);
228 do {
229 val = readl(regs + S3C64XX_SPI_STATUS);
230 if (RX_FIFO_LVL(val, sdd))
231 readl(regs + S3C64XX_SPI_RX_DATA);
232 else
233 break;
234 } while (loops--);
235
236 if (loops == 0)
237 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
238
239 val = readl(regs + S3C64XX_SPI_CH_CFG);
240 val &= ~S3C64XX_SPI_CH_SW_RST;
241 writel(val, regs + S3C64XX_SPI_CH_CFG);
242
243 val = readl(regs + S3C64XX_SPI_MODE_CFG);
244 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
245 writel(val, regs + S3C64XX_SPI_MODE_CFG);
246}
247
248static void s3c64xx_spi_dmacb(void *data)
249{
250 struct s3c64xx_spi_driver_data *sdd;
251 struct s3c64xx_spi_dma_data *dma = data;
252 unsigned long flags;
253
254 if (dma->direction == DMA_DEV_TO_MEM)
255 sdd = container_of(data,
256 struct s3c64xx_spi_driver_data, rx_dma);
257 else
258 sdd = container_of(data,
259 struct s3c64xx_spi_driver_data, tx_dma);
260
261 spin_lock_irqsave(&sdd->lock, flags);
262
263 if (dma->direction == DMA_DEV_TO_MEM) {
264 sdd->state &= ~RXBUSY;
265 if (!(sdd->state & TXBUSY))
266 complete(&sdd->xfer_completion);
267 } else {
268 sdd->state &= ~TXBUSY;
269 if (!(sdd->state & RXBUSY))
270 complete(&sdd->xfer_completion);
271 }
272
273 spin_unlock_irqrestore(&sdd->lock, flags);
274}
275
276static void prepare_dma(struct s3c64xx_spi_dma_data *dma,
277 struct sg_table *sgt)
278{
279 struct s3c64xx_spi_driver_data *sdd;
280 struct dma_slave_config config;
281 struct dma_async_tx_descriptor *desc;
282
283 memset(&config, 0, sizeof(config));
284
285 if (dma->direction == DMA_DEV_TO_MEM) {
286 sdd = container_of((void *)dma,
287 struct s3c64xx_spi_driver_data, rx_dma);
288 config.direction = dma->direction;
289 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
290 config.src_addr_width = sdd->cur_bpw / 8;
291 config.src_maxburst = 1;
292 dmaengine_slave_config(dma->ch, &config);
293 } else {
294 sdd = container_of((void *)dma,
295 struct s3c64xx_spi_driver_data, tx_dma);
296 config.direction = dma->direction;
297 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
298 config.dst_addr_width = sdd->cur_bpw / 8;
299 config.dst_maxburst = 1;
300 dmaengine_slave_config(dma->ch, &config);
301 }
302
303 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
304 dma->direction, DMA_PREP_INTERRUPT);
305
306 desc->callback = s3c64xx_spi_dmacb;
307 desc->callback_param = dma;
308
309 dmaengine_submit(desc);
310 dma_async_issue_pending(dma->ch);
311}
312
313static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
314{
315 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
316 dma_filter_fn filter = sdd->cntrlr_info->filter;
317 struct device *dev = &sdd->pdev->dev;
318 dma_cap_mask_t mask;
319 int ret;
320
321 if (!is_polling(sdd)) {
322 dma_cap_zero(mask);
323 dma_cap_set(DMA_SLAVE, mask);
324
325
326 sdd->rx_dma.ch = dma_request_slave_channel_compat(mask, filter,
327 sdd->cntrlr_info->dma_rx, dev, "rx");
328 if (!sdd->rx_dma.ch) {
329 dev_err(dev, "Failed to get RX DMA channel\n");
330 ret = -EBUSY;
331 goto out;
332 }
333 spi->dma_rx = sdd->rx_dma.ch;
334
335 sdd->tx_dma.ch = dma_request_slave_channel_compat(mask, filter,
336 sdd->cntrlr_info->dma_tx, dev, "tx");
337 if (!sdd->tx_dma.ch) {
338 dev_err(dev, "Failed to get TX DMA channel\n");
339 ret = -EBUSY;
340 goto out_rx;
341 }
342 spi->dma_tx = sdd->tx_dma.ch;
343 }
344
345 return 0;
346
347out_rx:
348 dma_release_channel(sdd->rx_dma.ch);
349out:
350 return ret;
351}
352
353static int s3c64xx_spi_unprepare_transfer(struct spi_master *spi)
354{
355 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
356
357
358 if (!is_polling(sdd)) {
359 dma_release_channel(sdd->rx_dma.ch);
360 dma_release_channel(sdd->tx_dma.ch);
361 }
362
363 return 0;
364}
365
366static bool s3c64xx_spi_can_dma(struct spi_master *master,
367 struct spi_device *spi,
368 struct spi_transfer *xfer)
369{
370 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
371
372 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
373}
374
375static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
376 struct spi_device *spi,
377 struct spi_transfer *xfer, int dma_mode)
378{
379 void __iomem *regs = sdd->regs;
380 u32 modecfg, chcfg;
381
382 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
383 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
384
385 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
386 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
387
388 if (dma_mode) {
389 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
390 } else {
391
392
393
394
395 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
396 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
397 | S3C64XX_SPI_PACKET_CNT_EN,
398 regs + S3C64XX_SPI_PACKET_CNT);
399 }
400
401 if (xfer->tx_buf != NULL) {
402 sdd->state |= TXBUSY;
403 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
404 if (dma_mode) {
405 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
406 prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
407 } else {
408 switch (sdd->cur_bpw) {
409 case 32:
410 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
411 xfer->tx_buf, xfer->len / 4);
412 break;
413 case 16:
414 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
415 xfer->tx_buf, xfer->len / 2);
416 break;
417 default:
418 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
419 xfer->tx_buf, xfer->len);
420 break;
421 }
422 }
423 }
424
425 if (xfer->rx_buf != NULL) {
426 sdd->state |= RXBUSY;
427
428 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
429 && !(sdd->cur_mode & SPI_CPHA))
430 chcfg |= S3C64XX_SPI_CH_HS_EN;
431
432 if (dma_mode) {
433 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
434 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
435 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
436 | S3C64XX_SPI_PACKET_CNT_EN,
437 regs + S3C64XX_SPI_PACKET_CNT);
438 prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
439 }
440 }
441
442 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
443 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
444}
445
446static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
447 int timeout_ms)
448{
449 void __iomem *regs = sdd->regs;
450 unsigned long val = 1;
451 u32 status;
452
453
454 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
455
456 if (timeout_ms)
457 val = msecs_to_loops(timeout_ms);
458
459 do {
460 status = readl(regs + S3C64XX_SPI_STATUS);
461 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
462
463
464 return RX_FIFO_LVL(status, sdd);
465}
466
467static int wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
468 struct spi_transfer *xfer)
469{
470 void __iomem *regs = sdd->regs;
471 unsigned long val;
472 u32 status;
473 int ms;
474
475
476 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
477 ms += 10;
478
479 val = msecs_to_jiffies(ms) + 10;
480 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
481
482
483
484
485
486
487
488
489
490
491 if (val && !xfer->rx_buf) {
492 val = msecs_to_loops(10);
493 status = readl(regs + S3C64XX_SPI_STATUS);
494 while ((TX_FIFO_LVL(status, sdd)
495 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
496 && --val) {
497 cpu_relax();
498 status = readl(regs + S3C64XX_SPI_STATUS);
499 }
500
501 }
502
503
504 if (!val)
505 return -EIO;
506
507 return 0;
508}
509
510static int wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
511 struct spi_transfer *xfer)
512{
513 void __iomem *regs = sdd->regs;
514 unsigned long val;
515 u32 status;
516 int loops;
517 u32 cpy_len;
518 u8 *buf;
519 int ms;
520
521
522 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
523 ms += 10;
524
525 val = msecs_to_loops(ms);
526 do {
527 status = readl(regs + S3C64XX_SPI_STATUS);
528 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
529
530
531
532 if (!xfer->rx_buf) {
533 sdd->state &= ~TXBUSY;
534 return 0;
535 }
536
537
538
539
540
541
542
543
544
545 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
546 buf = xfer->rx_buf;
547 do {
548
549 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
550 (loops ? ms : 0));
551
552 switch (sdd->cur_bpw) {
553 case 32:
554 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
555 buf, cpy_len / 4);
556 break;
557 case 16:
558 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
559 buf, cpy_len / 2);
560 break;
561 default:
562 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
563 buf, cpy_len);
564 break;
565 }
566
567 buf = buf + cpy_len;
568 } while (loops--);
569 sdd->state &= ~RXBUSY;
570
571 return 0;
572}
573
574static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
575{
576 void __iomem *regs = sdd->regs;
577 u32 val;
578
579
580 if (sdd->port_conf->clk_from_cmu) {
581 clk_disable_unprepare(sdd->src_clk);
582 } else {
583 val = readl(regs + S3C64XX_SPI_CLK_CFG);
584 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
585 writel(val, regs + S3C64XX_SPI_CLK_CFG);
586 }
587
588
589 val = readl(regs + S3C64XX_SPI_CH_CFG);
590 val &= ~(S3C64XX_SPI_CH_SLAVE |
591 S3C64XX_SPI_CPOL_L |
592 S3C64XX_SPI_CPHA_B);
593
594 if (sdd->cur_mode & SPI_CPOL)
595 val |= S3C64XX_SPI_CPOL_L;
596
597 if (sdd->cur_mode & SPI_CPHA)
598 val |= S3C64XX_SPI_CPHA_B;
599
600 writel(val, regs + S3C64XX_SPI_CH_CFG);
601
602
603 val = readl(regs + S3C64XX_SPI_MODE_CFG);
604 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
605 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
606
607 switch (sdd->cur_bpw) {
608 case 32:
609 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
610 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
611 break;
612 case 16:
613 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
614 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
615 break;
616 default:
617 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
618 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
619 break;
620 }
621
622 writel(val, regs + S3C64XX_SPI_MODE_CFG);
623
624 if (sdd->port_conf->clk_from_cmu) {
625
626
627 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
628
629 clk_prepare_enable(sdd->src_clk);
630 } else {
631
632 val = readl(regs + S3C64XX_SPI_CLK_CFG);
633 val &= ~S3C64XX_SPI_PSR_MASK;
634 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
635 & S3C64XX_SPI_PSR_MASK);
636 writel(val, regs + S3C64XX_SPI_CLK_CFG);
637
638
639 val = readl(regs + S3C64XX_SPI_CLK_CFG);
640 val |= S3C64XX_SPI_ENCLK_ENABLE;
641 writel(val, regs + S3C64XX_SPI_CLK_CFG);
642 }
643}
644
645#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
646
647static int s3c64xx_spi_prepare_message(struct spi_master *master,
648 struct spi_message *msg)
649{
650 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
651 struct spi_device *spi = msg->spi;
652 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
653
654
655 if (sdd->cur_speed != spi->max_speed_hz
656 || sdd->cur_mode != spi->mode
657 || sdd->cur_bpw != spi->bits_per_word) {
658 sdd->cur_bpw = spi->bits_per_word;
659 sdd->cur_speed = spi->max_speed_hz;
660 sdd->cur_mode = spi->mode;
661 s3c64xx_spi_config(sdd);
662 }
663
664
665 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
666
667 return 0;
668}
669
670static int s3c64xx_spi_transfer_one(struct spi_master *master,
671 struct spi_device *spi,
672 struct spi_transfer *xfer)
673{
674 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
675 int status;
676 u32 speed;
677 u8 bpw;
678 unsigned long flags;
679 int use_dma;
680
681 reinit_completion(&sdd->xfer_completion);
682
683
684 bpw = xfer->bits_per_word;
685 speed = xfer->speed_hz;
686
687 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
688 sdd->cur_bpw = bpw;
689 sdd->cur_speed = speed;
690 s3c64xx_spi_config(sdd);
691 }
692
693
694 use_dma = 0;
695 if (!is_polling(sdd) &&
696 (sdd->rx_dma.ch && sdd->tx_dma.ch &&
697 (xfer->len > ((FIFO_LVL_MASK(sdd) >> 1) + 1))))
698 use_dma = 1;
699
700 spin_lock_irqsave(&sdd->lock, flags);
701
702
703 sdd->state &= ~RXBUSY;
704 sdd->state &= ~TXBUSY;
705
706 enable_datapath(sdd, spi, xfer, use_dma);
707
708
709 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
710 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
711 else
712 writel(readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL)
713 | S3C64XX_SPI_SLAVE_AUTO | S3C64XX_SPI_SLAVE_NSC_CNT_2,
714 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
715
716 spin_unlock_irqrestore(&sdd->lock, flags);
717
718 if (use_dma)
719 status = wait_for_dma(sdd, xfer);
720 else
721 status = wait_for_pio(sdd, xfer);
722
723 if (status) {
724 dev_err(&spi->dev, "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
725 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
726 (sdd->state & RXBUSY) ? 'f' : 'p',
727 (sdd->state & TXBUSY) ? 'f' : 'p',
728 xfer->len);
729
730 if (use_dma) {
731 if (xfer->tx_buf != NULL
732 && (sdd->state & TXBUSY))
733 dmaengine_terminate_all(sdd->tx_dma.ch);
734 if (xfer->rx_buf != NULL
735 && (sdd->state & RXBUSY))
736 dmaengine_terminate_all(sdd->rx_dma.ch);
737 }
738 } else {
739 flush_fifo(sdd);
740 }
741
742 return status;
743}
744
745static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
746 struct spi_device *spi)
747{
748 struct s3c64xx_spi_csinfo *cs;
749 struct device_node *slave_np, *data_np = NULL;
750 u32 fb_delay = 0;
751
752 slave_np = spi->dev.of_node;
753 if (!slave_np) {
754 dev_err(&spi->dev, "device node not found\n");
755 return ERR_PTR(-EINVAL);
756 }
757
758 data_np = of_get_child_by_name(slave_np, "controller-data");
759 if (!data_np) {
760 dev_err(&spi->dev, "child node 'controller-data' not found\n");
761 return ERR_PTR(-EINVAL);
762 }
763
764 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
765 if (!cs) {
766 of_node_put(data_np);
767 return ERR_PTR(-ENOMEM);
768 }
769
770 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
771 cs->fb_delay = fb_delay;
772 of_node_put(data_np);
773 return cs;
774}
775
776
777
778
779
780
781
782static int s3c64xx_spi_setup(struct spi_device *spi)
783{
784 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
785 struct s3c64xx_spi_driver_data *sdd;
786 struct s3c64xx_spi_info *sci;
787 int err;
788
789 sdd = spi_master_get_devdata(spi->master);
790 if (spi->dev.of_node) {
791 cs = s3c64xx_get_slave_ctrldata(spi);
792 spi->controller_data = cs;
793 } else if (cs) {
794
795
796
797
798
799 spi->cs_gpio = cs->line;
800 }
801
802 if (IS_ERR_OR_NULL(cs)) {
803 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
804 return -ENODEV;
805 }
806
807 if (!spi_get_ctldata(spi)) {
808 if (gpio_is_valid(spi->cs_gpio)) {
809 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
810 dev_name(&spi->dev));
811 if (err) {
812 dev_err(&spi->dev,
813 "Failed to get /CS gpio [%d]: %d\n",
814 spi->cs_gpio, err);
815 goto err_gpio_req;
816 }
817 }
818
819 spi_set_ctldata(spi, cs);
820 }
821
822 sci = sdd->cntrlr_info;
823
824 pm_runtime_get_sync(&sdd->pdev->dev);
825
826
827 if (!sdd->port_conf->clk_from_cmu) {
828 u32 psr, speed;
829
830
831 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
832
833 if (spi->max_speed_hz > speed)
834 spi->max_speed_hz = speed;
835
836 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
837 psr &= S3C64XX_SPI_PSR_MASK;
838 if (psr == S3C64XX_SPI_PSR_MASK)
839 psr--;
840
841 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
842 if (spi->max_speed_hz < speed) {
843 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
844 psr++;
845 } else {
846 err = -EINVAL;
847 goto setup_exit;
848 }
849 }
850
851 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
852 if (spi->max_speed_hz >= speed) {
853 spi->max_speed_hz = speed;
854 } else {
855 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
856 spi->max_speed_hz);
857 err = -EINVAL;
858 goto setup_exit;
859 }
860 }
861
862 pm_runtime_mark_last_busy(&sdd->pdev->dev);
863 pm_runtime_put_autosuspend(&sdd->pdev->dev);
864 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
865 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
866 return 0;
867
868setup_exit:
869 pm_runtime_mark_last_busy(&sdd->pdev->dev);
870 pm_runtime_put_autosuspend(&sdd->pdev->dev);
871
872 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
873 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
874
875 if (gpio_is_valid(spi->cs_gpio))
876 gpio_free(spi->cs_gpio);
877 spi_set_ctldata(spi, NULL);
878
879err_gpio_req:
880 if (spi->dev.of_node)
881 kfree(cs);
882
883 return err;
884}
885
886static void s3c64xx_spi_cleanup(struct spi_device *spi)
887{
888 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
889
890 if (gpio_is_valid(spi->cs_gpio)) {
891 gpio_free(spi->cs_gpio);
892 if (spi->dev.of_node)
893 kfree(cs);
894 else {
895
896
897
898
899
900 spi->cs_gpio = -ENOENT;
901 }
902 }
903
904 spi_set_ctldata(spi, NULL);
905}
906
907static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
908{
909 struct s3c64xx_spi_driver_data *sdd = data;
910 struct spi_master *spi = sdd->master;
911 unsigned int val, clr = 0;
912
913 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
914
915 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
916 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
917 dev_err(&spi->dev, "RX overrun\n");
918 }
919 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
920 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
921 dev_err(&spi->dev, "RX underrun\n");
922 }
923 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
924 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
925 dev_err(&spi->dev, "TX overrun\n");
926 }
927 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
928 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
929 dev_err(&spi->dev, "TX underrun\n");
930 }
931
932
933 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
934 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
935
936 return IRQ_HANDLED;
937}
938
939static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
940{
941 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
942 void __iomem *regs = sdd->regs;
943 unsigned int val;
944
945 sdd->cur_speed = 0;
946
947 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
948 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
949
950
951 writel(0, regs + S3C64XX_SPI_INT_EN);
952
953 if (!sdd->port_conf->clk_from_cmu)
954 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
955 regs + S3C64XX_SPI_CLK_CFG);
956 writel(0, regs + S3C64XX_SPI_MODE_CFG);
957 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
958
959
960 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
961 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
962 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
963 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
964 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
965 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
966
967 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
968
969 val = readl(regs + S3C64XX_SPI_MODE_CFG);
970 val &= ~S3C64XX_SPI_MODE_4BURST;
971 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
972 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
973 writel(val, regs + S3C64XX_SPI_MODE_CFG);
974
975 flush_fifo(sdd);
976}
977
978#ifdef CONFIG_OF
979static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
980{
981 struct s3c64xx_spi_info *sci;
982 u32 temp;
983
984 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
985 if (!sci)
986 return ERR_PTR(-ENOMEM);
987
988 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
989 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
990 sci->src_clk_nr = 0;
991 } else {
992 sci->src_clk_nr = temp;
993 }
994
995 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
996 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
997 sci->num_cs = 1;
998 } else {
999 sci->num_cs = temp;
1000 }
1001
1002 return sci;
1003}
1004#else
1005static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1006{
1007 return dev_get_platdata(dev);
1008}
1009#endif
1010
1011static const struct of_device_id s3c64xx_spi_dt_match[];
1012
1013static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1014 struct platform_device *pdev)
1015{
1016#ifdef CONFIG_OF
1017 if (pdev->dev.of_node) {
1018 const struct of_device_id *match;
1019 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1020 return (struct s3c64xx_spi_port_config *)match->data;
1021 }
1022#endif
1023 return (struct s3c64xx_spi_port_config *)
1024 platform_get_device_id(pdev)->driver_data;
1025}
1026
1027static int s3c64xx_spi_probe(struct platform_device *pdev)
1028{
1029 struct resource *mem_res;
1030 struct s3c64xx_spi_driver_data *sdd;
1031 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1032 struct spi_master *master;
1033 int ret, irq;
1034 char clk_name[16];
1035
1036 if (!sci && pdev->dev.of_node) {
1037 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1038 if (IS_ERR(sci))
1039 return PTR_ERR(sci);
1040 }
1041
1042 if (!sci) {
1043 dev_err(&pdev->dev, "platform_data missing!\n");
1044 return -ENODEV;
1045 }
1046
1047 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1048 if (mem_res == NULL) {
1049 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1050 return -ENXIO;
1051 }
1052
1053 irq = platform_get_irq(pdev, 0);
1054 if (irq < 0) {
1055 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1056 return irq;
1057 }
1058
1059 master = spi_alloc_master(&pdev->dev,
1060 sizeof(struct s3c64xx_spi_driver_data));
1061 if (master == NULL) {
1062 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1063 return -ENOMEM;
1064 }
1065
1066 platform_set_drvdata(pdev, master);
1067
1068 sdd = spi_master_get_devdata(master);
1069 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1070 sdd->master = master;
1071 sdd->cntrlr_info = sci;
1072 sdd->pdev = pdev;
1073 sdd->sfr_start = mem_res->start;
1074 if (pdev->dev.of_node) {
1075 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1076 if (ret < 0) {
1077 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1078 ret);
1079 goto err0;
1080 }
1081 sdd->port_id = ret;
1082 } else {
1083 sdd->port_id = pdev->id;
1084 }
1085
1086 sdd->cur_bpw = 8;
1087
1088 if (!sdd->pdev->dev.of_node && (!sci->dma_tx || !sci->dma_rx)) {
1089 dev_warn(&pdev->dev, "Unable to get SPI tx/rx DMA data. Switching to poll mode\n");
1090 sdd->port_conf->quirks = S3C64XX_SPI_QUIRK_POLL;
1091 }
1092
1093 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1094 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1095
1096 master->dev.of_node = pdev->dev.of_node;
1097 master->bus_num = sdd->port_id;
1098 master->setup = s3c64xx_spi_setup;
1099 master->cleanup = s3c64xx_spi_cleanup;
1100 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1101 master->prepare_message = s3c64xx_spi_prepare_message;
1102 master->transfer_one = s3c64xx_spi_transfer_one;
1103 master->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer;
1104 master->num_chipselect = sci->num_cs;
1105 master->dma_alignment = 8;
1106 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1107 SPI_BPW_MASK(8);
1108
1109 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1110 master->auto_runtime_pm = true;
1111 if (!is_polling(sdd))
1112 master->can_dma = s3c64xx_spi_can_dma;
1113
1114 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1115 if (IS_ERR(sdd->regs)) {
1116 ret = PTR_ERR(sdd->regs);
1117 goto err0;
1118 }
1119
1120 if (sci->cfg_gpio && sci->cfg_gpio()) {
1121 dev_err(&pdev->dev, "Unable to config gpio\n");
1122 ret = -EBUSY;
1123 goto err0;
1124 }
1125
1126
1127 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1128 if (IS_ERR(sdd->clk)) {
1129 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1130 ret = PTR_ERR(sdd->clk);
1131 goto err0;
1132 }
1133
1134 if (clk_prepare_enable(sdd->clk)) {
1135 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1136 ret = -EBUSY;
1137 goto err0;
1138 }
1139
1140 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1141 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1142 if (IS_ERR(sdd->src_clk)) {
1143 dev_err(&pdev->dev,
1144 "Unable to acquire clock '%s'\n", clk_name);
1145 ret = PTR_ERR(sdd->src_clk);
1146 goto err2;
1147 }
1148
1149 if (clk_prepare_enable(sdd->src_clk)) {
1150 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1151 ret = -EBUSY;
1152 goto err2;
1153 }
1154
1155 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1156 pm_runtime_use_autosuspend(&pdev->dev);
1157 pm_runtime_set_active(&pdev->dev);
1158 pm_runtime_enable(&pdev->dev);
1159 pm_runtime_get_sync(&pdev->dev);
1160
1161
1162 s3c64xx_spi_hwinit(sdd, sdd->port_id);
1163
1164 spin_lock_init(&sdd->lock);
1165 init_completion(&sdd->xfer_completion);
1166
1167 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1168 "spi-s3c64xx", sdd);
1169 if (ret != 0) {
1170 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1171 irq, ret);
1172 goto err3;
1173 }
1174
1175 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1176 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1177 sdd->regs + S3C64XX_SPI_INT_EN);
1178
1179 ret = devm_spi_register_master(&pdev->dev, master);
1180 if (ret != 0) {
1181 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1182 goto err3;
1183 }
1184
1185 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1186 sdd->port_id, master->num_chipselect);
1187 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\tDMA=[Rx-%p, Tx-%p]\n",
1188 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1,
1189 sci->dma_rx, sci->dma_tx);
1190
1191 pm_runtime_mark_last_busy(&pdev->dev);
1192 pm_runtime_put_autosuspend(&pdev->dev);
1193
1194 return 0;
1195
1196err3:
1197 pm_runtime_put_noidle(&pdev->dev);
1198 pm_runtime_disable(&pdev->dev);
1199 pm_runtime_set_suspended(&pdev->dev);
1200
1201 clk_disable_unprepare(sdd->src_clk);
1202err2:
1203 clk_disable_unprepare(sdd->clk);
1204err0:
1205 spi_master_put(master);
1206
1207 return ret;
1208}
1209
1210static int s3c64xx_spi_remove(struct platform_device *pdev)
1211{
1212 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1213 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1214
1215 pm_runtime_get_sync(&pdev->dev);
1216
1217 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1218
1219 clk_disable_unprepare(sdd->src_clk);
1220
1221 clk_disable_unprepare(sdd->clk);
1222
1223 pm_runtime_put_noidle(&pdev->dev);
1224 pm_runtime_disable(&pdev->dev);
1225 pm_runtime_set_suspended(&pdev->dev);
1226
1227 return 0;
1228}
1229
1230#ifdef CONFIG_PM_SLEEP
1231static int s3c64xx_spi_suspend(struct device *dev)
1232{
1233 struct spi_master *master = dev_get_drvdata(dev);
1234 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1235
1236 int ret = spi_master_suspend(master);
1237 if (ret)
1238 return ret;
1239
1240 ret = pm_runtime_force_suspend(dev);
1241 if (ret < 0)
1242 return ret;
1243
1244 sdd->cur_speed = 0;
1245
1246 return 0;
1247}
1248
1249static int s3c64xx_spi_resume(struct device *dev)
1250{
1251 struct spi_master *master = dev_get_drvdata(dev);
1252 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1253 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1254 int ret;
1255
1256 if (sci->cfg_gpio)
1257 sci->cfg_gpio();
1258
1259 ret = pm_runtime_force_resume(dev);
1260 if (ret < 0)
1261 return ret;
1262
1263 s3c64xx_spi_hwinit(sdd, sdd->port_id);
1264
1265 return spi_master_resume(master);
1266}
1267#endif
1268
1269#ifdef CONFIG_PM
1270static int s3c64xx_spi_runtime_suspend(struct device *dev)
1271{
1272 struct spi_master *master = dev_get_drvdata(dev);
1273 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1274
1275 clk_disable_unprepare(sdd->clk);
1276 clk_disable_unprepare(sdd->src_clk);
1277
1278 return 0;
1279}
1280
1281static int s3c64xx_spi_runtime_resume(struct device *dev)
1282{
1283 struct spi_master *master = dev_get_drvdata(dev);
1284 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1285 int ret;
1286
1287 ret = clk_prepare_enable(sdd->src_clk);
1288 if (ret != 0)
1289 return ret;
1290
1291 ret = clk_prepare_enable(sdd->clk);
1292 if (ret != 0) {
1293 clk_disable_unprepare(sdd->src_clk);
1294 return ret;
1295 }
1296
1297 return 0;
1298}
1299#endif
1300
1301static const struct dev_pm_ops s3c64xx_spi_pm = {
1302 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1303 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1304 s3c64xx_spi_runtime_resume, NULL)
1305};
1306
1307static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1308 .fifo_lvl_mask = { 0x7f },
1309 .rx_lvl_offset = 13,
1310 .tx_st_done = 21,
1311 .high_speed = true,
1312};
1313
1314static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1315 .fifo_lvl_mask = { 0x7f, 0x7F },
1316 .rx_lvl_offset = 13,
1317 .tx_st_done = 21,
1318};
1319
1320static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1321 .fifo_lvl_mask = { 0x1ff, 0x7F },
1322 .rx_lvl_offset = 15,
1323 .tx_st_done = 25,
1324 .high_speed = true,
1325};
1326
1327static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1328 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1329 .rx_lvl_offset = 15,
1330 .tx_st_done = 25,
1331 .high_speed = true,
1332 .clk_from_cmu = true,
1333};
1334
1335static struct s3c64xx_spi_port_config exynos5440_spi_port_config = {
1336 .fifo_lvl_mask = { 0x1ff },
1337 .rx_lvl_offset = 15,
1338 .tx_st_done = 25,
1339 .high_speed = true,
1340 .clk_from_cmu = true,
1341 .quirks = S3C64XX_SPI_QUIRK_POLL,
1342};
1343
1344static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1345 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1346 .rx_lvl_offset = 15,
1347 .tx_st_done = 25,
1348 .high_speed = true,
1349 .clk_from_cmu = true,
1350 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1351};
1352
1353static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1354 {
1355 .name = "s3c2443-spi",
1356 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1357 }, {
1358 .name = "s3c6410-spi",
1359 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1360 },
1361 { },
1362};
1363
1364static const struct of_device_id s3c64xx_spi_dt_match[] = {
1365 { .compatible = "samsung,s3c2443-spi",
1366 .data = (void *)&s3c2443_spi_port_config,
1367 },
1368 { .compatible = "samsung,s3c6410-spi",
1369 .data = (void *)&s3c6410_spi_port_config,
1370 },
1371 { .compatible = "samsung,s5pv210-spi",
1372 .data = (void *)&s5pv210_spi_port_config,
1373 },
1374 { .compatible = "samsung,exynos4210-spi",
1375 .data = (void *)&exynos4_spi_port_config,
1376 },
1377 { .compatible = "samsung,exynos5440-spi",
1378 .data = (void *)&exynos5440_spi_port_config,
1379 },
1380 { .compatible = "samsung,exynos7-spi",
1381 .data = (void *)&exynos7_spi_port_config,
1382 },
1383 { },
1384};
1385MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1386
1387static struct platform_driver s3c64xx_spi_driver = {
1388 .driver = {
1389 .name = "s3c64xx-spi",
1390 .pm = &s3c64xx_spi_pm,
1391 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1392 },
1393 .probe = s3c64xx_spi_probe,
1394 .remove = s3c64xx_spi_remove,
1395 .id_table = s3c64xx_spi_driver_ids,
1396};
1397MODULE_ALIAS("platform:s3c64xx-spi");
1398
1399module_platform_driver(s3c64xx_spi_driver);
1400
1401MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1402MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1403MODULE_LICENSE("GPL");
1404