LXR linux/drivers/staging/comedi/drivers/adv

   1/*
   2 * COMEDI driver for the Advantech PCI-1760
   3 * Copyright (C) 2015 H Hartley Sweeten <hsweeten@visionengravers.com>
   4 *
   5 * Based on the pci1760 support in the adv_pci_dio driver written by:
   6 *      Michal Dobes <dobes@tesnet.cz>
   7 *
   8 * COMEDI - Linux Control and Measurement Device Interface
   9 * Copyright (C) 2000 David A. Schleef <ds@schleef.org>
  10 *
  11 * This program is free software; you can redistribute it and/or modify
  12 * it under the terms of the GNU General Public License as published by
  13 * the Free Software Foundation; either version 2 of the License, or
  14 * (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 */
  21
  22/*
  23 * Driver: adv_pci1760
  24 * Description: Advantech PCI-1760 Relay & Isolated Digital Input Card
  25 * Devices: [Advantech] PCI-1760 (adv_pci1760)
  26 * Author: H Hartley Sweeten <hsweeten@visionengravers.com>
  27 * Updated: Fri, 13 Nov 2015 12:34:00 -0700
  28 * Status: untested
  29 *
  30 * Configuration Options: not applicable, uses PCI auto config
  31 */
  32
  33#include <linux/module.h>
  34
  35#include "../comedi_pci.h"
  36
  37/*
  38 * PCI-1760 Register Map
  39 *
  40 * Outgoing Mailbox Bytes
  41 * OMB3: Not used (must be 0)
  42 * OMB2: The command code to the PCI-1760
  43 * OMB1: The hi byte of the parameter for the command in OMB2
  44 * OMB0: The lo byte of the parameter for the command in OMB2
  45 *
  46 * Incoming Mailbox Bytes
  47 * IMB3: The Isolated Digital Input status (updated every 100us)
  48 * IMB2: The current command (matches OMB2 when command is successful)
  49 * IMB1: The hi byte of the feedback data for the command in OMB2
  50 * IMB0: The lo byte of the feedback data for the command in OMB2
  51 *
  52 * Interrupt Control/Status
  53 * INTCSR3: Not used (must be 0)
  54 * INTCSR2: The interrupt status (read only)
  55 * INTCSR1: Interrupt enable/disable
  56 * INTCSR0: Not used (must be 0)
  57 */
  58#define PCI1760_OMB_REG(x)              (0x0c + (x))
  59#define PCI1760_IMB_REG(x)              (0x1c + (x))
  60#define PCI1760_INTCSR_REG(x)           (0x38 + (x))
  61#define PCI1760_INTCSR1_IRQ_ENA         BIT(5)
  62#define PCI1760_INTCSR2_OMB_IRQ         BIT(0)
  63#define PCI1760_INTCSR2_IMB_IRQ         BIT(1)
  64#define PCI1760_INTCSR2_IRQ_STATUS      BIT(6)
  65#define PCI1760_INTCSR2_IRQ_ASSERTED    BIT(7)
  66
  67/* PCI-1760 command codes */
  68#define PCI1760_CMD_CLR_IMB2            0x00    /* Clears IMB2 */
  69#define PCI1760_CMD_SET_DO              0x01    /* Set output state */
  70#define PCI1760_CMD_GET_DO              0x02    /* Read output status */
  71#define PCI1760_CMD_GET_STATUS          0x03    /* Read current status */
  72#define PCI1760_CMD_GET_FW_VER          0x0e    /* Read firware version */
  73#define PCI1760_CMD_GET_HW_VER          0x0f    /* Read hardware version */
  74#define PCI1760_CMD_SET_PWM_HI(x)       (0x10 + (x) * 2) /* Set "hi" period */
  75#define PCI1760_CMD_SET_PWM_LO(x)       (0x11 + (x) * 2) /* Set "lo" period */
  76#define PCI1760_CMD_SET_PWM_CNT(x)      (0x14 + (x)) /* Set burst count */
  77#define PCI1760_CMD_ENA_PWM             0x1f    /* Enable PWM outputs */
  78#define PCI1760_CMD_ENA_FILT            0x20    /* Enable input filter */
  79#define PCI1760_CMD_ENA_PAT_MATCH       0x21    /* Enable input pattern match */
  80#define PCI1760_CMD_SET_PAT_MATCH       0x22    /* Set input pattern match */
  81#define PCI1760_CMD_ENA_RISE_EDGE       0x23    /* Enable input rising edge */
  82#define PCI1760_CMD_ENA_FALL_EDGE       0x24    /* Enable input falling edge */
  83#define PCI1760_CMD_ENA_CNT             0x28    /* Enable counter */
  84#define PCI1760_CMD_RST_CNT             0x29    /* Reset counter */
  85#define PCI1760_CMD_ENA_CNT_OFLOW       0x2a    /* Enable counter overflow */
  86#define PCI1760_CMD_ENA_CNT_MATCH       0x2b    /* Enable counter match */
  87#define PCI1760_CMD_SET_CNT_EDGE        0x2c    /* Set counter edge */
  88#define PCI1760_CMD_GET_CNT             0x2f    /* Reads counter value */
  89#define PCI1760_CMD_SET_HI_SAMP(x)      (0x30 + (x)) /* Set "hi" sample time */
  90#define PCI1760_CMD_SET_LO_SAMP(x)      (0x38 + (x)) /* Set "lo" sample time */
  91#define PCI1760_CMD_SET_CNT(x)          (0x40 + (x)) /* Set counter reset val */
  92#define PCI1760_CMD_SET_CNT_MATCH(x)    (0x48 + (x)) /* Set counter match val */
  93#define PCI1760_CMD_GET_INT_FLAGS       0x60    /* Read interrupt flags */
  94#define PCI1760_CMD_GET_INT_FLAGS_MATCH BIT(0)
  95#define PCI1760_CMD_GET_INT_FLAGS_COS   BIT(1)
  96#define PCI1760_CMD_GET_INT_FLAGS_OFLOW BIT(2)
  97#define PCI1760_CMD_GET_OS              0x61    /* Read edge change flags */
  98#define PCI1760_CMD_GET_CNT_STATUS      0x62    /* Read counter oflow/match */
  99
 100#define PCI1760_CMD_TIMEOUT             250     /* 250 usec timeout */
 101#define PCI1760_CMD_RETRIES             3       /* limit number of retries */
 102
 103#define PCI1760_PWM_TIMEBASE            100000  /* 1 unit = 100 usec */
 104
 105static int pci1760_send_cmd(struct comedi_device *dev,
 106                            unsigned char cmd, unsigned short val)
 107{
 108        unsigned long timeout;
 109
 110        /* send the command and parameter */
 111        outb(val & 0xff, dev->iobase + PCI1760_OMB_REG(0));
 112        outb((val >> 8) & 0xff, dev->iobase + PCI1760_OMB_REG(1));
 113        outb(cmd, dev->iobase + PCI1760_OMB_REG(2));
 114        outb(0, dev->iobase + PCI1760_OMB_REG(3));
 115
 116        /* datasheet says to allow up to 250 usec for the command to complete */
 117        timeout = jiffies + usecs_to_jiffies(PCI1760_CMD_TIMEOUT);
 118        do {
 119                if (inb(dev->iobase + PCI1760_IMB_REG(2)) == cmd) {
 120                        /* command success; return the feedback data */
 121                        return inb(dev->iobase + PCI1760_IMB_REG(0)) |
 122                               (inb(dev->iobase + PCI1760_IMB_REG(1)) << 8);
 123                }
 124                cpu_relax();
 125        } while (time_before(jiffies, timeout));
 126
 127        return -EBUSY;
 128}
 129
 130static int pci1760_cmd(struct comedi_device *dev,
 131                       unsigned char cmd, unsigned short val)
 132{
 133        int repeats;
 134        int ret;
 135
 136        /* send PCI1760_CMD_CLR_IMB2 between identical commands */
 137        if (inb(dev->iobase + PCI1760_IMB_REG(2)) == cmd) {
 138                ret = pci1760_send_cmd(dev, PCI1760_CMD_CLR_IMB2, 0);
 139                if (ret < 0) {
 140                        /* timeout? try it once more */
 141                        ret = pci1760_send_cmd(dev, PCI1760_CMD_CLR_IMB2, 0);
 142                        if (ret < 0)
 143                                return -ETIMEDOUT;
 144                }
 145        }
 146
 147        /* datasheet says to keep retrying the command */
 148        for (repeats = 0; repeats < PCI1760_CMD_RETRIES; repeats++) {
 149                ret = pci1760_send_cmd(dev, cmd, val);
 150                if (ret >= 0)
 151                        return ret;
 152        }
 153
 154        /* command failed! */
 155        return -ETIMEDOUT;
 156}
 157
 158static int pci1760_di_insn_bits(struct comedi_device *dev,
 159                                struct comedi_subdevice *s,
 160                                struct comedi_insn *insn,
 161                                unsigned int *data)
 162{
 163        data[1] = inb(dev->iobase + PCI1760_IMB_REG(3));
 164
 165        return insn->n;
 166}
 167
 168static int pci1760_do_insn_bits(struct comedi_device *dev,
 169                                struct comedi_subdevice *s,
 170                                struct comedi_insn *insn,
 171                                unsigned int *data)
 172{
 173        int ret;
 174
 175        if (comedi_dio_update_state(s, data)) {
 176                ret = pci1760_cmd(dev, PCI1760_CMD_SET_DO, s->state);
 177                if (ret < 0)
 178                        return ret;
 179        }
 180
 181        data[1] = s->state;
 182
 183        return insn->n;
 184}
 185
 186static int pci1760_pwm_ns_to_div(unsigned int flags, unsigned int ns)
 187{
 188        unsigned int divisor;
 189
 190        switch (flags) {
 191        case CMDF_ROUND_NEAREST:
 192                divisor = DIV_ROUND_CLOSEST(ns, PCI1760_PWM_TIMEBASE);
 193                break;
 194        case CMDF_ROUND_UP:
 195                divisor = DIV_ROUND_UP(ns, PCI1760_PWM_TIMEBASE);
 196                break;
 197        case CMDF_ROUND_DOWN:
 198                divisor = ns / PCI1760_PWM_TIMEBASE;
 199        default:
 200                return -EINVAL;
 201        }
 202
 203        if (divisor < 1)
 204                divisor = 1;
 205        if (divisor > 0xffff)
 206                divisor = 0xffff;
 207
 208        return divisor;
 209}
 210
 211static int pci1760_pwm_enable(struct comedi_device *dev,
 212                              unsigned int chan, bool enable)
 213{
 214        int ret;
 215
 216        ret = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS, PCI1760_CMD_ENA_PWM);
 217        if (ret < 0)
 218                return ret;
 219
 220        if (enable)
 221                ret |= BIT(chan);
 222        else
 223                ret &= ~BIT(chan);
 224
 225        return pci1760_cmd(dev, PCI1760_CMD_ENA_PWM, ret);
 226}
 227
 228static int pci1760_pwm_insn_config(struct comedi_device *dev,
 229                                   struct comedi_subdevice *s,
 230                                   struct comedi_insn *insn,
 231                                   unsigned int *data)
 232{
 233        unsigned int chan = CR_CHAN(insn->chanspec);
 234        int hi_div;
 235        int lo_div;
 236        int ret;
 237
 238        switch (data[0]) {
 239        case INSN_CONFIG_ARM:
 240                ret = pci1760_pwm_enable(dev, chan, false);
 241                if (ret < 0)
 242                        return ret;
 243
 244                if (data[1] > 0xffff)
 245                        return -EINVAL;
 246                ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_CNT(chan), data[1]);
 247                if (ret < 0)
 248                        return ret;
 249
 250                ret = pci1760_pwm_enable(dev, chan, true);
 251                if (ret < 0)
 252                        return ret;
 253                break;
 254        case INSN_CONFIG_DISARM:
 255                ret = pci1760_pwm_enable(dev, chan, false);
 256                if (ret < 0)
 257                        return ret;
 258                break;
 259        case INSN_CONFIG_PWM_OUTPUT:
 260                ret = pci1760_pwm_enable(dev, chan, false);
 261                if (ret < 0)
 262                        return ret;
 263
 264                hi_div = pci1760_pwm_ns_to_div(data[1], data[2]);
 265                lo_div = pci1760_pwm_ns_to_div(data[3], data[4]);
 266                if (hi_div < 0 || lo_div < 0)
 267                        return -EINVAL;
 268                if ((hi_div * PCI1760_PWM_TIMEBASE) != data[2] ||
 269                    (lo_div * PCI1760_PWM_TIMEBASE) != data[4]) {
 270                        data[2] = hi_div * PCI1760_PWM_TIMEBASE;
 271                        data[4] = lo_div * PCI1760_PWM_TIMEBASE;
 272                        return -EAGAIN;
 273                }
 274                ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_HI(chan), hi_div);
 275                if (ret < 0)
 276                        return ret;
 277                ret = pci1760_cmd(dev, PCI1760_CMD_SET_PWM_LO(chan), lo_div);
 278                if (ret < 0)
 279                        return ret;
 280                break;
 281        case INSN_CONFIG_GET_PWM_OUTPUT:
 282                hi_div = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
 283                                     PCI1760_CMD_SET_PWM_HI(chan));
 284                lo_div = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
 285                                     PCI1760_CMD_SET_PWM_LO(chan));
 286                if (hi_div < 0 || lo_div < 0)
 287                        return -ETIMEDOUT;
 288
 289                data[1] = hi_div * PCI1760_PWM_TIMEBASE;
 290                data[2] = lo_div * PCI1760_PWM_TIMEBASE;
 291                break;
 292        case INSN_CONFIG_GET_PWM_STATUS:
 293                ret = pci1760_cmd(dev, PCI1760_CMD_GET_STATUS,
 294                                  PCI1760_CMD_ENA_PWM);
 295                if (ret < 0)
 296                        return ret;
 297
 298                data[1] = (ret & BIT(chan)) ? 1 : 0;
 299                break;
 300        default:
 301                return -EINVAL;
 302        }
 303
 304        return insn->n;
 305}
 306
 307static void pci1760_reset(struct comedi_device *dev)
 308{
 309        int i;
 310
 311        /* disable interrupts (intcsr2 is read-only) */
 312        outb(0, dev->iobase + PCI1760_INTCSR_REG(0));
 313        outb(0, dev->iobase + PCI1760_INTCSR_REG(1));
 314        outb(0, dev->iobase + PCI1760_INTCSR_REG(3));
 315
 316        /* disable counters */
 317        pci1760_cmd(dev, PCI1760_CMD_ENA_CNT, 0);
 318
 319        /* disable overflow interrupts */
 320        pci1760_cmd(dev, PCI1760_CMD_ENA_CNT_OFLOW, 0);
 321
 322        /* disable match */
 323        pci1760_cmd(dev, PCI1760_CMD_ENA_CNT_MATCH, 0);
 324
 325        /* set match and counter reset values */
 326        for (i = 0; i < 8; i++) {
 327                pci1760_cmd(dev, PCI1760_CMD_SET_CNT_MATCH(i), 0x8000);
 328                pci1760_cmd(dev, PCI1760_CMD_SET_CNT(i), 0x0000);
 329        }
 330
 331        /* reset counters to reset values */
 332        pci1760_cmd(dev, PCI1760_CMD_RST_CNT, 0xff);
 333
 334        /* set counter count edges */
 335        pci1760_cmd(dev, PCI1760_CMD_SET_CNT_EDGE, 0);
 336
 337        /* disable input filters */
 338        pci1760_cmd(dev, PCI1760_CMD_ENA_FILT, 0);
 339
 340        /* disable pattern matching */
 341        pci1760_cmd(dev, PCI1760_CMD_ENA_PAT_MATCH, 0);
 342
 343        /* set pattern match value */
 344        pci1760_cmd(dev, PCI1760_CMD_SET_PAT_MATCH, 0);
 345}
 346
 347static int pci1760_auto_attach(struct comedi_device *dev,
 348                               unsigned long context)
 349{
 350        struct pci_dev *pcidev = comedi_to_pci_dev(dev);
 351        struct comedi_subdevice *s;
 352        int ret;
 353
 354        ret = comedi_pci_enable(dev);
 355        if (ret)
 356                return ret;
 357        dev->iobase = pci_resource_start(pcidev, 0);
 358
 359        pci1760_reset(dev);
 360
 361        ret = comedi_alloc_subdevices(dev, 4);
 362        if (ret)
 363                return ret;
 364
 365        /* Digital Input subdevice */
 366        s = &dev->subdevices[0];
 367        s->type         = COMEDI_SUBD_DI;
 368        s->subdev_flags = SDF_READABLE;
 369        s->n_chan       = 8;
 370        s->maxdata      = 1;
 371        s->range_table  = &range_digital;
 372        s->insn_bits    = pci1760_di_insn_bits;
 373
 374        /* Digital Output subdevice */
 375        s = &dev->subdevices[1];
 376        s->type         = COMEDI_SUBD_DO;
 377        s->subdev_flags = SDF_WRITABLE;
 378        s->n_chan       = 8;
 379        s->maxdata      = 1;
 380        s->range_table  = &range_digital;
 381        s->insn_bits    = pci1760_do_insn_bits;
 382
 383        /* get the current state of the outputs */
 384        ret = pci1760_cmd(dev, PCI1760_CMD_GET_DO, 0);
 385        if (ret < 0)
 386                return ret;
 387        s->state        = ret;
 388
 389        /* PWM subdevice */
 390        s = &dev->subdevices[2];
 391        s->type         = COMEDI_SUBD_PWM;
 392        s->subdev_flags = SDF_PWM_COUNTER;
 393        s->n_chan       = 2;
 394        s->insn_config  = pci1760_pwm_insn_config;
 395
 396        /* Counter subdevice */
 397        s = &dev->subdevices[3];
 398        s->type         = COMEDI_SUBD_UNUSED;
 399
 400        return 0;
 401}
 402
 403static struct comedi_driver pci1760_driver = {
 404        .driver_name    = "adv_pci1760",
 405        .module         = THIS_MODULE,
 406        .auto_attach    = pci1760_auto_attach,
 407        .detach         = comedi_pci_detach,
 408};
 409
 410static int pci1760_pci_probe(struct pci_dev *dev,
 411                             const struct pci_device_id *id)
 412{
 413        return comedi_pci_auto_config(dev, &pci1760_driver, id->driver_data);
 414}
 415
 416static const struct pci_device_id pci1760_pci_table[] = {
 417        { PCI_DEVICE(PCI_VENDOR_ID_ADVANTECH, 0x1760) },
 418        { 0 }
 419};
 420MODULE_DEVICE_TABLE(pci, pci1760_pci_table);
 421
 422static struct pci_driver pci1760_pci_driver = {
 423        .name           = "adv_pci1760",
 424        .id_table       = pci1760_pci_table,
 425        .probe          = pci1760_pci_probe,
 426        .remove         = comedi_pci_auto_unconfig,
 427};
 428module_comedi_pci_driver(pci1760_driver, pci1760_pci_driver);
 429
 430MODULE_AUTHOR("Comedi http://www.comedi.org");
 431MODULE_DESCRIPTION("Comedi driver for Advantech PCI-1760");
 432MODULE_LICENSE("GPL");
 433