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9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/slab.h>
13#include <linux/sysfs.h>
14#include <linux/spi/spi.h>
15#include <linux/regulator/consumer.h>
16#include <linux/err.h>
17#include <linux/sched.h>
18#include <linux/delay.h>
19
20#include <linux/iio/iio.h>
21#include <linux/iio/sysfs.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/trigger.h>
24#include <linux/iio/trigger_consumer.h>
25#include <linux/iio/triggered_buffer.h>
26#include <linux/iio/adc/ad_sigma_delta.h>
27
28#include "ad7192.h"
29
30
31#define AD7192_REG_COMM 0
32#define AD7192_REG_STAT 0
33#define AD7192_REG_MODE 1
34#define AD7192_REG_CONF 2
35#define AD7192_REG_DATA 3
36#define AD7192_REG_ID 4
37#define AD7192_REG_GPOCON 5
38#define AD7192_REG_OFFSET 6
39
40#define AD7192_REG_FULLSALE 7
41
42
43
44#define AD7192_COMM_WEN BIT(7)
45#define AD7192_COMM_WRITE 0
46#define AD7192_COMM_READ BIT(6)
47#define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3)
48#define AD7192_COMM_CREAD BIT(2)
49
50
51#define AD7192_STAT_RDY BIT(7)
52#define AD7192_STAT_ERR BIT(6)
53#define AD7192_STAT_NOREF BIT(5)
54#define AD7192_STAT_PARITY BIT(4)
55#define AD7192_STAT_CH3 BIT(2)
56#define AD7192_STAT_CH2 BIT(1)
57#define AD7192_STAT_CH1 BIT(0)
58
59
60#define AD7192_MODE_SEL(x) (((x) & 0x7) << 21)
61#define AD7192_MODE_SEL_MASK (0x7 << 21)
62#define AD7192_MODE_DAT_STA BIT(20)
63#define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18)
64#define AD7192_MODE_SINC3 BIT(15)
65#define AD7192_MODE_ACX BIT(14)
66#define AD7192_MODE_ENPAR BIT(13)
67#define AD7192_MODE_CLKDIV BIT(12)
68#define AD7192_MODE_SCYCLE BIT(11)
69#define AD7192_MODE_REJ60 BIT(10)
70#define AD7192_MODE_RATE(x) ((x) & 0x3FF)
71
72
73#define AD7192_MODE_CONT 0
74#define AD7192_MODE_SINGLE 1
75#define AD7192_MODE_IDLE 2
76#define AD7192_MODE_PWRDN 3
77#define AD7192_MODE_CAL_INT_ZERO 4
78#define AD7192_MODE_CAL_INT_FULL 5
79#define AD7192_MODE_CAL_SYS_ZERO 6
80#define AD7192_MODE_CAL_SYS_FULL 7
81
82
83#define AD7192_CLK_EXT_MCLK1_2 0
84
85#define AD7192_CLK_EXT_MCLK2 1
86#define AD7192_CLK_INT 2
87
88#define AD7192_CLK_INT_CO 3
89
90
91
92
93#define AD7192_CONF_CHOP BIT(23)
94#define AD7192_CONF_REFSEL BIT(20)
95#define AD7192_CONF_CHAN(x) ((x) << 8)
96#define AD7192_CONF_CHAN_MASK (0x7FF << 8)
97#define AD7192_CONF_BURN BIT(7)
98#define AD7192_CONF_REFDET BIT(6)
99#define AD7192_CONF_BUF BIT(4)
100#define AD7192_CONF_UNIPOLAR BIT(3)
101#define AD7192_CONF_GAIN(x) ((x) & 0x7)
102
103#define AD7192_CH_AIN1P_AIN2M BIT(0)
104#define AD7192_CH_AIN3P_AIN4M BIT(1)
105#define AD7192_CH_TEMP BIT(2)
106#define AD7192_CH_AIN2P_AIN2M BIT(3)
107#define AD7192_CH_AIN1 BIT(4)
108#define AD7192_CH_AIN2 BIT(5)
109#define AD7192_CH_AIN3 BIT(6)
110#define AD7192_CH_AIN4 BIT(7)
111
112#define AD7193_CH_AIN1P_AIN2M 0x000
113#define AD7193_CH_AIN3P_AIN4M 0x001
114#define AD7193_CH_AIN5P_AIN6M 0x002
115#define AD7193_CH_AIN7P_AIN8M 0x004
116#define AD7193_CH_TEMP 0x100
117#define AD7193_CH_AIN2P_AIN2M 0x200
118#define AD7193_CH_AIN1 0x401
119#define AD7193_CH_AIN2 0x402
120#define AD7193_CH_AIN3 0x404
121#define AD7193_CH_AIN4 0x408
122#define AD7193_CH_AIN5 0x410
123#define AD7193_CH_AIN6 0x420
124#define AD7193_CH_AIN7 0x440
125#define AD7193_CH_AIN8 0x480
126#define AD7193_CH_AINCOM 0x600
127
128
129#define ID_AD7190 0x4
130#define ID_AD7192 0x0
131#define ID_AD7193 0x2
132#define ID_AD7195 0x6
133#define AD7192_ID_MASK 0x0F
134
135
136#define AD7192_GPOCON_BPDSW BIT(6)
137#define AD7192_GPOCON_GP32EN BIT(5)
138#define AD7192_GPOCON_GP10EN BIT(4)
139#define AD7192_GPOCON_P3DAT BIT(3)
140#define AD7192_GPOCON_P2DAT BIT(2)
141#define AD7192_GPOCON_P1DAT BIT(1)
142#define AD7192_GPOCON_P0DAT BIT(0)
143
144#define AD7192_INT_FREQ_MHZ 4915200
145
146
147
148
149
150
151
152
153
154struct ad7192_state {
155 struct regulator *reg;
156 u16 int_vref_mv;
157 u32 mclk;
158 u32 f_order;
159 u32 mode;
160 u32 conf;
161 u32 scale_avail[8][2];
162 u8 gpocon;
163 u8 devid;
164
165 struct ad_sigma_delta sd;
166};
167
168static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd)
169{
170 return container_of(sd, struct ad7192_state, sd);
171}
172
173static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
174{
175 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
176
177 st->conf &= ~AD7192_CONF_CHAN_MASK;
178 st->conf |= AD7192_CONF_CHAN(channel);
179
180 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
181}
182
183static int ad7192_set_mode(struct ad_sigma_delta *sd,
184 enum ad_sigma_delta_mode mode)
185{
186 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd);
187
188 st->mode &= ~AD7192_MODE_SEL_MASK;
189 st->mode |= AD7192_MODE_SEL(mode);
190
191 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
192}
193
194static const struct ad_sigma_delta_info ad7192_sigma_delta_info = {
195 .set_channel = ad7192_set_channel,
196 .set_mode = ad7192_set_mode,
197 .has_registers = true,
198 .addr_shift = 3,
199 .read_mask = BIT(6),
200};
201
202static const struct ad_sd_calib_data ad7192_calib_arr[8] = {
203 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1},
204 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1},
205 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2},
206 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2},
207 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3},
208 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3},
209 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4},
210 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4}
211};
212
213static int ad7192_calibrate_all(struct ad7192_state *st)
214{
215 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr,
216 ARRAY_SIZE(ad7192_calib_arr));
217}
218
219static int ad7192_setup(struct ad7192_state *st,
220 const struct ad7192_platform_data *pdata)
221{
222 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi);
223 unsigned long long scale_uv;
224 int i, ret, id;
225 u8 ones[6];
226
227
228 memset(&ones, 0xFF, 6);
229 ret = spi_write(st->sd.spi, &ones, 6);
230 if (ret < 0)
231 goto out;
232 usleep_range(500, 1000);
233
234
235 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id);
236 if (ret)
237 goto out;
238
239 id &= AD7192_ID_MASK;
240
241 if (id != st->devid)
242 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n",
243 id);
244
245 switch (pdata->clock_source_sel) {
246 case AD7192_CLK_EXT_MCLK1_2:
247 case AD7192_CLK_EXT_MCLK2:
248 st->mclk = AD7192_INT_FREQ_MHZ;
249 break;
250 case AD7192_CLK_INT:
251 case AD7192_CLK_INT_CO:
252 if (pdata->ext_clk_hz)
253 st->mclk = pdata->ext_clk_hz;
254 else
255 st->mclk = AD7192_INT_FREQ_MHZ;
256 break;
257 default:
258 ret = -EINVAL;
259 goto out;
260 }
261
262 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) |
263 AD7192_MODE_CLKSRC(pdata->clock_source_sel) |
264 AD7192_MODE_RATE(480);
265
266 st->conf = AD7192_CONF_GAIN(0);
267
268 if (pdata->rej60_en)
269 st->mode |= AD7192_MODE_REJ60;
270
271 if (pdata->sinc3_en)
272 st->mode |= AD7192_MODE_SINC3;
273
274 if (pdata->refin2_en && (st->devid != ID_AD7195))
275 st->conf |= AD7192_CONF_REFSEL;
276
277 if (pdata->chop_en) {
278 st->conf |= AD7192_CONF_CHOP;
279 if (pdata->sinc3_en)
280 st->f_order = 3;
281 else
282 st->f_order = 4;
283 } else {
284 st->f_order = 1;
285 }
286
287 if (pdata->buf_en)
288 st->conf |= AD7192_CONF_BUF;
289
290 if (pdata->unipolar_en)
291 st->conf |= AD7192_CONF_UNIPOLAR;
292
293 if (pdata->burnout_curr_en)
294 st->conf |= AD7192_CONF_BURN;
295
296 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
297 if (ret)
298 goto out;
299
300 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf);
301 if (ret)
302 goto out;
303
304 ret = ad7192_calibrate_all(st);
305 if (ret)
306 goto out;
307
308
309 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
310 scale_uv = ((u64)st->int_vref_mv * 100000000)
311 >> (indio_dev->channels[0].scan_type.realbits -
312 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1));
313 scale_uv >>= i;
314
315 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
316 st->scale_avail[i][0] = scale_uv;
317 }
318
319 return 0;
320out:
321 dev_err(&st->sd.spi->dev, "setup failed\n");
322 return ret;
323}
324
325static ssize_t ad7192_read_frequency(struct device *dev,
326 struct device_attribute *attr,
327 char *buf)
328{
329 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
330 struct ad7192_state *st = iio_priv(indio_dev);
331
332 return sprintf(buf, "%d\n", st->mclk /
333 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)));
334}
335
336static ssize_t ad7192_write_frequency(struct device *dev,
337 struct device_attribute *attr,
338 const char *buf,
339 size_t len)
340{
341 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
342 struct ad7192_state *st = iio_priv(indio_dev);
343 unsigned long lval;
344 int div, ret;
345
346 ret = kstrtoul(buf, 10, &lval);
347 if (ret)
348 return ret;
349 if (lval == 0)
350 return -EINVAL;
351
352 mutex_lock(&indio_dev->mlock);
353 if (iio_buffer_enabled(indio_dev)) {
354 mutex_unlock(&indio_dev->mlock);
355 return -EBUSY;
356 }
357
358 div = st->mclk / (lval * st->f_order * 1024);
359 if (div < 1 || div > 1023) {
360 ret = -EINVAL;
361 goto out;
362 }
363
364 st->mode &= ~AD7192_MODE_RATE(-1);
365 st->mode |= AD7192_MODE_RATE(div);
366 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
367
368out:
369 mutex_unlock(&indio_dev->mlock);
370
371 return ret ? ret : len;
372}
373
374static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
375 ad7192_read_frequency,
376 ad7192_write_frequency);
377
378static ssize_t
379ad7192_show_scale_available(struct device *dev,
380 struct device_attribute *attr, char *buf)
381{
382 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
383 struct ad7192_state *st = iio_priv(indio_dev);
384 int i, len = 0;
385
386 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
387 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
388 st->scale_avail[i][1]);
389
390 len += sprintf(buf + len, "\n");
391
392 return len;
393}
394
395static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available,
396 in_voltage-voltage_scale_available,
397 S_IRUGO, ad7192_show_scale_available, NULL, 0);
398
399static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
400 ad7192_show_scale_available, NULL, 0);
401
402static ssize_t ad7192_show_ac_excitation(struct device *dev,
403 struct device_attribute *attr,
404 char *buf)
405{
406 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
407 struct ad7192_state *st = iio_priv(indio_dev);
408
409 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX));
410}
411
412static ssize_t ad7192_show_bridge_switch(struct device *dev,
413 struct device_attribute *attr,
414 char *buf)
415{
416 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
417 struct ad7192_state *st = iio_priv(indio_dev);
418
419 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW));
420}
421
422static ssize_t ad7192_set(struct device *dev,
423 struct device_attribute *attr,
424 const char *buf,
425 size_t len)
426{
427 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
428 struct ad7192_state *st = iio_priv(indio_dev);
429 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
430 int ret;
431 bool val;
432
433 ret = strtobool(buf, &val);
434 if (ret < 0)
435 return ret;
436
437 mutex_lock(&indio_dev->mlock);
438 if (iio_buffer_enabled(indio_dev)) {
439 mutex_unlock(&indio_dev->mlock);
440 return -EBUSY;
441 }
442
443 switch ((u32)this_attr->address) {
444 case AD7192_REG_GPOCON:
445 if (val)
446 st->gpocon |= AD7192_GPOCON_BPDSW;
447 else
448 st->gpocon &= ~AD7192_GPOCON_BPDSW;
449
450 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon);
451 break;
452 case AD7192_REG_MODE:
453 if (val)
454 st->mode |= AD7192_MODE_ACX;
455 else
456 st->mode &= ~AD7192_MODE_ACX;
457
458 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode);
459 break;
460 default:
461 ret = -EINVAL;
462 }
463
464 mutex_unlock(&indio_dev->mlock);
465
466 return ret ? ret : len;
467}
468
469static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR,
470 ad7192_show_bridge_switch, ad7192_set,
471 AD7192_REG_GPOCON);
472
473static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR,
474 ad7192_show_ac_excitation, ad7192_set,
475 AD7192_REG_MODE);
476
477static struct attribute *ad7192_attributes[] = {
478 &iio_dev_attr_sampling_frequency.dev_attr.attr,
479 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
480 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
481 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
482 &iio_dev_attr_ac_excitation_en.dev_attr.attr,
483 NULL
484};
485
486static const struct attribute_group ad7192_attribute_group = {
487 .attrs = ad7192_attributes,
488};
489
490static struct attribute *ad7195_attributes[] = {
491 &iio_dev_attr_sampling_frequency.dev_attr.attr,
492 &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr,
493 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
494 &iio_dev_attr_bridge_switch_en.dev_attr.attr,
495 NULL
496};
497
498static const struct attribute_group ad7195_attribute_group = {
499 .attrs = ad7195_attributes,
500};
501
502static unsigned int ad7192_get_temp_scale(bool unipolar)
503{
504 return unipolar ? 2815 * 2 : 2815;
505}
506
507static int ad7192_read_raw(struct iio_dev *indio_dev,
508 struct iio_chan_spec const *chan,
509 int *val,
510 int *val2,
511 long m)
512{
513 struct ad7192_state *st = iio_priv(indio_dev);
514 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR);
515
516 switch (m) {
517 case IIO_CHAN_INFO_RAW:
518 return ad_sigma_delta_single_conversion(indio_dev, chan, val);
519 case IIO_CHAN_INFO_SCALE:
520 switch (chan->type) {
521 case IIO_VOLTAGE:
522 mutex_lock(&indio_dev->mlock);
523 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0];
524 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1];
525 mutex_unlock(&indio_dev->mlock);
526 return IIO_VAL_INT_PLUS_NANO;
527 case IIO_TEMP:
528 *val = 0;
529 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar);
530 return IIO_VAL_INT_PLUS_NANO;
531 default:
532 return -EINVAL;
533 }
534 case IIO_CHAN_INFO_OFFSET:
535 if (!unipolar)
536 *val = -(1 << (chan->scan_type.realbits - 1));
537 else
538 *val = 0;
539
540 if (chan->type == IIO_TEMP)
541 *val -= 273 * ad7192_get_temp_scale(unipolar);
542 return IIO_VAL_INT;
543 }
544
545 return -EINVAL;
546}
547
548static int ad7192_write_raw(struct iio_dev *indio_dev,
549 struct iio_chan_spec const *chan,
550 int val,
551 int val2,
552 long mask)
553{
554 struct ad7192_state *st = iio_priv(indio_dev);
555 int ret, i;
556 unsigned int tmp;
557
558 mutex_lock(&indio_dev->mlock);
559 if (iio_buffer_enabled(indio_dev)) {
560 mutex_unlock(&indio_dev->mlock);
561 return -EBUSY;
562 }
563
564 switch (mask) {
565 case IIO_CHAN_INFO_SCALE:
566 ret = -EINVAL;
567 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
568 if (val2 == st->scale_avail[i][1]) {
569 ret = 0;
570 tmp = st->conf;
571 st->conf &= ~AD7192_CONF_GAIN(-1);
572 st->conf |= AD7192_CONF_GAIN(i);
573 if (tmp == st->conf)
574 break;
575 ad_sd_write_reg(&st->sd, AD7192_REG_CONF,
576 3, st->conf);
577 ad7192_calibrate_all(st);
578 break;
579 }
580 break;
581 default:
582 ret = -EINVAL;
583 }
584
585 mutex_unlock(&indio_dev->mlock);
586
587 return ret;
588}
589
590static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev,
591 struct iio_chan_spec const *chan,
592 long mask)
593{
594 return IIO_VAL_INT_PLUS_NANO;
595}
596
597static const struct iio_info ad7192_info = {
598 .read_raw = &ad7192_read_raw,
599 .write_raw = &ad7192_write_raw,
600 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
601 .attrs = &ad7192_attribute_group,
602 .validate_trigger = ad_sd_validate_trigger,
603 .driver_module = THIS_MODULE,
604};
605
606static const struct iio_info ad7195_info = {
607 .read_raw = &ad7192_read_raw,
608 .write_raw = &ad7192_write_raw,
609 .write_raw_get_fmt = &ad7192_write_raw_get_fmt,
610 .attrs = &ad7195_attribute_group,
611 .validate_trigger = ad_sd_validate_trigger,
612 .driver_module = THIS_MODULE,
613};
614
615static const struct iio_chan_spec ad7192_channels[] = {
616 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M, 24, 32, 0),
617 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M, 24, 32, 0),
618 AD_SD_TEMP_CHANNEL(2, AD7192_CH_TEMP, 24, 32, 0),
619 AD_SD_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M, 24, 32, 0),
620 AD_SD_CHANNEL(4, 1, AD7192_CH_AIN1, 24, 32, 0),
621 AD_SD_CHANNEL(5, 2, AD7192_CH_AIN2, 24, 32, 0),
622 AD_SD_CHANNEL(6, 3, AD7192_CH_AIN3, 24, 32, 0),
623 AD_SD_CHANNEL(7, 4, AD7192_CH_AIN4, 24, 32, 0),
624 IIO_CHAN_SOFT_TIMESTAMP(8),
625};
626
627static const struct iio_chan_spec ad7193_channels[] = {
628 AD_SD_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M, 24, 32, 0),
629 AD_SD_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M, 24, 32, 0),
630 AD_SD_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M, 24, 32, 0),
631 AD_SD_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M, 24, 32, 0),
632 AD_SD_TEMP_CHANNEL(4, AD7193_CH_TEMP, 24, 32, 0),
633 AD_SD_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M, 24, 32, 0),
634 AD_SD_CHANNEL(6, 1, AD7193_CH_AIN1, 24, 32, 0),
635 AD_SD_CHANNEL(7, 2, AD7193_CH_AIN2, 24, 32, 0),
636 AD_SD_CHANNEL(8, 3, AD7193_CH_AIN3, 24, 32, 0),
637 AD_SD_CHANNEL(9, 4, AD7193_CH_AIN4, 24, 32, 0),
638 AD_SD_CHANNEL(10, 5, AD7193_CH_AIN5, 24, 32, 0),
639 AD_SD_CHANNEL(11, 6, AD7193_CH_AIN6, 24, 32, 0),
640 AD_SD_CHANNEL(12, 7, AD7193_CH_AIN7, 24, 32, 0),
641 AD_SD_CHANNEL(13, 8, AD7193_CH_AIN8, 24, 32, 0),
642 IIO_CHAN_SOFT_TIMESTAMP(14),
643};
644
645static int ad7192_probe(struct spi_device *spi)
646{
647 const struct ad7192_platform_data *pdata = dev_get_platdata(&spi->dev);
648 struct ad7192_state *st;
649 struct iio_dev *indio_dev;
650 int ret, voltage_uv = 0;
651
652 if (!pdata) {
653 dev_err(&spi->dev, "no platform data?\n");
654 return -ENODEV;
655 }
656
657 if (!spi->irq) {
658 dev_err(&spi->dev, "no IRQ?\n");
659 return -ENODEV;
660 }
661
662 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
663 if (!indio_dev)
664 return -ENOMEM;
665
666 st = iio_priv(indio_dev);
667
668 st->reg = devm_regulator_get(&spi->dev, "vcc");
669 if (!IS_ERR(st->reg)) {
670 ret = regulator_enable(st->reg);
671 if (ret)
672 return ret;
673
674 voltage_uv = regulator_get_voltage(st->reg);
675 }
676
677 if (pdata->vref_mv)
678 st->int_vref_mv = pdata->vref_mv;
679 else if (voltage_uv)
680 st->int_vref_mv = voltage_uv / 1000;
681 else
682 dev_warn(&spi->dev, "reference voltage undefined\n");
683
684 spi_set_drvdata(spi, indio_dev);
685 st->devid = spi_get_device_id(spi)->driver_data;
686 indio_dev->dev.parent = &spi->dev;
687 indio_dev->name = spi_get_device_id(spi)->name;
688 indio_dev->modes = INDIO_DIRECT_MODE;
689
690 switch (st->devid) {
691 case ID_AD7193:
692 indio_dev->channels = ad7193_channels;
693 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels);
694 break;
695 default:
696 indio_dev->channels = ad7192_channels;
697 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels);
698 break;
699 }
700
701 if (st->devid == ID_AD7195)
702 indio_dev->info = &ad7195_info;
703 else
704 indio_dev->info = &ad7192_info;
705
706 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info);
707
708 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
709 if (ret)
710 goto error_disable_reg;
711
712 ret = ad7192_setup(st, pdata);
713 if (ret)
714 goto error_remove_trigger;
715
716 ret = iio_device_register(indio_dev);
717 if (ret < 0)
718 goto error_remove_trigger;
719 return 0;
720
721error_remove_trigger:
722 ad_sd_cleanup_buffer_and_trigger(indio_dev);
723error_disable_reg:
724 if (!IS_ERR(st->reg))
725 regulator_disable(st->reg);
726
727 return ret;
728}
729
730static int ad7192_remove(struct spi_device *spi)
731{
732 struct iio_dev *indio_dev = spi_get_drvdata(spi);
733 struct ad7192_state *st = iio_priv(indio_dev);
734
735 iio_device_unregister(indio_dev);
736 ad_sd_cleanup_buffer_and_trigger(indio_dev);
737
738 if (!IS_ERR(st->reg))
739 regulator_disable(st->reg);
740
741 return 0;
742}
743
744static const struct spi_device_id ad7192_id[] = {
745 {"ad7190", ID_AD7190},
746 {"ad7192", ID_AD7192},
747 {"ad7193", ID_AD7193},
748 {"ad7195", ID_AD7195},
749 {}
750};
751MODULE_DEVICE_TABLE(spi, ad7192_id);
752
753static struct spi_driver ad7192_driver = {
754 .driver = {
755 .name = "ad7192",
756 },
757 .probe = ad7192_probe,
758 .remove = ad7192_remove,
759 .id_table = ad7192_id,
760};
761module_spi_driver(ad7192_driver);
762
763MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
764MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC");
765MODULE_LICENSE("GPL v2");
766